4 * Copyright(c) 2014-2017 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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34 /* This file should not be included directly. Include common.h instead. */
36 #ifndef __T4_ADAPTER_H__
37 #define __T4_ADAPTER_H__
39 #include <rte_bus_pci.h>
43 #include "cxgbe_compat.h"
44 #include "t4_regs_values.h"
47 MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
54 PORT_RSS_DONE = (1 << 0),
58 struct adapter *adapter; /* adapter that this port belongs to */
59 struct rte_eth_dev *eth_dev; /* associated rte eth device */
60 struct port_stats stats_base; /* port statistics base */
61 struct link_config link_cfg; /* link configuration info */
63 unsigned long flags; /* port related flags */
64 short int xact_addr_filt; /* index of exact MAC address filter */
66 u16 viid; /* associated virtual interface id */
67 s8 mdio_addr; /* address of the PHY */
68 u8 port_type; /* firmware port type */
69 u8 mod_type; /* firmware module type */
70 u8 port_id; /* physical port ID */
71 u8 tx_chan; /* associated channel */
73 u8 n_rx_qsets; /* # of rx qsets */
74 u8 n_tx_qsets; /* # of tx qsets */
75 u8 first_qset; /* index of first qset */
77 u16 *rss; /* rss table */
78 u8 rss_mode; /* rss mode */
79 u16 rss_size; /* size of VI's RSS table slice */
82 /* Enable or disable autonegotiation. If this is set to enable,
83 * the forced link modes above are completely ignored.
85 #define AUTONEG_DISABLE 0x00
86 #define AUTONEG_ENABLE 0x01
88 enum { /* adapter flags */
89 FULL_INIT_DONE = (1 << 0),
91 USING_MSIX = (1 << 2),
92 FW_QUEUE_BOUND = (1 << 3),
94 CFG_QUEUES = (1 << 5),
98 struct rx_sw_desc { /* SW state per Rx descriptor */
99 void *buf; /* struct page or mbuf */
103 struct sge_fl { /* SGE free-buffer queue state */
105 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
107 dma_addr_t addr; /* bus address of HW ring start */
108 __be64 *desc; /* address of HW Rx descriptor ring */
110 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
111 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
113 unsigned int cntxt_id; /* SGE relative QID for the free list */
114 unsigned int size; /* capacity of free list */
116 unsigned int avail; /* # of available Rx buffers */
117 unsigned int pend_cred; /* new buffers since last FL DB ring */
118 unsigned int cidx; /* consumer index */
119 unsigned int pidx; /* producer index */
121 unsigned long alloc_failed; /* # of times buffer allocation failed */
122 unsigned long low; /* # of times momentarily starving */
125 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
127 /* A packet gather list */
130 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
132 void *va; /* virtual address of first byte */
133 unsigned int nfrags; /* # of fragments */
134 unsigned int tot_len; /* total length of fragments */
135 bool usembufs; /* use mbufs for fragments */
138 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
139 const struct pkt_gl *gl);
141 struct sge_rspq { /* state for an SGE response queue */
142 struct adapter *adapter; /* adapter that this queue belongs to */
143 struct rte_eth_dev *eth_dev; /* associated rte eth device */
144 struct rte_mempool *mb_pool; /* associated mempool */
146 dma_addr_t phys_addr; /* physical address of the ring */
147 __be64 *desc; /* address of HW response ring */
148 const __be64 *cur_desc; /* current descriptor in queue */
150 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
151 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
152 struct sge_qstat *stat;
154 unsigned int cidx; /* consumer index */
155 unsigned int gts_idx; /* last gts write sent */
156 unsigned int iqe_len; /* entry size */
157 unsigned int size; /* capacity of response queue */
158 int offset; /* offset into current Rx buffer */
160 u8 gen; /* current generation bit */
161 u8 intr_params; /* interrupt holdoff parameters */
162 u8 next_intr_params; /* holdoff params for next interrupt */
163 u8 pktcnt_idx; /* interrupt packet threshold */
164 u8 port_id; /* associated port-id */
165 u8 idx; /* queue index within its group */
166 u16 cntxt_id; /* SGE relative QID for the response Q */
167 u16 abs_id; /* absolute SGE id for the response q */
169 rspq_handler_t handler; /* associated handler for this response q */
172 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
173 u64 pkts; /* # of ethernet packets */
174 u64 rx_bytes; /* # of ethernet bytes */
175 u64 rx_cso; /* # of Rx checksum offloads */
176 u64 vlan_ex; /* # of Rx VLAN extractions */
177 u64 rx_drops; /* # of packets dropped due to no mem */
180 struct sge_eth_rxq { /* a SW Ethernet Rx queue */
181 struct sge_rspq rspq;
183 struct sge_eth_rx_stats stats;
184 bool usembufs; /* one ingress packet per mbuf FL buffer */
185 } __rte_cache_aligned;
188 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
189 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
190 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
191 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
192 * to be able to free those mbufs when we get completions back from the FW.
193 * Allocating the maximum number of pointers in every tx desc is a waste
194 * of memory resources so we only store 2 pointers per tx desc which should
195 * be enough since a tx desc can only fit 2 packets in the best case
196 * scenario where a packet needs 32 bytes.
198 #define ETH_COALESCE_PKT_NUM 15
199 #define ETH_COALESCE_PKT_PER_DESC 2
201 struct tx_eth_coal_desc {
202 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
203 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
211 struct tx_sw_desc { /* SW state per Tx descriptor */
212 struct rte_mbuf *mbuf;
213 struct ulptx_sgl *sgl;
214 struct tx_eth_coal_desc coalesce;
218 EQ_STOPPED = (1 << 0),
221 struct eth_coalesce {
231 struct tx_desc *desc; /* address of HW Tx descriptor ring */
232 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
233 struct sge_qstat *stat; /* queue status entry */
234 struct eth_coalesce coalesce; /* coalesce info */
236 uint64_t phys_addr; /* physical address of the ring */
238 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
239 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
241 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
242 unsigned int in_use; /* # of in-use Tx descriptors */
243 unsigned int size; /* # of descriptors */
244 unsigned int cidx; /* SW consumer index */
245 unsigned int pidx; /* producer index */
246 unsigned int dbidx; /* last idx when db ring was done */
247 unsigned int equeidx; /* last sent credit request */
248 unsigned int last_pidx; /* last pidx recorded by tx monitor */
249 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
251 int db_disabled; /* doorbell state */
252 unsigned short db_pidx; /* doorbell producer index */
253 unsigned short db_pidx_inc; /* doorbell producer increment */
256 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
257 u64 pkts; /* # of ethernet packets */
258 u64 tx_bytes; /* # of ethernet bytes */
259 u64 tso; /* # of TSO requests */
260 u64 tx_cso; /* # of Tx checksum offloads */
261 u64 vlan_ins; /* # of Tx VLAN insertions */
262 u64 mapping_err; /* # of I/O MMU packet mapping errors */
263 u64 coal_wr; /* # of coalesced wr */
264 u64 coal_pkts; /* # of coalesced packets */
267 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
269 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
270 struct sge_eth_tx_stats stats; /* queue statistics */
271 rte_spinlock_t txq_lock;
273 unsigned int flags; /* flags for state of the queue */
274 } __rte_cache_aligned;
277 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
278 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
279 struct sge_rspq fw_evtq __rte_cache_aligned;
281 u16 max_ethqsets; /* # of available Ethernet queue sets */
282 u32 stat_len; /* length of status page at ring end */
283 u32 pktshift; /* padding between CPL & packet data */
285 /* response queue interrupt parameters */
286 u16 timer_val[SGE_NTIMERS];
287 u8 counter_val[SGE_NCOUNTERS];
289 u32 fl_align; /* response queue message alignment */
290 u32 fl_pg_order; /* large page allocation size */
291 u32 fl_starve_thres; /* Free List starvation threshold */
294 #define T4_OS_NEEDS_MBOX_LOCKING 1
297 * OS Lock/List primitives for those interfaces in the Common Code which
302 TAILQ_ENTRY(mbox_entry) next;
305 TAILQ_HEAD(mbox_list, mbox_entry);
308 struct rte_pci_device *pdev; /* associated rte pci device */
309 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
310 struct adapter_params params; /* adapter parameters */
311 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
312 struct sge sge; /* associated SGE */
314 /* support for single-threading access to adapter mailbox registers */
315 struct mbox_list mbox_list;
316 rte_spinlock_t mbox_lock;
318 u8 *regs; /* pointer to registers region */
319 u8 *bar2; /* pointer to bar2 region */
320 unsigned long flags; /* adapter flags */
321 unsigned int mbox; /* associated mailbox */
322 unsigned int pf; /* associated physical function id */
324 unsigned int vpd_busy;
325 unsigned int vpd_flag;
327 int use_unpacked_mode; /* unpacked rx mode state */
331 * adap2pinfo - return the port_info of a port
333 * @idx: the port index
335 * Return the port_info structure for the port of the given index.
337 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
339 return adap->port[idx];
342 #define CXGBE_PCI_REG(reg) rte_read32(reg)
344 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
346 uint64_t val = CXGBE_PCI_REG(addr);
347 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
349 val2 = (uint64_t)(val2 << 32);
354 static inline uint32_t cxgbe_read_addr(volatile void *addr)
356 return CXGBE_PCI_REG(addr);
359 #define CXGBE_PCI_REG_ADDR(adap, reg) \
360 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
362 #define CXGBE_READ_REG(adap, reg) \
363 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
365 #define CXGBE_READ_REG64(adap, reg) \
366 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
368 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
370 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
371 rte_write32_relaxed((value), (reg))
373 #define CXGBE_WRITE_REG(adap, reg, value) \
374 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
376 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
377 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
379 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
381 CXGBE_PCI_REG_WRITE(addr, val);
382 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
386 #define CXGBE_WRITE_REG64(adap, reg, value) \
387 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
390 * t4_read_reg - read a HW register
391 * @adapter: the adapter
392 * @reg_addr: the register address
394 * Returns the 32-bit value of the given HW register.
396 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
398 u32 val = CXGBE_READ_REG(adapter, reg_addr);
400 CXGBE_DEBUG_REG(adapter, "read register 0x%x value 0x%x\n", reg_addr,
406 * t4_write_reg - write a HW register with barrier
407 * @adapter: the adapter
408 * @reg_addr: the register address
409 * @val: the value to write
411 * Write a 32-bit value into the given HW register.
413 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
415 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
417 CXGBE_WRITE_REG(adapter, reg_addr, val);
421 * t4_write_reg_relaxed - write a HW register with no barrier
422 * @adapter: the adapter
423 * @reg_addr: the register address
424 * @val: the value to write
426 * Write a 32-bit value into the given HW register.
428 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
431 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
433 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
437 * t4_read_reg64 - read a 64-bit HW register
438 * @adapter: the adapter
439 * @reg_addr: the register address
441 * Returns the 64-bit value of the given HW register.
443 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
445 u64 val = CXGBE_READ_REG64(adapter, reg_addr);
447 CXGBE_DEBUG_REG(adapter, "64-bit read register %#x value %#llx\n",
448 reg_addr, (unsigned long long)val);
453 * t4_write_reg64 - write a 64-bit HW register
454 * @adapter: the adapter
455 * @reg_addr: the register address
456 * @val: the value to write
458 * Write a 64-bit value into the given HW register.
460 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
463 CXGBE_DEBUG_REG(adapter, "setting register %#x to %#llx\n", reg_addr,
464 (unsigned long long)val);
466 CXGBE_WRITE_REG64(adapter, reg_addr, val);
469 #define PCI_STATUS 0x06 /* 16 bits */
470 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
471 #define PCI_CAPABILITY_LIST 0x34
472 /* Offset of first capability list entry */
473 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
474 #define PCI_CAP_LIST_ID 0 /* Capability ID */
475 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
476 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
477 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
478 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
479 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
480 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
481 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
482 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
483 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
486 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
487 * @adapter: the adapter
488 * @addr: the register address
489 * @val: the value to write
491 * Write a 32-bit value into the given register in PCI config space.
493 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
498 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
500 dev_err(adapter, "Can't write to PCI config space\n");
504 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
505 * @adapter: the adapter
506 * @addr: the register address
507 * @val: where to store the value read
509 * Read a 32-bit value from the given register in PCI config space.
511 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
514 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
516 dev_err(adapter, "Can't read from PCI config space\n");
520 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
521 * @adapter: the adapter
522 * @addr: the register address
523 * @val: the value to write
525 * Write a 16-bit value into the given register in PCI config space.
527 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
532 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
534 dev_err(adapter, "Can't write to PCI config space\n");
538 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
539 * @adapter: the adapter
540 * @addr: the register address
541 * @val: where to store the value read
543 * Read a 16-bit value from the given register in PCI config space.
545 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
548 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
550 dev_err(adapter, "Can't read from PCI config space\n");
554 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
555 * @adapter: the adapter
556 * @addr: the register address
557 * @val: where to store the value read
559 * Read a 8-bit value from the given register in PCI config space.
561 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
564 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
566 dev_err(adapter, "Can't read from PCI config space\n");
570 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
571 * @adapter: the adapter
572 * @cap: the capability
574 * Return the address of the given capability within the PCI capability list.
576 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
583 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
584 if (!(status & PCI_STATUS_CAP_LIST)) {
585 dev_err(adapter, "PCIe capability reading failed\n");
589 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
590 while (ttl-- && pos >= 0x40) {
592 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
600 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
606 * t4_os_set_hw_addr - store a port's MAC address in SW
607 * @adapter: the adapter
608 * @port_idx: the port index
609 * @hw_addr: the Ethernet address
611 * Store the Ethernet address of the given port in SW. Called by the
612 * common code when it retrieves a port's Ethernet address from EEPROM.
614 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
617 struct port_info *pi = adap2pinfo(adapter, port_idx);
619 ether_addr_copy((struct ether_addr *)hw_addr,
620 &pi->eth_dev->data->mac_addrs[0]);
624 * t4_os_lock_init - initialize spinlock
625 * @lock: the spinlock
627 static inline void t4_os_lock_init(rte_spinlock_t *lock)
629 rte_spinlock_init(lock);
633 * t4_os_lock - spin until lock is acquired
634 * @lock: the spinlock
636 static inline void t4_os_lock(rte_spinlock_t *lock)
638 rte_spinlock_lock(lock);
642 * t4_os_unlock - unlock a spinlock
643 * @lock: the spinlock
645 static inline void t4_os_unlock(rte_spinlock_t *lock)
647 rte_spinlock_unlock(lock);
651 * t4_os_trylock - try to get a lock
652 * @lock: the spinlock
654 static inline int t4_os_trylock(rte_spinlock_t *lock)
656 return rte_spinlock_trylock(lock);
660 * t4_os_init_list_head - initialize
661 * @head: head of list to initialize [to empty]
663 static inline void t4_os_init_list_head(struct mbox_list *head)
668 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
670 return TAILQ_FIRST(head);
674 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
675 * @new: the entry to be addded to the queue
676 * @head: current head of the linked list
677 * @lock: lock to use to guarantee atomicity
679 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
680 struct mbox_list *head,
681 rte_spinlock_t *lock)
684 TAILQ_INSERT_TAIL(head, entry, next);
689 * t4_os_atomic_list_del - Dequeue list element atomically from list
690 * @entry: the entry to be remove/dequeued from the list.
691 * @lock: the spinlock
693 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
694 struct mbox_list *head,
695 rte_spinlock_t *lock)
698 TAILQ_REMOVE(head, entry, next);
702 void *t4_alloc_mem(size_t size);
703 void t4_free_mem(void *addr);
704 #define t4_os_alloc(_size) t4_alloc_mem((_size))
705 #define t4_os_free(_ptr) t4_free_mem((_ptr))
707 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
708 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
710 void reclaim_completed_tx(struct sge_txq *q);
711 void t4_free_sge_resources(struct adapter *adap);
712 void t4_sge_tx_monitor_start(struct adapter *adap);
713 void t4_sge_tx_monitor_stop(struct adapter *adap);
714 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
716 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
717 const struct pkt_gl *gl);
718 int t4_sge_init(struct adapter *adap);
719 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
720 struct rte_eth_dev *eth_dev, uint16_t queue_id,
721 unsigned int iqid, int socket_id);
722 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
723 struct rte_eth_dev *eth_dev, int intr_idx,
724 struct sge_fl *fl, rspq_handler_t handler,
725 int cong, struct rte_mempool *mp, int queue_id,
727 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
728 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
729 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
730 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);
731 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);
732 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
733 void t4_sge_eth_clear_queues(struct port_info *pi);
734 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
736 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
737 unsigned int budget, unsigned int *work_done);
738 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
740 #endif /* __T4_ADAPTER_H__ */