1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 /* This file should not be included directly. Include common.h instead. */
8 #ifndef __T4_ADAPTER_H__
9 #define __T4_ADAPTER_H__
11 #include <rte_bus_pci.h>
15 #include "cxgbe_compat.h"
16 #include "t4_regs_values.h"
19 MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
26 PORT_RSS_DONE = (1 << 0),
30 struct adapter *adapter; /* adapter that this port belongs to */
31 struct rte_eth_dev *eth_dev; /* associated rte eth device */
32 struct port_stats stats_base; /* port statistics base */
33 struct link_config link_cfg; /* link configuration info */
35 unsigned long flags; /* port related flags */
36 short int xact_addr_filt; /* index of exact MAC address filter */
38 u16 viid; /* associated virtual interface id */
39 s8 mdio_addr; /* address of the PHY */
40 u8 port_type; /* firmware port type */
41 u8 mod_type; /* firmware module type */
42 u8 port_id; /* physical port ID */
43 u8 pidx; /* port index for this PF */
44 u8 tx_chan; /* associated channel */
46 u8 n_rx_qsets; /* # of rx qsets */
47 u8 n_tx_qsets; /* # of tx qsets */
48 u8 first_qset; /* index of first qset */
50 u16 *rss; /* rss table */
51 u8 rss_mode; /* rss mode */
52 u16 rss_size; /* size of VI's RSS table slice */
53 u64 rss_hf; /* RSS Hash Function */
56 /* Enable or disable autonegotiation. If this is set to enable,
57 * the forced link modes above are completely ignored.
59 #define AUTONEG_DISABLE 0x00
60 #define AUTONEG_ENABLE 0x01
62 enum { /* adapter flags */
63 FULL_INIT_DONE = (1 << 0),
65 USING_MSIX = (1 << 2),
66 FW_QUEUE_BOUND = (1 << 3),
68 CFG_QUEUES = (1 << 5),
72 struct rx_sw_desc { /* SW state per Rx descriptor */
73 void *buf; /* struct page or mbuf */
77 struct sge_fl { /* SGE free-buffer queue state */
79 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
81 dma_addr_t addr; /* bus address of HW ring start */
82 __be64 *desc; /* address of HW Rx descriptor ring */
84 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
85 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
87 unsigned int cntxt_id; /* SGE relative QID for the free list */
88 unsigned int size; /* capacity of free list */
90 unsigned int avail; /* # of available Rx buffers */
91 unsigned int pend_cred; /* new buffers since last FL DB ring */
92 unsigned int cidx; /* consumer index */
93 unsigned int pidx; /* producer index */
95 unsigned long alloc_failed; /* # of times buffer allocation failed */
96 unsigned long low; /* # of times momentarily starving */
99 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
101 /* A packet gather list */
104 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
106 void *va; /* virtual address of first byte */
107 unsigned int nfrags; /* # of fragments */
108 unsigned int tot_len; /* total length of fragments */
109 bool usembufs; /* use mbufs for fragments */
112 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
113 const struct pkt_gl *gl);
115 struct sge_rspq { /* state for an SGE response queue */
116 struct adapter *adapter; /* adapter that this queue belongs to */
117 struct rte_eth_dev *eth_dev; /* associated rte eth device */
118 struct rte_mempool *mb_pool; /* associated mempool */
120 dma_addr_t phys_addr; /* physical address of the ring */
121 __be64 *desc; /* address of HW response ring */
122 const __be64 *cur_desc; /* current descriptor in queue */
124 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
125 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
126 struct sge_qstat *stat;
128 unsigned int cidx; /* consumer index */
129 unsigned int gts_idx; /* last gts write sent */
130 unsigned int iqe_len; /* entry size */
131 unsigned int size; /* capacity of response queue */
132 int offset; /* offset into current Rx buffer */
134 u8 gen; /* current generation bit */
135 u8 intr_params; /* interrupt holdoff parameters */
136 u8 next_intr_params; /* holdoff params for next interrupt */
137 u8 pktcnt_idx; /* interrupt packet threshold */
138 u8 port_id; /* associated port-id */
139 u8 idx; /* queue index within its group */
140 u16 cntxt_id; /* SGE relative QID for the response Q */
141 u16 abs_id; /* absolute SGE id for the response q */
143 rspq_handler_t handler; /* associated handler for this response q */
146 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
147 u64 pkts; /* # of ethernet packets */
148 u64 rx_bytes; /* # of ethernet bytes */
149 u64 rx_cso; /* # of Rx checksum offloads */
150 u64 vlan_ex; /* # of Rx VLAN extractions */
151 u64 rx_drops; /* # of packets dropped due to no mem */
154 struct sge_eth_rxq { /* a SW Ethernet Rx queue */
155 struct sge_rspq rspq;
157 struct sge_eth_rx_stats stats;
158 bool usembufs; /* one ingress packet per mbuf FL buffer */
159 } __rte_cache_aligned;
162 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
163 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
164 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
165 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
166 * to be able to free those mbufs when we get completions back from the FW.
167 * Allocating the maximum number of pointers in every tx desc is a waste
168 * of memory resources so we only store 2 pointers per tx desc which should
169 * be enough since a tx desc can only fit 2 packets in the best case
170 * scenario where a packet needs 32 bytes.
172 #define ETH_COALESCE_PKT_NUM 15
173 #define ETH_COALESCE_VF_PKT_NUM 7
174 #define ETH_COALESCE_PKT_PER_DESC 2
176 struct tx_eth_coal_desc {
177 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
178 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
186 struct tx_sw_desc { /* SW state per Tx descriptor */
187 struct rte_mbuf *mbuf;
188 struct ulptx_sgl *sgl;
189 struct tx_eth_coal_desc coalesce;
193 EQ_STOPPED = (1 << 0),
196 struct eth_coalesce {
203 __u8 ethmacdst[ETHER_ADDR_LEN];
204 __u8 ethmacsrc[ETHER_ADDR_LEN];
210 struct tx_desc *desc; /* address of HW Tx descriptor ring */
211 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
212 struct sge_qstat *stat; /* queue status entry */
213 struct eth_coalesce coalesce; /* coalesce info */
215 uint64_t phys_addr; /* physical address of the ring */
217 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
218 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
220 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
221 unsigned int in_use; /* # of in-use Tx descriptors */
222 unsigned int size; /* # of descriptors */
223 unsigned int cidx; /* SW consumer index */
224 unsigned int pidx; /* producer index */
225 unsigned int dbidx; /* last idx when db ring was done */
226 unsigned int equeidx; /* last sent credit request */
227 unsigned int last_pidx; /* last pidx recorded by tx monitor */
228 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
231 int db_disabled; /* doorbell state */
232 unsigned short db_pidx; /* doorbell producer index */
233 unsigned short db_pidx_inc; /* doorbell producer increment */
236 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
237 u64 pkts; /* # of ethernet packets */
238 u64 tx_bytes; /* # of ethernet bytes */
239 u64 tso; /* # of TSO requests */
240 u64 tx_cso; /* # of Tx checksum offloads */
241 u64 vlan_ins; /* # of Tx VLAN insertions */
242 u64 mapping_err; /* # of I/O MMU packet mapping errors */
243 u64 coal_wr; /* # of coalesced wr */
244 u64 coal_pkts; /* # of coalesced packets */
247 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
249 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
250 struct rte_eth_dev_data *data;
251 struct sge_eth_tx_stats stats; /* queue statistics */
252 rte_spinlock_t txq_lock;
254 unsigned int flags; /* flags for state of the queue */
255 } __rte_cache_aligned;
258 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
259 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
260 struct sge_rspq fw_evtq __rte_cache_aligned;
262 u16 max_ethqsets; /* # of available Ethernet queue sets */
263 u32 stat_len; /* length of status page at ring end */
264 u32 pktshift; /* padding between CPL & packet data */
266 /* response queue interrupt parameters */
267 u16 timer_val[SGE_NTIMERS];
268 u8 counter_val[SGE_NCOUNTERS];
270 u32 fl_align; /* response queue message alignment */
271 u32 fl_pg_order; /* large page allocation size */
272 u32 fl_starve_thres; /* Free List starvation threshold */
275 #define T4_OS_NEEDS_MBOX_LOCKING 1
278 * OS Lock/List primitives for those interfaces in the Common Code which
283 TAILQ_ENTRY(mbox_entry) next;
286 TAILQ_HEAD(mbox_list, mbox_entry);
289 struct rte_pci_device *pdev; /* associated rte pci device */
290 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
291 struct adapter_params params; /* adapter parameters */
292 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
293 struct sge sge; /* associated SGE */
295 /* support for single-threading access to adapter mailbox registers */
296 struct mbox_list mbox_list;
297 rte_spinlock_t mbox_lock;
299 u8 *regs; /* pointer to registers region */
300 u8 *bar2; /* pointer to bar2 region */
301 unsigned long flags; /* adapter flags */
302 unsigned int mbox; /* associated mailbox */
303 unsigned int pf; /* associated physical function id */
305 unsigned int vpd_busy;
306 unsigned int vpd_flag;
308 int use_unpacked_mode; /* unpacked rx mode state */
312 * adap2pinfo - return the port_info of a port
314 * @idx: the port index
316 * Return the port_info structure for the port of the given index.
318 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
320 return adap->port[idx];
323 #define CXGBE_PCI_REG(reg) rte_read32(reg)
325 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
327 uint64_t val = CXGBE_PCI_REG(addr);
328 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
330 val2 = (uint64_t)(val2 << 32);
335 static inline uint32_t cxgbe_read_addr(volatile void *addr)
337 return CXGBE_PCI_REG(addr);
340 #define CXGBE_PCI_REG_ADDR(adap, reg) \
341 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
343 #define CXGBE_READ_REG(adap, reg) \
344 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
346 #define CXGBE_READ_REG64(adap, reg) \
347 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
349 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
351 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
352 rte_write32_relaxed((value), (reg))
354 #define CXGBE_WRITE_REG(adap, reg, value) \
355 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
357 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
358 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
360 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
362 CXGBE_PCI_REG_WRITE(addr, val);
363 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
367 #define CXGBE_WRITE_REG64(adap, reg, value) \
368 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
371 * t4_read_reg - read a HW register
372 * @adapter: the adapter
373 * @reg_addr: the register address
375 * Returns the 32-bit value of the given HW register.
377 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
379 u32 val = CXGBE_READ_REG(adapter, reg_addr);
381 CXGBE_DEBUG_REG(adapter, "read register 0x%x value 0x%x\n", reg_addr,
387 * t4_write_reg - write a HW register with barrier
388 * @adapter: the adapter
389 * @reg_addr: the register address
390 * @val: the value to write
392 * Write a 32-bit value into the given HW register.
394 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
396 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
398 CXGBE_WRITE_REG(adapter, reg_addr, val);
402 * t4_write_reg_relaxed - write a HW register with no barrier
403 * @adapter: the adapter
404 * @reg_addr: the register address
405 * @val: the value to write
407 * Write a 32-bit value into the given HW register.
409 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
412 CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
414 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
418 * t4_read_reg64 - read a 64-bit HW register
419 * @adapter: the adapter
420 * @reg_addr: the register address
422 * Returns the 64-bit value of the given HW register.
424 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
426 u64 val = CXGBE_READ_REG64(adapter, reg_addr);
428 CXGBE_DEBUG_REG(adapter, "64-bit read register %#x value %#llx\n",
429 reg_addr, (unsigned long long)val);
434 * t4_write_reg64 - write a 64-bit HW register
435 * @adapter: the adapter
436 * @reg_addr: the register address
437 * @val: the value to write
439 * Write a 64-bit value into the given HW register.
441 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
444 CXGBE_DEBUG_REG(adapter, "setting register %#x to %#llx\n", reg_addr,
445 (unsigned long long)val);
447 CXGBE_WRITE_REG64(adapter, reg_addr, val);
450 #define PCI_STATUS 0x06 /* 16 bits */
451 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
452 #define PCI_CAPABILITY_LIST 0x34
453 /* Offset of first capability list entry */
454 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
455 #define PCI_CAP_LIST_ID 0 /* Capability ID */
456 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
457 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
458 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
459 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
460 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
461 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
462 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
463 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
464 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
467 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
468 * @adapter: the adapter
469 * @addr: the register address
470 * @val: the value to write
472 * Write a 32-bit value into the given register in PCI config space.
474 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
479 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
481 dev_err(adapter, "Can't write to PCI config space\n");
485 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
486 * @adapter: the adapter
487 * @addr: the register address
488 * @val: where to store the value read
490 * Read a 32-bit value from the given register in PCI config space.
492 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
495 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
497 dev_err(adapter, "Can't read from PCI config space\n");
501 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
502 * @adapter: the adapter
503 * @addr: the register address
504 * @val: the value to write
506 * Write a 16-bit value into the given register in PCI config space.
508 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
513 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
515 dev_err(adapter, "Can't write to PCI config space\n");
519 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
520 * @adapter: the adapter
521 * @addr: the register address
522 * @val: where to store the value read
524 * Read a 16-bit value from the given register in PCI config space.
526 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
529 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
531 dev_err(adapter, "Can't read from PCI config space\n");
535 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
536 * @adapter: the adapter
537 * @addr: the register address
538 * @val: where to store the value read
540 * Read a 8-bit value from the given register in PCI config space.
542 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
545 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
547 dev_err(adapter, "Can't read from PCI config space\n");
551 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
552 * @adapter: the adapter
553 * @cap: the capability
555 * Return the address of the given capability within the PCI capability list.
557 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
564 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
565 if (!(status & PCI_STATUS_CAP_LIST)) {
566 dev_err(adapter, "PCIe capability reading failed\n");
570 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
571 while (ttl-- && pos >= 0x40) {
573 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
581 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
587 * t4_os_set_hw_addr - store a port's MAC address in SW
588 * @adapter: the adapter
589 * @port_idx: the port index
590 * @hw_addr: the Ethernet address
592 * Store the Ethernet address of the given port in SW. Called by the
593 * common code when it retrieves a port's Ethernet address from EEPROM.
595 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
598 struct port_info *pi = adap2pinfo(adapter, port_idx);
600 ether_addr_copy((struct ether_addr *)hw_addr,
601 &pi->eth_dev->data->mac_addrs[0]);
605 * t4_os_lock_init - initialize spinlock
606 * @lock: the spinlock
608 static inline void t4_os_lock_init(rte_spinlock_t *lock)
610 rte_spinlock_init(lock);
614 * t4_os_lock - spin until lock is acquired
615 * @lock: the spinlock
617 static inline void t4_os_lock(rte_spinlock_t *lock)
619 rte_spinlock_lock(lock);
623 * t4_os_unlock - unlock a spinlock
624 * @lock: the spinlock
626 static inline void t4_os_unlock(rte_spinlock_t *lock)
628 rte_spinlock_unlock(lock);
632 * t4_os_trylock - try to get a lock
633 * @lock: the spinlock
635 static inline int t4_os_trylock(rte_spinlock_t *lock)
637 return rte_spinlock_trylock(lock);
641 * t4_os_init_list_head - initialize
642 * @head: head of list to initialize [to empty]
644 static inline void t4_os_init_list_head(struct mbox_list *head)
649 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
651 return TAILQ_FIRST(head);
655 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
656 * @new: the entry to be addded to the queue
657 * @head: current head of the linked list
658 * @lock: lock to use to guarantee atomicity
660 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
661 struct mbox_list *head,
662 rte_spinlock_t *lock)
665 TAILQ_INSERT_TAIL(head, entry, next);
670 * t4_os_atomic_list_del - Dequeue list element atomically from list
671 * @entry: the entry to be remove/dequeued from the list.
672 * @lock: the spinlock
674 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
675 struct mbox_list *head,
676 rte_spinlock_t *lock)
679 TAILQ_REMOVE(head, entry, next);
683 void *t4_alloc_mem(size_t size);
684 void t4_free_mem(void *addr);
685 #define t4_os_alloc(_size) t4_alloc_mem((_size))
686 #define t4_os_free(_ptr) t4_free_mem((_ptr))
688 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
689 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
691 void reclaim_completed_tx(struct sge_txq *q);
692 void t4_free_sge_resources(struct adapter *adap);
693 void t4_sge_tx_monitor_start(struct adapter *adap);
694 void t4_sge_tx_monitor_stop(struct adapter *adap);
695 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
697 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
698 const struct pkt_gl *gl);
699 int t4_sge_init(struct adapter *adap);
700 int t4vf_sge_init(struct adapter *adap);
701 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
702 struct rte_eth_dev *eth_dev, uint16_t queue_id,
703 unsigned int iqid, int socket_id);
704 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
705 struct rte_eth_dev *eth_dev, int intr_idx,
706 struct sge_fl *fl, rspq_handler_t handler,
707 int cong, struct rte_mempool *mp, int queue_id,
709 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
710 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
711 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
712 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);
713 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);
714 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
715 void t4_sge_eth_clear_queues(struct port_info *pi);
716 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
718 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
719 unsigned int budget, unsigned int *work_done);
720 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);
721 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);
723 #endif /* __T4_ADAPTER_H__ */