1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef __CHELSIO_COMMON_H
7 #define __CHELSIO_COMMON_H
9 #include "cxgbe_compat.h"
12 #include "t4_chip_type.h"
13 #include "t4fw_interface.h"
19 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K
22 MAX_NPORTS = 4, /* max # of ports */
26 T5_REGMAP_SIZE = (332 * 1024),
30 MEMWIN0_APERTURE = 2048,
31 MEMWIN0_BASE = 0x1b800,
34 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
36 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
41 PAUSE_AUTONEG = 1 << 2
45 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
46 FEC_RS = 1 << 1, /* Reed-Solomon */
47 FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */
51 u64 tx_octets; /* total # of octets in good frames */
52 u64 tx_frames; /* all good frames */
53 u64 tx_bcast_frames; /* all broadcast frames */
54 u64 tx_mcast_frames; /* all multicast frames */
55 u64 tx_ucast_frames; /* all unicast frames */
56 u64 tx_error_frames; /* all error frames */
58 u64 tx_frames_64; /* # of Tx frames in a particular range */
60 u64 tx_frames_128_255;
61 u64 tx_frames_256_511;
62 u64 tx_frames_512_1023;
63 u64 tx_frames_1024_1518;
64 u64 tx_frames_1519_max;
66 u64 tx_drop; /* # of dropped Tx frames */
67 u64 tx_pause; /* # of transmitted pause frames */
68 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
69 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
70 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
71 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
72 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
73 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
74 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
75 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
77 u64 rx_octets; /* total # of octets in good frames */
78 u64 rx_frames; /* all good frames */
79 u64 rx_bcast_frames; /* all broadcast frames */
80 u64 rx_mcast_frames; /* all multicast frames */
81 u64 rx_ucast_frames; /* all unicast frames */
82 u64 rx_too_long; /* # of frames exceeding MTU */
83 u64 rx_jabber; /* # of jabber frames */
84 u64 rx_fcs_err; /* # of received frames with bad FCS */
85 u64 rx_len_err; /* # of received frames with length error */
86 u64 rx_symbol_err; /* symbol errors */
87 u64 rx_runt; /* # of short frames */
89 u64 rx_frames_64; /* # of Rx frames in a particular range */
91 u64 rx_frames_128_255;
92 u64 rx_frames_256_511;
93 u64 rx_frames_512_1023;
94 u64 rx_frames_1024_1518;
95 u64 rx_frames_1519_max;
97 u64 rx_pause; /* # of received pause frames */
98 u64 rx_ppp0; /* # of received PPP prio 0 frames */
99 u64 rx_ppp1; /* # of received PPP prio 1 frames */
100 u64 rx_ppp2; /* # of received PPP prio 2 frames */
101 u64 rx_ppp3; /* # of received PPP prio 3 frames */
102 u64 rx_ppp4; /* # of received PPP prio 4 frames */
103 u64 rx_ppp5; /* # of received PPP prio 5 frames */
104 u64 rx_ppp6; /* # of received PPP prio 6 frames */
105 u64 rx_ppp7; /* # of received PPP prio 7 frames */
107 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
108 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
109 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
110 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
111 u64 rx_trunc0; /* buffer-group 0 truncated packets */
112 u64 rx_trunc1; /* buffer-group 1 truncated packets */
113 u64 rx_trunc2; /* buffer-group 2 truncated packets */
114 u64 rx_trunc3; /* buffer-group 3 truncated packets */
118 u32 hps; /* host page size for our PF/VF */
119 u32 eq_qpp; /* egress queues/page for our PF/VF */
120 u32 iq_qpp; /* egress queues/page for our PF/VF */
124 unsigned int ntxchan; /* # of Tx channels */
125 unsigned int tre; /* log2 of core clocks per TP tick */
126 unsigned int dack_re; /* DACK timer resolution */
127 unsigned int la_mask; /* what events are recorded by TP LA */
128 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
130 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
131 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
133 /* cached TP_OUT_CONFIG compressed error vector
134 * and passing outer header info for encapsulated packets.
139 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
140 * subset of the set of fields which may be present in the Compressed
141 * Filter Tuple portion of filters and TCP TCB connections. The
142 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
143 * Since a variable number of fields may or may not be present, their
144 * shifted field positions within the Compressed Filter Tuple may
145 * vary, or not even be present if the field isn't selected in
146 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
147 * places we store their offsets here, or a -1 if the field isn't
163 uint32_t vpd_cap_addr;
169 * Firmware device log.
171 struct devlog_params {
172 u32 memtype; /* which memory (EDC0, EDC1, MC) */
173 u32 start; /* start of log in firmware memory */
174 u32 size; /* size of log */
177 struct arch_specific_params {
186 * Global Receive Side Scaling (RSS) parameters in host-native format.
189 unsigned int mode; /* RSS mode */
192 uint synmapen:1; /* SYN Map Enable */
193 uint syn4tupenipv6:1; /* en 4-tuple IPv6 SYNs hash */
194 uint syn2tupenipv6:1; /* en 2-tuple IPv6 SYNs hash */
195 uint syn4tupenipv4:1; /* en 4-tuple IPv4 SYNs hash */
196 uint syn2tupenipv4:1; /* en 2-tuple IPv4 SYNs hash */
197 uint ofdmapen:1; /* Offload Map Enable */
198 uint tnlmapen:1; /* Tunnel Map Enable */
199 uint tnlalllookup:1; /* Tunnel All Lookup */
200 uint hashtoeplitz:1; /* use Toeplitz hash */
206 * Maximum resources provisioned for a PCI VF.
208 struct vf_resources {
209 unsigned int nvi; /* N virtual interfaces */
210 unsigned int neq; /* N egress Qs */
211 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
212 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
213 unsigned int niq; /* N ingress Qs */
214 unsigned int tc; /* PCI-E traffic class */
215 unsigned int pmask; /* port access rights mask */
216 unsigned int nexactf; /* N exact MPS filters */
217 unsigned int r_caps; /* read capabilities */
218 unsigned int wx_caps; /* write/execute capabilities */
221 struct adapter_params {
222 struct sge_params sge;
224 struct vpd_params vpd;
225 struct pci_params pci;
226 struct devlog_params devlog;
227 struct rss_params rss;
228 struct vf_resources vfres;
229 enum pcie_memwin drv_memwin;
231 unsigned int sf_size; /* serial flash size in bytes */
232 unsigned int sf_nsec; /* # of flash sectors */
234 unsigned int fw_vers;
235 unsigned int bs_vers;
236 unsigned int tp_vers;
237 unsigned int er_vers;
239 unsigned short mtus[NMTUS];
240 unsigned short a_wnd[NCCTRL_WIN];
241 unsigned short b_wnd[NCCTRL_WIN];
243 unsigned int mc_size; /* MC memory size */
244 unsigned int cim_la_size;
246 unsigned char nports; /* # of ethernet ports */
247 unsigned char portvec;
249 enum chip_type chip; /* chip code */
250 struct arch_specific_params arch; /* chip specific params */
252 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
253 u8 fw_caps_support; /* 32-bit Port Capabilities */
256 /* Firmware Port Capabilities types.
258 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
259 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
262 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
263 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
264 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
268 fw_port_cap32_t pcaps; /* link capabilities */
269 fw_port_cap32_t acaps; /* advertised capabilities */
271 u32 requested_speed; /* speed (Mb/s) user has requested */
272 u32 speed; /* actual link speed (Mb/s) */
274 enum cc_pause requested_fc; /* flow control user has requested */
275 enum cc_pause fc; /* actual link flow control */
277 enum cc_fec auto_fec; /* Forward Error Correction
278 * "automatic" (IEEE 802.3)
280 enum cc_fec requested_fec; /* Forward Error Correction requested */
281 enum cc_fec fec; /* Forward Error Correction actual */
283 unsigned char autoneg; /* autonegotiating? */
285 unsigned char link_ok; /* link up? */
286 unsigned char link_down_rc; /* link down reason */
291 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
293 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
295 int attempts, int delay, u32 *valp);
297 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
298 int polarity, int attempts, int delay)
300 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
304 static inline int is_pf4(struct adapter *adap)
306 return adap->pf == 4;
309 #define for_each_port(adapter, iter) \
310 for (iter = 0; iter < (adapter)->params.nports; ++iter)
312 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
313 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
314 unsigned int mask, unsigned int val);
315 void t4_intr_enable(struct adapter *adapter);
316 void t4_intr_disable(struct adapter *adapter);
317 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
318 struct link_config *lc);
319 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
320 const unsigned short *alpha, const unsigned short *beta);
321 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
322 enum dev_master master, enum dev_state *state);
323 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
324 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
325 int t4vf_fw_reset(struct adapter *adap);
326 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
327 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
328 int t4_fl_pkt_align(struct adapter *adap);
329 int t4vf_fl_pkt_align(struct adapter *adap, u32 sge_control, u32 sge_control2);
330 int t4vf_get_vfres(struct adapter *adap);
331 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
332 unsigned int cache_line_size,
333 enum chip_type chip_compat);
334 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
335 unsigned int cache_line_size);
336 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
337 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
338 unsigned int vf, unsigned int nparams, const u32 *params,
340 int t4vf_query_params(struct adapter *adap, unsigned int nparams,
341 const u32 *params, u32 *vals);
342 int t4vf_get_dev_params(struct adapter *adap);
343 int t4vf_get_vpd_params(struct adapter *adap);
344 int t4vf_get_rss_glb_config(struct adapter *adap);
345 int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
346 const u32 *params, const u32 *vals);
347 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
348 unsigned int pf, unsigned int vf,
349 unsigned int nparams, const u32 *params,
350 const u32 *val, int timeout);
351 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
352 unsigned int vf, unsigned int nparams, const u32 *params,
354 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
355 unsigned int port, unsigned int pf, unsigned int vf,
356 unsigned int nmac, u8 *mac, unsigned int *rss_size,
357 unsigned int portfunc, unsigned int idstype);
358 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
359 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
360 unsigned int *rss_size);
361 int t4_free_vi(struct adapter *adap, unsigned int mbox,
362 unsigned int pf, unsigned int vf,
364 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
365 int mtu, int promisc, int all_multi, int bcast, int vlanex,
367 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
368 int idx, const u8 *addr, bool persist, bool add_smt);
369 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
370 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
371 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
372 bool rx_en, bool tx_en);
373 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
374 unsigned int pf, unsigned int vf, unsigned int iqid,
375 unsigned int fl0id, unsigned int fl1id);
376 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
377 unsigned int vf, unsigned int iqtype, unsigned int iqid,
378 unsigned int fl0id, unsigned int fl1id);
379 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
380 unsigned int vf, unsigned int eqid);
382 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
384 return adap->params.vpd.cclk / 1000;
387 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
390 return (us * adap->params.vpd.cclk) / 1000;
393 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
396 /* add Core Clock / 2 to round ticks to nearest uS */
397 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) /
398 adapter->params.vpd.cclk);
401 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
402 int size, void *rpl, bool sleep_ok, int timeout);
403 int t4_wr_mbox_meat(struct adapter *adap, int mbox,
404 const void __attribute__((__may_alias__)) *cmd, int size,
405 void *rpl, bool sleep_ok);
407 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
408 const void *cmd, int size, void *rpl,
411 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
415 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p);
417 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
420 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
423 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
426 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
429 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);
431 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
434 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
437 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
440 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
444 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
445 unsigned int data_reg, u32 *vals, unsigned int nregs,
446 unsigned int start_idx);
447 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
448 unsigned int data_reg, const u32 *vals,
449 unsigned int nregs, unsigned int start_idx);
451 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
452 int t4_read_flash(struct adapter *adapter, unsigned int addr,
453 unsigned int nwords, u32 *data, int byte_oriented);
454 int t4_flash_cfg_addr(struct adapter *adapter);
455 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx);
456 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx);
457 const char *t4_get_port_type_description(enum fw_port_type port_type);
458 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
459 void t4vf_get_port_stats(struct adapter *adapter, int pidx,
460 struct port_stats *p);
461 void t4_get_port_stats_offset(struct adapter *adap, int idx,
462 struct port_stats *stats,
463 struct port_stats *offset);
464 void t4_clr_port_stats(struct adapter *adap, int idx);
465 void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
466 fw_port_cap32_t acaps);
467 void t4_reset_link_config(struct adapter *adap, int idx);
468 int t4_get_version_info(struct adapter *adapter);
469 void t4_dump_version_info(struct adapter *adapter);
470 int t4_get_flash_params(struct adapter *adapter);
471 int t4_get_chip_type(struct adapter *adap, int ver);
472 int t4_prep_adapter(struct adapter *adapter);
473 int t4vf_prep_adapter(struct adapter *adapter);
474 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
475 int t4vf_port_init(struct adapter *adap);
476 int t4_init_rss_mode(struct adapter *adap, int mbox);
477 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
478 int start, int n, const u16 *rspq, unsigned int nrspq);
479 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
480 unsigned int flags, unsigned int defq);
481 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
482 u64 *flags, unsigned int *defq);
483 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
484 unsigned int start_index, unsigned int rw);
485 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);
486 void t4_read_rss_key(struct adapter *adap, u32 *key);
488 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
489 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
490 unsigned int qtype, u64 *pbar2_qoffset,
491 unsigned int *pbar2_qid);
493 int t4_init_sge_params(struct adapter *adapter);
494 int t4_init_tp_params(struct adapter *adap);
495 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);
496 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
497 unsigned int t4_get_regs_len(struct adapter *adap);
498 unsigned int t4vf_get_pf_from_vf(struct adapter *adap);
499 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
500 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
501 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
502 int t4_seeprom_wp(struct adapter *adapter, int enable);
503 fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
504 #endif /* __CHELSIO_COMMON_H */