1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef __CHELSIO_COMMON_H
7 #define __CHELSIO_COMMON_H
9 #include "../cxgbe_compat.h"
12 #include "t4_chip_type.h"
13 #include "t4fw_interface.h"
19 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K
21 #define T4_MEMORY_WRITE 0
22 #define T4_MEMORY_READ 1
25 MAX_NPORTS = 4, /* max # of ports */
29 T5_REGMAP_SIZE = (332 * 1024),
33 MEMWIN0_APERTURE = 2048,
34 MEMWIN0_BASE = 0x1b800,
37 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
39 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
41 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
44 u64 tx_octets; /* total # of octets in good frames */
45 u64 tx_frames; /* all good frames */
46 u64 tx_bcast_frames; /* all broadcast frames */
47 u64 tx_mcast_frames; /* all multicast frames */
48 u64 tx_ucast_frames; /* all unicast frames */
49 u64 tx_error_frames; /* all error frames */
51 u64 tx_frames_64; /* # of Tx frames in a particular range */
53 u64 tx_frames_128_255;
54 u64 tx_frames_256_511;
55 u64 tx_frames_512_1023;
56 u64 tx_frames_1024_1518;
57 u64 tx_frames_1519_max;
59 u64 tx_drop; /* # of dropped Tx frames */
60 u64 tx_pause; /* # of transmitted pause frames */
61 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
62 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
63 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
64 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
65 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
66 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
67 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
68 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
70 u64 rx_octets; /* total # of octets in good frames */
71 u64 rx_frames; /* all good frames */
72 u64 rx_bcast_frames; /* all broadcast frames */
73 u64 rx_mcast_frames; /* all multicast frames */
74 u64 rx_ucast_frames; /* all unicast frames */
75 u64 rx_too_long; /* # of frames exceeding MTU */
76 u64 rx_jabber; /* # of jabber frames */
77 u64 rx_fcs_err; /* # of received frames with bad FCS */
78 u64 rx_len_err; /* # of received frames with length error */
79 u64 rx_symbol_err; /* symbol errors */
80 u64 rx_runt; /* # of short frames */
82 u64 rx_frames_64; /* # of Rx frames in a particular range */
84 u64 rx_frames_128_255;
85 u64 rx_frames_256_511;
86 u64 rx_frames_512_1023;
87 u64 rx_frames_1024_1518;
88 u64 rx_frames_1519_max;
90 u64 rx_pause; /* # of received pause frames */
91 u64 rx_ppp0; /* # of received PPP prio 0 frames */
92 u64 rx_ppp1; /* # of received PPP prio 1 frames */
93 u64 rx_ppp2; /* # of received PPP prio 2 frames */
94 u64 rx_ppp3; /* # of received PPP prio 3 frames */
95 u64 rx_ppp4; /* # of received PPP prio 4 frames */
96 u64 rx_ppp5; /* # of received PPP prio 5 frames */
97 u64 rx_ppp6; /* # of received PPP prio 6 frames */
98 u64 rx_ppp7; /* # of received PPP prio 7 frames */
100 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
101 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
102 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
103 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
104 u64 rx_trunc0; /* buffer-group 0 truncated packets */
105 u64 rx_trunc1; /* buffer-group 1 truncated packets */
106 u64 rx_trunc2; /* buffer-group 2 truncated packets */
107 u64 rx_trunc3; /* buffer-group 3 truncated packets */
111 u32 hps; /* host page size for our PF/VF */
112 u32 eq_qpp; /* egress queues/page for our PF/VF */
113 u32 iq_qpp; /* egress queues/page for our PF/VF */
117 unsigned int ntxchan; /* # of Tx channels */
118 unsigned int tre; /* log2 of core clocks per TP tick */
119 unsigned int dack_re; /* DACK timer resolution */
120 unsigned int la_mask; /* what events are recorded by TP LA */
121 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
123 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
125 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
127 /* cached TP_OUT_CONFIG compressed error vector
128 * and passing outer header info for encapsulated packets.
133 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
134 * subset of the set of fields which may be present in the Compressed
135 * Filter Tuple portion of filters and TCP TCB connections. The
136 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
137 * Since a variable number of fields may or may not be present, their
138 * shifted field positions within the Compressed Filter Tuple may
139 * vary, or not even be present if the field isn't selected in
140 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
141 * places we store their offsets here, or a -1 if the field isn't
152 u64 hash_filter_mask;
162 uint32_t vpd_cap_addr;
168 * Firmware device log.
170 struct devlog_params {
171 u32 memtype; /* which memory (EDC0, EDC1, MC) */
172 u32 start; /* start of log in firmware memory */
173 u32 size; /* size of log */
176 struct arch_specific_params {
178 u8 cng_ch_bits_log; /* congestion channel map bits width */
186 * Global Receive Side Scaling (RSS) parameters in host-native format.
189 unsigned int mode; /* RSS mode */
192 unsigned int synmapen:1; /* SYN Map Enable */
193 unsigned int syn4tupenipv6:1; /* en 4-tuple IPv6 SYNs hash */
194 unsigned int syn2tupenipv6:1; /* en 2-tuple IPv6 SYNs hash */
195 unsigned int syn4tupenipv4:1; /* en 4-tuple IPv4 SYNs hash */
196 unsigned int syn2tupenipv4:1; /* en 2-tuple IPv4 SYNs hash */
197 unsigned int ofdmapen:1; /* Offload Map Enable */
198 unsigned int tnlmapen:1; /* Tunnel Map Enable */
199 unsigned int tnlalllookup:1; /* Tunnel All Lookup */
200 unsigned int hashtoeplitz:1; /* use Toeplitz hash */
206 * Maximum resources provisioned for a PCI PF.
208 struct pf_resources {
209 unsigned int neq; /* N egress Qs */
210 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
211 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
215 * Maximum resources provisioned for a PCI VF.
217 struct vf_resources {
218 unsigned int nvi; /* N virtual interfaces */
219 unsigned int neq; /* N egress Qs */
220 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
221 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
222 unsigned int niq; /* N ingress Qs */
223 unsigned int tc; /* PCI-E traffic class */
224 unsigned int pmask; /* port access rights mask */
225 unsigned int nexactf; /* N exact MPS filters */
226 unsigned int r_caps; /* read capabilities */
227 unsigned int wx_caps; /* write/execute capabilities */
230 struct adapter_params {
231 struct sge_params sge;
233 struct vpd_params vpd;
234 struct pci_params pci;
235 struct devlog_params devlog;
236 struct rss_params rss;
237 struct pf_resources pfres;
238 struct vf_resources vfres;
239 enum pcie_memwin drv_memwin;
241 unsigned int sf_size; /* serial flash size in bytes */
242 unsigned int sf_nsec; /* # of flash sectors */
244 unsigned int fw_vers;
245 unsigned int bs_vers;
246 unsigned int tp_vers;
247 unsigned int er_vers;
249 unsigned short mtus[NMTUS];
250 unsigned short a_wnd[NCCTRL_WIN];
251 unsigned short b_wnd[NCCTRL_WIN];
253 unsigned int mc_size; /* MC memory size */
254 unsigned int cim_la_size;
256 unsigned char nports; /* # of ethernet ports */
257 unsigned char portvec;
259 unsigned char hash_filter;
261 enum chip_type chip; /* chip code */
262 struct arch_specific_params arch; /* chip specific params */
264 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
265 u8 filter2_wr_support; /* FW support for FILTER2_WR */
266 u32 viid_smt_extn_support:1; /* FW returns vin and smt index */
267 u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */
268 u8 vi_enable_rx; /* FW support for enable/disable VI Rx at runtime */
271 /* Firmware Port Capabilities types.
274 u32 pcaps; /* Physically supported link caps */
275 u32 acaps; /* Advertised link caps */
277 u32 link_caps; /* Current link caps */
278 u32 admin_caps; /* Admin configured link caps */
280 u8 mdio_addr; /* Address of the PHY */
281 u8 port_type; /* Firmware port type */
282 u8 mod_type; /* Firmware module type */
284 u8 link_ok; /* Link up? */
285 u8 link_down_rc; /* Link down reason */
290 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
292 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
294 int attempts, int delay, u32 *valp);
296 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
297 int polarity, int attempts, int delay)
299 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
303 static inline int is_pf4(struct adapter *adap)
305 return adap->pf == 4;
308 #define for_each_port(adapter, iter) \
309 for (iter = 0; iter < (adapter)->params.nports; ++iter)
311 static inline int is_hashfilter(const struct adapter *adap)
313 return adap->params.hash_filter;
316 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
317 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
318 unsigned int mask, unsigned int val);
319 void t4_intr_enable(struct adapter *adapter);
320 void t4_intr_disable(struct adapter *adapter);
321 int t4_link_l1cfg_core(struct port_info *pi, u32 caps, u8 sleep_ok);
322 static inline int t4_link_l1cfg(struct port_info *pi, u32 caps)
324 return t4_link_l1cfg_core(pi, caps, true);
327 static inline int t4_link_l1cfg_ns(struct port_info *pi, u32 caps)
329 return t4_link_l1cfg_core(pi, caps, false);
332 int t4_set_link_speed(struct port_info *pi, u32 speed, u32 *new_caps);
333 int t4_set_link_pause(struct port_info *pi, u8 autoneg, u8 pause_tx,
334 u8 pause_rx, u32 *new_caps);
335 int t4_set_link_fec(struct port_info *pi, u8 fec_rs, u8 fec_baser,
336 u8 fec_none, u32 *new_caps);
337 unsigned int t4_fwcap_to_speed(u32 caps);
338 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
339 const unsigned short *alpha, const unsigned short *beta);
340 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
341 enum dev_master master, enum dev_state *state);
342 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
343 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
344 int t4vf_fw_reset(struct adapter *adap);
345 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
346 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
347 int t4_fl_pkt_align(struct adapter *adap);
348 int t4vf_fl_pkt_align(struct adapter *adap, u32 sge_control, u32 sge_control2);
349 int t4vf_get_vfres(struct adapter *adap);
350 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
351 unsigned int cache_line_size,
352 enum chip_type chip_compat);
353 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
354 unsigned int cache_line_size);
355 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
356 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
357 unsigned int vf, unsigned int nparams, const u32 *params,
359 int t4vf_query_params(struct adapter *adap, unsigned int nparams,
360 const u32 *params, u32 *vals);
361 int t4vf_get_dev_params(struct adapter *adap);
362 int t4vf_get_vpd_params(struct adapter *adap);
363 int t4vf_get_rss_glb_config(struct adapter *adap);
364 int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
365 const u32 *params, const u32 *vals);
366 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
367 unsigned int pf, unsigned int vf,
368 unsigned int nparams, const u32 *params,
369 const u32 *val, int timeout);
370 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
371 unsigned int vf, unsigned int nparams, const u32 *params,
373 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
374 unsigned int port, unsigned int pf, unsigned int vf,
375 unsigned int nmac, u8 *mac, unsigned int *rss_size,
376 unsigned int portfunc, unsigned int idstype,
378 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
379 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
380 unsigned int *rss_size, u8 *vivild, u8 *vin);
381 int t4_free_vi(struct adapter *adap, unsigned int mbox,
382 unsigned int pf, unsigned int vf,
384 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
385 int mtu, int promisc, int all_multi, int bcast, int vlanex,
387 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
388 const u8 *addr, const u8 *mask, unsigned int idx,
389 u8 lookup_type, u8 port_id, bool sleep_ok);
390 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
391 const u8 *addr, const u8 *mask, unsigned int idx,
392 u8 lookup_type, u8 port_id, bool sleep_ok);
393 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
394 int idx, const u8 *addr, bool persist, bool add_smt);
395 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
396 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
397 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
398 bool rx_en, bool tx_en);
399 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
400 unsigned int pf, unsigned int vf, unsigned int iqid,
401 unsigned int fl0id, unsigned int fl1id);
402 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
403 unsigned int vf, unsigned int iqtype, unsigned int iqid,
404 unsigned int fl0id, unsigned int fl1id);
405 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
406 unsigned int vf, unsigned int eqid);
407 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
408 unsigned int vf, unsigned int eqid);
410 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
412 return adap->params.vpd.cclk / 1000;
415 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
418 return (us * adap->params.vpd.cclk) / 1000;
421 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
424 /* add Core Clock / 2 to round ticks to nearest uS */
425 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) /
426 adapter->params.vpd.cclk);
429 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
430 int size, void *rpl, bool sleep_ok, int timeout);
431 int t4_wr_mbox_meat(struct adapter *adap, int mbox,
432 const void __attribute__((__may_alias__)) *cmd, int size,
433 void *rpl, bool sleep_ok);
435 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
436 const void *cmd, int size, void *rpl,
439 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
443 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p);
445 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
448 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
451 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
454 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
457 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);
459 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
462 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
465 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
468 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
472 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
473 unsigned int data_reg, u32 *vals, unsigned int nregs,
474 unsigned int start_idx);
475 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
476 unsigned int data_reg, const u32 *vals,
477 unsigned int nregs, unsigned int start_idx);
479 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
480 int t4_get_pfres(struct adapter *adapter);
481 int t4_read_flash(struct adapter *adapter, unsigned int addr,
482 unsigned int nwords, u32 *data, int byte_oriented);
483 int t4_flash_cfg_addr(struct adapter *adapter);
484 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx);
485 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx);
486 const char *t4_get_port_type_description(enum fw_port_type port_type);
487 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
488 void t4vf_get_port_stats(struct adapter *adapter, int pidx,
489 struct port_stats *p);
490 void t4_get_port_stats_offset(struct adapter *adap, int idx,
491 struct port_stats *stats,
492 struct port_stats *offset);
493 void t4_clr_port_stats(struct adapter *adap, int idx);
494 void t4_init_link_config(struct port_info *pi, u32 pcaps, u32 acaps,
495 u8 mdio_addr, u8 port_type, u8 mod_type);
496 void t4_reset_link_config(struct adapter *adap, int idx);
497 int t4_get_version_info(struct adapter *adapter);
498 void t4_dump_version_info(struct adapter *adapter);
499 int t4_get_flash_params(struct adapter *adapter);
500 int t4_get_chip_type(struct adapter *adap, int ver);
501 int t4_prep_adapter(struct adapter *adapter);
502 int t4vf_prep_adapter(struct adapter *adapter);
503 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
504 int t4vf_port_init(struct adapter *adap);
505 int t4_init_rss_mode(struct adapter *adap, int mbox);
506 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
507 int start, int n, const u16 *rspq, unsigned int nrspq);
508 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
509 unsigned int flags, unsigned int defq);
510 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
511 u64 *flags, unsigned int *defq);
512 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
513 unsigned int start_index, unsigned int rw);
514 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);
515 void t4_read_rss_key(struct adapter *adap, u32 *key);
517 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
518 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
519 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
520 unsigned int *pbar2_qid);
522 int t4_init_sge_params(struct adapter *adapter);
523 int t4_init_tp_params(struct adapter *adap);
524 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);
525 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
526 unsigned int t4_get_regs_len(struct adapter *adap);
527 unsigned int t4vf_get_pf_from_vf(struct adapter *adap);
528 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
529 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
530 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
531 int t4_seeprom_wp(struct adapter *adapter, int enable);
532 int t4_memory_rw_addr(struct adapter *adap, int win,
533 u32 addr, u32 len, void *hbuf, int dir);
534 int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr,
535 u32 len, void *hbuf, int dir);
536 static inline int t4_memory_rw(struct adapter *adap, int win,
537 int mtype, u32 maddr, u32 len,
540 return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir);
542 #endif /* __CHELSIO_COMMON_H */