4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef __CHELSIO_COMMON_H
35 #define __CHELSIO_COMMON_H
37 #include "cxgbe_compat.h"
40 #include "t4_chip_type.h"
41 #include "t4fw_interface.h"
47 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K
50 MAX_NPORTS = 4, /* max # of ports */
54 T5_REGMAP_SIZE = (332 * 1024),
58 MEMWIN0_APERTURE = 2048,
59 MEMWIN0_BASE = 0x1b800,
62 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
64 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
69 PAUSE_AUTONEG = 1 << 2
73 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
74 FEC_RS = 1 << 1, /* Reed-Solomon */
75 FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */
79 u64 tx_octets; /* total # of octets in good frames */
80 u64 tx_frames; /* all good frames */
81 u64 tx_bcast_frames; /* all broadcast frames */
82 u64 tx_mcast_frames; /* all multicast frames */
83 u64 tx_ucast_frames; /* all unicast frames */
84 u64 tx_error_frames; /* all error frames */
86 u64 tx_frames_64; /* # of Tx frames in a particular range */
88 u64 tx_frames_128_255;
89 u64 tx_frames_256_511;
90 u64 tx_frames_512_1023;
91 u64 tx_frames_1024_1518;
92 u64 tx_frames_1519_max;
94 u64 tx_drop; /* # of dropped Tx frames */
95 u64 tx_pause; /* # of transmitted pause frames */
96 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
97 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
98 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
99 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
100 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
101 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
102 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
103 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
105 u64 rx_octets; /* total # of octets in good frames */
106 u64 rx_frames; /* all good frames */
107 u64 rx_bcast_frames; /* all broadcast frames */
108 u64 rx_mcast_frames; /* all multicast frames */
109 u64 rx_ucast_frames; /* all unicast frames */
110 u64 rx_too_long; /* # of frames exceeding MTU */
111 u64 rx_jabber; /* # of jabber frames */
112 u64 rx_fcs_err; /* # of received frames with bad FCS */
113 u64 rx_len_err; /* # of received frames with length error */
114 u64 rx_symbol_err; /* symbol errors */
115 u64 rx_runt; /* # of short frames */
117 u64 rx_frames_64; /* # of Rx frames in a particular range */
118 u64 rx_frames_65_127;
119 u64 rx_frames_128_255;
120 u64 rx_frames_256_511;
121 u64 rx_frames_512_1023;
122 u64 rx_frames_1024_1518;
123 u64 rx_frames_1519_max;
125 u64 rx_pause; /* # of received pause frames */
126 u64 rx_ppp0; /* # of received PPP prio 0 frames */
127 u64 rx_ppp1; /* # of received PPP prio 1 frames */
128 u64 rx_ppp2; /* # of received PPP prio 2 frames */
129 u64 rx_ppp3; /* # of received PPP prio 3 frames */
130 u64 rx_ppp4; /* # of received PPP prio 4 frames */
131 u64 rx_ppp5; /* # of received PPP prio 5 frames */
132 u64 rx_ppp6; /* # of received PPP prio 6 frames */
133 u64 rx_ppp7; /* # of received PPP prio 7 frames */
135 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
136 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
137 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
138 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
139 u64 rx_trunc0; /* buffer-group 0 truncated packets */
140 u64 rx_trunc1; /* buffer-group 1 truncated packets */
141 u64 rx_trunc2; /* buffer-group 2 truncated packets */
142 u64 rx_trunc3; /* buffer-group 3 truncated packets */
146 u32 hps; /* host page size for our PF/VF */
147 u32 eq_qpp; /* egress queues/page for our PF/VF */
148 u32 iq_qpp; /* egress queues/page for our PF/VF */
152 unsigned int ntxchan; /* # of Tx channels */
153 unsigned int tre; /* log2 of core clocks per TP tick */
154 unsigned int dack_re; /* DACK timer resolution */
155 unsigned int la_mask; /* what events are recorded by TP LA */
156 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
158 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
159 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
161 /* cached TP_OUT_CONFIG compressed error vector
162 * and passing outer header info for encapsulated packets.
167 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
168 * subset of the set of fields which may be present in the Compressed
169 * Filter Tuple portion of filters and TCP TCB connections. The
170 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
171 * Since a variable number of fields may or may not be present, their
172 * shifted field positions within the Compressed Filter Tuple may
173 * vary, or not even be present if the field isn't selected in
174 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
175 * places we store their offsets here, or a -1 if the field isn't
191 uint32_t vpd_cap_addr;
197 * Firmware device log.
199 struct devlog_params {
200 u32 memtype; /* which memory (EDC0, EDC1, MC) */
201 u32 start; /* start of log in firmware memory */
202 u32 size; /* size of log */
205 struct arch_specific_params {
214 * Global Receive Side Scaling (RSS) parameters in host-native format.
217 unsigned int mode; /* RSS mode */
220 uint synmapen:1; /* SYN Map Enable */
221 uint syn4tupenipv6:1; /* en 4-tuple IPv6 SYNs hash */
222 uint syn2tupenipv6:1; /* en 2-tuple IPv6 SYNs hash */
223 uint syn4tupenipv4:1; /* en 4-tuple IPv4 SYNs hash */
224 uint syn2tupenipv4:1; /* en 2-tuple IPv4 SYNs hash */
225 uint ofdmapen:1; /* Offload Map Enable */
226 uint tnlmapen:1; /* Tunnel Map Enable */
227 uint tnlalllookup:1; /* Tunnel All Lookup */
228 uint hashtoeplitz:1; /* use Toeplitz hash */
234 * Maximum resources provisioned for a PCI VF.
236 struct vf_resources {
237 unsigned int nvi; /* N virtual interfaces */
238 unsigned int neq; /* N egress Qs */
239 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
240 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
241 unsigned int niq; /* N ingress Qs */
242 unsigned int tc; /* PCI-E traffic class */
243 unsigned int pmask; /* port access rights mask */
244 unsigned int nexactf; /* N exact MPS filters */
245 unsigned int r_caps; /* read capabilities */
246 unsigned int wx_caps; /* write/execute capabilities */
249 struct adapter_params {
250 struct sge_params sge;
252 struct vpd_params vpd;
253 struct pci_params pci;
254 struct devlog_params devlog;
255 struct rss_params rss;
256 struct vf_resources vfres;
257 enum pcie_memwin drv_memwin;
259 unsigned int sf_size; /* serial flash size in bytes */
260 unsigned int sf_nsec; /* # of flash sectors */
262 unsigned int fw_vers;
263 unsigned int bs_vers;
264 unsigned int tp_vers;
265 unsigned int er_vers;
267 unsigned short mtus[NMTUS];
268 unsigned short a_wnd[NCCTRL_WIN];
269 unsigned short b_wnd[NCCTRL_WIN];
271 unsigned int mc_size; /* MC memory size */
272 unsigned int cim_la_size;
274 unsigned char nports; /* # of ethernet ports */
275 unsigned char portvec;
277 enum chip_type chip; /* chip code */
278 struct arch_specific_params arch; /* chip specific params */
280 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
281 u8 fw_caps_support; /* 32-bit Port Capabilities */
284 /* Firmware Port Capabilities types.
286 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
287 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
290 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
291 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
292 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
296 fw_port_cap32_t pcaps; /* link capabilities */
297 fw_port_cap32_t acaps; /* advertised capabilities */
299 u32 requested_speed; /* speed (Mb/s) user has requested */
300 u32 speed; /* actual link speed (Mb/s) */
302 enum cc_pause requested_fc; /* flow control user has requested */
303 enum cc_pause fc; /* actual link flow control */
305 enum cc_fec auto_fec; /* Forward Error Correction
306 * "automatic" (IEEE 802.3)
308 enum cc_fec requested_fec; /* Forward Error Correction requested */
309 enum cc_fec fec; /* Forward Error Correction actual */
311 unsigned char autoneg; /* autonegotiating? */
313 unsigned char link_ok; /* link up? */
314 unsigned char link_down_rc; /* link down reason */
319 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
321 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
323 int attempts, int delay, u32 *valp);
325 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
326 int polarity, int attempts, int delay)
328 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
332 static inline int is_pf4(struct adapter *adap)
334 return adap->pf == 4;
337 #define for_each_port(adapter, iter) \
338 for (iter = 0; iter < (adapter)->params.nports; ++iter)
340 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
341 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
342 unsigned int mask, unsigned int val);
343 void t4_intr_enable(struct adapter *adapter);
344 void t4_intr_disable(struct adapter *adapter);
345 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
346 struct link_config *lc);
347 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
348 const unsigned short *alpha, const unsigned short *beta);
349 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
350 enum dev_master master, enum dev_state *state);
351 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
352 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
353 int t4vf_fw_reset(struct adapter *adap);
354 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
355 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
356 int t4_fl_pkt_align(struct adapter *adap);
357 int t4vf_fl_pkt_align(struct adapter *adap, u32 sge_control, u32 sge_control2);
358 int t4vf_get_vfres(struct adapter *adap);
359 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
360 unsigned int cache_line_size,
361 enum chip_type chip_compat);
362 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
363 unsigned int cache_line_size);
364 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
365 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
366 unsigned int vf, unsigned int nparams, const u32 *params,
368 int t4vf_query_params(struct adapter *adap, unsigned int nparams,
369 const u32 *params, u32 *vals);
370 int t4vf_get_dev_params(struct adapter *adap);
371 int t4vf_get_vpd_params(struct adapter *adap);
372 int t4vf_get_rss_glb_config(struct adapter *adap);
373 int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
374 const u32 *params, const u32 *vals);
375 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
376 unsigned int pf, unsigned int vf,
377 unsigned int nparams, const u32 *params,
378 const u32 *val, int timeout);
379 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
380 unsigned int vf, unsigned int nparams, const u32 *params,
382 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
383 unsigned int port, unsigned int pf, unsigned int vf,
384 unsigned int nmac, u8 *mac, unsigned int *rss_size,
385 unsigned int portfunc, unsigned int idstype);
386 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
387 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
388 unsigned int *rss_size);
389 int t4_free_vi(struct adapter *adap, unsigned int mbox,
390 unsigned int pf, unsigned int vf,
392 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
393 int mtu, int promisc, int all_multi, int bcast, int vlanex,
395 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
396 int idx, const u8 *addr, bool persist, bool add_smt);
397 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
398 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
399 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
400 bool rx_en, bool tx_en);
401 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
402 unsigned int pf, unsigned int vf, unsigned int iqid,
403 unsigned int fl0id, unsigned int fl1id);
404 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
405 unsigned int vf, unsigned int iqtype, unsigned int iqid,
406 unsigned int fl0id, unsigned int fl1id);
407 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
408 unsigned int vf, unsigned int eqid);
410 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
412 return adap->params.vpd.cclk / 1000;
415 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
418 return (us * adap->params.vpd.cclk) / 1000;
421 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
424 /* add Core Clock / 2 to round ticks to nearest uS */
425 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) /
426 adapter->params.vpd.cclk);
429 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
430 int size, void *rpl, bool sleep_ok, int timeout);
431 int t4_wr_mbox_meat(struct adapter *adap, int mbox,
432 const void __attribute__((__may_alias__)) *cmd, int size,
433 void *rpl, bool sleep_ok);
435 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
436 const void *cmd, int size, void *rpl,
439 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
443 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p);
445 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
448 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
451 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
454 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
457 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);
459 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
462 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
465 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
468 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
472 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
473 unsigned int data_reg, u32 *vals, unsigned int nregs,
474 unsigned int start_idx);
475 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
476 unsigned int data_reg, const u32 *vals,
477 unsigned int nregs, unsigned int start_idx);
479 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
480 int t4_read_flash(struct adapter *adapter, unsigned int addr,
481 unsigned int nwords, u32 *data, int byte_oriented);
482 int t4_flash_cfg_addr(struct adapter *adapter);
483 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx);
484 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx);
485 const char *t4_get_port_type_description(enum fw_port_type port_type);
486 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
487 void t4_get_port_stats_offset(struct adapter *adap, int idx,
488 struct port_stats *stats,
489 struct port_stats *offset);
490 void t4_clr_port_stats(struct adapter *adap, int idx);
491 void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
492 fw_port_cap32_t acaps);
493 void t4_reset_link_config(struct adapter *adap, int idx);
494 int t4_get_version_info(struct adapter *adapter);
495 void t4_dump_version_info(struct adapter *adapter);
496 int t4_get_flash_params(struct adapter *adapter);
497 int t4_get_chip_type(struct adapter *adap, int ver);
498 int t4_prep_adapter(struct adapter *adapter);
499 int t4vf_prep_adapter(struct adapter *adapter);
500 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
501 int t4vf_port_init(struct adapter *adap);
502 int t4_init_rss_mode(struct adapter *adap, int mbox);
503 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
504 int start, int n, const u16 *rspq, unsigned int nrspq);
505 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
506 unsigned int flags, unsigned int defq);
507 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
508 u64 *flags, unsigned int *defq);
509 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
510 unsigned int start_index, unsigned int rw);
511 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);
512 void t4_read_rss_key(struct adapter *adap, u32 *key);
514 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
515 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
516 unsigned int qtype, u64 *pbar2_qoffset,
517 unsigned int *pbar2_qid);
519 int t4_init_sge_params(struct adapter *adapter);
520 int t4_init_tp_params(struct adapter *adap);
521 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);
522 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
523 unsigned int t4_get_regs_len(struct adapter *adap);
524 unsigned int t4vf_get_pf_from_vf(struct adapter *adap);
525 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
526 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
527 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
528 int t4_seeprom_wp(struct adapter *adapter, int enable);
529 fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
530 #endif /* __CHELSIO_COMMON_H */