4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <netinet/in.h>
36 #include <rte_interrupts.h>
38 #include <rte_debug.h>
40 #include <rte_atomic.h>
41 #include <rte_branch_prediction.h>
42 #include <rte_memory.h>
43 #include <rte_memzone.h>
44 #include <rte_tailq.h>
46 #include <rte_alarm.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include <rte_byteorder.h>
56 #include "t4_regs_values.h"
57 #include "t4fw_interface.h"
59 static void init_link_config(struct link_config *lc, unsigned int pcaps,
63 * t4_read_mtu_tbl - returns the values in the HW path MTU table
65 * @mtus: where to store the MTU values
66 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
68 * Reads the HW path MTU table.
70 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
75 for (i = 0; i < NMTUS; ++i) {
76 t4_write_reg(adap, A_TP_MTU_TABLE,
77 V_MTUINDEX(0xff) | V_MTUVALUE(i));
78 v = t4_read_reg(adap, A_TP_MTU_TABLE);
79 mtus[i] = G_MTUVALUE(v);
81 mtu_log[i] = G_MTUWIDTH(v);
86 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
88 * @addr: the indirect TP register address
89 * @mask: specifies the field within the register to modify
90 * @val: new value for the field
92 * Sets a field of an indirect TP register to the given value.
94 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
95 unsigned int mask, unsigned int val)
97 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
98 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
99 t4_write_reg(adap, A_TP_PIO_DATA, val);
102 /* The minimum additive increment value for the congestion control table */
103 #define CC_MIN_INCR 2U
106 * t4_load_mtus - write the MTU and congestion control HW tables
108 * @mtus: the values for the MTU table
109 * @alpha: the values for the congestion control alpha parameter
110 * @beta: the values for the congestion control beta parameter
112 * Write the HW MTU table with the supplied MTUs and the high-speed
113 * congestion control table with the supplied alpha, beta, and MTUs.
114 * We write the two tables together because the additive increments
115 * depend on the MTUs.
117 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
118 const unsigned short *alpha, const unsigned short *beta)
120 static const unsigned int avg_pkts[NCCTRL_WIN] = {
121 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
122 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
123 28672, 40960, 57344, 81920, 114688, 163840, 229376
128 for (i = 0; i < NMTUS; ++i) {
129 unsigned int mtu = mtus[i];
130 unsigned int log2 = cxgbe_fls(mtu);
132 if (!(mtu & ((1 << log2) >> 2))) /* round */
134 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
135 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
137 for (w = 0; w < NCCTRL_WIN; ++w) {
140 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
143 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
144 (w << 16) | (beta[w] << 13) | inc);
150 * t4_wait_op_done_val - wait until an operation is completed
151 * @adapter: the adapter performing the operation
152 * @reg: the register to check for completion
153 * @mask: a single-bit field within @reg that indicates completion
154 * @polarity: the value of the field when the operation is completed
155 * @attempts: number of check iterations
156 * @delay: delay in usecs between iterations
157 * @valp: where to store the value of the register at completion time
159 * Wait until an operation is completed by checking a bit in a register
160 * up to @attempts times. If @valp is not NULL the value of the register
161 * at the time it indicated completion is stored there. Returns 0 if the
162 * operation completes and -EAGAIN otherwise.
164 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
165 int polarity, int attempts, int delay, u32 *valp)
168 u32 val = t4_read_reg(adapter, reg);
170 if (!!(val & mask) == polarity) {
183 * t4_set_reg_field - set a register field to a value
184 * @adapter: the adapter to program
185 * @addr: the register address
186 * @mask: specifies the portion of the register to modify
187 * @val: the new value for the register field
189 * Sets a register field specified by the supplied mask to the
192 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
195 u32 v = t4_read_reg(adapter, addr) & ~mask;
197 t4_write_reg(adapter, addr, v | val);
198 (void)t4_read_reg(adapter, addr); /* flush */
202 * t4_read_indirect - read indirectly addressed registers
204 * @addr_reg: register holding the indirect address
205 * @data_reg: register holding the value of the indirect register
206 * @vals: where the read register values are stored
207 * @nregs: how many indirect registers to read
208 * @start_idx: index of first indirect register to read
210 * Reads registers that are accessed indirectly through an address/data
213 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
214 unsigned int data_reg, u32 *vals, unsigned int nregs,
215 unsigned int start_idx)
218 t4_write_reg(adap, addr_reg, start_idx);
219 *vals++ = t4_read_reg(adap, data_reg);
225 * t4_write_indirect - write indirectly addressed registers
227 * @addr_reg: register holding the indirect addresses
228 * @data_reg: register holding the value for the indirect registers
229 * @vals: values to write
230 * @nregs: how many indirect registers to write
231 * @start_idx: address of first indirect register to write
233 * Writes a sequential block of registers that are accessed indirectly
234 * through an address/data register pair.
236 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
237 unsigned int data_reg, const u32 *vals,
238 unsigned int nregs, unsigned int start_idx)
241 t4_write_reg(adap, addr_reg, start_idx++);
242 t4_write_reg(adap, data_reg, *vals++);
247 * t4_report_fw_error - report firmware error
250 * The adapter firmware can indicate error conditions to the host.
251 * If the firmware has indicated an error, print out the reason for
252 * the firmware error.
254 static void t4_report_fw_error(struct adapter *adap)
256 static const char * const reason[] = {
257 "Crash", /* PCIE_FW_EVAL_CRASH */
258 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
259 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
260 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
261 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
262 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
263 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
264 "Reserved", /* reserved */
268 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
269 if (pcie_fw & F_PCIE_FW_ERR)
270 pr_err("%s: Firmware reports adapter error: %s\n",
271 __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
275 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
277 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
280 for ( ; nflit; nflit--, mbox_addr += 8)
281 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
285 * Handle a FW assertion reported in a mailbox.
287 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
289 struct fw_debug_cmd asrt;
291 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
292 pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
293 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
294 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
297 #define X_CIM_PF_NOACCESS 0xeeeeeeee
300 * If the Host OS Driver needs locking arround accesses to the mailbox, this
301 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
303 /* makes single-statement usage a bit cleaner ... */
304 #ifdef T4_OS_NEEDS_MBOX_LOCKING
305 #define T4_OS_MBOX_LOCKING(x) x
307 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
311 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
313 * @mbox: index of the mailbox to use
314 * @cmd: the command to write
315 * @size: command length in bytes
316 * @rpl: where to optionally store the reply
317 * @sleep_ok: if true we may sleep while awaiting command completion
318 * @timeout: time to wait for command to finish before timing out
319 * (negative implies @sleep_ok=false)
321 * Sends the given command to FW through the selected mailbox and waits
322 * for the FW to execute the command. If @rpl is not %NULL it is used to
323 * store the FW's reply to the command. The command and its optional
324 * reply are of the same length. Some FW commands like RESET and
325 * INITIALIZE can take a considerable amount of time to execute.
326 * @sleep_ok determines whether we may sleep while awaiting the response.
327 * If sleeping is allowed we use progressive backoff otherwise we spin.
328 * Note that passing in a negative @timeout is an alternate mechanism
329 * for specifying @sleep_ok=false. This is useful when a higher level
330 * interface allows for specification of @timeout but not @sleep_ok ...
332 * Returns 0 on success or a negative errno on failure. A
333 * failure can happen either because we are not able to execute the
334 * command or FW executes it but signals an error. In the latter case
335 * the return value is the error code indicated by FW (negated).
337 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
338 const void __attribute__((__may_alias__)) *cmd,
339 int size, void *rpl, bool sleep_ok, int timeout)
342 * We delay in small increments at first in an effort to maintain
343 * responsiveness for simple, fast executing commands but then back
344 * off to larger delays to a maximum retry delay.
346 static const int delay[] = {
347 1, 1, 3, 5, 10, 10, 20, 50, 100
353 unsigned int delay_idx;
354 __be64 *temp = (__be64 *)malloc(size * sizeof(char));
356 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
357 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
359 struct mbox_entry entry;
365 if ((size & 15) || size > MBOX_LEN) {
371 memcpy(p, (const __be64 *)cmd, size);
374 * If we have a negative timeout, that implies that we can't sleep.
381 #ifdef T4_OS_NEEDS_MBOX_LOCKING
383 * Queue ourselves onto the mailbox access list. When our entry is at
384 * the front of the list, we have rights to access the mailbox. So we
385 * wait [for a while] till we're at the front [or bail out with an
388 t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
393 for (i = 0; ; i += ms) {
395 * If we've waited too long, return a busy indication. This
396 * really ought to be based on our initial position in the
397 * mailbox access list but this is a start. We very rarely
398 * contend on access to the mailbox ... Also check for a
399 * firmware error which we'll report as a device error.
401 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
402 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
403 t4_os_atomic_list_del(&entry, &adap->mbox_list,
405 t4_report_fw_error(adap);
407 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
411 * If we're at the head, break out and start the mailbox
414 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
418 * Delay for a bit before checking again ...
421 ms = delay[delay_idx]; /* last element may repeat */
422 if (delay_idx < ARRAY_SIZE(delay) - 1)
429 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
432 * Attempt to gain access to the mailbox.
434 for (i = 0; i < 4; i++) {
435 ctl = t4_read_reg(adap, ctl_reg);
437 if (v != X_MBOWNER_NONE)
442 * If we were unable to gain access, dequeue ourselves from the
443 * mailbox atomic access list and report the error to our caller.
445 if (v != X_MBOWNER_PL) {
446 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
449 t4_report_fw_error(adap);
451 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
455 * If we gain ownership of the mailbox and there's a "valid" message
456 * in it, this is likely an asynchronous error message from the
457 * firmware. So we'll report that and then proceed on with attempting
458 * to issue our own command ... which may well fail if the error
459 * presaged the firmware crashing ...
461 if (ctl & F_MBMSGVALID) {
462 dev_err(adap, "found VALID command in mbox %u: "
463 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
464 (unsigned long long)t4_read_reg64(adap, data_reg),
465 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
466 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
467 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
468 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
469 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
470 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
471 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
475 * Copy in the new mailbox command and send it on its way ...
477 for (i = 0; i < size; i += 8, p++)
478 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
480 CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
481 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
482 (unsigned long long)t4_read_reg64(adap, data_reg),
483 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
484 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
485 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
486 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
487 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
488 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
489 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
491 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
492 t4_read_reg(adap, ctl_reg); /* flush write */
498 * Loop waiting for the reply; bail out if we time out or the firmware
501 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
502 for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
504 ms = delay[delay_idx]; /* last element may repeat */
505 if (delay_idx < ARRAY_SIZE(delay) - 1)
512 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
513 v = t4_read_reg(adap, ctl_reg);
514 if (v == X_CIM_PF_NOACCESS)
516 if (G_MBOWNER(v) == X_MBOWNER_PL) {
517 if (!(v & F_MBMSGVALID)) {
518 t4_write_reg(adap, ctl_reg,
519 V_MBOWNER(X_MBOWNER_NONE));
523 CXGBE_DEBUG_MBOX(adap,
524 "%s: mbox %u: %016llx %016llx %016llx %016llx "
525 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
526 (unsigned long long)t4_read_reg64(adap, data_reg),
527 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
528 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
529 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
530 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
531 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
532 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
533 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
535 CXGBE_DEBUG_MBOX(adap,
536 "command %#x completed in %d ms (%ssleeping)\n",
538 i + ms, sleep_ok ? "" : "non-");
540 res = t4_read_reg64(adap, data_reg);
541 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
542 fw_asrt(adap, data_reg);
543 res = V_FW_CMD_RETVAL(EIO);
545 get_mbox_rpl(adap, rpl, size / 8, data_reg);
547 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
549 t4_os_atomic_list_del(&entry, &adap->mbox_list,
552 return -G_FW_CMD_RETVAL((int)res);
557 * We timed out waiting for a reply to our mailbox command. Report
558 * the error and also check to see if the firmware reported any
561 dev_err(adap, "command %#x in mailbox %d timed out\n",
562 *(const u8 *)cmd, mbox);
563 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
566 t4_report_fw_error(adap);
568 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
571 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
572 void *rpl, bool sleep_ok)
574 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
579 * t4_get_regs_len - return the size of the chips register set
580 * @adapter: the adapter
582 * Returns the size of the chip's BAR0 register space.
584 unsigned int t4_get_regs_len(struct adapter *adapter)
586 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
588 switch (chip_version) {
591 return T5_REGMAP_SIZE;
595 "Unsupported chip version %d\n", chip_version);
600 * t4_get_regs - read chip registers into provided buffer
602 * @buf: register buffer
603 * @buf_size: size (in bytes) of register buffer
605 * If the provided register buffer isn't large enough for the chip's
606 * full register range, the register dump will be truncated to the
607 * register buffer's size.
609 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
611 static const unsigned int t5_reg_ranges[] = {
1386 static const unsigned int t6_reg_ranges[] = {
1947 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1948 const unsigned int *reg_ranges;
1949 int reg_ranges_size, range;
1950 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1952 /* Select the right set of register ranges to dump depending on the
1953 * adapter chip type.
1955 switch (chip_version) {
1957 reg_ranges = t5_reg_ranges;
1958 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1962 reg_ranges = t6_reg_ranges;
1963 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1968 "Unsupported chip version %d\n", chip_version);
1972 /* Clear the register buffer and insert the appropriate register
1973 * values selected by the above register ranges.
1975 memset(buf, 0, buf_size);
1976 for (range = 0; range < reg_ranges_size; range += 2) {
1977 unsigned int reg = reg_ranges[range];
1978 unsigned int last_reg = reg_ranges[range + 1];
1979 u32 *bufp = (u32 *)((char *)buf + reg);
1981 /* Iterate across the register range filling in the register
1982 * buffer but don't write past the end of the register buffer.
1984 while (reg <= last_reg && bufp < buf_end) {
1985 *bufp++ = t4_read_reg(adap, reg);
1991 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1992 #define EEPROM_DELAY 10 /* 10us per poll spin */
1993 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
1995 #define EEPROM_STAT_ADDR 0x7bfc
1998 * Small utility function to wait till any outstanding VPD Access is complete.
1999 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2000 * VPD Access in flight. This allows us to handle the problem of having a
2001 * previous VPD Access time out and prevent an attempt to inject a new VPD
2002 * Request before any in-flight VPD request has completed.
2004 static int t4_seeprom_wait(struct adapter *adapter)
2006 unsigned int base = adapter->params.pci.vpd_cap_addr;
2009 /* If no VPD Access is in flight, we can just return success right
2012 if (!adapter->vpd_busy)
2015 /* Poll the VPD Capability Address/Flag register waiting for it
2016 * to indicate that the operation is complete.
2018 max_poll = EEPROM_MAX_POLL;
2022 udelay(EEPROM_DELAY);
2023 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2025 /* If the operation is complete, mark the VPD as no longer
2026 * busy and return success.
2028 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2029 adapter->vpd_busy = 0;
2032 } while (--max_poll);
2034 /* Failure! Note that we leave the VPD Busy status set in order to
2035 * avoid pushing a new VPD Access request into the VPD Capability till
2036 * the current operation eventually succeeds. It's a bug to issue a
2037 * new request when an existing request is in flight and will result
2038 * in corrupt hardware state.
2044 * t4_seeprom_read - read a serial EEPROM location
2045 * @adapter: adapter to read
2046 * @addr: EEPROM virtual address
2047 * @data: where to store the read data
2049 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2050 * VPD capability. Note that this function must be called with a virtual
2053 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2055 unsigned int base = adapter->params.pci.vpd_cap_addr;
2058 /* VPD Accesses must alway be 4-byte aligned!
2060 if (addr >= EEPROMVSIZE || (addr & 3))
2063 /* Wait for any previous operation which may still be in flight to
2066 ret = t4_seeprom_wait(adapter);
2068 dev_err(adapter, "VPD still busy from previous operation\n");
2072 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2073 * for our request to complete. If it doesn't complete, note the
2074 * error and return it to our caller. Note that we do not reset the
2077 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2078 adapter->vpd_busy = 1;
2079 adapter->vpd_flag = PCI_VPD_ADDR_F;
2080 ret = t4_seeprom_wait(adapter);
2082 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2086 /* Grab the returned data, swizzle it into our endianness and
2089 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2090 *data = le32_to_cpu(*data);
2095 * t4_seeprom_write - write a serial EEPROM location
2096 * @adapter: adapter to write
2097 * @addr: virtual EEPROM address
2098 * @data: value to write
2100 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2101 * VPD capability. Note that this function must be called with a virtual
2104 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2106 unsigned int base = adapter->params.pci.vpd_cap_addr;
2111 /* VPD Accesses must alway be 4-byte aligned!
2113 if (addr >= EEPROMVSIZE || (addr & 3))
2116 /* Wait for any previous operation which may still be in flight to
2119 ret = t4_seeprom_wait(adapter);
2121 dev_err(adapter, "VPD still busy from previous operation\n");
2125 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2126 * for our request to complete. If it doesn't complete, note the
2127 * error and return it to our caller. Note that we do not reset the
2130 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2132 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2133 (u16)addr | PCI_VPD_ADDR_F);
2134 adapter->vpd_busy = 1;
2135 adapter->vpd_flag = 0;
2136 ret = t4_seeprom_wait(adapter);
2138 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2142 /* Reset PCI_VPD_DATA register after a transaction and wait for our
2143 * request to complete. If it doesn't complete, return error.
2145 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2146 max_poll = EEPROM_MAX_POLL;
2148 udelay(EEPROM_DELAY);
2149 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2150 } while ((stats_reg & 0x1) && --max_poll);
2154 /* Return success! */
2159 * t4_seeprom_wp - enable/disable EEPROM write protection
2160 * @adapter: the adapter
2161 * @enable: whether to enable or disable write protection
2163 * Enables or disables write protection on the serial EEPROM.
2165 int t4_seeprom_wp(struct adapter *adapter, int enable)
2167 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2171 * t4_config_rss_range - configure a portion of the RSS mapping table
2172 * @adapter: the adapter
2173 * @mbox: mbox to use for the FW command
2174 * @viid: virtual interface whose RSS subtable is to be written
2175 * @start: start entry in the table to write
2176 * @n: how many table entries to write
2177 * @rspq: values for the "response queue" (Ingress Queue) lookup table
2178 * @nrspq: number of values in @rspq
2180 * Programs the selected part of the VI's RSS mapping table with the
2181 * provided values. If @nrspq < @n the supplied values are used repeatedly
2182 * until the full table range is populated.
2184 * The caller must ensure the values in @rspq are in the range allowed for
2187 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2188 int start, int n, const u16 *rspq, unsigned int nrspq)
2191 const u16 *rsp = rspq;
2192 const u16 *rsp_end = rspq + nrspq;
2193 struct fw_rss_ind_tbl_cmd cmd;
2195 memset(&cmd, 0, sizeof(cmd));
2196 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2197 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2198 V_FW_RSS_IND_TBL_CMD_VIID(viid));
2199 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2202 * Each firmware RSS command can accommodate up to 32 RSS Ingress
2203 * Queue Identifiers. These Ingress Queue IDs are packed three to
2204 * a 32-bit word as 10-bit values with the upper remaining 2 bits
2208 int nq = min(n, 32);
2210 __be32 *qp = &cmd.iq0_to_iq2;
2213 * Set up the firmware RSS command header to send the next
2214 * "nq" Ingress Queue IDs to the firmware.
2216 cmd.niqid = cpu_to_be16(nq);
2217 cmd.startidx = cpu_to_be16(start);
2220 * "nq" more done for the start of the next loop.
2226 * While there are still Ingress Queue IDs to stuff into the
2227 * current firmware RSS command, retrieve them from the
2228 * Ingress Queue ID array and insert them into the command.
2232 * Grab up to the next 3 Ingress Queue IDs (wrapping
2233 * around the Ingress Queue ID array if necessary) and
2234 * insert them into the firmware RSS command at the
2235 * current 3-tuple position within the commad.
2239 int nqbuf = min(3, nq);
2245 while (nqbuf && nq_packed < 32) {
2252 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2253 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2254 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2258 * Send this portion of the RRS table update to the firmware;
2259 * bail out on any errors.
2261 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2270 * t4_config_vi_rss - configure per VI RSS settings
2271 * @adapter: the adapter
2272 * @mbox: mbox to use for the FW command
2275 * @defq: id of the default RSS queue for the VI.
2277 * Configures VI-specific RSS properties.
2279 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2280 unsigned int flags, unsigned int defq)
2282 struct fw_rss_vi_config_cmd c;
2284 memset(&c, 0, sizeof(c));
2285 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2286 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2287 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2288 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2289 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2290 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2291 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2295 * init_cong_ctrl - initialize congestion control parameters
2296 * @a: the alpha values for congestion control
2297 * @b: the beta values for congestion control
2299 * Initialize the congestion control parameters.
2301 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2305 for (i = 0; i < 9; i++) {
2359 #define INIT_CMD(var, cmd, rd_wr) do { \
2360 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2361 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2362 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2365 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2367 u32 cclk_param, cclk_val;
2371 * Ask firmware for the Core Clock since it knows how to translate the
2372 * Reference Clock ('V2') VPD field into a Core Clock value ...
2374 cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2375 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2376 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2377 1, &cclk_param, &cclk_val);
2379 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2385 dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2389 /* serial flash and firmware constants and flash config file constants */
2391 SF_ATTEMPTS = 10, /* max retries for SF operations */
2393 /* flash command opcodes */
2394 SF_PROG_PAGE = 2, /* program page */
2395 SF_WR_DISABLE = 4, /* disable writes */
2396 SF_RD_STATUS = 5, /* read status register */
2397 SF_WR_ENABLE = 6, /* enable writes */
2398 SF_RD_DATA_FAST = 0xb, /* read flash */
2399 SF_RD_ID = 0x9f, /* read ID */
2400 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2404 * sf1_read - read data from the serial flash
2405 * @adapter: the adapter
2406 * @byte_cnt: number of bytes to read
2407 * @cont: whether another operation will be chained
2408 * @lock: whether to lock SF for PL access only
2409 * @valp: where to store the read data
2411 * Reads up to 4 bytes of data from the serial flash. The location of
2412 * the read needs to be specified prior to calling this by issuing the
2413 * appropriate commands to the serial flash.
2415 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2416 int lock, u32 *valp)
2420 if (!byte_cnt || byte_cnt > 4)
2422 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2424 t4_write_reg(adapter, A_SF_OP,
2425 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2426 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2428 *valp = t4_read_reg(adapter, A_SF_DATA);
2433 * sf1_write - write data to the serial flash
2434 * @adapter: the adapter
2435 * @byte_cnt: number of bytes to write
2436 * @cont: whether another operation will be chained
2437 * @lock: whether to lock SF for PL access only
2438 * @val: value to write
2440 * Writes up to 4 bytes of data to the serial flash. The location of
2441 * the write needs to be specified prior to calling this by issuing the
2442 * appropriate commands to the serial flash.
2444 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2447 if (!byte_cnt || byte_cnt > 4)
2449 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2451 t4_write_reg(adapter, A_SF_DATA, val);
2452 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2453 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2454 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2458 * t4_read_flash - read words from serial flash
2459 * @adapter: the adapter
2460 * @addr: the start address for the read
2461 * @nwords: how many 32-bit words to read
2462 * @data: where to store the read data
2463 * @byte_oriented: whether to store data as bytes or as words
2465 * Read the specified number of 32-bit words from the serial flash.
2466 * If @byte_oriented is set the read data is stored as a byte array
2467 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2468 * natural endianness.
2470 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2471 unsigned int nwords, u32 *data, int byte_oriented)
2475 if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2479 addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2481 ret = sf1_write(adapter, 4, 1, 0, addr);
2485 ret = sf1_read(adapter, 1, 1, 0, data);
2489 for ( ; nwords; nwords--, data++) {
2490 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2492 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
2496 *data = cpu_to_be32(*data);
2502 * t4_get_exprom_version - return the Expansion ROM version (if any)
2503 * @adapter: the adapter
2504 * @vers: where to place the version
2506 * Reads the Expansion ROM header from FLASH and returns the version
2507 * number (if present) through the @vers return value pointer. We return
2508 * this in the Firmware Version Format since it's convenient. Return
2509 * 0 on success, -ENOENT if no Expansion ROM is present.
2511 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2513 struct exprom_header {
2514 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2515 unsigned char hdr_ver[4]; /* Expansion ROM version */
2517 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2521 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2522 ARRAY_SIZE(exprom_header_buf),
2523 exprom_header_buf, 0);
2527 hdr = (struct exprom_header *)exprom_header_buf;
2528 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2531 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2532 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2533 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2534 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2539 * t4_get_fw_version - read the firmware version
2540 * @adapter: the adapter
2541 * @vers: where to place the version
2543 * Reads the FW version from flash.
2545 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2547 return t4_read_flash(adapter, FLASH_FW_START +
2548 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2552 * t4_get_bs_version - read the firmware bootstrap version
2553 * @adapter: the adapter
2554 * @vers: where to place the version
2556 * Reads the FW Bootstrap version from flash.
2558 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2560 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2561 offsetof(struct fw_hdr, fw_ver), 1,
2566 * t4_get_tp_version - read the TP microcode version
2567 * @adapter: the adapter
2568 * @vers: where to place the version
2570 * Reads the TP microcode version from flash.
2572 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2574 return t4_read_flash(adapter, FLASH_FW_START +
2575 offsetof(struct fw_hdr, tp_microcode_ver),
2580 * t4_get_version_info - extract various chip/firmware version information
2581 * @adapter: the adapter
2583 * Reads various chip/firmware version numbers and stores them into the
2584 * adapter Adapter Parameters structure. If any of the efforts fails
2585 * the first failure will be returned, but all of the version numbers
2588 int t4_get_version_info(struct adapter *adapter)
2592 #define FIRST_RET(__getvinfo) \
2594 int __ret = __getvinfo; \
2595 if (__ret && !ret) \
2599 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2600 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2601 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2602 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2610 * t4_dump_version_info - dump all of the adapter configuration IDs
2611 * @adapter: the adapter
2613 * Dumps all of the various bits of adapter configuration version/revision
2614 * IDs information. This is typically called at some point after
2615 * t4_get_version_info() has been called.
2617 void t4_dump_version_info(struct adapter *adapter)
2620 * Device information.
2622 dev_info(adapter, "Chelsio rev %d\n",
2623 CHELSIO_CHIP_RELEASE(adapter->params.chip));
2628 if (!adapter->params.fw_vers)
2629 dev_warn(adapter, "No firmware loaded\n");
2631 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2632 G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2633 G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2634 G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2635 G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2638 * Bootstrap Firmware Version.
2640 if (!adapter->params.bs_vers)
2641 dev_warn(adapter, "No bootstrap loaded\n");
2643 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2644 G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2645 G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2646 G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2647 G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2650 * TP Microcode Version.
2652 if (!adapter->params.tp_vers)
2653 dev_warn(adapter, "No TP Microcode loaded\n");
2655 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2656 G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2657 G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2658 G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2659 G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2662 * Expansion ROM version.
2664 if (!adapter->params.er_vers)
2665 dev_info(adapter, "No Expansion ROM loaded\n");
2667 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2668 G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2669 G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2670 G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2671 G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2674 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
2678 * t4_link_l1cfg - apply link configuration to MAC/PHY
2679 * @phy: the PHY to setup
2680 * @mac: the MAC to setup
2681 * @lc: the requested link configuration
2683 * Set up a port's MAC and PHY according to a desired link configuration.
2684 * - If the PHY can auto-negotiate first decide what to advertise, then
2685 * enable/disable auto-negotiation as desired, and reset.
2686 * - If the PHY does not auto-negotiate just reset it.
2687 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2688 * otherwise do it later based on the outcome of auto-negotiation.
2690 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2691 struct link_config *lc)
2693 struct fw_port_cmd c;
2694 unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
2695 unsigned int fc, fec;
2699 if (lc->requested_fc & PAUSE_RX)
2700 fc |= FW_PORT_CAP_FC_RX;
2701 if (lc->requested_fc & PAUSE_TX)
2702 fc |= FW_PORT_CAP_FC_TX;
2705 if (lc->requested_fec & FEC_RS)
2706 fec |= FW_PORT_CAP_FEC_RS;
2707 if (lc->requested_fec & FEC_BASER_RS)
2708 fec |= FW_PORT_CAP_FEC_BASER_RS;
2709 if (lc->requested_fec & FEC_RESERVED)
2710 fec |= FW_PORT_CAP_FEC_RESERVED;
2712 memset(&c, 0, sizeof(c));
2713 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2714 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2715 V_FW_PORT_CMD_PORTID(port));
2717 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2720 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2721 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2723 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2724 lc->fec = lc->requested_fec;
2725 } else if (lc->autoneg == AUTONEG_DISABLE) {
2726 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
2728 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2729 lc->fec = lc->requested_fec;
2731 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | fec | mdi);
2734 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2738 * t4_flash_cfg_addr - return the address of the flash configuration file
2739 * @adapter: the adapter
2741 * Return the address within the flash where the Firmware Configuration
2742 * File is stored, or an error if the device FLASH is too small to contain
2743 * a Firmware Configuration File.
2745 int t4_flash_cfg_addr(struct adapter *adapter)
2748 * If the device FLASH isn't large enough to hold a Firmware
2749 * Configuration File, return an error.
2751 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2754 return FLASH_CFG_START;
2757 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2760 * t4_intr_enable - enable interrupts
2761 * @adapter: the adapter whose interrupts should be enabled
2763 * Enable PF-specific interrupts for the calling function and the top-level
2764 * interrupt concentrator for global interrupts. Interrupts are already
2765 * enabled at each module, here we just enable the roots of the interrupt
2768 * Note: this function should be called only when the driver manages
2769 * non PF-specific interrupts from the various HW modules. Only one PCI
2770 * function at a time should be doing this.
2772 void t4_intr_enable(struct adapter *adapter)
2775 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2776 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2777 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2779 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2780 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2781 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2782 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2783 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2784 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2785 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2786 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2787 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2788 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2789 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2793 * t4_intr_disable - disable interrupts
2794 * @adapter: the adapter whose interrupts should be disabled
2796 * Disable interrupts. We only disable the top-level interrupt
2797 * concentrators. The caller must be a PCI function managing global
2800 void t4_intr_disable(struct adapter *adapter)
2802 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2803 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2804 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2806 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2807 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2811 * t4_get_port_type_description - return Port Type string description
2812 * @port_type: firmware Port Type enumeration
2814 const char *t4_get_port_type_description(enum fw_port_type port_type)
2816 static const char * const port_type_description[] = {
2841 if (port_type < ARRAY_SIZE(port_type_description))
2842 return port_type_description[port_type];
2847 * t4_get_mps_bg_map - return the buffer groups associated with a port
2848 * @adap: the adapter
2849 * @pidx: the port index
2851 * Returns a bitmap indicating which MPS buffer groups are associated
2852 * with the given port. Bit i is set if buffer group i is used by the
2855 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
2857 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2858 unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
2861 if (pidx >= nports) {
2862 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
2867 switch (chip_version) {
2872 case 2: return 3 << (2 * pidx);
2873 case 4: return 1 << pidx;
2879 case 2: return 1 << (2 * pidx);
2884 dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
2885 chip_version, nports);
2890 * t4_get_tp_ch_map - return TP ingress channels associated with a port
2891 * @adapter: the adapter
2892 * @pidx: the port index
2894 * Returns a bitmap indicating which TP Ingress Channels are associated with
2895 * a given Port. Bit i is set if TP Ingress Channel i is used by the Port.
2897 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
2899 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
2900 unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
2903 if (pidx >= nports) {
2904 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
2909 switch (chip_version) {
2912 /* Note that this happens to be the same values as the MPS
2913 * Buffer Group Map for these Chips. But we replicate the code
2914 * here because they're really separate concepts.
2918 case 2: return 3 << (2 * pidx);
2919 case 4: return 1 << pidx;
2925 case 2: return 1 << pidx;
2930 dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
2931 chip_version, nports);
2936 * t4_get_port_stats - collect port statistics
2937 * @adap: the adapter
2938 * @idx: the port index
2939 * @p: the stats structure to fill
2941 * Collect statistics related to the given port from HW.
2943 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2945 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2946 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
2948 #define GET_STAT(name) \
2949 t4_read_reg64(adap, \
2950 (is_t4(adap->params.chip) ? \
2951 PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2952 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2953 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2955 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2956 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2957 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2958 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2959 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2960 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2961 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2962 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2963 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2964 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2965 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2966 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2967 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2968 p->tx_drop = GET_STAT(TX_PORT_DROP);
2969 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2970 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2971 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2972 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2973 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2974 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2975 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2976 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2977 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2979 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
2980 if (stat_ctl & F_COUNTPAUSESTATTX) {
2981 p->tx_frames -= p->tx_pause;
2982 p->tx_octets -= p->tx_pause * 64;
2984 if (stat_ctl & F_COUNTPAUSEMCTX)
2985 p->tx_mcast_frames -= p->tx_pause;
2988 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2989 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2990 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2991 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2992 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2993 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2994 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2995 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2996 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2997 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2998 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2999 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
3000 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
3001 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
3002 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
3003 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
3004 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3005 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
3006 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
3007 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
3008 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
3009 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
3010 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
3011 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
3012 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
3013 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
3014 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
3016 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3017 if (stat_ctl & F_COUNTPAUSESTATRX) {
3018 p->rx_frames -= p->rx_pause;
3019 p->rx_octets -= p->rx_pause * 64;
3021 if (stat_ctl & F_COUNTPAUSEMCRX)
3022 p->rx_mcast_frames -= p->rx_pause;
3025 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3026 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3027 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3028 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3029 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3030 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3031 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3032 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3039 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3040 * @adap: The adapter
3042 * @stats: Current stats to fill
3043 * @offset: Previous stats snapshot
3045 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3046 struct port_stats *stats,
3047 struct port_stats *offset)
3052 t4_get_port_stats(adap, idx, stats);
3053 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3054 i < (sizeof(struct port_stats) / sizeof(u64));
3060 * t4_clr_port_stats - clear port statistics
3061 * @adap: the adapter
3062 * @idx: the port index
3064 * Clear HW statistics for the given port.
3066 void t4_clr_port_stats(struct adapter *adap, int idx)
3069 u32 bgmap = t4_get_mps_bg_map(adap, idx);
3072 if (is_t4(adap->params.chip))
3073 port_base_addr = PORT_BASE(idx);
3075 port_base_addr = T5_PORT_BASE(idx);
3077 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3078 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3079 t4_write_reg(adap, port_base_addr + i, 0);
3080 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3081 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3082 t4_write_reg(adap, port_base_addr + i, 0);
3083 for (i = 0; i < 4; i++)
3084 if (bgmap & (1 << i)) {
3086 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3089 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3095 * t4_fw_hello - establish communication with FW
3096 * @adap: the adapter
3097 * @mbox: mailbox to use for the FW command
3098 * @evt_mbox: mailbox to receive async FW events
3099 * @master: specifies the caller's willingness to be the device master
3100 * @state: returns the current device state (if non-NULL)
3102 * Issues a command to establish communication with FW. Returns either
3103 * an error (negative integer) or the mailbox of the Master PF.
3105 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3106 enum dev_master master, enum dev_state *state)
3109 struct fw_hello_cmd c;
3111 unsigned int master_mbox;
3112 int retries = FW_CMD_HELLO_RETRIES;
3115 memset(&c, 0, sizeof(c));
3116 INIT_CMD(c, HELLO, WRITE);
3117 c.err_to_clearinit = cpu_to_be32(
3118 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3119 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3120 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3121 M_FW_HELLO_CMD_MBMASTER) |
3122 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3123 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3124 F_FW_HELLO_CMD_CLEARINIT);
3127 * Issue the HELLO command to the firmware. If it's not successful
3128 * but indicates that we got a "busy" or "timeout" condition, retry
3129 * the HELLO until we exhaust our retry limit. If we do exceed our
3130 * retry limit, check to see if the firmware left us any error
3131 * information and report that if so ...
3133 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3134 if (ret != FW_SUCCESS) {
3135 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3137 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3138 t4_report_fw_error(adap);
3142 v = be32_to_cpu(c.err_to_clearinit);
3143 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3145 if (v & F_FW_HELLO_CMD_ERR)
3146 *state = DEV_STATE_ERR;
3147 else if (v & F_FW_HELLO_CMD_INIT)
3148 *state = DEV_STATE_INIT;
3150 *state = DEV_STATE_UNINIT;
3154 * If we're not the Master PF then we need to wait around for the
3155 * Master PF Driver to finish setting up the adapter.
3157 * Note that we also do this wait if we're a non-Master-capable PF and
3158 * there is no current Master PF; a Master PF may show up momentarily
3159 * and we wouldn't want to fail pointlessly. (This can happen when an
3160 * OS loads lots of different drivers rapidly at the same time). In
3161 * this case, the Master PF returned by the firmware will be
3162 * M_PCIE_FW_MASTER so the test below will work ...
3164 if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3165 master_mbox != mbox) {
3166 int waiting = FW_CMD_HELLO_TIMEOUT;
3169 * Wait for the firmware to either indicate an error or
3170 * initialized state. If we see either of these we bail out
3171 * and report the issue to the caller. If we exhaust the
3172 * "hello timeout" and we haven't exhausted our retries, try
3173 * again. Otherwise bail with a timeout error.
3182 * If neither Error nor Initialialized are indicated
3183 * by the firmware keep waiting till we exaust our
3184 * timeout ... and then retry if we haven't exhausted
3187 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3188 if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3199 * We either have an Error or Initialized condition
3200 * report errors preferentially.
3203 if (pcie_fw & F_PCIE_FW_ERR)
3204 *state = DEV_STATE_ERR;
3205 else if (pcie_fw & F_PCIE_FW_INIT)
3206 *state = DEV_STATE_INIT;
3210 * If we arrived before a Master PF was selected and
3211 * there's not a valid Master PF, grab its identity
3214 if (master_mbox == M_PCIE_FW_MASTER &&
3215 (pcie_fw & F_PCIE_FW_MASTER_VLD))
3216 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3225 * t4_fw_bye - end communication with FW
3226 * @adap: the adapter
3227 * @mbox: mailbox to use for the FW command
3229 * Issues a command to terminate communication with FW.
3231 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3233 struct fw_bye_cmd c;
3235 memset(&c, 0, sizeof(c));
3236 INIT_CMD(c, BYE, WRITE);
3237 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3241 * t4_fw_reset - issue a reset to FW
3242 * @adap: the adapter
3243 * @mbox: mailbox to use for the FW command
3244 * @reset: specifies the type of reset to perform
3246 * Issues a reset command of the specified type to FW.
3248 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3250 struct fw_reset_cmd c;
3252 memset(&c, 0, sizeof(c));
3253 INIT_CMD(c, RESET, WRITE);
3254 c.val = cpu_to_be32(reset);
3255 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3259 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3260 * @adap: the adapter
3261 * @mbox: mailbox to use for the FW RESET command (if desired)
3262 * @force: force uP into RESET even if FW RESET command fails
3264 * Issues a RESET command to firmware (if desired) with a HALT indication
3265 * and then puts the microprocessor into RESET state. The RESET command
3266 * will only be issued if a legitimate mailbox is provided (mbox <=
3267 * M_PCIE_FW_MASTER).
3269 * This is generally used in order for the host to safely manipulate the
3270 * adapter without fear of conflicting with whatever the firmware might
3271 * be doing. The only way out of this state is to RESTART the firmware
3274 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3279 * If a legitimate mailbox is provided, issue a RESET command
3280 * with a HALT indication.
3282 if (mbox <= M_PCIE_FW_MASTER) {
3283 struct fw_reset_cmd c;
3285 memset(&c, 0, sizeof(c));
3286 INIT_CMD(c, RESET, WRITE);
3287 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3288 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3289 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3293 * Normally we won't complete the operation if the firmware RESET
3294 * command fails but if our caller insists we'll go ahead and put the
3295 * uP into RESET. This can be useful if the firmware is hung or even
3296 * missing ... We'll have to take the risk of putting the uP into
3297 * RESET without the cooperation of firmware in that case.
3299 * We also force the firmware's HALT flag to be on in case we bypassed
3300 * the firmware RESET command above or we're dealing with old firmware
3301 * which doesn't have the HALT capability. This will serve as a flag
3302 * for the incoming firmware to know that it's coming out of a HALT
3303 * rather than a RESET ... if it's new enough to understand that ...
3305 if (ret == 0 || force) {
3306 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3307 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3312 * And we always return the result of the firmware RESET command
3313 * even when we force the uP into RESET ...
3319 * t4_fw_restart - restart the firmware by taking the uP out of RESET
3320 * @adap: the adapter
3321 * @mbox: mailbox to use for the FW RESET command (if desired)
3322 * @reset: if we want to do a RESET to restart things
3324 * Restart firmware previously halted by t4_fw_halt(). On successful
3325 * return the previous PF Master remains as the new PF Master and there
3326 * is no need to issue a new HELLO command, etc.
3328 * We do this in two ways:
3330 * 1. If we're dealing with newer firmware we'll simply want to take
3331 * the chip's microprocessor out of RESET. This will cause the
3332 * firmware to start up from its start vector. And then we'll loop
3333 * until the firmware indicates it's started again (PCIE_FW.HALT
3334 * reset to 0) or we timeout.
3336 * 2. If we're dealing with older firmware then we'll need to RESET
3337 * the chip since older firmware won't recognize the PCIE_FW.HALT
3338 * flag and automatically RESET itself on startup.
3340 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3344 * Since we're directing the RESET instead of the firmware
3345 * doing it automatically, we need to clear the PCIE_FW.HALT
3348 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3351 * If we've been given a valid mailbox, first try to get the
3352 * firmware to do the RESET. If that works, great and we can
3353 * return success. Otherwise, if we haven't been given a
3354 * valid mailbox or the RESET command failed, fall back to
3355 * hitting the chip with a hammer.
3357 if (mbox <= M_PCIE_FW_MASTER) {
3358 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3360 if (t4_fw_reset(adap, mbox,
3361 F_PIORST | F_PIORSTMODE) == 0)
3365 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3370 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3371 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3372 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3383 * t4_fl_pkt_align - return the fl packet alignment
3384 * @adap: the adapter
3386 * T4 has a single field to specify the packing and padding boundary.
3387 * T5 onwards has separate fields for this and hence the alignment for
3388 * next packet offset is maximum of these two.
3390 int t4_fl_pkt_align(struct adapter *adap)
3392 u32 sge_control, sge_control2;
3393 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3395 sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3397 /* T4 uses a single control field to specify both the PCIe Padding and
3398 * Packing Boundary. T5 introduced the ability to specify these
3399 * separately. The actual Ingress Packet Data alignment boundary
3400 * within Packed Buffer Mode is the maximum of these two
3403 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3404 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3406 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3408 ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3410 fl_align = ingpadboundary;
3411 if (!is_t4(adap->params.chip)) {
3412 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3413 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3414 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3415 ingpackboundary = 16;
3417 ingpackboundary = 1 << (ingpackboundary +
3418 X_INGPACKBOUNDARY_SHIFT);
3420 fl_align = max(ingpadboundary, ingpackboundary);
3426 * t4_fixup_host_params_compat - fix up host-dependent parameters
3427 * @adap: the adapter
3428 * @page_size: the host's Base Page Size
3429 * @cache_line_size: the host's Cache Line Size
3430 * @chip_compat: maintain compatibility with designated chip
3432 * Various registers in the chip contain values which are dependent on the
3433 * host's Base Page and Cache Line Sizes. This function will fix all of
3434 * those registers with the appropriate values as passed in ...
3436 * @chip_compat is used to limit the set of changes that are made
3437 * to be compatible with the indicated chip release. This is used by
3438 * drivers to maintain compatibility with chip register settings when
3439 * the drivers haven't [yet] been updated with new chip support.
3441 int t4_fixup_host_params_compat(struct adapter *adap,
3442 unsigned int page_size,
3443 unsigned int cache_line_size,
3444 enum chip_type chip_compat)
3446 unsigned int page_shift = cxgbe_fls(page_size) - 1;
3447 unsigned int sge_hps = page_shift - 10;
3448 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3449 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3450 unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3452 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3453 V_HOSTPAGESIZEPF0(sge_hps) |
3454 V_HOSTPAGESIZEPF1(sge_hps) |
3455 V_HOSTPAGESIZEPF2(sge_hps) |
3456 V_HOSTPAGESIZEPF3(sge_hps) |
3457 V_HOSTPAGESIZEPF4(sge_hps) |
3458 V_HOSTPAGESIZEPF5(sge_hps) |
3459 V_HOSTPAGESIZEPF6(sge_hps) |
3460 V_HOSTPAGESIZEPF7(sge_hps));
3462 if (is_t4(adap->params.chip) || is_t4(chip_compat))
3463 t4_set_reg_field(adap, A_SGE_CONTROL,
3464 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3465 F_EGRSTATUSPAGESIZE,
3466 V_INGPADBOUNDARY(fl_align_log -
3467 X_INGPADBOUNDARY_SHIFT) |
3468 V_EGRSTATUSPAGESIZE(stat_len != 64));
3470 unsigned int pack_align;
3471 unsigned int ingpad, ingpack;
3472 unsigned int pcie_cap;
3475 * T5 introduced the separation of the Free List Padding and
3476 * Packing Boundaries. Thus, we can select a smaller Padding
3477 * Boundary to avoid uselessly chewing up PCIe Link and Memory
3478 * Bandwidth, and use a Packing Boundary which is large enough
3479 * to avoid false sharing between CPUs, etc.
3481 * For the PCI Link, the smaller the Padding Boundary the
3482 * better. For the Memory Controller, a smaller Padding
3483 * Boundary is better until we cross under the Memory Line
3484 * Size (the minimum unit of transfer to/from Memory). If we
3485 * have a Padding Boundary which is smaller than the Memory
3486 * Line Size, that'll involve a Read-Modify-Write cycle on the
3487 * Memory Controller which is never good.
3490 /* We want the Packing Boundary to be based on the Cache Line
3491 * Size in order to help avoid False Sharing performance
3492 * issues between CPUs, etc. We also want the Packing
3493 * Boundary to incorporate the PCI-E Maximum Payload Size. We
3494 * get best performance when the Packing Boundary is a
3495 * multiple of the Maximum Payload Size.
3497 pack_align = fl_align;
3498 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3500 unsigned int mps, mps_log;
3503 /* The PCIe Device Control Maximum Payload Size field
3504 * [bits 7:5] encodes sizes as powers of 2 starting at
3507 t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3509 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3511 if (mps > pack_align)
3516 * N.B. T5 has a different interpretation of the "0" value for
3517 * the Packing Boundary. This corresponds to 16 bytes instead
3518 * of the expected 32 bytes. We never have a Packing Boundary
3519 * less than 32 bytes so we can't use that special value but
3520 * on the other hand, if we wanted 32 bytes, the best we can
3521 * really do is 64 bytes ...
3523 if (pack_align <= 16) {
3524 ingpack = X_INGPACKBOUNDARY_16B;
3526 } else if (pack_align == 32) {
3527 ingpack = X_INGPACKBOUNDARY_64B;
3530 unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3532 ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3533 fl_align = pack_align;
3536 /* Use the smallest Ingress Padding which isn't smaller than
3537 * the Memory Controller Read/Write Size. We'll take that as
3538 * being 8 bytes since we don't know of any system with a
3539 * wider Memory Controller Bus Width.
3541 if (is_t5(adap->params.chip))
3542 ingpad = X_INGPADBOUNDARY_32B;
3544 ingpad = X_T6_INGPADBOUNDARY_8B;
3545 t4_set_reg_field(adap, A_SGE_CONTROL,
3546 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3547 F_EGRSTATUSPAGESIZE,
3548 V_INGPADBOUNDARY(ingpad) |
3549 V_EGRSTATUSPAGESIZE(stat_len != 64));
3550 t4_set_reg_field(adap, A_SGE_CONTROL2,
3551 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3552 V_INGPACKBOUNDARY(ingpack));
3556 * Adjust various SGE Free List Host Buffer Sizes.
3558 * The first four entries are:
3562 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3563 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3565 * For the single-MTU buffers in unpacked mode we need to include
3566 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3567 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3568 * Padding boundary. All of these are accommodated in the Factory
3569 * Default Firmware Configuration File but we need to adjust it for
3570 * this host's cache line size.
3572 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3573 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3574 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3576 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3577 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3580 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3586 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3587 * @adap: the adapter
3588 * @page_size: the host's Base Page Size
3589 * @cache_line_size: the host's Cache Line Size
3591 * Various registers in T4 contain values which are dependent on the
3592 * host's Base Page and Cache Line Sizes. This function will fix all of
3593 * those registers with the appropriate values as passed in ...
3595 * This routine makes changes which are compatible with T4 chips.
3597 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3598 unsigned int cache_line_size)
3600 return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3605 * t4_fw_initialize - ask FW to initialize the device
3606 * @adap: the adapter
3607 * @mbox: mailbox to use for the FW command
3609 * Issues a command to FW to partially initialize the device. This
3610 * performs initialization that generally doesn't depend on user input.
3612 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3614 struct fw_initialize_cmd c;
3616 memset(&c, 0, sizeof(c));
3617 INIT_CMD(c, INITIALIZE, WRITE);
3618 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3622 * t4_query_params_rw - query FW or device parameters
3623 * @adap: the adapter
3624 * @mbox: mailbox to use for the FW command
3627 * @nparams: the number of parameters
3628 * @params: the parameter names
3629 * @val: the parameter values
3630 * @rw: Write and read flag
3632 * Reads the value of FW or device parameters. Up to 7 parameters can be
3635 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3636 unsigned int pf, unsigned int vf,
3637 unsigned int nparams, const u32 *params,
3642 struct fw_params_cmd c;
3643 __be32 *p = &c.param[0].mnem;
3648 memset(&c, 0, sizeof(c));
3649 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3650 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3651 V_FW_PARAMS_CMD_PFN(pf) |
3652 V_FW_PARAMS_CMD_VFN(vf));
3653 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3655 for (i = 0; i < nparams; i++) {
3656 *p++ = cpu_to_be32(*params++);
3658 *p = cpu_to_be32(*(val + i));
3662 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3664 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3665 *val++ = be32_to_cpu(*p);
3669 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3670 unsigned int vf, unsigned int nparams, const u32 *params,
3673 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3677 * t4_set_params_timeout - sets FW or device parameters
3678 * @adap: the adapter
3679 * @mbox: mailbox to use for the FW command
3682 * @nparams: the number of parameters
3683 * @params: the parameter names
3684 * @val: the parameter values
3685 * @timeout: the timeout time
3687 * Sets the value of FW or device parameters. Up to 7 parameters can be
3688 * specified at once.
3690 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3691 unsigned int pf, unsigned int vf,
3692 unsigned int nparams, const u32 *params,
3693 const u32 *val, int timeout)
3695 struct fw_params_cmd c;
3696 __be32 *p = &c.param[0].mnem;
3701 memset(&c, 0, sizeof(c));
3702 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3703 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3704 V_FW_PARAMS_CMD_PFN(pf) |
3705 V_FW_PARAMS_CMD_VFN(vf));
3706 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3709 *p++ = cpu_to_be32(*params++);
3710 *p++ = cpu_to_be32(*val++);
3713 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3716 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3717 unsigned int vf, unsigned int nparams, const u32 *params,
3720 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3721 FW_CMD_MAX_TIMEOUT);
3725 * t4_alloc_vi_func - allocate a virtual interface
3726 * @adap: the adapter
3727 * @mbox: mailbox to use for the FW command
3728 * @port: physical port associated with the VI
3729 * @pf: the PF owning the VI
3730 * @vf: the VF owning the VI
3731 * @nmac: number of MAC addresses needed (1 to 5)
3732 * @mac: the MAC addresses of the VI
3733 * @rss_size: size of RSS table slice associated with this VI
3734 * @portfunc: which Port Application Function MAC Address is desired
3735 * @idstype: Intrusion Detection Type
3737 * Allocates a virtual interface for the given physical port. If @mac is
3738 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3739 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3740 * stored consecutively so the space needed is @nmac * 6 bytes.
3741 * Returns a negative error number or the non-negative VI id.
3743 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3744 unsigned int port, unsigned int pf, unsigned int vf,
3745 unsigned int nmac, u8 *mac, unsigned int *rss_size,
3746 unsigned int portfunc, unsigned int idstype)
3751 memset(&c, 0, sizeof(c));
3752 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3753 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3754 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3755 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3756 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3757 V_FW_VI_CMD_FUNC(portfunc));
3758 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3761 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3766 memcpy(mac, c.mac, sizeof(c.mac));
3769 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3772 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3775 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3778 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3783 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3784 return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3788 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3789 * @adap: the adapter
3790 * @mbox: mailbox to use for the FW command
3791 * @port: physical port associated with the VI
3792 * @pf: the PF owning the VI
3793 * @vf: the VF owning the VI
3794 * @nmac: number of MAC addresses needed (1 to 5)
3795 * @mac: the MAC addresses of the VI
3796 * @rss_size: size of RSS table slice associated with this VI
3798 * Backwards compatible and convieniance routine to allocate a Virtual
3799 * Interface with a Ethernet Port Application Function and Intrustion
3800 * Detection System disabled.
3802 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3803 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3804 unsigned int *rss_size)
3806 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3811 * t4_free_vi - free a virtual interface
3812 * @adap: the adapter
3813 * @mbox: mailbox to use for the FW command
3814 * @pf: the PF owning the VI
3815 * @vf: the VF owning the VI
3816 * @viid: virtual interface identifiler
3818 * Free a previously allocated virtual interface.
3820 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3821 unsigned int vf, unsigned int viid)
3825 memset(&c, 0, sizeof(c));
3826 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3827 F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
3828 V_FW_VI_CMD_VFN(vf));
3829 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
3830 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
3832 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3836 * t4_set_rxmode - set Rx properties of a virtual interface
3837 * @adap: the adapter
3838 * @mbox: mailbox to use for the FW command
3840 * @mtu: the new MTU or -1
3841 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3842 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3843 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3844 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
3846 * @sleep_ok: if true we may sleep while awaiting command completion
3848 * Sets Rx properties of a virtual interface.
3850 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3851 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3854 struct fw_vi_rxmode_cmd c;
3856 /* convert to FW values */
3858 mtu = M_FW_VI_RXMODE_CMD_MTU;
3860 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
3862 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
3864 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
3866 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
3868 memset(&c, 0, sizeof(c));
3869 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
3870 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3871 V_FW_VI_RXMODE_CMD_VIID(viid));
3872 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3873 c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
3874 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3875 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3876 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3877 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3878 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3882 * t4_change_mac - modifies the exact-match filter for a MAC address
3883 * @adap: the adapter
3884 * @mbox: mailbox to use for the FW command
3886 * @idx: index of existing filter for old value of MAC address, or -1
3887 * @addr: the new MAC address value
3888 * @persist: whether a new MAC allocation should be persistent
3889 * @add_smt: if true also add the address to the HW SMT
3891 * Modifies an exact-match filter and sets it to the new MAC address if
3892 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
3893 * latter case the address is added persistently if @persist is %true.
3895 * Note that in general it is not possible to modify the value of a given
3896 * filter so the generic way to modify an address filter is to free the one
3897 * being used by the old address value and allocate a new filter for the
3898 * new address value.
3900 * Returns a negative error number or the index of the filter with the new
3901 * MAC value. Note that this index may differ from @idx.
3903 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3904 int idx, const u8 *addr, bool persist, bool add_smt)
3907 struct fw_vi_mac_cmd c;
3908 struct fw_vi_mac_exact *p = c.u.exact;
3909 int max_mac_addr = adap->params.arch.mps_tcam_size;
3911 if (idx < 0) /* new allocation */
3912 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3913 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3915 memset(&c, 0, sizeof(c));
3916 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3917 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3918 V_FW_VI_MAC_CMD_VIID(viid));
3919 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3920 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3921 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3922 V_FW_VI_MAC_CMD_IDX(idx));
3923 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3925 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3927 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3928 if (ret >= max_mac_addr)
3935 * t4_enable_vi_params - enable/disable a virtual interface
3936 * @adap: the adapter
3937 * @mbox: mailbox to use for the FW command
3939 * @rx_en: 1=enable Rx, 0=disable Rx
3940 * @tx_en: 1=enable Tx, 0=disable Tx
3941 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3943 * Enables/disables a virtual interface. Note that setting DCB Enable
3944 * only makes sense when enabling a Virtual Interface ...
3946 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3947 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3949 struct fw_vi_enable_cmd c;
3951 memset(&c, 0, sizeof(c));
3952 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3953 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3954 V_FW_VI_ENABLE_CMD_VIID(viid));
3955 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3956 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3957 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3959 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3963 * t4_enable_vi - enable/disable a virtual interface
3964 * @adap: the adapter
3965 * @mbox: mailbox to use for the FW command
3967 * @rx_en: 1=enable Rx, 0=disable Rx
3968 * @tx_en: 1=enable Tx, 0=disable Tx
3970 * Enables/disables a virtual interface. Note that setting DCB Enable
3971 * only makes sense when enabling a Virtual Interface ...
3973 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3974 bool rx_en, bool tx_en)
3976 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3980 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3981 * @adap: the adapter
3982 * @mbox: mailbox to use for the FW command
3983 * @start: %true to enable the queues, %false to disable them
3984 * @pf: the PF owning the queues
3985 * @vf: the VF owning the queues
3986 * @iqid: ingress queue id
3987 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3988 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3990 * Starts or stops an ingress queue and its associated FLs, if any.
3992 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3993 unsigned int pf, unsigned int vf, unsigned int iqid,
3994 unsigned int fl0id, unsigned int fl1id)
3998 memset(&c, 0, sizeof(c));
3999 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4000 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4001 V_FW_IQ_CMD_VFN(vf));
4002 c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4003 V_FW_IQ_CMD_IQSTOP(!start) |
4005 c.iqid = cpu_to_be16(iqid);
4006 c.fl0id = cpu_to_be16(fl0id);
4007 c.fl1id = cpu_to_be16(fl1id);
4008 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4012 * t4_iq_free - free an ingress queue and its FLs
4013 * @adap: the adapter
4014 * @mbox: mailbox to use for the FW command
4015 * @pf: the PF owning the queues
4016 * @vf: the VF owning the queues
4017 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4018 * @iqid: ingress queue id
4019 * @fl0id: FL0 queue id or 0xffff if no attached FL0
4020 * @fl1id: FL1 queue id or 0xffff if no attached FL1
4022 * Frees an ingress queue and its associated FLs, if any.
4024 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4025 unsigned int vf, unsigned int iqtype, unsigned int iqid,
4026 unsigned int fl0id, unsigned int fl1id)
4030 memset(&c, 0, sizeof(c));
4031 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4032 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4033 V_FW_IQ_CMD_VFN(vf));
4034 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4035 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4036 c.iqid = cpu_to_be16(iqid);
4037 c.fl0id = cpu_to_be16(fl0id);
4038 c.fl1id = cpu_to_be16(fl1id);
4039 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4043 * t4_eth_eq_free - free an Ethernet egress queue
4044 * @adap: the adapter
4045 * @mbox: mailbox to use for the FW command
4046 * @pf: the PF owning the queue
4047 * @vf: the VF owning the queue
4048 * @eqid: egress queue id
4050 * Frees an Ethernet egress queue.
4052 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4053 unsigned int vf, unsigned int eqid)
4055 struct fw_eq_eth_cmd c;
4057 memset(&c, 0, sizeof(c));
4058 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4059 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4060 V_FW_EQ_ETH_CMD_PFN(pf) |
4061 V_FW_EQ_ETH_CMD_VFN(vf));
4062 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4063 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4064 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4068 * t4_handle_fw_rpl - process a FW reply message
4069 * @adap: the adapter
4070 * @rpl: start of the FW message
4072 * Processes a FW message, such as link state change messages.
4074 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4076 u8 opcode = *(const u8 *)rpl;
4079 * This might be a port command ... this simplifies the following
4080 * conditionals ... We can get away with pre-dereferencing
4081 * action_to_len16 because it's in the first 16 bytes and all messages
4082 * will be at least that long.
4084 const struct fw_port_cmd *p = (const void *)rpl;
4085 unsigned int action =
4086 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4088 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
4089 /* link/module state change message */
4090 unsigned int speed = 0, fc = 0, i;
4091 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4092 struct port_info *pi = NULL;
4093 struct link_config *lc;
4094 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
4095 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
4096 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
4098 if (stat & F_FW_PORT_CMD_RXPAUSE)
4100 if (stat & F_FW_PORT_CMD_TXPAUSE)
4102 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4103 speed = ETH_SPEED_NUM_100M;
4104 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4105 speed = ETH_SPEED_NUM_1G;
4106 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4107 speed = ETH_SPEED_NUM_10G;
4108 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4109 speed = ETH_SPEED_NUM_25G;
4110 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4111 speed = ETH_SPEED_NUM_40G;
4112 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4113 speed = ETH_SPEED_NUM_100G;
4115 for_each_port(adap, i) {
4116 pi = adap2pinfo(adap, i);
4117 if (pi->tx_chan == chan)
4122 if (mod != pi->mod_type) {
4124 t4_os_portmod_changed(adap, i);
4126 if (link_ok != lc->link_ok || speed != lc->speed ||
4127 fc != lc->fc) { /* something changed */
4128 if (!link_ok && lc->link_ok) {
4129 static const char * const reason[] = {
4132 "Auto-negotiation Failure",
4134 "Insufficient Airflow",
4135 "Unable To Determine Reason",
4136 "No RX Signal Detected",
4139 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
4141 dev_warn(adap, "Port %d link down, reason: %s\n",
4144 lc->link_ok = link_ok;
4147 lc->supported = be16_to_cpu(p->u.info.pcap);
4150 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4156 void t4_reset_link_config(struct adapter *adap, int idx)
4158 struct port_info *pi = adap2pinfo(adap, idx);
4159 struct link_config *lc = &pi->link_cfg;
4162 lc->requested_speed = 0;
4163 lc->requested_fc = 0;
4169 * init_link_config - initialize a link's SW state
4170 * @lc: structure holding the link state
4171 * @pcaps: link Port Capabilities
4172 * @acaps: link current Advertised Port Capabilities
4174 * Initializes the SW state maintained for each link, including the link's
4175 * capabilities and default speed/flow-control/autonegotiation settings.
4177 static void init_link_config(struct link_config *lc, unsigned int pcaps,
4182 lc->supported = pcaps;
4183 lc->requested_speed = 0;
4185 lc->requested_fc = 0;
4189 * For Forward Error Control, we default to whatever the Firmware
4190 * tells us the Link is currently advertising.
4193 if (acaps & FW_PORT_CAP_FEC_RS)
4195 if (acaps & FW_PORT_CAP_FEC_BASER_RS)
4196 fec |= FEC_BASER_RS;
4197 if (acaps & FW_PORT_CAP_FEC_RESERVED)
4198 fec |= FEC_RESERVED;
4199 lc->requested_fec = fec;
4202 if (lc->supported & FW_PORT_CAP_ANEG) {
4203 lc->advertising = lc->supported & ADVERT_MASK;
4204 lc->autoneg = AUTONEG_ENABLE;
4206 lc->advertising = 0;
4207 lc->autoneg = AUTONEG_DISABLE;
4212 * t4_wait_dev_ready - wait till to reads of registers work
4214 * Right after the device is RESET is can take a small amount of time
4215 * for it to respond to register reads. Until then, all reads will
4216 * return either 0xff...ff or 0xee...ee. Return an error if reads
4217 * don't work within a reasonable time frame.
4219 static int t4_wait_dev_ready(struct adapter *adapter)
4223 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4225 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4229 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4230 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4233 dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4239 u32 vendor_and_model_id;
4243 int t4_get_flash_params(struct adapter *adapter)
4246 * Table for non-Numonix supported flash parts. Numonix parts are left
4247 * to the preexisting well-tested code. All flash parts have 64KB
4250 static struct flash_desc supported_flash[] = {
4251 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
4256 unsigned int part, manufacturer;
4257 unsigned int density, size;
4260 * Issue a Read ID Command to the Flash part. We decode supported
4261 * Flash parts and their sizes from this. There's a newer Query
4262 * Command which can retrieve detailed geometry information but
4263 * many Flash parts don't support it.
4265 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4267 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4268 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
4272 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4273 if (supported_flash[part].vendor_and_model_id == flashid) {
4274 adapter->params.sf_size =
4275 supported_flash[part].size_mb;
4276 adapter->params.sf_nsec =
4277 adapter->params.sf_size / SF_SEC_SIZE;
4282 manufacturer = flashid & 0xff;
4283 switch (manufacturer) {
4284 case 0x20: { /* Micron/Numonix */
4286 * This Density -> Size decoding table is taken from Micron
4289 density = (flashid >> 16) & 0xff;
4292 size = 1 << 20; /* 1MB */
4295 size = 1 << 21; /* 2MB */
4298 size = 1 << 22; /* 4MB */
4301 size = 1 << 23; /* 8MB */
4304 size = 1 << 24; /* 16MB */
4307 size = 1 << 25; /* 32MB */
4310 size = 1 << 26; /* 64MB */
4313 size = 1 << 27; /* 128MB */
4316 size = 1 << 28; /* 256MB */
4319 dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4324 adapter->params.sf_size = size;
4325 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4329 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4335 * We should reject adapters with FLASHes which are too small. So, emit
4338 if (adapter->params.sf_size < FLASH_MIN_SIZE)
4339 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4340 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4345 static void set_pcie_completion_timeout(struct adapter *adapter,
4351 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4353 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4356 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4361 * t4_get_chip_type - Determine chip type from device ID
4362 * @adap: the adapter
4363 * @ver: adapter version
4365 int t4_get_chip_type(struct adapter *adap, int ver)
4367 enum chip_type chip = 0;
4368 u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4370 /* Retrieve adapter's device ID */
4373 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4376 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4379 dev_err(adap, "Device %d is not supported\n",
4380 adap->params.pci.device_id);
4388 * t4_prep_adapter - prepare SW and HW for operation
4389 * @adapter: the adapter
4391 * Initialize adapter SW state for the various HW modules, set initial
4392 * values for some adapter tunables, take PHYs out of reset, and
4393 * initialize the MDIO interface.
4395 int t4_prep_adapter(struct adapter *adapter)
4400 ret = t4_wait_dev_ready(adapter);
4404 pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4405 adapter->params.pci.device_id = adapter->pdev->id.device_id;
4406 adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4409 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4410 * ADAPTER (VERSION << 4 | REVISION)
4412 ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4413 adapter->params.chip = 0;
4416 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4417 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4418 adapter->params.arch.mps_tcam_size =
4419 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4420 adapter->params.arch.mps_rplc_size = 128;
4421 adapter->params.arch.nchan = NCHAN;
4422 adapter->params.arch.vfcount = 128;
4425 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4426 adapter->params.arch.sge_fl_db = 0;
4427 adapter->params.arch.mps_tcam_size =
4428 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4429 adapter->params.arch.mps_rplc_size = 256;
4430 adapter->params.arch.nchan = 2;
4431 adapter->params.arch.vfcount = 256;
4434 dev_err(adapter, "%s: Device %d is not supported\n",
4435 __func__, adapter->params.pci.device_id);
4439 adapter->params.pci.vpd_cap_addr =
4440 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4442 ret = t4_get_flash_params(adapter);
4444 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4449 adapter->params.cim_la_size = CIMLA_SIZE;
4451 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4454 * Default port and clock for debugging in case we can't reach FW.
4456 adapter->params.nports = 1;
4457 adapter->params.portvec = 1;
4458 adapter->params.vpd.cclk = 50000;
4460 /* Set pci completion timeout value to 4 seconds. */
4461 set_pcie_completion_timeout(adapter, 0xd);
4466 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4467 * @adapter: the adapter
4468 * @qid: the Queue ID
4469 * @qtype: the Ingress or Egress type for @qid
4470 * @pbar2_qoffset: BAR2 Queue Offset
4471 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4473 * Returns the BAR2 SGE Queue Registers information associated with the
4474 * indicated Absolute Queue ID. These are passed back in return value
4475 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4476 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4478 * This may return an error which indicates that BAR2 SGE Queue
4479 * registers aren't available. If an error is not returned, then the
4480 * following values are returned:
4482 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4483 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4485 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4486 * require the "Inferred Queue ID" ability may be used. E.g. the
4487 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4488 * then these "Inferred Queue ID" register may not be used.
4490 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4491 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4492 unsigned int *pbar2_qid)
4494 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4495 u64 bar2_page_offset, bar2_qoffset;
4496 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4499 * T4 doesn't support BAR2 SGE Queue registers.
4501 if (is_t4(adapter->params.chip))
4505 * Get our SGE Page Size parameters.
4507 page_shift = adapter->params.sge.hps + 10;
4508 page_size = 1 << page_shift;
4511 * Get the right Queues per Page parameters for our Queue.
4513 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4514 adapter->params.sge.eq_qpp :
4515 adapter->params.sge.iq_qpp);
4516 qpp_mask = (1 << qpp_shift) - 1;
4519 * Calculate the basics of the BAR2 SGE Queue register area:
4520 * o The BAR2 page the Queue registers will be in.
4521 * o The BAR2 Queue ID.
4522 * o The BAR2 Queue ID Offset into the BAR2 page.
4524 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4525 bar2_qid = qid & qpp_mask;
4526 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4529 * If the BAR2 Queue ID Offset is less than the Page Size, then the
4530 * hardware will infer the Absolute Queue ID simply from the writes to
4531 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4532 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
4533 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4534 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4535 * from the BAR2 Page and BAR2 Queue ID.
4537 * One important censequence of this is that some BAR2 SGE registers
4538 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4539 * there. But other registers synthesize the SGE Queue ID purely
4540 * from the writes to the registers -- the Write Combined Doorbell
4541 * Buffer is a good example. These BAR2 SGE Registers are only
4542 * available for those BAR2 SGE Register areas where the SGE Absolute
4543 * Queue ID can be inferred from simple writes.
4545 bar2_qoffset = bar2_page_offset;
4546 bar2_qinferred = (bar2_qid_offset < page_size);
4547 if (bar2_qinferred) {
4548 bar2_qoffset += bar2_qid_offset;
4552 *pbar2_qoffset = bar2_qoffset;
4553 *pbar2_qid = bar2_qid;
4558 * t4_init_sge_params - initialize adap->params.sge
4559 * @adapter: the adapter
4561 * Initialize various fields of the adapter's SGE Parameters structure.
4563 int t4_init_sge_params(struct adapter *adapter)
4565 struct sge_params *sge_params = &adapter->params.sge;
4567 unsigned int s_hps, s_qpp;
4570 * Extract the SGE Page Size for our PF.
4572 hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4573 s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4575 sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4578 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4580 s_qpp = (S_QUEUESPERPAGEPF0 +
4581 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4582 qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4583 sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4584 qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4585 sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4591 * t4_init_tp_params - initialize adap->params.tp
4592 * @adap: the adapter
4594 * Initialize various fields of the adapter's TP Parameters structure.
4596 int t4_init_tp_params(struct adapter *adap)
4601 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4602 adap->params.tp.tre = G_TIMERRESOLUTION(v);
4603 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4605 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4606 for (chan = 0; chan < NCHAN; chan++)
4607 adap->params.tp.tx_modq[chan] = chan;
4610 * Cache the adapter's Compressed Filter Mode and global Incress
4613 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4614 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4615 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4616 &adap->params.tp.ingress_config, 1,
4617 A_TP_INGRESS_CONFIG);
4619 /* For T6, cache the adapter's compressed error vector
4620 * and passing outer header info for encapsulated packets.
4622 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4623 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
4624 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
4628 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4629 * shift positions of several elements of the Compressed Filter Tuple
4630 * for this adapter which we need frequently ...
4632 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4633 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4634 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4635 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4639 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4640 * represents the presense of an Outer VLAN instead of a VNIC ID.
4642 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4643 adap->params.tp.vnic_shift = -1;
4649 * t4_filter_field_shift - calculate filter field shift
4650 * @adap: the adapter
4651 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4653 * Return the shift position of a filter field within the Compressed
4654 * Filter Tuple. The filter field is specified via its selection bit
4655 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
4657 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4659 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4663 if ((filter_mode & filter_sel) == 0)
4666 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4667 switch (filter_mode & sel) {
4669 field_shift += W_FT_FCOE;
4672 field_shift += W_FT_PORT;
4675 field_shift += W_FT_VNIC_ID;
4678 field_shift += W_FT_VLAN;
4681 field_shift += W_FT_TOS;
4684 field_shift += W_FT_PROTOCOL;
4687 field_shift += W_FT_ETHERTYPE;
4690 field_shift += W_FT_MACMATCH;
4693 field_shift += W_FT_MPSHITTYPE;
4695 case F_FRAGMENTATION:
4696 field_shift += W_FT_FRAGMENTATION;
4703 int t4_init_rss_mode(struct adapter *adap, int mbox)
4706 struct fw_rss_vi_config_cmd rvc;
4708 memset(&rvc, 0, sizeof(rvc));
4710 for_each_port(adap, i) {
4711 struct port_info *p = adap2pinfo(adap, i);
4713 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4714 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4715 V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4716 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4717 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4720 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4725 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4729 struct fw_port_cmd c;
4731 memset(&c, 0, sizeof(c));
4733 for_each_port(adap, i) {
4734 unsigned int rss_size = 0;
4735 struct port_info *p = adap2pinfo(adap, i);
4737 while ((adap->params.portvec & (1 << j)) == 0)
4740 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4741 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4742 V_FW_PORT_CMD_PORTID(j));
4743 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4744 FW_PORT_ACTION_GET_PORT_INFO) |
4746 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4750 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4756 p->rss_size = rss_size;
4757 t4_os_set_hw_addr(adap, i, addr);
4759 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
4760 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
4761 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
4762 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
4763 p->mod_type = FW_PORT_MOD_TYPE_NA;
4765 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
4766 be16_to_cpu(c.u.info.acap));