4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <netinet/in.h>
36 #include <rte_interrupts.h>
38 #include <rte_debug.h>
40 #include <rte_atomic.h>
41 #include <rte_branch_prediction.h>
42 #include <rte_memory.h>
43 #include <rte_memzone.h>
44 #include <rte_tailq.h>
46 #include <rte_alarm.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_atomic.h>
50 #include <rte_malloc.h>
51 #include <rte_random.h>
53 #include <rte_byteorder.h>
57 #include "t4_regs_values.h"
58 #include "t4fw_interface.h"
60 static void init_link_config(struct link_config *lc, unsigned int pcaps,
64 * t4_read_mtu_tbl - returns the values in the HW path MTU table
66 * @mtus: where to store the MTU values
67 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
69 * Reads the HW path MTU table.
71 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
76 for (i = 0; i < NMTUS; ++i) {
77 t4_write_reg(adap, A_TP_MTU_TABLE,
78 V_MTUINDEX(0xff) | V_MTUVALUE(i));
79 v = t4_read_reg(adap, A_TP_MTU_TABLE);
80 mtus[i] = G_MTUVALUE(v);
82 mtu_log[i] = G_MTUWIDTH(v);
87 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
89 * @addr: the indirect TP register address
90 * @mask: specifies the field within the register to modify
91 * @val: new value for the field
93 * Sets a field of an indirect TP register to the given value.
95 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
96 unsigned int mask, unsigned int val)
98 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
99 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
100 t4_write_reg(adap, A_TP_PIO_DATA, val);
103 /* The minimum additive increment value for the congestion control table */
104 #define CC_MIN_INCR 2U
107 * t4_load_mtus - write the MTU and congestion control HW tables
109 * @mtus: the values for the MTU table
110 * @alpha: the values for the congestion control alpha parameter
111 * @beta: the values for the congestion control beta parameter
113 * Write the HW MTU table with the supplied MTUs and the high-speed
114 * congestion control table with the supplied alpha, beta, and MTUs.
115 * We write the two tables together because the additive increments
116 * depend on the MTUs.
118 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
119 const unsigned short *alpha, const unsigned short *beta)
121 static const unsigned int avg_pkts[NCCTRL_WIN] = {
122 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
123 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
124 28672, 40960, 57344, 81920, 114688, 163840, 229376
129 for (i = 0; i < NMTUS; ++i) {
130 unsigned int mtu = mtus[i];
131 unsigned int log2 = cxgbe_fls(mtu);
133 if (!(mtu & ((1 << log2) >> 2))) /* round */
135 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
136 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
138 for (w = 0; w < NCCTRL_WIN; ++w) {
141 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
144 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
145 (w << 16) | (beta[w] << 13) | inc);
151 * t4_wait_op_done_val - wait until an operation is completed
152 * @adapter: the adapter performing the operation
153 * @reg: the register to check for completion
154 * @mask: a single-bit field within @reg that indicates completion
155 * @polarity: the value of the field when the operation is completed
156 * @attempts: number of check iterations
157 * @delay: delay in usecs between iterations
158 * @valp: where to store the value of the register at completion time
160 * Wait until an operation is completed by checking a bit in a register
161 * up to @attempts times. If @valp is not NULL the value of the register
162 * at the time it indicated completion is stored there. Returns 0 if the
163 * operation completes and -EAGAIN otherwise.
165 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
166 int polarity, int attempts, int delay, u32 *valp)
169 u32 val = t4_read_reg(adapter, reg);
171 if (!!(val & mask) == polarity) {
184 * t4_set_reg_field - set a register field to a value
185 * @adapter: the adapter to program
186 * @addr: the register address
187 * @mask: specifies the portion of the register to modify
188 * @val: the new value for the register field
190 * Sets a register field specified by the supplied mask to the
193 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
196 u32 v = t4_read_reg(adapter, addr) & ~mask;
198 t4_write_reg(adapter, addr, v | val);
199 (void)t4_read_reg(adapter, addr); /* flush */
203 * t4_read_indirect - read indirectly addressed registers
205 * @addr_reg: register holding the indirect address
206 * @data_reg: register holding the value of the indirect register
207 * @vals: where the read register values are stored
208 * @nregs: how many indirect registers to read
209 * @start_idx: index of first indirect register to read
211 * Reads registers that are accessed indirectly through an address/data
214 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
215 unsigned int data_reg, u32 *vals, unsigned int nregs,
216 unsigned int start_idx)
219 t4_write_reg(adap, addr_reg, start_idx);
220 *vals++ = t4_read_reg(adap, data_reg);
226 * t4_write_indirect - write indirectly addressed registers
228 * @addr_reg: register holding the indirect addresses
229 * @data_reg: register holding the value for the indirect registers
230 * @vals: values to write
231 * @nregs: how many indirect registers to write
232 * @start_idx: address of first indirect register to write
234 * Writes a sequential block of registers that are accessed indirectly
235 * through an address/data register pair.
237 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
238 unsigned int data_reg, const u32 *vals,
239 unsigned int nregs, unsigned int start_idx)
242 t4_write_reg(adap, addr_reg, start_idx++);
243 t4_write_reg(adap, data_reg, *vals++);
248 * t4_report_fw_error - report firmware error
251 * The adapter firmware can indicate error conditions to the host.
252 * If the firmware has indicated an error, print out the reason for
253 * the firmware error.
255 static void t4_report_fw_error(struct adapter *adap)
257 static const char * const reason[] = {
258 "Crash", /* PCIE_FW_EVAL_CRASH */
259 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
260 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
261 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
262 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
263 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
264 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
265 "Reserved", /* reserved */
269 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
270 if (pcie_fw & F_PCIE_FW_ERR)
271 pr_err("%s: Firmware reports adapter error: %s\n",
272 __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
276 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
278 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
281 for ( ; nflit; nflit--, mbox_addr += 8)
282 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
286 * Handle a FW assertion reported in a mailbox.
288 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
290 struct fw_debug_cmd asrt;
292 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
293 pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
294 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
295 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
298 #define X_CIM_PF_NOACCESS 0xeeeeeeee
301 * If the Host OS Driver needs locking arround accesses to the mailbox, this
302 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
304 /* makes single-statement usage a bit cleaner ... */
305 #ifdef T4_OS_NEEDS_MBOX_LOCKING
306 #define T4_OS_MBOX_LOCKING(x) x
308 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
312 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
314 * @mbox: index of the mailbox to use
315 * @cmd: the command to write
316 * @size: command length in bytes
317 * @rpl: where to optionally store the reply
318 * @sleep_ok: if true we may sleep while awaiting command completion
319 * @timeout: time to wait for command to finish before timing out
320 * (negative implies @sleep_ok=false)
322 * Sends the given command to FW through the selected mailbox and waits
323 * for the FW to execute the command. If @rpl is not %NULL it is used to
324 * store the FW's reply to the command. The command and its optional
325 * reply are of the same length. Some FW commands like RESET and
326 * INITIALIZE can take a considerable amount of time to execute.
327 * @sleep_ok determines whether we may sleep while awaiting the response.
328 * If sleeping is allowed we use progressive backoff otherwise we spin.
329 * Note that passing in a negative @timeout is an alternate mechanism
330 * for specifying @sleep_ok=false. This is useful when a higher level
331 * interface allows for specification of @timeout but not @sleep_ok ...
333 * Returns 0 on success or a negative errno on failure. A
334 * failure can happen either because we are not able to execute the
335 * command or FW executes it but signals an error. In the latter case
336 * the return value is the error code indicated by FW (negated).
338 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
339 const void __attribute__((__may_alias__)) *cmd,
340 int size, void *rpl, bool sleep_ok, int timeout)
343 * We delay in small increments at first in an effort to maintain
344 * responsiveness for simple, fast executing commands but then back
345 * off to larger delays to a maximum retry delay.
347 static const int delay[] = {
348 1, 1, 3, 5, 10, 10, 20, 50, 100
354 unsigned int delay_idx;
355 __be64 *temp = (__be64 *)malloc(size * sizeof(char));
357 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
358 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
360 struct mbox_entry entry;
366 if ((size & 15) || size > MBOX_LEN) {
372 memcpy(p, (const __be64 *)cmd, size);
375 * If we have a negative timeout, that implies that we can't sleep.
382 #ifdef T4_OS_NEEDS_MBOX_LOCKING
384 * Queue ourselves onto the mailbox access list. When our entry is at
385 * the front of the list, we have rights to access the mailbox. So we
386 * wait [for a while] till we're at the front [or bail out with an
389 t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
394 for (i = 0; ; i += ms) {
396 * If we've waited too long, return a busy indication. This
397 * really ought to be based on our initial position in the
398 * mailbox access list but this is a start. We very rarely
399 * contend on access to the mailbox ... Also check for a
400 * firmware error which we'll report as a device error.
402 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
403 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
404 t4_os_atomic_list_del(&entry, &adap->mbox_list,
406 t4_report_fw_error(adap);
407 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
411 * If we're at the head, break out and start the mailbox
414 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
418 * Delay for a bit before checking again ...
421 ms = delay[delay_idx]; /* last element may repeat */
422 if (delay_idx < ARRAY_SIZE(delay) - 1)
429 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
432 * Attempt to gain access to the mailbox.
434 for (i = 0; i < 4; i++) {
435 ctl = t4_read_reg(adap, ctl_reg);
437 if (v != X_MBOWNER_NONE)
442 * If we were unable to gain access, dequeue ourselves from the
443 * mailbox atomic access list and report the error to our caller.
445 if (v != X_MBOWNER_PL) {
446 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
449 t4_report_fw_error(adap);
450 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
454 * If we gain ownership of the mailbox and there's a "valid" message
455 * in it, this is likely an asynchronous error message from the
456 * firmware. So we'll report that and then proceed on with attempting
457 * to issue our own command ... which may well fail if the error
458 * presaged the firmware crashing ...
460 if (ctl & F_MBMSGVALID) {
461 dev_err(adap, "found VALID command in mbox %u: "
462 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
463 (unsigned long long)t4_read_reg64(adap, data_reg),
464 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
465 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
466 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
467 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
468 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
469 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
470 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
474 * Copy in the new mailbox command and send it on its way ...
476 for (i = 0; i < size; i += 8, p++)
477 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
479 CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
480 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
481 (unsigned long long)t4_read_reg64(adap, data_reg),
482 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
483 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
484 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
485 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
486 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
487 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
488 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
490 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
491 t4_read_reg(adap, ctl_reg); /* flush write */
497 * Loop waiting for the reply; bail out if we time out or the firmware
500 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
501 for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
503 ms = delay[delay_idx]; /* last element may repeat */
504 if (delay_idx < ARRAY_SIZE(delay) - 1)
511 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
512 v = t4_read_reg(adap, ctl_reg);
513 if (v == X_CIM_PF_NOACCESS)
515 if (G_MBOWNER(v) == X_MBOWNER_PL) {
516 if (!(v & F_MBMSGVALID)) {
517 t4_write_reg(adap, ctl_reg,
518 V_MBOWNER(X_MBOWNER_NONE));
522 CXGBE_DEBUG_MBOX(adap,
523 "%s: mbox %u: %016llx %016llx %016llx %016llx "
524 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
525 (unsigned long long)t4_read_reg64(adap, data_reg),
526 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
527 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
528 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
529 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
530 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
531 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
532 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
534 CXGBE_DEBUG_MBOX(adap,
535 "command %#x completed in %d ms (%ssleeping)\n",
537 i + ms, sleep_ok ? "" : "non-");
539 res = t4_read_reg64(adap, data_reg);
540 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
541 fw_asrt(adap, data_reg);
542 res = V_FW_CMD_RETVAL(EIO);
544 get_mbox_rpl(adap, rpl, size / 8, data_reg);
546 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
548 t4_os_atomic_list_del(&entry, &adap->mbox_list,
550 return -G_FW_CMD_RETVAL((int)res);
555 * We timed out waiting for a reply to our mailbox command. Report
556 * the error and also check to see if the firmware reported any
559 dev_err(adap, "command %#x in mailbox %d timed out\n",
560 *(const u8 *)cmd, mbox);
561 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
564 t4_report_fw_error(adap);
566 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
569 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
570 void *rpl, bool sleep_ok)
572 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
577 * t4_get_regs_len - return the size of the chips register set
578 * @adapter: the adapter
580 * Returns the size of the chip's BAR0 register space.
582 unsigned int t4_get_regs_len(struct adapter *adapter)
584 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
586 switch (chip_version) {
589 return T5_REGMAP_SIZE;
593 "Unsupported chip version %d\n", chip_version);
598 * t4_get_regs - read chip registers into provided buffer
600 * @buf: register buffer
601 * @buf_size: size (in bytes) of register buffer
603 * If the provided register buffer isn't large enough for the chip's
604 * full register range, the register dump will be truncated to the
605 * register buffer's size.
607 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
609 static const unsigned int t5_reg_ranges[] = {
1384 static const unsigned int t6_reg_ranges[] = {
1945 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1946 const unsigned int *reg_ranges;
1947 int reg_ranges_size, range;
1948 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1950 /* Select the right set of register ranges to dump depending on the
1951 * adapter chip type.
1953 switch (chip_version) {
1955 reg_ranges = t5_reg_ranges;
1956 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1960 reg_ranges = t6_reg_ranges;
1961 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1966 "Unsupported chip version %d\n", chip_version);
1970 /* Clear the register buffer and insert the appropriate register
1971 * values selected by the above register ranges.
1973 memset(buf, 0, buf_size);
1974 for (range = 0; range < reg_ranges_size; range += 2) {
1975 unsigned int reg = reg_ranges[range];
1976 unsigned int last_reg = reg_ranges[range + 1];
1977 u32 *bufp = (u32 *)((char *)buf + reg);
1979 /* Iterate across the register range filling in the register
1980 * buffer but don't write past the end of the register buffer.
1982 while (reg <= last_reg && bufp < buf_end) {
1983 *bufp++ = t4_read_reg(adap, reg);
1989 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1990 #define EEPROM_DELAY 10 /* 10us per poll spin */
1991 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
1993 #define EEPROM_STAT_ADDR 0x7bfc
1996 * Small utility function to wait till any outstanding VPD Access is complete.
1997 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1998 * VPD Access in flight. This allows us to handle the problem of having a
1999 * previous VPD Access time out and prevent an attempt to inject a new VPD
2000 * Request before any in-flight VPD request has completed.
2002 static int t4_seeprom_wait(struct adapter *adapter)
2004 unsigned int base = adapter->params.pci.vpd_cap_addr;
2007 /* If no VPD Access is in flight, we can just return success right
2010 if (!adapter->vpd_busy)
2013 /* Poll the VPD Capability Address/Flag register waiting for it
2014 * to indicate that the operation is complete.
2016 max_poll = EEPROM_MAX_POLL;
2020 udelay(EEPROM_DELAY);
2021 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2023 /* If the operation is complete, mark the VPD as no longer
2024 * busy and return success.
2026 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2027 adapter->vpd_busy = 0;
2030 } while (--max_poll);
2032 /* Failure! Note that we leave the VPD Busy status set in order to
2033 * avoid pushing a new VPD Access request into the VPD Capability till
2034 * the current operation eventually succeeds. It's a bug to issue a
2035 * new request when an existing request is in flight and will result
2036 * in corrupt hardware state.
2042 * t4_seeprom_read - read a serial EEPROM location
2043 * @adapter: adapter to read
2044 * @addr: EEPROM virtual address
2045 * @data: where to store the read data
2047 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2048 * VPD capability. Note that this function must be called with a virtual
2051 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2053 unsigned int base = adapter->params.pci.vpd_cap_addr;
2056 /* VPD Accesses must alway be 4-byte aligned!
2058 if (addr >= EEPROMVSIZE || (addr & 3))
2061 /* Wait for any previous operation which may still be in flight to
2064 ret = t4_seeprom_wait(adapter);
2066 dev_err(adapter, "VPD still busy from previous operation\n");
2070 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2071 * for our request to complete. If it doesn't complete, note the
2072 * error and return it to our caller. Note that we do not reset the
2075 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2076 adapter->vpd_busy = 1;
2077 adapter->vpd_flag = PCI_VPD_ADDR_F;
2078 ret = t4_seeprom_wait(adapter);
2080 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2084 /* Grab the returned data, swizzle it into our endianness and
2087 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2088 *data = le32_to_cpu(*data);
2093 * t4_seeprom_write - write a serial EEPROM location
2094 * @adapter: adapter to write
2095 * @addr: virtual EEPROM address
2096 * @data: value to write
2098 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2099 * VPD capability. Note that this function must be called with a virtual
2102 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2104 unsigned int base = adapter->params.pci.vpd_cap_addr;
2109 /* VPD Accesses must alway be 4-byte aligned!
2111 if (addr >= EEPROMVSIZE || (addr & 3))
2114 /* Wait for any previous operation which may still be in flight to
2117 ret = t4_seeprom_wait(adapter);
2119 dev_err(adapter, "VPD still busy from previous operation\n");
2123 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2124 * for our request to complete. If it doesn't complete, note the
2125 * error and return it to our caller. Note that we do not reset the
2128 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2130 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2131 (u16)addr | PCI_VPD_ADDR_F);
2132 adapter->vpd_busy = 1;
2133 adapter->vpd_flag = 0;
2134 ret = t4_seeprom_wait(adapter);
2136 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2140 /* Reset PCI_VPD_DATA register after a transaction and wait for our
2141 * request to complete. If it doesn't complete, return error.
2143 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2144 max_poll = EEPROM_MAX_POLL;
2146 udelay(EEPROM_DELAY);
2147 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2148 } while ((stats_reg & 0x1) && --max_poll);
2152 /* Return success! */
2157 * t4_seeprom_wp - enable/disable EEPROM write protection
2158 * @adapter: the adapter
2159 * @enable: whether to enable or disable write protection
2161 * Enables or disables write protection on the serial EEPROM.
2163 int t4_seeprom_wp(struct adapter *adapter, int enable)
2165 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2169 * t4_config_rss_range - configure a portion of the RSS mapping table
2170 * @adapter: the adapter
2171 * @mbox: mbox to use for the FW command
2172 * @viid: virtual interface whose RSS subtable is to be written
2173 * @start: start entry in the table to write
2174 * @n: how many table entries to write
2175 * @rspq: values for the "response queue" (Ingress Queue) lookup table
2176 * @nrspq: number of values in @rspq
2178 * Programs the selected part of the VI's RSS mapping table with the
2179 * provided values. If @nrspq < @n the supplied values are used repeatedly
2180 * until the full table range is populated.
2182 * The caller must ensure the values in @rspq are in the range allowed for
2185 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2186 int start, int n, const u16 *rspq, unsigned int nrspq)
2189 const u16 *rsp = rspq;
2190 const u16 *rsp_end = rspq + nrspq;
2191 struct fw_rss_ind_tbl_cmd cmd;
2193 memset(&cmd, 0, sizeof(cmd));
2194 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2195 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2196 V_FW_RSS_IND_TBL_CMD_VIID(viid));
2197 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2200 * Each firmware RSS command can accommodate up to 32 RSS Ingress
2201 * Queue Identifiers. These Ingress Queue IDs are packed three to
2202 * a 32-bit word as 10-bit values with the upper remaining 2 bits
2206 int nq = min(n, 32);
2208 __be32 *qp = &cmd.iq0_to_iq2;
2211 * Set up the firmware RSS command header to send the next
2212 * "nq" Ingress Queue IDs to the firmware.
2214 cmd.niqid = cpu_to_be16(nq);
2215 cmd.startidx = cpu_to_be16(start);
2218 * "nq" more done for the start of the next loop.
2224 * While there are still Ingress Queue IDs to stuff into the
2225 * current firmware RSS command, retrieve them from the
2226 * Ingress Queue ID array and insert them into the command.
2230 * Grab up to the next 3 Ingress Queue IDs (wrapping
2231 * around the Ingress Queue ID array if necessary) and
2232 * insert them into the firmware RSS command at the
2233 * current 3-tuple position within the commad.
2237 int nqbuf = min(3, nq);
2243 while (nqbuf && nq_packed < 32) {
2250 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2251 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2252 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2256 * Send this portion of the RRS table update to the firmware;
2257 * bail out on any errors.
2259 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2268 * t4_config_vi_rss - configure per VI RSS settings
2269 * @adapter: the adapter
2270 * @mbox: mbox to use for the FW command
2273 * @defq: id of the default RSS queue for the VI.
2275 * Configures VI-specific RSS properties.
2277 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2278 unsigned int flags, unsigned int defq)
2280 struct fw_rss_vi_config_cmd c;
2282 memset(&c, 0, sizeof(c));
2283 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2284 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2285 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2286 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2287 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2288 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2289 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2293 * init_cong_ctrl - initialize congestion control parameters
2294 * @a: the alpha values for congestion control
2295 * @b: the beta values for congestion control
2297 * Initialize the congestion control parameters.
2299 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2303 for (i = 0; i < 9; i++) {
2357 #define INIT_CMD(var, cmd, rd_wr) do { \
2358 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2359 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2360 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2363 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2365 u32 cclk_param, cclk_val;
2369 * Ask firmware for the Core Clock since it knows how to translate the
2370 * Reference Clock ('V2') VPD field into a Core Clock value ...
2372 cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2373 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2374 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2375 1, &cclk_param, &cclk_val);
2377 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2383 dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2387 /* serial flash and firmware constants and flash config file constants */
2389 SF_ATTEMPTS = 10, /* max retries for SF operations */
2391 /* flash command opcodes */
2392 SF_PROG_PAGE = 2, /* program page */
2393 SF_WR_DISABLE = 4, /* disable writes */
2394 SF_RD_STATUS = 5, /* read status register */
2395 SF_WR_ENABLE = 6, /* enable writes */
2396 SF_RD_DATA_FAST = 0xb, /* read flash */
2397 SF_RD_ID = 0x9f, /* read ID */
2398 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2402 * sf1_read - read data from the serial flash
2403 * @adapter: the adapter
2404 * @byte_cnt: number of bytes to read
2405 * @cont: whether another operation will be chained
2406 * @lock: whether to lock SF for PL access only
2407 * @valp: where to store the read data
2409 * Reads up to 4 bytes of data from the serial flash. The location of
2410 * the read needs to be specified prior to calling this by issuing the
2411 * appropriate commands to the serial flash.
2413 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2414 int lock, u32 *valp)
2418 if (!byte_cnt || byte_cnt > 4)
2420 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2422 t4_write_reg(adapter, A_SF_OP,
2423 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2424 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2426 *valp = t4_read_reg(adapter, A_SF_DATA);
2431 * sf1_write - write data to the serial flash
2432 * @adapter: the adapter
2433 * @byte_cnt: number of bytes to write
2434 * @cont: whether another operation will be chained
2435 * @lock: whether to lock SF for PL access only
2436 * @val: value to write
2438 * Writes up to 4 bytes of data to the serial flash. The location of
2439 * the write needs to be specified prior to calling this by issuing the
2440 * appropriate commands to the serial flash.
2442 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2445 if (!byte_cnt || byte_cnt > 4)
2447 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2449 t4_write_reg(adapter, A_SF_DATA, val);
2450 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2451 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2452 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2456 * t4_read_flash - read words from serial flash
2457 * @adapter: the adapter
2458 * @addr: the start address for the read
2459 * @nwords: how many 32-bit words to read
2460 * @data: where to store the read data
2461 * @byte_oriented: whether to store data as bytes or as words
2463 * Read the specified number of 32-bit words from the serial flash.
2464 * If @byte_oriented is set the read data is stored as a byte array
2465 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2466 * natural endianness.
2468 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2469 unsigned int nwords, u32 *data, int byte_oriented)
2473 if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2477 addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2479 ret = sf1_write(adapter, 4, 1, 0, addr);
2483 ret = sf1_read(adapter, 1, 1, 0, data);
2487 for ( ; nwords; nwords--, data++) {
2488 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2490 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
2494 *data = cpu_to_be32(*data);
2500 * t4_get_fw_version - read the firmware version
2501 * @adapter: the adapter
2502 * @vers: where to place the version
2504 * Reads the FW version from flash.
2506 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2508 return t4_read_flash(adapter, FLASH_FW_START +
2509 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2513 * t4_get_tp_version - read the TP microcode version
2514 * @adapter: the adapter
2515 * @vers: where to place the version
2517 * Reads the TP microcode version from flash.
2519 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2521 return t4_read_flash(adapter, FLASH_FW_START +
2522 offsetof(struct fw_hdr, tp_microcode_ver),
2526 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
2530 * t4_link_l1cfg - apply link configuration to MAC/PHY
2531 * @phy: the PHY to setup
2532 * @mac: the MAC to setup
2533 * @lc: the requested link configuration
2535 * Set up a port's MAC and PHY according to a desired link configuration.
2536 * - If the PHY can auto-negotiate first decide what to advertise, then
2537 * enable/disable auto-negotiation as desired, and reset.
2538 * - If the PHY does not auto-negotiate just reset it.
2539 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2540 * otherwise do it later based on the outcome of auto-negotiation.
2542 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2543 struct link_config *lc)
2545 struct fw_port_cmd c;
2546 unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
2547 unsigned int fc, fec;
2551 if (lc->requested_fc & PAUSE_RX)
2552 fc |= FW_PORT_CAP_FC_RX;
2553 if (lc->requested_fc & PAUSE_TX)
2554 fc |= FW_PORT_CAP_FC_TX;
2557 if (lc->requested_fec & FEC_RS)
2558 fec |= FW_PORT_CAP_FEC_RS;
2559 if (lc->requested_fec & FEC_BASER_RS)
2560 fec |= FW_PORT_CAP_FEC_BASER_RS;
2561 if (lc->requested_fec & FEC_RESERVED)
2562 fec |= FW_PORT_CAP_FEC_RESERVED;
2564 memset(&c, 0, sizeof(c));
2565 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2566 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2567 V_FW_PORT_CMD_PORTID(port));
2569 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2572 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2573 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2575 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2576 lc->fec = lc->requested_fec;
2577 } else if (lc->autoneg == AUTONEG_DISABLE) {
2578 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
2580 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2581 lc->fec = lc->requested_fec;
2583 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | fec | mdi);
2586 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2590 * t4_flash_cfg_addr - return the address of the flash configuration file
2591 * @adapter: the adapter
2593 * Return the address within the flash where the Firmware Configuration
2594 * File is stored, or an error if the device FLASH is too small to contain
2595 * a Firmware Configuration File.
2597 int t4_flash_cfg_addr(struct adapter *adapter)
2600 * If the device FLASH isn't large enough to hold a Firmware
2601 * Configuration File, return an error.
2603 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2606 return FLASH_CFG_START;
2609 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2612 * t4_intr_enable - enable interrupts
2613 * @adapter: the adapter whose interrupts should be enabled
2615 * Enable PF-specific interrupts for the calling function and the top-level
2616 * interrupt concentrator for global interrupts. Interrupts are already
2617 * enabled at each module, here we just enable the roots of the interrupt
2620 * Note: this function should be called only when the driver manages
2621 * non PF-specific interrupts from the various HW modules. Only one PCI
2622 * function at a time should be doing this.
2624 void t4_intr_enable(struct adapter *adapter)
2627 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2628 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2629 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2631 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2632 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2633 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2634 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2635 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2636 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2637 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2638 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2639 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2640 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2641 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2645 * t4_intr_disable - disable interrupts
2646 * @adapter: the adapter whose interrupts should be disabled
2648 * Disable interrupts. We only disable the top-level interrupt
2649 * concentrators. The caller must be a PCI function managing global
2652 void t4_intr_disable(struct adapter *adapter)
2654 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2655 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2656 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2658 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2659 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2663 * t4_get_port_type_description - return Port Type string description
2664 * @port_type: firmware Port Type enumeration
2666 const char *t4_get_port_type_description(enum fw_port_type port_type)
2668 static const char * const port_type_description[] = {
2693 if (port_type < ARRAY_SIZE(port_type_description))
2694 return port_type_description[port_type];
2699 * t4_get_mps_bg_map - return the buffer groups associated with a port
2700 * @adap: the adapter
2701 * @idx: the port index
2703 * Returns a bitmap indicating which MPS buffer groups are associated
2704 * with the given port. Bit i is set if buffer group i is used by the
2707 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
2709 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
2712 return idx == 0 ? 0xf : 0;
2714 return idx < 2 ? (3 << (2 * idx)) : 0;
2719 * t4_get_port_stats - collect port statistics
2720 * @adap: the adapter
2721 * @idx: the port index
2722 * @p: the stats structure to fill
2724 * Collect statistics related to the given port from HW.
2726 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2728 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2730 #define GET_STAT(name) \
2731 t4_read_reg64(adap, \
2732 (is_t4(adap->params.chip) ? \
2733 PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2734 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2735 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2737 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2738 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2739 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2740 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2741 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2742 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2743 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2744 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2745 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2746 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2747 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2748 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2749 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2750 p->tx_drop = GET_STAT(TX_PORT_DROP);
2751 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2752 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2753 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2754 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2755 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2756 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2757 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2758 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2759 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2761 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2762 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2763 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2764 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2765 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2766 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2767 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2768 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2769 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2770 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2771 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2772 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2773 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2774 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2775 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2776 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2777 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2778 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2779 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2780 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2781 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2782 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2783 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2784 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2785 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2786 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2787 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2788 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2789 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2790 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2791 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2792 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2793 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2794 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2795 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2802 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
2803 * @adap: The adapter
2805 * @stats: Current stats to fill
2806 * @offset: Previous stats snapshot
2808 void t4_get_port_stats_offset(struct adapter *adap, int idx,
2809 struct port_stats *stats,
2810 struct port_stats *offset)
2815 t4_get_port_stats(adap, idx, stats);
2816 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
2817 i < (sizeof(struct port_stats) / sizeof(u64));
2823 * t4_clr_port_stats - clear port statistics
2824 * @adap: the adapter
2825 * @idx: the port index
2827 * Clear HW statistics for the given port.
2829 void t4_clr_port_stats(struct adapter *adap, int idx)
2832 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2835 if (is_t4(adap->params.chip))
2836 port_base_addr = PORT_BASE(idx);
2838 port_base_addr = T5_PORT_BASE(idx);
2840 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
2841 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
2842 t4_write_reg(adap, port_base_addr + i, 0);
2843 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
2844 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
2845 t4_write_reg(adap, port_base_addr + i, 0);
2846 for (i = 0; i < 4; i++)
2847 if (bgmap & (1 << i)) {
2849 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
2852 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
2858 * t4_fw_hello - establish communication with FW
2859 * @adap: the adapter
2860 * @mbox: mailbox to use for the FW command
2861 * @evt_mbox: mailbox to receive async FW events
2862 * @master: specifies the caller's willingness to be the device master
2863 * @state: returns the current device state (if non-NULL)
2865 * Issues a command to establish communication with FW. Returns either
2866 * an error (negative integer) or the mailbox of the Master PF.
2868 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2869 enum dev_master master, enum dev_state *state)
2872 struct fw_hello_cmd c;
2874 unsigned int master_mbox;
2875 int retries = FW_CMD_HELLO_RETRIES;
2878 memset(&c, 0, sizeof(c));
2879 INIT_CMD(c, HELLO, WRITE);
2880 c.err_to_clearinit = cpu_to_be32(
2881 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2882 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2883 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2884 M_FW_HELLO_CMD_MBMASTER) |
2885 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2886 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
2887 F_FW_HELLO_CMD_CLEARINIT);
2890 * Issue the HELLO command to the firmware. If it's not successful
2891 * but indicates that we got a "busy" or "timeout" condition, retry
2892 * the HELLO until we exhaust our retry limit. If we do exceed our
2893 * retry limit, check to see if the firmware left us any error
2894 * information and report that if so ...
2896 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2897 if (ret != FW_SUCCESS) {
2898 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2900 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
2901 t4_report_fw_error(adap);
2905 v = be32_to_cpu(c.err_to_clearinit);
2906 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
2908 if (v & F_FW_HELLO_CMD_ERR)
2909 *state = DEV_STATE_ERR;
2910 else if (v & F_FW_HELLO_CMD_INIT)
2911 *state = DEV_STATE_INIT;
2913 *state = DEV_STATE_UNINIT;
2917 * If we're not the Master PF then we need to wait around for the
2918 * Master PF Driver to finish setting up the adapter.
2920 * Note that we also do this wait if we're a non-Master-capable PF and
2921 * there is no current Master PF; a Master PF may show up momentarily
2922 * and we wouldn't want to fail pointlessly. (This can happen when an
2923 * OS loads lots of different drivers rapidly at the same time). In
2924 * this case, the Master PF returned by the firmware will be
2925 * M_PCIE_FW_MASTER so the test below will work ...
2927 if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
2928 master_mbox != mbox) {
2929 int waiting = FW_CMD_HELLO_TIMEOUT;
2932 * Wait for the firmware to either indicate an error or
2933 * initialized state. If we see either of these we bail out
2934 * and report the issue to the caller. If we exhaust the
2935 * "hello timeout" and we haven't exhausted our retries, try
2936 * again. Otherwise bail with a timeout error.
2945 * If neither Error nor Initialialized are indicated
2946 * by the firmware keep waiting till we exaust our
2947 * timeout ... and then retry if we haven't exhausted
2950 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
2951 if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
2962 * We either have an Error or Initialized condition
2963 * report errors preferentially.
2966 if (pcie_fw & F_PCIE_FW_ERR)
2967 *state = DEV_STATE_ERR;
2968 else if (pcie_fw & F_PCIE_FW_INIT)
2969 *state = DEV_STATE_INIT;
2973 * If we arrived before a Master PF was selected and
2974 * there's not a valid Master PF, grab its identity
2977 if (master_mbox == M_PCIE_FW_MASTER &&
2978 (pcie_fw & F_PCIE_FW_MASTER_VLD))
2979 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
2988 * t4_fw_bye - end communication with FW
2989 * @adap: the adapter
2990 * @mbox: mailbox to use for the FW command
2992 * Issues a command to terminate communication with FW.
2994 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2996 struct fw_bye_cmd c;
2998 memset(&c, 0, sizeof(c));
2999 INIT_CMD(c, BYE, WRITE);
3000 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3004 * t4_fw_reset - issue a reset to FW
3005 * @adap: the adapter
3006 * @mbox: mailbox to use for the FW command
3007 * @reset: specifies the type of reset to perform
3009 * Issues a reset command of the specified type to FW.
3011 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3013 struct fw_reset_cmd c;
3015 memset(&c, 0, sizeof(c));
3016 INIT_CMD(c, RESET, WRITE);
3017 c.val = cpu_to_be32(reset);
3018 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3022 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3023 * @adap: the adapter
3024 * @mbox: mailbox to use for the FW RESET command (if desired)
3025 * @force: force uP into RESET even if FW RESET command fails
3027 * Issues a RESET command to firmware (if desired) with a HALT indication
3028 * and then puts the microprocessor into RESET state. The RESET command
3029 * will only be issued if a legitimate mailbox is provided (mbox <=
3030 * M_PCIE_FW_MASTER).
3032 * This is generally used in order for the host to safely manipulate the
3033 * adapter without fear of conflicting with whatever the firmware might
3034 * be doing. The only way out of this state is to RESTART the firmware
3037 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3042 * If a legitimate mailbox is provided, issue a RESET command
3043 * with a HALT indication.
3045 if (mbox <= M_PCIE_FW_MASTER) {
3046 struct fw_reset_cmd c;
3048 memset(&c, 0, sizeof(c));
3049 INIT_CMD(c, RESET, WRITE);
3050 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3051 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3052 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3056 * Normally we won't complete the operation if the firmware RESET
3057 * command fails but if our caller insists we'll go ahead and put the
3058 * uP into RESET. This can be useful if the firmware is hung or even
3059 * missing ... We'll have to take the risk of putting the uP into
3060 * RESET without the cooperation of firmware in that case.
3062 * We also force the firmware's HALT flag to be on in case we bypassed
3063 * the firmware RESET command above or we're dealing with old firmware
3064 * which doesn't have the HALT capability. This will serve as a flag
3065 * for the incoming firmware to know that it's coming out of a HALT
3066 * rather than a RESET ... if it's new enough to understand that ...
3068 if (ret == 0 || force) {
3069 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3070 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3075 * And we always return the result of the firmware RESET command
3076 * even when we force the uP into RESET ...
3082 * t4_fw_restart - restart the firmware by taking the uP out of RESET
3083 * @adap: the adapter
3084 * @mbox: mailbox to use for the FW RESET command (if desired)
3085 * @reset: if we want to do a RESET to restart things
3087 * Restart firmware previously halted by t4_fw_halt(). On successful
3088 * return the previous PF Master remains as the new PF Master and there
3089 * is no need to issue a new HELLO command, etc.
3091 * We do this in two ways:
3093 * 1. If we're dealing with newer firmware we'll simply want to take
3094 * the chip's microprocessor out of RESET. This will cause the
3095 * firmware to start up from its start vector. And then we'll loop
3096 * until the firmware indicates it's started again (PCIE_FW.HALT
3097 * reset to 0) or we timeout.
3099 * 2. If we're dealing with older firmware then we'll need to RESET
3100 * the chip since older firmware won't recognize the PCIE_FW.HALT
3101 * flag and automatically RESET itself on startup.
3103 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3107 * Since we're directing the RESET instead of the firmware
3108 * doing it automatically, we need to clear the PCIE_FW.HALT
3111 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3114 * If we've been given a valid mailbox, first try to get the
3115 * firmware to do the RESET. If that works, great and we can
3116 * return success. Otherwise, if we haven't been given a
3117 * valid mailbox or the RESET command failed, fall back to
3118 * hitting the chip with a hammer.
3120 if (mbox <= M_PCIE_FW_MASTER) {
3121 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3123 if (t4_fw_reset(adap, mbox,
3124 F_PIORST | F_PIORSTMODE) == 0)
3128 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3133 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3134 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3135 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3146 * t4_fixup_host_params_compat - fix up host-dependent parameters
3147 * @adap: the adapter
3148 * @page_size: the host's Base Page Size
3149 * @cache_line_size: the host's Cache Line Size
3150 * @chip_compat: maintain compatibility with designated chip
3152 * Various registers in the chip contain values which are dependent on the
3153 * host's Base Page and Cache Line Sizes. This function will fix all of
3154 * those registers with the appropriate values as passed in ...
3156 * @chip_compat is used to limit the set of changes that are made
3157 * to be compatible with the indicated chip release. This is used by
3158 * drivers to maintain compatibility with chip register settings when
3159 * the drivers haven't [yet] been updated with new chip support.
3161 int t4_fixup_host_params_compat(struct adapter *adap,
3162 unsigned int page_size,
3163 unsigned int cache_line_size,
3164 enum chip_type chip_compat)
3166 unsigned int page_shift = cxgbe_fls(page_size) - 1;
3167 unsigned int sge_hps = page_shift - 10;
3168 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3169 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3170 unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3172 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3173 V_HOSTPAGESIZEPF0(sge_hps) |
3174 V_HOSTPAGESIZEPF1(sge_hps) |
3175 V_HOSTPAGESIZEPF2(sge_hps) |
3176 V_HOSTPAGESIZEPF3(sge_hps) |
3177 V_HOSTPAGESIZEPF4(sge_hps) |
3178 V_HOSTPAGESIZEPF5(sge_hps) |
3179 V_HOSTPAGESIZEPF6(sge_hps) |
3180 V_HOSTPAGESIZEPF7(sge_hps));
3182 if (is_t4(adap->params.chip) || is_t4(chip_compat))
3183 t4_set_reg_field(adap, A_SGE_CONTROL,
3184 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3185 F_EGRSTATUSPAGESIZE,
3186 V_INGPADBOUNDARY(fl_align_log -
3187 X_INGPADBOUNDARY_SHIFT) |
3188 V_EGRSTATUSPAGESIZE(stat_len != 64));
3191 * T5 introduced the separation of the Free List Padding and
3192 * Packing Boundaries. Thus, we can select a smaller Padding
3193 * Boundary to avoid uselessly chewing up PCIe Link and Memory
3194 * Bandwidth, and use a Packing Boundary which is large enough
3195 * to avoid false sharing between CPUs, etc.
3197 * For the PCI Link, the smaller the Padding Boundary the
3198 * better. For the Memory Controller, a smaller Padding
3199 * Boundary is better until we cross under the Memory Line
3200 * Size (the minimum unit of transfer to/from Memory). If we
3201 * have a Padding Boundary which is smaller than the Memory
3202 * Line Size, that'll involve a Read-Modify-Write cycle on the
3203 * Memory Controller which is never good. For T5 the smallest
3204 * Padding Boundary which we can select is 32 bytes which is
3205 * larger than any known Memory Controller Line Size so we'll
3210 * N.B. T5 has a different interpretation of the "0" value for
3211 * the Packing Boundary. This corresponds to 16 bytes instead
3212 * of the expected 32 bytes. We never have a Packing Boundary
3213 * less than 32 bytes so we can't use that special value but
3214 * on the other hand, if we wanted 32 bytes, the best we can
3215 * really do is 64 bytes ...
3217 if (fl_align <= 32) {
3221 t4_set_reg_field(adap, A_SGE_CONTROL,
3222 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3223 F_EGRSTATUSPAGESIZE,
3224 V_INGPADBOUNDARY(X_INGPCIEBOUNDARY_32B) |
3225 V_EGRSTATUSPAGESIZE(stat_len != 64));
3226 t4_set_reg_field(adap, A_SGE_CONTROL2,
3227 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3228 V_INGPACKBOUNDARY(fl_align_log -
3229 X_INGPACKBOUNDARY_SHIFT));
3233 * Adjust various SGE Free List Host Buffer Sizes.
3235 * The first four entries are:
3239 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3240 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3242 * For the single-MTU buffers in unpacked mode we need to include
3243 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3244 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3245 * Padding boundary. All of these are accommodated in the Factory
3246 * Default Firmware Configuration File but we need to adjust it for
3247 * this host's cache line size.
3249 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3250 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3251 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3253 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3254 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3257 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3263 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3264 * @adap: the adapter
3265 * @page_size: the host's Base Page Size
3266 * @cache_line_size: the host's Cache Line Size
3268 * Various registers in T4 contain values which are dependent on the
3269 * host's Base Page and Cache Line Sizes. This function will fix all of
3270 * those registers with the appropriate values as passed in ...
3272 * This routine makes changes which are compatible with T4 chips.
3274 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3275 unsigned int cache_line_size)
3277 return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3282 * t4_fw_initialize - ask FW to initialize the device
3283 * @adap: the adapter
3284 * @mbox: mailbox to use for the FW command
3286 * Issues a command to FW to partially initialize the device. This
3287 * performs initialization that generally doesn't depend on user input.
3289 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3291 struct fw_initialize_cmd c;
3293 memset(&c, 0, sizeof(c));
3294 INIT_CMD(c, INITIALIZE, WRITE);
3295 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3299 * t4_query_params_rw - query FW or device parameters
3300 * @adap: the adapter
3301 * @mbox: mailbox to use for the FW command
3304 * @nparams: the number of parameters
3305 * @params: the parameter names
3306 * @val: the parameter values
3307 * @rw: Write and read flag
3309 * Reads the value of FW or device parameters. Up to 7 parameters can be
3312 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3313 unsigned int pf, unsigned int vf,
3314 unsigned int nparams, const u32 *params,
3319 struct fw_params_cmd c;
3320 __be32 *p = &c.param[0].mnem;
3325 memset(&c, 0, sizeof(c));
3326 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3327 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3328 V_FW_PARAMS_CMD_PFN(pf) |
3329 V_FW_PARAMS_CMD_VFN(vf));
3330 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3332 for (i = 0; i < nparams; i++) {
3333 *p++ = cpu_to_be32(*params++);
3335 *p = cpu_to_be32(*(val + i));
3339 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3341 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3342 *val++ = be32_to_cpu(*p);
3346 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3347 unsigned int vf, unsigned int nparams, const u32 *params,
3350 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3354 * t4_set_params_timeout - sets FW or device parameters
3355 * @adap: the adapter
3356 * @mbox: mailbox to use for the FW command
3359 * @nparams: the number of parameters
3360 * @params: the parameter names
3361 * @val: the parameter values
3362 * @timeout: the timeout time
3364 * Sets the value of FW or device parameters. Up to 7 parameters can be
3365 * specified at once.
3367 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3368 unsigned int pf, unsigned int vf,
3369 unsigned int nparams, const u32 *params,
3370 const u32 *val, int timeout)
3372 struct fw_params_cmd c;
3373 __be32 *p = &c.param[0].mnem;
3378 memset(&c, 0, sizeof(c));
3379 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3380 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3381 V_FW_PARAMS_CMD_PFN(pf) |
3382 V_FW_PARAMS_CMD_VFN(vf));
3383 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3386 *p++ = cpu_to_be32(*params++);
3387 *p++ = cpu_to_be32(*val++);
3390 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3393 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3394 unsigned int vf, unsigned int nparams, const u32 *params,
3397 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3398 FW_CMD_MAX_TIMEOUT);
3402 * t4_alloc_vi_func - allocate a virtual interface
3403 * @adap: the adapter
3404 * @mbox: mailbox to use for the FW command
3405 * @port: physical port associated with the VI
3406 * @pf: the PF owning the VI
3407 * @vf: the VF owning the VI
3408 * @nmac: number of MAC addresses needed (1 to 5)
3409 * @mac: the MAC addresses of the VI
3410 * @rss_size: size of RSS table slice associated with this VI
3411 * @portfunc: which Port Application Function MAC Address is desired
3412 * @idstype: Intrusion Detection Type
3414 * Allocates a virtual interface for the given physical port. If @mac is
3415 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3416 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3417 * stored consecutively so the space needed is @nmac * 6 bytes.
3418 * Returns a negative error number or the non-negative VI id.
3420 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3421 unsigned int port, unsigned int pf, unsigned int vf,
3422 unsigned int nmac, u8 *mac, unsigned int *rss_size,
3423 unsigned int portfunc, unsigned int idstype)
3428 memset(&c, 0, sizeof(c));
3429 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3430 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3431 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3432 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3433 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3434 V_FW_VI_CMD_FUNC(portfunc));
3435 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3438 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3443 memcpy(mac, c.mac, sizeof(c.mac));
3446 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3449 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3452 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3455 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3460 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3461 return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3465 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3466 * @adap: the adapter
3467 * @mbox: mailbox to use for the FW command
3468 * @port: physical port associated with the VI
3469 * @pf: the PF owning the VI
3470 * @vf: the VF owning the VI
3471 * @nmac: number of MAC addresses needed (1 to 5)
3472 * @mac: the MAC addresses of the VI
3473 * @rss_size: size of RSS table slice associated with this VI
3475 * Backwards compatible and convieniance routine to allocate a Virtual
3476 * Interface with a Ethernet Port Application Function and Intrustion
3477 * Detection System disabled.
3479 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3480 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3481 unsigned int *rss_size)
3483 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3488 * t4_free_vi - free a virtual interface
3489 * @adap: the adapter
3490 * @mbox: mailbox to use for the FW command
3491 * @pf: the PF owning the VI
3492 * @vf: the VF owning the VI
3493 * @viid: virtual interface identifiler
3495 * Free a previously allocated virtual interface.
3497 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3498 unsigned int vf, unsigned int viid)
3502 memset(&c, 0, sizeof(c));
3503 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3504 F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
3505 V_FW_VI_CMD_VFN(vf));
3506 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
3507 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
3509 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3513 * t4_set_rxmode - set Rx properties of a virtual interface
3514 * @adap: the adapter
3515 * @mbox: mailbox to use for the FW command
3517 * @mtu: the new MTU or -1
3518 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3519 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3520 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3521 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
3523 * @sleep_ok: if true we may sleep while awaiting command completion
3525 * Sets Rx properties of a virtual interface.
3527 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3528 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3531 struct fw_vi_rxmode_cmd c;
3533 /* convert to FW values */
3535 mtu = M_FW_VI_RXMODE_CMD_MTU;
3537 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
3539 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
3541 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
3543 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
3545 memset(&c, 0, sizeof(c));
3546 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
3547 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3548 V_FW_VI_RXMODE_CMD_VIID(viid));
3549 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3550 c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
3551 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3552 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3553 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3554 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3555 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3559 * t4_change_mac - modifies the exact-match filter for a MAC address
3560 * @adap: the adapter
3561 * @mbox: mailbox to use for the FW command
3563 * @idx: index of existing filter for old value of MAC address, or -1
3564 * @addr: the new MAC address value
3565 * @persist: whether a new MAC allocation should be persistent
3566 * @add_smt: if true also add the address to the HW SMT
3568 * Modifies an exact-match filter and sets it to the new MAC address if
3569 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
3570 * latter case the address is added persistently if @persist is %true.
3572 * Note that in general it is not possible to modify the value of a given
3573 * filter so the generic way to modify an address filter is to free the one
3574 * being used by the old address value and allocate a new filter for the
3575 * new address value.
3577 * Returns a negative error number or the index of the filter with the new
3578 * MAC value. Note that this index may differ from @idx.
3580 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3581 int idx, const u8 *addr, bool persist, bool add_smt)
3584 struct fw_vi_mac_cmd c;
3585 struct fw_vi_mac_exact *p = c.u.exact;
3586 int max_mac_addr = adap->params.arch.mps_tcam_size;
3588 if (idx < 0) /* new allocation */
3589 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3590 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3592 memset(&c, 0, sizeof(c));
3593 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3594 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3595 V_FW_VI_MAC_CMD_VIID(viid));
3596 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3597 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3598 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3599 V_FW_VI_MAC_CMD_IDX(idx));
3600 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3602 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3604 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3605 if (ret >= max_mac_addr)
3612 * t4_enable_vi_params - enable/disable a virtual interface
3613 * @adap: the adapter
3614 * @mbox: mailbox to use for the FW command
3616 * @rx_en: 1=enable Rx, 0=disable Rx
3617 * @tx_en: 1=enable Tx, 0=disable Tx
3618 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3620 * Enables/disables a virtual interface. Note that setting DCB Enable
3621 * only makes sense when enabling a Virtual Interface ...
3623 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3624 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3626 struct fw_vi_enable_cmd c;
3628 memset(&c, 0, sizeof(c));
3629 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3630 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3631 V_FW_VI_ENABLE_CMD_VIID(viid));
3632 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3633 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3634 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3636 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3640 * t4_enable_vi - enable/disable a virtual interface
3641 * @adap: the adapter
3642 * @mbox: mailbox to use for the FW command
3644 * @rx_en: 1=enable Rx, 0=disable Rx
3645 * @tx_en: 1=enable Tx, 0=disable Tx
3647 * Enables/disables a virtual interface. Note that setting DCB Enable
3648 * only makes sense when enabling a Virtual Interface ...
3650 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3651 bool rx_en, bool tx_en)
3653 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3657 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3658 * @adap: the adapter
3659 * @mbox: mailbox to use for the FW command
3660 * @start: %true to enable the queues, %false to disable them
3661 * @pf: the PF owning the queues
3662 * @vf: the VF owning the queues
3663 * @iqid: ingress queue id
3664 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3665 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3667 * Starts or stops an ingress queue and its associated FLs, if any.
3669 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3670 unsigned int pf, unsigned int vf, unsigned int iqid,
3671 unsigned int fl0id, unsigned int fl1id)
3675 memset(&c, 0, sizeof(c));
3676 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3677 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3678 V_FW_IQ_CMD_VFN(vf));
3679 c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
3680 V_FW_IQ_CMD_IQSTOP(!start) |
3682 c.iqid = cpu_to_be16(iqid);
3683 c.fl0id = cpu_to_be16(fl0id);
3684 c.fl1id = cpu_to_be16(fl1id);
3685 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3689 * t4_iq_free - free an ingress queue and its FLs
3690 * @adap: the adapter
3691 * @mbox: mailbox to use for the FW command
3692 * @pf: the PF owning the queues
3693 * @vf: the VF owning the queues
3694 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
3695 * @iqid: ingress queue id
3696 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3697 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3699 * Frees an ingress queue and its associated FLs, if any.
3701 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3702 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3703 unsigned int fl0id, unsigned int fl1id)
3707 memset(&c, 0, sizeof(c));
3708 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3709 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3710 V_FW_IQ_CMD_VFN(vf));
3711 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
3712 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
3713 c.iqid = cpu_to_be16(iqid);
3714 c.fl0id = cpu_to_be16(fl0id);
3715 c.fl1id = cpu_to_be16(fl1id);
3716 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3720 * t4_eth_eq_free - free an Ethernet egress queue
3721 * @adap: the adapter
3722 * @mbox: mailbox to use for the FW command
3723 * @pf: the PF owning the queue
3724 * @vf: the VF owning the queue
3725 * @eqid: egress queue id
3727 * Frees an Ethernet egress queue.
3729 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3730 unsigned int vf, unsigned int eqid)
3732 struct fw_eq_eth_cmd c;
3734 memset(&c, 0, sizeof(c));
3735 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
3736 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3737 V_FW_EQ_ETH_CMD_PFN(pf) |
3738 V_FW_EQ_ETH_CMD_VFN(vf));
3739 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3740 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
3741 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3745 * t4_handle_fw_rpl - process a FW reply message
3746 * @adap: the adapter
3747 * @rpl: start of the FW message
3749 * Processes a FW message, such as link state change messages.
3751 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3753 u8 opcode = *(const u8 *)rpl;
3756 * This might be a port command ... this simplifies the following
3757 * conditionals ... We can get away with pre-dereferencing
3758 * action_to_len16 because it's in the first 16 bytes and all messages
3759 * will be at least that long.
3761 const struct fw_port_cmd *p = (const void *)rpl;
3762 unsigned int action =
3763 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
3765 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
3766 /* link/module state change message */
3767 unsigned int speed = 0, fc = 0, i;
3768 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
3769 struct port_info *pi = NULL;
3770 struct link_config *lc;
3771 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
3772 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
3773 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
3775 if (stat & F_FW_PORT_CMD_RXPAUSE)
3777 if (stat & F_FW_PORT_CMD_TXPAUSE)
3779 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3780 speed = ETH_SPEED_NUM_100M;
3781 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3782 speed = ETH_SPEED_NUM_1G;
3783 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3784 speed = ETH_SPEED_NUM_10G;
3785 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
3786 speed = ETH_SPEED_NUM_25G;
3787 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
3788 speed = ETH_SPEED_NUM_40G;
3789 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
3790 speed = ETH_SPEED_NUM_100G;
3792 for_each_port(adap, i) {
3793 pi = adap2pinfo(adap, i);
3794 if (pi->tx_chan == chan)
3799 if (mod != pi->mod_type) {
3801 t4_os_portmod_changed(adap, i);
3803 if (link_ok != lc->link_ok || speed != lc->speed ||
3804 fc != lc->fc) { /* something changed */
3805 if (!link_ok && lc->link_ok) {
3806 static const char * const reason[] = {
3809 "Auto-negotiation Failure",
3811 "Insufficient Airflow",
3812 "Unable To Determine Reason",
3813 "No RX Signal Detected",
3816 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
3818 dev_warn(adap, "Port %d link down, reason: %s\n",
3821 lc->link_ok = link_ok;
3824 lc->supported = be16_to_cpu(p->u.info.pcap);
3827 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
3833 void t4_reset_link_config(struct adapter *adap, int idx)
3835 struct port_info *pi = adap2pinfo(adap, idx);
3836 struct link_config *lc = &pi->link_cfg;
3839 lc->requested_speed = 0;
3840 lc->requested_fc = 0;
3846 * init_link_config - initialize a link's SW state
3847 * @lc: structure holding the link state
3848 * @pcaps: link Port Capabilities
3849 * @acaps: link current Advertised Port Capabilities
3851 * Initializes the SW state maintained for each link, including the link's
3852 * capabilities and default speed/flow-control/autonegotiation settings.
3854 static void init_link_config(struct link_config *lc, unsigned int pcaps,
3859 lc->supported = pcaps;
3860 lc->requested_speed = 0;
3862 lc->requested_fc = 0;
3866 * For Forward Error Control, we default to whatever the Firmware
3867 * tells us the Link is currently advertising.
3870 if (acaps & FW_PORT_CAP_FEC_RS)
3872 if (acaps & FW_PORT_CAP_FEC_BASER_RS)
3873 fec |= FEC_BASER_RS;
3874 if (acaps & FW_PORT_CAP_FEC_RESERVED)
3875 fec |= FEC_RESERVED;
3876 lc->requested_fec = fec;
3879 if (lc->supported & FW_PORT_CAP_ANEG) {
3880 lc->advertising = lc->supported & ADVERT_MASK;
3881 lc->autoneg = AUTONEG_ENABLE;
3883 lc->advertising = 0;
3884 lc->autoneg = AUTONEG_DISABLE;
3889 * t4_wait_dev_ready - wait till to reads of registers work
3891 * Right after the device is RESET is can take a small amount of time
3892 * for it to respond to register reads. Until then, all reads will
3893 * return either 0xff...ff or 0xee...ee. Return an error if reads
3894 * don't work within a reasonable time frame.
3896 static int t4_wait_dev_ready(struct adapter *adapter)
3900 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3902 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
3906 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3907 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
3910 dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
3916 u32 vendor_and_model_id;
3920 int t4_get_flash_params(struct adapter *adapter)
3923 * Table for non-Numonix supported flash parts. Numonix parts are left
3924 * to the preexisting well-tested code. All flash parts have 64KB
3927 static struct flash_desc supported_flash[] = {
3928 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
3933 unsigned int part, manufacturer;
3934 unsigned int density, size;
3937 * Issue a Read ID Command to the Flash part. We decode supported
3938 * Flash parts and their sizes from this. There's a newer Query
3939 * Command which can retrieve detailed geometry information but
3940 * many Flash parts don't support it.
3942 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
3944 ret = sf1_read(adapter, 3, 0, 1, &flashid);
3945 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3949 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
3950 if (supported_flash[part].vendor_and_model_id == flashid) {
3951 adapter->params.sf_size =
3952 supported_flash[part].size_mb;
3953 adapter->params.sf_nsec =
3954 adapter->params.sf_size / SF_SEC_SIZE;
3959 manufacturer = flashid & 0xff;
3960 switch (manufacturer) {
3961 case 0x20: { /* Micron/Numonix */
3963 * This Density -> Size decoding table is taken from Micron
3966 density = (flashid >> 16) & 0xff;
3969 size = 1 << 20; /* 1MB */
3972 size = 1 << 21; /* 2MB */
3975 size = 1 << 22; /* 4MB */
3978 size = 1 << 23; /* 8MB */
3981 size = 1 << 24; /* 16MB */
3984 size = 1 << 25; /* 32MB */
3987 size = 1 << 26; /* 64MB */
3990 size = 1 << 27; /* 128MB */
3993 size = 1 << 28; /* 256MB */
3996 dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4001 adapter->params.sf_size = size;
4002 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4006 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4012 * We should reject adapters with FLASHes which are too small. So, emit
4015 if (adapter->params.sf_size < FLASH_MIN_SIZE)
4016 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4017 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4022 static void set_pcie_completion_timeout(struct adapter *adapter,
4028 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4030 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4033 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4038 * t4_get_chip_type - Determine chip type from device ID
4039 * @adap: the adapter
4040 * @ver: adapter version
4042 int t4_get_chip_type(struct adapter *adap, int ver)
4044 enum chip_type chip = 0;
4045 u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4047 /* Retrieve adapter's device ID */
4050 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4053 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4056 dev_err(adap, "Device %d is not supported\n",
4057 adap->params.pci.device_id);
4065 * t4_prep_adapter - prepare SW and HW for operation
4066 * @adapter: the adapter
4068 * Initialize adapter SW state for the various HW modules, set initial
4069 * values for some adapter tunables, take PHYs out of reset, and
4070 * initialize the MDIO interface.
4072 int t4_prep_adapter(struct adapter *adapter)
4077 ret = t4_wait_dev_ready(adapter);
4081 pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4082 adapter->params.pci.device_id = adapter->pdev->id.device_id;
4083 adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4086 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4087 * ADAPTER (VERSION << 4 | REVISION)
4089 ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4090 adapter->params.chip = 0;
4093 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4094 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4095 adapter->params.arch.mps_tcam_size =
4096 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4097 adapter->params.arch.mps_rplc_size = 128;
4098 adapter->params.arch.nchan = NCHAN;
4099 adapter->params.arch.vfcount = 128;
4102 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4103 adapter->params.arch.sge_fl_db = 0;
4104 adapter->params.arch.mps_tcam_size =
4105 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4106 adapter->params.arch.mps_rplc_size = 256;
4107 adapter->params.arch.nchan = 2;
4108 adapter->params.arch.vfcount = 256;
4111 dev_err(adapter, "%s: Device %d is not supported\n",
4112 __func__, adapter->params.pci.device_id);
4116 adapter->params.pci.vpd_cap_addr =
4117 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4119 ret = t4_get_flash_params(adapter);
4121 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4126 adapter->params.cim_la_size = CIMLA_SIZE;
4128 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4131 * Default port and clock for debugging in case we can't reach FW.
4133 adapter->params.nports = 1;
4134 adapter->params.portvec = 1;
4135 adapter->params.vpd.cclk = 50000;
4137 /* Set pci completion timeout value to 4 seconds. */
4138 set_pcie_completion_timeout(adapter, 0xd);
4143 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4144 * @adapter: the adapter
4145 * @qid: the Queue ID
4146 * @qtype: the Ingress or Egress type for @qid
4147 * @pbar2_qoffset: BAR2 Queue Offset
4148 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4150 * Returns the BAR2 SGE Queue Registers information associated with the
4151 * indicated Absolute Queue ID. These are passed back in return value
4152 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4153 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4155 * This may return an error which indicates that BAR2 SGE Queue
4156 * registers aren't available. If an error is not returned, then the
4157 * following values are returned:
4159 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4160 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4162 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4163 * require the "Inferred Queue ID" ability may be used. E.g. the
4164 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4165 * then these "Inferred Queue ID" register may not be used.
4167 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4168 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4169 unsigned int *pbar2_qid)
4171 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4172 u64 bar2_page_offset, bar2_qoffset;
4173 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4176 * T4 doesn't support BAR2 SGE Queue registers.
4178 if (is_t4(adapter->params.chip))
4182 * Get our SGE Page Size parameters.
4184 page_shift = adapter->params.sge.hps + 10;
4185 page_size = 1 << page_shift;
4188 * Get the right Queues per Page parameters for our Queue.
4190 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4191 adapter->params.sge.eq_qpp :
4192 adapter->params.sge.iq_qpp);
4193 qpp_mask = (1 << qpp_shift) - 1;
4196 * Calculate the basics of the BAR2 SGE Queue register area:
4197 * o The BAR2 page the Queue registers will be in.
4198 * o The BAR2 Queue ID.
4199 * o The BAR2 Queue ID Offset into the BAR2 page.
4201 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4202 bar2_qid = qid & qpp_mask;
4203 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4206 * If the BAR2 Queue ID Offset is less than the Page Size, then the
4207 * hardware will infer the Absolute Queue ID simply from the writes to
4208 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4209 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
4210 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4211 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4212 * from the BAR2 Page and BAR2 Queue ID.
4214 * One important censequence of this is that some BAR2 SGE registers
4215 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4216 * there. But other registers synthesize the SGE Queue ID purely
4217 * from the writes to the registers -- the Write Combined Doorbell
4218 * Buffer is a good example. These BAR2 SGE Registers are only
4219 * available for those BAR2 SGE Register areas where the SGE Absolute
4220 * Queue ID can be inferred from simple writes.
4222 bar2_qoffset = bar2_page_offset;
4223 bar2_qinferred = (bar2_qid_offset < page_size);
4224 if (bar2_qinferred) {
4225 bar2_qoffset += bar2_qid_offset;
4229 *pbar2_qoffset = bar2_qoffset;
4230 *pbar2_qid = bar2_qid;
4235 * t4_init_sge_params - initialize adap->params.sge
4236 * @adapter: the adapter
4238 * Initialize various fields of the adapter's SGE Parameters structure.
4240 int t4_init_sge_params(struct adapter *adapter)
4242 struct sge_params *sge_params = &adapter->params.sge;
4244 unsigned int s_hps, s_qpp;
4247 * Extract the SGE Page Size for our PF.
4249 hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4250 s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4252 sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4255 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4257 s_qpp = (S_QUEUESPERPAGEPF0 +
4258 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4259 qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4260 sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4261 qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4262 sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4268 * t4_init_tp_params - initialize adap->params.tp
4269 * @adap: the adapter
4271 * Initialize various fields of the adapter's TP Parameters structure.
4273 int t4_init_tp_params(struct adapter *adap)
4278 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4279 adap->params.tp.tre = G_TIMERRESOLUTION(v);
4280 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4282 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4283 for (chan = 0; chan < NCHAN; chan++)
4284 adap->params.tp.tx_modq[chan] = chan;
4287 * Cache the adapter's Compressed Filter Mode and global Incress
4290 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4291 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4292 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4293 &adap->params.tp.ingress_config, 1,
4294 A_TP_INGRESS_CONFIG);
4297 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4298 * shift positions of several elements of the Compressed Filter Tuple
4299 * for this adapter which we need frequently ...
4301 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4302 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4303 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4304 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4308 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4309 * represents the presense of an Outer VLAN instead of a VNIC ID.
4311 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4312 adap->params.tp.vnic_shift = -1;
4318 * t4_filter_field_shift - calculate filter field shift
4319 * @adap: the adapter
4320 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4322 * Return the shift position of a filter field within the Compressed
4323 * Filter Tuple. The filter field is specified via its selection bit
4324 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
4326 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4328 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4332 if ((filter_mode & filter_sel) == 0)
4335 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4336 switch (filter_mode & sel) {
4338 field_shift += W_FT_FCOE;
4341 field_shift += W_FT_PORT;
4344 field_shift += W_FT_VNIC_ID;
4347 field_shift += W_FT_VLAN;
4350 field_shift += W_FT_TOS;
4353 field_shift += W_FT_PROTOCOL;
4356 field_shift += W_FT_ETHERTYPE;
4359 field_shift += W_FT_MACMATCH;
4362 field_shift += W_FT_MPSHITTYPE;
4364 case F_FRAGMENTATION:
4365 field_shift += W_FT_FRAGMENTATION;
4372 int t4_init_rss_mode(struct adapter *adap, int mbox)
4375 struct fw_rss_vi_config_cmd rvc;
4377 memset(&rvc, 0, sizeof(rvc));
4379 for_each_port(adap, i) {
4380 struct port_info *p = adap2pinfo(adap, i);
4382 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4383 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4384 V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4385 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4386 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4389 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4394 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4398 struct fw_port_cmd c;
4400 memset(&c, 0, sizeof(c));
4402 for_each_port(adap, i) {
4403 unsigned int rss_size = 0;
4404 struct port_info *p = adap2pinfo(adap, i);
4406 while ((adap->params.portvec & (1 << j)) == 0)
4409 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4410 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4411 V_FW_PORT_CMD_PORTID(j));
4412 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4413 FW_PORT_ACTION_GET_PORT_INFO) |
4415 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4419 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4425 p->rss_size = rss_size;
4426 t4_os_set_hw_addr(adap, i, addr);
4428 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
4429 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
4430 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
4431 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
4432 p->mod_type = FW_PORT_MOD_TYPE_NA;
4434 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
4435 be16_to_cpu(c.u.info.acap));