4 * Copyright(c) 2014-2016 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <netinet/in.h>
36 #include <rte_interrupts.h>
38 #include <rte_debug.h>
40 #include <rte_atomic.h>
41 #include <rte_branch_prediction.h>
42 #include <rte_memory.h>
43 #include <rte_memzone.h>
44 #include <rte_tailq.h>
46 #include <rte_alarm.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_atomic.h>
50 #include <rte_malloc.h>
51 #include <rte_random.h>
53 #include <rte_byteorder.h>
57 #include "t4_regs_values.h"
58 #include "t4fw_interface.h"
60 static void init_link_config(struct link_config *lc, unsigned int caps);
63 * t4_read_mtu_tbl - returns the values in the HW path MTU table
65 * @mtus: where to store the MTU values
66 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
68 * Reads the HW path MTU table.
70 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
75 for (i = 0; i < NMTUS; ++i) {
76 t4_write_reg(adap, A_TP_MTU_TABLE,
77 V_MTUINDEX(0xff) | V_MTUVALUE(i));
78 v = t4_read_reg(adap, A_TP_MTU_TABLE);
79 mtus[i] = G_MTUVALUE(v);
81 mtu_log[i] = G_MTUWIDTH(v);
86 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
88 * @addr: the indirect TP register address
89 * @mask: specifies the field within the register to modify
90 * @val: new value for the field
92 * Sets a field of an indirect TP register to the given value.
94 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
95 unsigned int mask, unsigned int val)
97 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
98 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
99 t4_write_reg(adap, A_TP_PIO_DATA, val);
102 /* The minimum additive increment value for the congestion control table */
103 #define CC_MIN_INCR 2U
106 * t4_load_mtus - write the MTU and congestion control HW tables
108 * @mtus: the values for the MTU table
109 * @alpha: the values for the congestion control alpha parameter
110 * @beta: the values for the congestion control beta parameter
112 * Write the HW MTU table with the supplied MTUs and the high-speed
113 * congestion control table with the supplied alpha, beta, and MTUs.
114 * We write the two tables together because the additive increments
115 * depend on the MTUs.
117 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
118 const unsigned short *alpha, const unsigned short *beta)
120 static const unsigned int avg_pkts[NCCTRL_WIN] = {
121 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
122 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
123 28672, 40960, 57344, 81920, 114688, 163840, 229376
128 for (i = 0; i < NMTUS; ++i) {
129 unsigned int mtu = mtus[i];
130 unsigned int log2 = cxgbe_fls(mtu);
132 if (!(mtu & ((1 << log2) >> 2))) /* round */
134 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
135 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
137 for (w = 0; w < NCCTRL_WIN; ++w) {
140 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
143 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
144 (w << 16) | (beta[w] << 13) | inc);
150 * t4_wait_op_done_val - wait until an operation is completed
151 * @adapter: the adapter performing the operation
152 * @reg: the register to check for completion
153 * @mask: a single-bit field within @reg that indicates completion
154 * @polarity: the value of the field when the operation is completed
155 * @attempts: number of check iterations
156 * @delay: delay in usecs between iterations
157 * @valp: where to store the value of the register at completion time
159 * Wait until an operation is completed by checking a bit in a register
160 * up to @attempts times. If @valp is not NULL the value of the register
161 * at the time it indicated completion is stored there. Returns 0 if the
162 * operation completes and -EAGAIN otherwise.
164 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
165 int polarity, int attempts, int delay, u32 *valp)
168 u32 val = t4_read_reg(adapter, reg);
170 if (!!(val & mask) == polarity) {
183 * t4_set_reg_field - set a register field to a value
184 * @adapter: the adapter to program
185 * @addr: the register address
186 * @mask: specifies the portion of the register to modify
187 * @val: the new value for the register field
189 * Sets a register field specified by the supplied mask to the
192 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
195 u32 v = t4_read_reg(adapter, addr) & ~mask;
197 t4_write_reg(adapter, addr, v | val);
198 (void)t4_read_reg(adapter, addr); /* flush */
202 * t4_read_indirect - read indirectly addressed registers
204 * @addr_reg: register holding the indirect address
205 * @data_reg: register holding the value of the indirect register
206 * @vals: where the read register values are stored
207 * @nregs: how many indirect registers to read
208 * @start_idx: index of first indirect register to read
210 * Reads registers that are accessed indirectly through an address/data
213 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
214 unsigned int data_reg, u32 *vals, unsigned int nregs,
215 unsigned int start_idx)
218 t4_write_reg(adap, addr_reg, start_idx);
219 *vals++ = t4_read_reg(adap, data_reg);
225 * t4_write_indirect - write indirectly addressed registers
227 * @addr_reg: register holding the indirect addresses
228 * @data_reg: register holding the value for the indirect registers
229 * @vals: values to write
230 * @nregs: how many indirect registers to write
231 * @start_idx: address of first indirect register to write
233 * Writes a sequential block of registers that are accessed indirectly
234 * through an address/data register pair.
236 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
237 unsigned int data_reg, const u32 *vals,
238 unsigned int nregs, unsigned int start_idx)
241 t4_write_reg(adap, addr_reg, start_idx++);
242 t4_write_reg(adap, data_reg, *vals++);
247 * t4_report_fw_error - report firmware error
250 * The adapter firmware can indicate error conditions to the host.
251 * If the firmware has indicated an error, print out the reason for
252 * the firmware error.
254 static void t4_report_fw_error(struct adapter *adap)
256 static const char * const reason[] = {
257 "Crash", /* PCIE_FW_EVAL_CRASH */
258 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
259 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
260 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
261 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
262 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
263 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
264 "Reserved", /* reserved */
268 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
269 if (pcie_fw & F_PCIE_FW_ERR)
270 pr_err("%s: Firmware reports adapter error: %s\n",
271 __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
275 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
277 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
280 for ( ; nflit; nflit--, mbox_addr += 8)
281 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
285 * Handle a FW assertion reported in a mailbox.
287 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
289 struct fw_debug_cmd asrt;
291 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
292 pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
293 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
294 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
297 #define X_CIM_PF_NOACCESS 0xeeeeeeee
300 * If the Host OS Driver needs locking arround accesses to the mailbox, this
301 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
303 /* makes single-statement usage a bit cleaner ... */
304 #ifdef T4_OS_NEEDS_MBOX_LOCKING
305 #define T4_OS_MBOX_LOCKING(x) x
307 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
311 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
313 * @mbox: index of the mailbox to use
314 * @cmd: the command to write
315 * @size: command length in bytes
316 * @rpl: where to optionally store the reply
317 * @sleep_ok: if true we may sleep while awaiting command completion
318 * @timeout: time to wait for command to finish before timing out
319 * (negative implies @sleep_ok=false)
321 * Sends the given command to FW through the selected mailbox and waits
322 * for the FW to execute the command. If @rpl is not %NULL it is used to
323 * store the FW's reply to the command. The command and its optional
324 * reply are of the same length. Some FW commands like RESET and
325 * INITIALIZE can take a considerable amount of time to execute.
326 * @sleep_ok determines whether we may sleep while awaiting the response.
327 * If sleeping is allowed we use progressive backoff otherwise we spin.
328 * Note that passing in a negative @timeout is an alternate mechanism
329 * for specifying @sleep_ok=false. This is useful when a higher level
330 * interface allows for specification of @timeout but not @sleep_ok ...
332 * Returns 0 on success or a negative errno on failure. A
333 * failure can happen either because we are not able to execute the
334 * command or FW executes it but signals an error. In the latter case
335 * the return value is the error code indicated by FW (negated).
337 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
338 const void __attribute__((__may_alias__)) *cmd,
339 int size, void *rpl, bool sleep_ok, int timeout)
342 * We delay in small increments at first in an effort to maintain
343 * responsiveness for simple, fast executing commands but then back
344 * off to larger delays to a maximum retry delay.
346 static const int delay[] = {
347 1, 1, 3, 5, 10, 10, 20, 50, 100
353 unsigned int delay_idx;
354 __be64 *temp = (__be64 *)malloc(size * sizeof(char));
356 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
357 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
359 struct mbox_entry entry;
362 if ((size & 15) || size > MBOX_LEN) {
368 memcpy(p, (const __be64 *)cmd, size);
371 * If we have a negative timeout, that implies that we can't sleep.
378 #ifdef T4_OS_NEEDS_MBOX_LOCKING
380 * Queue ourselves onto the mailbox access list. When our entry is at
381 * the front of the list, we have rights to access the mailbox. So we
382 * wait [for a while] till we're at the front [or bail out with an
385 t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
390 for (i = 0; ; i += ms) {
392 * If we've waited too long, return a busy indication. This
393 * really ought to be based on our initial position in the
394 * mailbox access list but this is a start. We very rarely
395 * contend on access to the mailbox ... Also check for a
396 * firmware error which we'll report as a device error.
398 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
399 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
400 t4_os_atomic_list_del(&entry, &adap->mbox_list,
402 t4_report_fw_error(adap);
403 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
407 * If we're at the head, break out and start the mailbox
410 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
414 * Delay for a bit before checking again ...
417 ms = delay[delay_idx]; /* last element may repeat */
418 if (delay_idx < ARRAY_SIZE(delay) - 1)
425 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
428 * Attempt to gain access to the mailbox.
430 for (i = 0; i < 4; i++) {
431 ctl = t4_read_reg(adap, ctl_reg);
433 if (v != X_MBOWNER_NONE)
438 * If we were unable to gain access, dequeue ourselves from the
439 * mailbox atomic access list and report the error to our caller.
441 if (v != X_MBOWNER_PL) {
442 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
445 t4_report_fw_error(adap);
446 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
450 * If we gain ownership of the mailbox and there's a "valid" message
451 * in it, this is likely an asynchronous error message from the
452 * firmware. So we'll report that and then proceed on with attempting
453 * to issue our own command ... which may well fail if the error
454 * presaged the firmware crashing ...
456 if (ctl & F_MBMSGVALID) {
457 dev_err(adap, "found VALID command in mbox %u: "
458 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
459 (unsigned long long)t4_read_reg64(adap, data_reg),
460 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
461 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
462 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
463 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
464 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
465 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
466 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
470 * Copy in the new mailbox command and send it on its way ...
472 for (i = 0; i < size; i += 8, p++)
473 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
475 CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
476 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
477 (unsigned long long)t4_read_reg64(adap, data_reg),
478 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
479 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
480 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
481 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
482 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
483 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
484 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
486 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
487 t4_read_reg(adap, ctl_reg); /* flush write */
493 * Loop waiting for the reply; bail out if we time out or the firmware
496 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
497 for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
499 ms = delay[delay_idx]; /* last element may repeat */
500 if (delay_idx < ARRAY_SIZE(delay) - 1)
507 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
508 v = t4_read_reg(adap, ctl_reg);
509 if (v == X_CIM_PF_NOACCESS)
511 if (G_MBOWNER(v) == X_MBOWNER_PL) {
512 if (!(v & F_MBMSGVALID)) {
513 t4_write_reg(adap, ctl_reg,
514 V_MBOWNER(X_MBOWNER_NONE));
518 CXGBE_DEBUG_MBOX(adap,
519 "%s: mbox %u: %016llx %016llx %016llx %016llx "
520 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
521 (unsigned long long)t4_read_reg64(adap, data_reg),
522 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
523 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
524 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
525 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
526 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
527 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
528 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
530 CXGBE_DEBUG_MBOX(adap,
531 "command %#x completed in %d ms (%ssleeping)\n",
533 i + ms, sleep_ok ? "" : "non-");
535 res = t4_read_reg64(adap, data_reg);
536 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
537 fw_asrt(adap, data_reg);
538 res = V_FW_CMD_RETVAL(EIO);
540 get_mbox_rpl(adap, rpl, size / 8, data_reg);
542 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
544 t4_os_atomic_list_del(&entry, &adap->mbox_list,
546 return -G_FW_CMD_RETVAL((int)res);
551 * We timed out waiting for a reply to our mailbox command. Report
552 * the error and also check to see if the firmware reported any
555 dev_err(adap, "command %#x in mailbox %d timed out\n",
556 *(const u8 *)cmd, mbox);
557 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
560 t4_report_fw_error(adap);
562 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
565 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
566 void *rpl, bool sleep_ok)
568 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
573 * t4_get_regs_len - return the size of the chips register set
574 * @adapter: the adapter
576 * Returns the size of the chip's BAR0 register space.
578 unsigned int t4_get_regs_len(struct adapter *adapter)
580 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
582 switch (chip_version) {
584 return T5_REGMAP_SIZE;
588 "Unsupported chip version %d\n", chip_version);
593 * t4_get_regs - read chip registers into provided buffer
595 * @buf: register buffer
596 * @buf_size: size (in bytes) of register buffer
598 * If the provided register buffer isn't large enough for the chip's
599 * full register range, the register dump will be truncated to the
600 * register buffer's size.
602 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
604 static const unsigned int t5_reg_ranges[] = {
1379 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1380 const unsigned int *reg_ranges;
1381 int reg_ranges_size, range;
1382 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1384 /* Select the right set of register ranges to dump depending on the
1385 * adapter chip type.
1387 switch (chip_version) {
1389 reg_ranges = t5_reg_ranges;
1390 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1395 "Unsupported chip version %d\n", chip_version);
1399 /* Clear the register buffer and insert the appropriate register
1400 * values selected by the above register ranges.
1402 memset(buf, 0, buf_size);
1403 for (range = 0; range < reg_ranges_size; range += 2) {
1404 unsigned int reg = reg_ranges[range];
1405 unsigned int last_reg = reg_ranges[range + 1];
1406 u32 *bufp = (u32 *)((char *)buf + reg);
1408 /* Iterate across the register range filling in the register
1409 * buffer but don't write past the end of the register buffer.
1411 while (reg <= last_reg && bufp < buf_end) {
1412 *bufp++ = t4_read_reg(adap, reg);
1418 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1419 #define EEPROM_DELAY 10 /* 10us per poll spin */
1420 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
1422 #define EEPROM_STAT_ADDR 0x7bfc
1425 * Small utility function to wait till any outstanding VPD Access is complete.
1426 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1427 * VPD Access in flight. This allows us to handle the problem of having a
1428 * previous VPD Access time out and prevent an attempt to inject a new VPD
1429 * Request before any in-flight VPD request has completed.
1431 static int t4_seeprom_wait(struct adapter *adapter)
1433 unsigned int base = adapter->params.pci.vpd_cap_addr;
1436 /* If no VPD Access is in flight, we can just return success right
1439 if (!adapter->vpd_busy)
1442 /* Poll the VPD Capability Address/Flag register waiting for it
1443 * to indicate that the operation is complete.
1445 max_poll = EEPROM_MAX_POLL;
1449 udelay(EEPROM_DELAY);
1450 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
1452 /* If the operation is complete, mark the VPD as no longer
1453 * busy and return success.
1455 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
1456 adapter->vpd_busy = 0;
1459 } while (--max_poll);
1461 /* Failure! Note that we leave the VPD Busy status set in order to
1462 * avoid pushing a new VPD Access request into the VPD Capability till
1463 * the current operation eventually succeeds. It's a bug to issue a
1464 * new request when an existing request is in flight and will result
1465 * in corrupt hardware state.
1471 * t4_seeprom_read - read a serial EEPROM location
1472 * @adapter: adapter to read
1473 * @addr: EEPROM virtual address
1474 * @data: where to store the read data
1476 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
1477 * VPD capability. Note that this function must be called with a virtual
1480 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
1482 unsigned int base = adapter->params.pci.vpd_cap_addr;
1485 /* VPD Accesses must alway be 4-byte aligned!
1487 if (addr >= EEPROMVSIZE || (addr & 3))
1490 /* Wait for any previous operation which may still be in flight to
1493 ret = t4_seeprom_wait(adapter);
1495 dev_err(adapter, "VPD still busy from previous operation\n");
1499 /* Issue our new VPD Read request, mark the VPD as being busy and wait
1500 * for our request to complete. If it doesn't complete, note the
1501 * error and return it to our caller. Note that we do not reset the
1504 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
1505 adapter->vpd_busy = 1;
1506 adapter->vpd_flag = PCI_VPD_ADDR_F;
1507 ret = t4_seeprom_wait(adapter);
1509 dev_err(adapter, "VPD read of address %#x failed\n", addr);
1513 /* Grab the returned data, swizzle it into our endianness and
1516 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
1517 *data = le32_to_cpu(*data);
1522 * t4_seeprom_write - write a serial EEPROM location
1523 * @adapter: adapter to write
1524 * @addr: virtual EEPROM address
1525 * @data: value to write
1527 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
1528 * VPD capability. Note that this function must be called with a virtual
1531 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
1533 unsigned int base = adapter->params.pci.vpd_cap_addr;
1538 /* VPD Accesses must alway be 4-byte aligned!
1540 if (addr >= EEPROMVSIZE || (addr & 3))
1543 /* Wait for any previous operation which may still be in flight to
1546 ret = t4_seeprom_wait(adapter);
1548 dev_err(adapter, "VPD still busy from previous operation\n");
1552 /* Issue our new VPD Read request, mark the VPD as being busy and wait
1553 * for our request to complete. If it doesn't complete, note the
1554 * error and return it to our caller. Note that we do not reset the
1557 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
1559 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
1560 (u16)addr | PCI_VPD_ADDR_F);
1561 adapter->vpd_busy = 1;
1562 adapter->vpd_flag = 0;
1563 ret = t4_seeprom_wait(adapter);
1565 dev_err(adapter, "VPD write of address %#x failed\n", addr);
1569 /* Reset PCI_VPD_DATA register after a transaction and wait for our
1570 * request to complete. If it doesn't complete, return error.
1572 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
1573 max_poll = EEPROM_MAX_POLL;
1575 udelay(EEPROM_DELAY);
1576 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
1577 } while ((stats_reg & 0x1) && --max_poll);
1581 /* Return success! */
1586 * t4_seeprom_wp - enable/disable EEPROM write protection
1587 * @adapter: the adapter
1588 * @enable: whether to enable or disable write protection
1590 * Enables or disables write protection on the serial EEPROM.
1592 int t4_seeprom_wp(struct adapter *adapter, int enable)
1594 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
1598 * t4_config_rss_range - configure a portion of the RSS mapping table
1599 * @adapter: the adapter
1600 * @mbox: mbox to use for the FW command
1601 * @viid: virtual interface whose RSS subtable is to be written
1602 * @start: start entry in the table to write
1603 * @n: how many table entries to write
1604 * @rspq: values for the "response queue" (Ingress Queue) lookup table
1605 * @nrspq: number of values in @rspq
1607 * Programs the selected part of the VI's RSS mapping table with the
1608 * provided values. If @nrspq < @n the supplied values are used repeatedly
1609 * until the full table range is populated.
1611 * The caller must ensure the values in @rspq are in the range allowed for
1614 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1615 int start, int n, const u16 *rspq, unsigned int nrspq)
1618 const u16 *rsp = rspq;
1619 const u16 *rsp_end = rspq + nrspq;
1620 struct fw_rss_ind_tbl_cmd cmd;
1622 memset(&cmd, 0, sizeof(cmd));
1623 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
1624 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
1625 V_FW_RSS_IND_TBL_CMD_VIID(viid));
1626 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1629 * Each firmware RSS command can accommodate up to 32 RSS Ingress
1630 * Queue Identifiers. These Ingress Queue IDs are packed three to
1631 * a 32-bit word as 10-bit values with the upper remaining 2 bits
1635 int nq = min(n, 32);
1637 __be32 *qp = &cmd.iq0_to_iq2;
1640 * Set up the firmware RSS command header to send the next
1641 * "nq" Ingress Queue IDs to the firmware.
1643 cmd.niqid = cpu_to_be16(nq);
1644 cmd.startidx = cpu_to_be16(start);
1647 * "nq" more done for the start of the next loop.
1653 * While there are still Ingress Queue IDs to stuff into the
1654 * current firmware RSS command, retrieve them from the
1655 * Ingress Queue ID array and insert them into the command.
1659 * Grab up to the next 3 Ingress Queue IDs (wrapping
1660 * around the Ingress Queue ID array if necessary) and
1661 * insert them into the firmware RSS command at the
1662 * current 3-tuple position within the commad.
1666 int nqbuf = min(3, nq);
1672 while (nqbuf && nq_packed < 32) {
1679 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
1680 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
1681 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
1685 * Send this portion of the RRS table update to the firmware;
1686 * bail out on any errors.
1688 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
1697 * t4_config_vi_rss - configure per VI RSS settings
1698 * @adapter: the adapter
1699 * @mbox: mbox to use for the FW command
1702 * @defq: id of the default RSS queue for the VI.
1704 * Configures VI-specific RSS properties.
1706 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1707 unsigned int flags, unsigned int defq)
1709 struct fw_rss_vi_config_cmd c;
1711 memset(&c, 0, sizeof(c));
1712 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
1713 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
1714 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
1715 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
1716 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
1717 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
1718 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
1722 * init_cong_ctrl - initialize congestion control parameters
1723 * @a: the alpha values for congestion control
1724 * @b: the beta values for congestion control
1726 * Initialize the congestion control parameters.
1728 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
1732 for (i = 0; i < 9; i++) {
1786 #define INIT_CMD(var, cmd, rd_wr) do { \
1787 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
1788 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
1789 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
1792 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
1794 u32 cclk_param, cclk_val;
1798 * Ask firmware for the Core Clock since it knows how to translate the
1799 * Reference Clock ('V2') VPD field into a Core Clock value ...
1801 cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1802 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
1803 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
1804 1, &cclk_param, &cclk_val);
1806 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
1812 dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
1816 /* serial flash and firmware constants and flash config file constants */
1818 SF_ATTEMPTS = 10, /* max retries for SF operations */
1820 /* flash command opcodes */
1821 SF_PROG_PAGE = 2, /* program page */
1822 SF_WR_DISABLE = 4, /* disable writes */
1823 SF_RD_STATUS = 5, /* read status register */
1824 SF_WR_ENABLE = 6, /* enable writes */
1825 SF_RD_DATA_FAST = 0xb, /* read flash */
1826 SF_RD_ID = 0x9f, /* read ID */
1827 SF_ERASE_SECTOR = 0xd8, /* erase sector */
1831 * sf1_read - read data from the serial flash
1832 * @adapter: the adapter
1833 * @byte_cnt: number of bytes to read
1834 * @cont: whether another operation will be chained
1835 * @lock: whether to lock SF for PL access only
1836 * @valp: where to store the read data
1838 * Reads up to 4 bytes of data from the serial flash. The location of
1839 * the read needs to be specified prior to calling this by issuing the
1840 * appropriate commands to the serial flash.
1842 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
1843 int lock, u32 *valp)
1847 if (!byte_cnt || byte_cnt > 4)
1849 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
1851 t4_write_reg(adapter, A_SF_OP,
1852 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
1853 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
1855 *valp = t4_read_reg(adapter, A_SF_DATA);
1860 * sf1_write - write data to the serial flash
1861 * @adapter: the adapter
1862 * @byte_cnt: number of bytes to write
1863 * @cont: whether another operation will be chained
1864 * @lock: whether to lock SF for PL access only
1865 * @val: value to write
1867 * Writes up to 4 bytes of data to the serial flash. The location of
1868 * the write needs to be specified prior to calling this by issuing the
1869 * appropriate commands to the serial flash.
1871 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
1874 if (!byte_cnt || byte_cnt > 4)
1876 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
1878 t4_write_reg(adapter, A_SF_DATA, val);
1879 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
1880 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
1881 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
1885 * t4_read_flash - read words from serial flash
1886 * @adapter: the adapter
1887 * @addr: the start address for the read
1888 * @nwords: how many 32-bit words to read
1889 * @data: where to store the read data
1890 * @byte_oriented: whether to store data as bytes or as words
1892 * Read the specified number of 32-bit words from the serial flash.
1893 * If @byte_oriented is set the read data is stored as a byte array
1894 * (i.e., big-endian), otherwise as 32-bit words in the platform's
1895 * natural endianness.
1897 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1898 unsigned int nwords, u32 *data, int byte_oriented)
1902 if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
1906 addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
1908 ret = sf1_write(adapter, 4, 1, 0, addr);
1912 ret = sf1_read(adapter, 1, 1, 0, data);
1916 for ( ; nwords; nwords--, data++) {
1917 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
1919 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
1923 *data = cpu_to_be32(*data);
1929 * t4_get_fw_version - read the firmware version
1930 * @adapter: the adapter
1931 * @vers: where to place the version
1933 * Reads the FW version from flash.
1935 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
1937 return t4_read_flash(adapter, FLASH_FW_START +
1938 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
1942 * t4_get_tp_version - read the TP microcode version
1943 * @adapter: the adapter
1944 * @vers: where to place the version
1946 * Reads the TP microcode version from flash.
1948 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
1950 return t4_read_flash(adapter, FLASH_FW_START +
1951 offsetof(struct fw_hdr, tp_microcode_ver),
1955 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1956 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
1957 FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG)
1960 * t4_link_l1cfg - apply link configuration to MAC/PHY
1961 * @phy: the PHY to setup
1962 * @mac: the MAC to setup
1963 * @lc: the requested link configuration
1965 * Set up a port's MAC and PHY according to a desired link configuration.
1966 * - If the PHY can auto-negotiate first decide what to advertise, then
1967 * enable/disable auto-negotiation as desired, and reset.
1968 * - If the PHY does not auto-negotiate just reset it.
1969 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1970 * otherwise do it later based on the outcome of auto-negotiation.
1972 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1973 struct link_config *lc)
1975 struct fw_port_cmd c;
1976 unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
1979 if (lc->requested_fc & PAUSE_RX)
1980 fc |= FW_PORT_CAP_FC_RX;
1981 if (lc->requested_fc & PAUSE_TX)
1982 fc |= FW_PORT_CAP_FC_TX;
1984 memset(&c, 0, sizeof(c));
1985 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
1986 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
1987 V_FW_PORT_CMD_PORTID(port));
1989 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1992 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1993 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
1995 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1996 } else if (lc->autoneg == AUTONEG_DISABLE) {
1997 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
1998 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
2000 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
2003 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2007 * t4_flash_cfg_addr - return the address of the flash configuration file
2008 * @adapter: the adapter
2010 * Return the address within the flash where the Firmware Configuration
2011 * File is stored, or an error if the device FLASH is too small to contain
2012 * a Firmware Configuration File.
2014 int t4_flash_cfg_addr(struct adapter *adapter)
2017 * If the device FLASH isn't large enough to hold a Firmware
2018 * Configuration File, return an error.
2020 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2023 return FLASH_CFG_START;
2026 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2029 * t4_intr_enable - enable interrupts
2030 * @adapter: the adapter whose interrupts should be enabled
2032 * Enable PF-specific interrupts for the calling function and the top-level
2033 * interrupt concentrator for global interrupts. Interrupts are already
2034 * enabled at each module, here we just enable the roots of the interrupt
2037 * Note: this function should be called only when the driver manages
2038 * non PF-specific interrupts from the various HW modules. Only one PCI
2039 * function at a time should be doing this.
2041 void t4_intr_enable(struct adapter *adapter)
2044 u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));
2046 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2047 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2048 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2049 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2050 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2051 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2052 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2053 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2054 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2055 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2056 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2060 * t4_intr_disable - disable interrupts
2061 * @adapter: the adapter whose interrupts should be disabled
2063 * Disable interrupts. We only disable the top-level interrupt
2064 * concentrators. The caller must be a PCI function managing global
2067 void t4_intr_disable(struct adapter *adapter)
2069 u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));
2071 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2072 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2076 * t4_get_port_type_description - return Port Type string description
2077 * @port_type: firmware Port Type enumeration
2079 const char *t4_get_port_type_description(enum fw_port_type port_type)
2081 static const char * const port_type_description[] = {
2100 if (port_type < ARRAY_SIZE(port_type_description))
2101 return port_type_description[port_type];
2106 * t4_get_mps_bg_map - return the buffer groups associated with a port
2107 * @adap: the adapter
2108 * @idx: the port index
2110 * Returns a bitmap indicating which MPS buffer groups are associated
2111 * with the given port. Bit i is set if buffer group i is used by the
2114 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
2116 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
2119 return idx == 0 ? 0xf : 0;
2121 return idx < 2 ? (3 << (2 * idx)) : 0;
2126 * t4_get_port_stats - collect port statistics
2127 * @adap: the adapter
2128 * @idx: the port index
2129 * @p: the stats structure to fill
2131 * Collect statistics related to the given port from HW.
2133 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2135 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2137 #define GET_STAT(name) \
2138 t4_read_reg64(adap, \
2139 (is_t4(adap->params.chip) ? \
2140 PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2141 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2142 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2144 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2145 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2146 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2147 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2148 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2149 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2150 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2151 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2152 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2153 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2154 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2155 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2156 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2157 p->tx_drop = GET_STAT(TX_PORT_DROP);
2158 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2159 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2160 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2161 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2162 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2163 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2164 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2165 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2166 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2168 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2169 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2170 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2171 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2172 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2173 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2174 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2175 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2176 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2177 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2178 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2179 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2180 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2181 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2182 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2183 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2184 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2185 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2186 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2187 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2188 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2189 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2190 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2191 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2192 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2193 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2194 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2195 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2196 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2197 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2198 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2199 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2200 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2201 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2202 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2209 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
2210 * @adap: The adapter
2212 * @stats: Current stats to fill
2213 * @offset: Previous stats snapshot
2215 void t4_get_port_stats_offset(struct adapter *adap, int idx,
2216 struct port_stats *stats,
2217 struct port_stats *offset)
2222 t4_get_port_stats(adap, idx, stats);
2223 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
2224 i < (sizeof(struct port_stats) / sizeof(u64));
2230 * t4_clr_port_stats - clear port statistics
2231 * @adap: the adapter
2232 * @idx: the port index
2234 * Clear HW statistics for the given port.
2236 void t4_clr_port_stats(struct adapter *adap, int idx)
2239 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2242 if (is_t4(adap->params.chip))
2243 port_base_addr = PORT_BASE(idx);
2245 port_base_addr = T5_PORT_BASE(idx);
2247 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
2248 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
2249 t4_write_reg(adap, port_base_addr + i, 0);
2250 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
2251 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
2252 t4_write_reg(adap, port_base_addr + i, 0);
2253 for (i = 0; i < 4; i++)
2254 if (bgmap & (1 << i)) {
2256 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
2259 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
2265 * t4_fw_hello - establish communication with FW
2266 * @adap: the adapter
2267 * @mbox: mailbox to use for the FW command
2268 * @evt_mbox: mailbox to receive async FW events
2269 * @master: specifies the caller's willingness to be the device master
2270 * @state: returns the current device state (if non-NULL)
2272 * Issues a command to establish communication with FW. Returns either
2273 * an error (negative integer) or the mailbox of the Master PF.
2275 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2276 enum dev_master master, enum dev_state *state)
2279 struct fw_hello_cmd c;
2281 unsigned int master_mbox;
2282 int retries = FW_CMD_HELLO_RETRIES;
2285 memset(&c, 0, sizeof(c));
2286 INIT_CMD(c, HELLO, WRITE);
2287 c.err_to_clearinit = cpu_to_be32(
2288 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2289 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2290 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2291 M_FW_HELLO_CMD_MBMASTER) |
2292 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2293 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
2294 F_FW_HELLO_CMD_CLEARINIT);
2297 * Issue the HELLO command to the firmware. If it's not successful
2298 * but indicates that we got a "busy" or "timeout" condition, retry
2299 * the HELLO until we exhaust our retry limit. If we do exceed our
2300 * retry limit, check to see if the firmware left us any error
2301 * information and report that if so ...
2303 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2304 if (ret != FW_SUCCESS) {
2305 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2307 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
2308 t4_report_fw_error(adap);
2312 v = be32_to_cpu(c.err_to_clearinit);
2313 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
2315 if (v & F_FW_HELLO_CMD_ERR)
2316 *state = DEV_STATE_ERR;
2317 else if (v & F_FW_HELLO_CMD_INIT)
2318 *state = DEV_STATE_INIT;
2320 *state = DEV_STATE_UNINIT;
2324 * If we're not the Master PF then we need to wait around for the
2325 * Master PF Driver to finish setting up the adapter.
2327 * Note that we also do this wait if we're a non-Master-capable PF and
2328 * there is no current Master PF; a Master PF may show up momentarily
2329 * and we wouldn't want to fail pointlessly. (This can happen when an
2330 * OS loads lots of different drivers rapidly at the same time). In
2331 * this case, the Master PF returned by the firmware will be
2332 * M_PCIE_FW_MASTER so the test below will work ...
2334 if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
2335 master_mbox != mbox) {
2336 int waiting = FW_CMD_HELLO_TIMEOUT;
2339 * Wait for the firmware to either indicate an error or
2340 * initialized state. If we see either of these we bail out
2341 * and report the issue to the caller. If we exhaust the
2342 * "hello timeout" and we haven't exhausted our retries, try
2343 * again. Otherwise bail with a timeout error.
2352 * If neither Error nor Initialialized are indicated
2353 * by the firmware keep waiting till we exaust our
2354 * timeout ... and then retry if we haven't exhausted
2357 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
2358 if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
2369 * We either have an Error or Initialized condition
2370 * report errors preferentially.
2373 if (pcie_fw & F_PCIE_FW_ERR)
2374 *state = DEV_STATE_ERR;
2375 else if (pcie_fw & F_PCIE_FW_INIT)
2376 *state = DEV_STATE_INIT;
2380 * If we arrived before a Master PF was selected and
2381 * there's not a valid Master PF, grab its identity
2384 if (master_mbox == M_PCIE_FW_MASTER &&
2385 (pcie_fw & F_PCIE_FW_MASTER_VLD))
2386 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
2395 * t4_fw_bye - end communication with FW
2396 * @adap: the adapter
2397 * @mbox: mailbox to use for the FW command
2399 * Issues a command to terminate communication with FW.
2401 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2403 struct fw_bye_cmd c;
2405 memset(&c, 0, sizeof(c));
2406 INIT_CMD(c, BYE, WRITE);
2407 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2411 * t4_fw_reset - issue a reset to FW
2412 * @adap: the adapter
2413 * @mbox: mailbox to use for the FW command
2414 * @reset: specifies the type of reset to perform
2416 * Issues a reset command of the specified type to FW.
2418 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2420 struct fw_reset_cmd c;
2422 memset(&c, 0, sizeof(c));
2423 INIT_CMD(c, RESET, WRITE);
2424 c.val = cpu_to_be32(reset);
2425 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2429 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2430 * @adap: the adapter
2431 * @mbox: mailbox to use for the FW RESET command (if desired)
2432 * @force: force uP into RESET even if FW RESET command fails
2434 * Issues a RESET command to firmware (if desired) with a HALT indication
2435 * and then puts the microprocessor into RESET state. The RESET command
2436 * will only be issued if a legitimate mailbox is provided (mbox <=
2437 * M_PCIE_FW_MASTER).
2439 * This is generally used in order for the host to safely manipulate the
2440 * adapter without fear of conflicting with whatever the firmware might
2441 * be doing. The only way out of this state is to RESTART the firmware
2444 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2449 * If a legitimate mailbox is provided, issue a RESET command
2450 * with a HALT indication.
2452 if (mbox <= M_PCIE_FW_MASTER) {
2453 struct fw_reset_cmd c;
2455 memset(&c, 0, sizeof(c));
2456 INIT_CMD(c, RESET, WRITE);
2457 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
2458 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
2459 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2463 * Normally we won't complete the operation if the firmware RESET
2464 * command fails but if our caller insists we'll go ahead and put the
2465 * uP into RESET. This can be useful if the firmware is hung or even
2466 * missing ... We'll have to take the risk of putting the uP into
2467 * RESET without the cooperation of firmware in that case.
2469 * We also force the firmware's HALT flag to be on in case we bypassed
2470 * the firmware RESET command above or we're dealing with old firmware
2471 * which doesn't have the HALT capability. This will serve as a flag
2472 * for the incoming firmware to know that it's coming out of a HALT
2473 * rather than a RESET ... if it's new enough to understand that ...
2475 if (ret == 0 || force) {
2476 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
2477 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
2482 * And we always return the result of the firmware RESET command
2483 * even when we force the uP into RESET ...
2489 * t4_fw_restart - restart the firmware by taking the uP out of RESET
2490 * @adap: the adapter
2491 * @mbox: mailbox to use for the FW RESET command (if desired)
2492 * @reset: if we want to do a RESET to restart things
2494 * Restart firmware previously halted by t4_fw_halt(). On successful
2495 * return the previous PF Master remains as the new PF Master and there
2496 * is no need to issue a new HELLO command, etc.
2498 * We do this in two ways:
2500 * 1. If we're dealing with newer firmware we'll simply want to take
2501 * the chip's microprocessor out of RESET. This will cause the
2502 * firmware to start up from its start vector. And then we'll loop
2503 * until the firmware indicates it's started again (PCIE_FW.HALT
2504 * reset to 0) or we timeout.
2506 * 2. If we're dealing with older firmware then we'll need to RESET
2507 * the chip since older firmware won't recognize the PCIE_FW.HALT
2508 * flag and automatically RESET itself on startup.
2510 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
2514 * Since we're directing the RESET instead of the firmware
2515 * doing it automatically, we need to clear the PCIE_FW.HALT
2518 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
2521 * If we've been given a valid mailbox, first try to get the
2522 * firmware to do the RESET. If that works, great and we can
2523 * return success. Otherwise, if we haven't been given a
2524 * valid mailbox or the RESET command failed, fall back to
2525 * hitting the chip with a hammer.
2527 if (mbox <= M_PCIE_FW_MASTER) {
2528 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
2530 if (t4_fw_reset(adap, mbox,
2531 F_PIORST | F_PIORSTMODE) == 0)
2535 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
2540 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
2541 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
2542 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
2553 * t4_fixup_host_params_compat - fix up host-dependent parameters
2554 * @adap: the adapter
2555 * @page_size: the host's Base Page Size
2556 * @cache_line_size: the host's Cache Line Size
2557 * @chip_compat: maintain compatibility with designated chip
2559 * Various registers in the chip contain values which are dependent on the
2560 * host's Base Page and Cache Line Sizes. This function will fix all of
2561 * those registers with the appropriate values as passed in ...
2563 * @chip_compat is used to limit the set of changes that are made
2564 * to be compatible with the indicated chip release. This is used by
2565 * drivers to maintain compatibility with chip register settings when
2566 * the drivers haven't [yet] been updated with new chip support.
2568 int t4_fixup_host_params_compat(struct adapter *adap,
2569 unsigned int page_size,
2570 unsigned int cache_line_size,
2571 enum chip_type chip_compat)
2573 unsigned int page_shift = cxgbe_fls(page_size) - 1;
2574 unsigned int sge_hps = page_shift - 10;
2575 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
2576 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
2577 unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
2579 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
2580 V_HOSTPAGESIZEPF0(sge_hps) |
2581 V_HOSTPAGESIZEPF1(sge_hps) |
2582 V_HOSTPAGESIZEPF2(sge_hps) |
2583 V_HOSTPAGESIZEPF3(sge_hps) |
2584 V_HOSTPAGESIZEPF4(sge_hps) |
2585 V_HOSTPAGESIZEPF5(sge_hps) |
2586 V_HOSTPAGESIZEPF6(sge_hps) |
2587 V_HOSTPAGESIZEPF7(sge_hps));
2589 if (is_t4(adap->params.chip) || is_t4(chip_compat))
2590 t4_set_reg_field(adap, A_SGE_CONTROL,
2591 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
2592 F_EGRSTATUSPAGESIZE,
2593 V_INGPADBOUNDARY(fl_align_log -
2594 X_INGPADBOUNDARY_SHIFT) |
2595 V_EGRSTATUSPAGESIZE(stat_len != 64));
2598 * T5 introduced the separation of the Free List Padding and
2599 * Packing Boundaries. Thus, we can select a smaller Padding
2600 * Boundary to avoid uselessly chewing up PCIe Link and Memory
2601 * Bandwidth, and use a Packing Boundary which is large enough
2602 * to avoid false sharing between CPUs, etc.
2604 * For the PCI Link, the smaller the Padding Boundary the
2605 * better. For the Memory Controller, a smaller Padding
2606 * Boundary is better until we cross under the Memory Line
2607 * Size (the minimum unit of transfer to/from Memory). If we
2608 * have a Padding Boundary which is smaller than the Memory
2609 * Line Size, that'll involve a Read-Modify-Write cycle on the
2610 * Memory Controller which is never good. For T5 the smallest
2611 * Padding Boundary which we can select is 32 bytes which is
2612 * larger than any known Memory Controller Line Size so we'll
2617 * N.B. T5 has a different interpretation of the "0" value for
2618 * the Packing Boundary. This corresponds to 16 bytes instead
2619 * of the expected 32 bytes. We never have a Packing Boundary
2620 * less than 32 bytes so we can't use that special value but
2621 * on the other hand, if we wanted 32 bytes, the best we can
2622 * really do is 64 bytes ...
2624 if (fl_align <= 32) {
2628 t4_set_reg_field(adap, A_SGE_CONTROL,
2629 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
2630 F_EGRSTATUSPAGESIZE,
2631 V_INGPADBOUNDARY(X_INGPCIEBOUNDARY_32B) |
2632 V_EGRSTATUSPAGESIZE(stat_len != 64));
2633 t4_set_reg_field(adap, A_SGE_CONTROL2,
2634 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
2635 V_INGPACKBOUNDARY(fl_align_log -
2636 X_INGPACKBOUNDARY_SHIFT));
2640 * Adjust various SGE Free List Host Buffer Sizes.
2642 * The first four entries are:
2646 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
2647 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
2649 * For the single-MTU buffers in unpacked mode we need to include
2650 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
2651 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
2652 * Padding boundary. All of these are accommodated in the Factory
2653 * Default Firmware Configuration File but we need to adjust it for
2654 * this host's cache line size.
2656 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
2657 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
2658 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
2660 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
2661 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
2664 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
2670 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
2671 * @adap: the adapter
2672 * @page_size: the host's Base Page Size
2673 * @cache_line_size: the host's Cache Line Size
2675 * Various registers in T4 contain values which are dependent on the
2676 * host's Base Page and Cache Line Sizes. This function will fix all of
2677 * those registers with the appropriate values as passed in ...
2679 * This routine makes changes which are compatible with T4 chips.
2681 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
2682 unsigned int cache_line_size)
2684 return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
2689 * t4_fw_initialize - ask FW to initialize the device
2690 * @adap: the adapter
2691 * @mbox: mailbox to use for the FW command
2693 * Issues a command to FW to partially initialize the device. This
2694 * performs initialization that generally doesn't depend on user input.
2696 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
2698 struct fw_initialize_cmd c;
2700 memset(&c, 0, sizeof(c));
2701 INIT_CMD(c, INITIALIZE, WRITE);
2702 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2706 * t4_query_params_rw - query FW or device parameters
2707 * @adap: the adapter
2708 * @mbox: mailbox to use for the FW command
2711 * @nparams: the number of parameters
2712 * @params: the parameter names
2713 * @val: the parameter values
2714 * @rw: Write and read flag
2716 * Reads the value of FW or device parameters. Up to 7 parameters can be
2719 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
2720 unsigned int pf, unsigned int vf,
2721 unsigned int nparams, const u32 *params,
2726 struct fw_params_cmd c;
2727 __be32 *p = &c.param[0].mnem;
2732 memset(&c, 0, sizeof(c));
2733 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
2734 F_FW_CMD_REQUEST | F_FW_CMD_READ |
2735 V_FW_PARAMS_CMD_PFN(pf) |
2736 V_FW_PARAMS_CMD_VFN(vf));
2737 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2739 for (i = 0; i < nparams; i++) {
2740 *p++ = cpu_to_be32(*params++);
2742 *p = cpu_to_be32(*(val + i));
2746 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2748 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
2749 *val++ = be32_to_cpu(*p);
2753 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2754 unsigned int vf, unsigned int nparams, const u32 *params,
2757 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
2761 * t4_set_params_timeout - sets FW or device parameters
2762 * @adap: the adapter
2763 * @mbox: mailbox to use for the FW command
2766 * @nparams: the number of parameters
2767 * @params: the parameter names
2768 * @val: the parameter values
2769 * @timeout: the timeout time
2771 * Sets the value of FW or device parameters. Up to 7 parameters can be
2772 * specified at once.
2774 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
2775 unsigned int pf, unsigned int vf,
2776 unsigned int nparams, const u32 *params,
2777 const u32 *val, int timeout)
2779 struct fw_params_cmd c;
2780 __be32 *p = &c.param[0].mnem;
2785 memset(&c, 0, sizeof(c));
2786 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
2787 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2788 V_FW_PARAMS_CMD_PFN(pf) |
2789 V_FW_PARAMS_CMD_VFN(vf));
2790 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2793 *p++ = cpu_to_be32(*params++);
2794 *p++ = cpu_to_be32(*val++);
2797 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
2800 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2801 unsigned int vf, unsigned int nparams, const u32 *params,
2804 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
2805 FW_CMD_MAX_TIMEOUT);
2809 * t4_alloc_vi_func - allocate a virtual interface
2810 * @adap: the adapter
2811 * @mbox: mailbox to use for the FW command
2812 * @port: physical port associated with the VI
2813 * @pf: the PF owning the VI
2814 * @vf: the VF owning the VI
2815 * @nmac: number of MAC addresses needed (1 to 5)
2816 * @mac: the MAC addresses of the VI
2817 * @rss_size: size of RSS table slice associated with this VI
2818 * @portfunc: which Port Application Function MAC Address is desired
2819 * @idstype: Intrusion Detection Type
2821 * Allocates a virtual interface for the given physical port. If @mac is
2822 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
2823 * @mac should be large enough to hold @nmac Ethernet addresses, they are
2824 * stored consecutively so the space needed is @nmac * 6 bytes.
2825 * Returns a negative error number or the non-negative VI id.
2827 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
2828 unsigned int port, unsigned int pf, unsigned int vf,
2829 unsigned int nmac, u8 *mac, unsigned int *rss_size,
2830 unsigned int portfunc, unsigned int idstype)
2835 memset(&c, 0, sizeof(c));
2836 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
2837 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
2838 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
2839 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
2840 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
2841 V_FW_VI_CMD_FUNC(portfunc));
2842 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
2845 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2850 memcpy(mac, c.mac, sizeof(c.mac));
2853 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
2856 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
2859 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
2862 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
2867 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
2868 return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
2872 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
2873 * @adap: the adapter
2874 * @mbox: mailbox to use for the FW command
2875 * @port: physical port associated with the VI
2876 * @pf: the PF owning the VI
2877 * @vf: the VF owning the VI
2878 * @nmac: number of MAC addresses needed (1 to 5)
2879 * @mac: the MAC addresses of the VI
2880 * @rss_size: size of RSS table slice associated with this VI
2882 * Backwards compatible and convieniance routine to allocate a Virtual
2883 * Interface with a Ethernet Port Application Function and Intrustion
2884 * Detection System disabled.
2886 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
2887 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
2888 unsigned int *rss_size)
2890 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
2895 * t4_free_vi - free a virtual interface
2896 * @adap: the adapter
2897 * @mbox: mailbox to use for the FW command
2898 * @pf: the PF owning the VI
2899 * @vf: the VF owning the VI
2900 * @viid: virtual interface identifiler
2902 * Free a previously allocated virtual interface.
2904 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
2905 unsigned int vf, unsigned int viid)
2909 memset(&c, 0, sizeof(c));
2910 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
2911 F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
2912 V_FW_VI_CMD_VFN(vf));
2913 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
2914 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
2916 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2920 * t4_set_rxmode - set Rx properties of a virtual interface
2921 * @adap: the adapter
2922 * @mbox: mailbox to use for the FW command
2924 * @mtu: the new MTU or -1
2925 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
2926 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
2927 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
2928 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
2930 * @sleep_ok: if true we may sleep while awaiting command completion
2932 * Sets Rx properties of a virtual interface.
2934 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
2935 int mtu, int promisc, int all_multi, int bcast, int vlanex,
2938 struct fw_vi_rxmode_cmd c;
2940 /* convert to FW values */
2942 mtu = M_FW_VI_RXMODE_CMD_MTU;
2944 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
2946 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
2948 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
2950 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
2952 memset(&c, 0, sizeof(c));
2953 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
2954 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2955 V_FW_VI_RXMODE_CMD_VIID(viid));
2956 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2957 c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
2958 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
2959 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
2960 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
2961 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
2962 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
2966 * t4_change_mac - modifies the exact-match filter for a MAC address
2967 * @adap: the adapter
2968 * @mbox: mailbox to use for the FW command
2970 * @idx: index of existing filter for old value of MAC address, or -1
2971 * @addr: the new MAC address value
2972 * @persist: whether a new MAC allocation should be persistent
2973 * @add_smt: if true also add the address to the HW SMT
2975 * Modifies an exact-match filter and sets it to the new MAC address if
2976 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
2977 * latter case the address is added persistently if @persist is %true.
2979 * Note that in general it is not possible to modify the value of a given
2980 * filter so the generic way to modify an address filter is to free the one
2981 * being used by the old address value and allocate a new filter for the
2982 * new address value.
2984 * Returns a negative error number or the index of the filter with the new
2985 * MAC value. Note that this index may differ from @idx.
2987 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
2988 int idx, const u8 *addr, bool persist, bool add_smt)
2991 struct fw_vi_mac_cmd c;
2992 struct fw_vi_mac_exact *p = c.u.exact;
2993 int max_mac_addr = adap->params.arch.mps_tcam_size;
2995 if (idx < 0) /* new allocation */
2996 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
2997 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
2999 memset(&c, 0, sizeof(c));
3000 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3001 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3002 V_FW_VI_MAC_CMD_VIID(viid));
3003 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3004 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3005 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3006 V_FW_VI_MAC_CMD_IDX(idx));
3007 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3009 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3011 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3012 if (ret >= max_mac_addr)
3019 * t4_enable_vi_params - enable/disable a virtual interface
3020 * @adap: the adapter
3021 * @mbox: mailbox to use for the FW command
3023 * @rx_en: 1=enable Rx, 0=disable Rx
3024 * @tx_en: 1=enable Tx, 0=disable Tx
3025 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3027 * Enables/disables a virtual interface. Note that setting DCB Enable
3028 * only makes sense when enabling a Virtual Interface ...
3030 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3031 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3033 struct fw_vi_enable_cmd c;
3035 memset(&c, 0, sizeof(c));
3036 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3037 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3038 V_FW_VI_ENABLE_CMD_VIID(viid));
3039 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3040 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3041 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3043 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3047 * t4_enable_vi - enable/disable a virtual interface
3048 * @adap: the adapter
3049 * @mbox: mailbox to use for the FW command
3051 * @rx_en: 1=enable Rx, 0=disable Rx
3052 * @tx_en: 1=enable Tx, 0=disable Tx
3054 * Enables/disables a virtual interface. Note that setting DCB Enable
3055 * only makes sense when enabling a Virtual Interface ...
3057 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3058 bool rx_en, bool tx_en)
3060 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3064 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3065 * @adap: the adapter
3066 * @mbox: mailbox to use for the FW command
3067 * @start: %true to enable the queues, %false to disable them
3068 * @pf: the PF owning the queues
3069 * @vf: the VF owning the queues
3070 * @iqid: ingress queue id
3071 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3072 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3074 * Starts or stops an ingress queue and its associated FLs, if any.
3076 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3077 unsigned int pf, unsigned int vf, unsigned int iqid,
3078 unsigned int fl0id, unsigned int fl1id)
3082 memset(&c, 0, sizeof(c));
3083 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3084 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3085 V_FW_IQ_CMD_VFN(vf));
3086 c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
3087 V_FW_IQ_CMD_IQSTOP(!start) |
3089 c.iqid = cpu_to_be16(iqid);
3090 c.fl0id = cpu_to_be16(fl0id);
3091 c.fl1id = cpu_to_be16(fl1id);
3092 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3096 * t4_iq_free - free an ingress queue and its FLs
3097 * @adap: the adapter
3098 * @mbox: mailbox to use for the FW command
3099 * @pf: the PF owning the queues
3100 * @vf: the VF owning the queues
3101 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
3102 * @iqid: ingress queue id
3103 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3104 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3106 * Frees an ingress queue and its associated FLs, if any.
3108 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3109 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3110 unsigned int fl0id, unsigned int fl1id)
3114 memset(&c, 0, sizeof(c));
3115 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3116 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3117 V_FW_IQ_CMD_VFN(vf));
3118 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
3119 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
3120 c.iqid = cpu_to_be16(iqid);
3121 c.fl0id = cpu_to_be16(fl0id);
3122 c.fl1id = cpu_to_be16(fl1id);
3123 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3127 * t4_eth_eq_free - free an Ethernet egress queue
3128 * @adap: the adapter
3129 * @mbox: mailbox to use for the FW command
3130 * @pf: the PF owning the queue
3131 * @vf: the VF owning the queue
3132 * @eqid: egress queue id
3134 * Frees an Ethernet egress queue.
3136 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3137 unsigned int vf, unsigned int eqid)
3139 struct fw_eq_eth_cmd c;
3141 memset(&c, 0, sizeof(c));
3142 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
3143 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3144 V_FW_EQ_ETH_CMD_PFN(pf) |
3145 V_FW_EQ_ETH_CMD_VFN(vf));
3146 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3147 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
3148 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3152 * t4_handle_fw_rpl - process a FW reply message
3153 * @adap: the adapter
3154 * @rpl: start of the FW message
3156 * Processes a FW message, such as link state change messages.
3158 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3160 u8 opcode = *(const u8 *)rpl;
3163 * This might be a port command ... this simplifies the following
3164 * conditionals ... We can get away with pre-dereferencing
3165 * action_to_len16 because it's in the first 16 bytes and all messages
3166 * will be at least that long.
3168 const struct fw_port_cmd *p = (const void *)rpl;
3169 unsigned int action =
3170 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
3172 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
3173 /* link/module state change message */
3174 int speed = 0, fc = 0, i;
3175 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
3176 struct port_info *pi = NULL;
3177 struct link_config *lc;
3178 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
3179 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
3180 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
3182 if (stat & F_FW_PORT_CMD_RXPAUSE)
3184 if (stat & F_FW_PORT_CMD_TXPAUSE)
3186 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3187 speed = ETH_SPEED_NUM_100M;
3188 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3189 speed = ETH_SPEED_NUM_1G;
3190 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3191 speed = ETH_SPEED_NUM_10G;
3192 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
3193 speed = ETH_SPEED_NUM_40G;
3195 for_each_port(adap, i) {
3196 pi = adap2pinfo(adap, i);
3197 if (pi->tx_chan == chan)
3202 if (mod != pi->mod_type) {
3204 t4_os_portmod_changed(adap, i);
3206 if (link_ok != lc->link_ok || speed != lc->speed ||
3207 fc != lc->fc) { /* something changed */
3208 if (!link_ok && lc->link_ok) {
3209 static const char * const reason[] = {
3212 "Auto-negotiation Failure",
3214 "Insufficient Airflow",
3215 "Unable To Determine Reason",
3216 "No RX Signal Detected",
3219 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
3221 dev_warn(adap, "Port %d link down, reason: %s\n",
3224 lc->link_ok = link_ok;
3227 lc->supported = be16_to_cpu(p->u.info.pcap);
3230 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
3236 void t4_reset_link_config(struct adapter *adap, int idx)
3238 struct port_info *pi = adap2pinfo(adap, idx);
3239 struct link_config *lc = &pi->link_cfg;
3242 lc->requested_speed = 0;
3243 lc->requested_fc = 0;
3249 * init_link_config - initialize a link's SW state
3250 * @lc: structure holding the link state
3251 * @caps: link capabilities
3253 * Initializes the SW state maintained for each link, including the link's
3254 * capabilities and default speed/flow-control/autonegotiation settings.
3256 static void init_link_config(struct link_config *lc,
3259 lc->supported = caps;
3260 lc->requested_speed = 0;
3262 lc->requested_fc = 0;
3264 if (lc->supported & FW_PORT_CAP_ANEG) {
3265 lc->advertising = lc->supported & ADVERT_MASK;
3266 lc->autoneg = AUTONEG_ENABLE;
3268 lc->advertising = 0;
3269 lc->autoneg = AUTONEG_DISABLE;
3274 * t4_wait_dev_ready - wait till to reads of registers work
3276 * Right after the device is RESET is can take a small amount of time
3277 * for it to respond to register reads. Until then, all reads will
3278 * return either 0xff...ff or 0xee...ee. Return an error if reads
3279 * don't work within a reasonable time frame.
3281 static int t4_wait_dev_ready(struct adapter *adapter)
3285 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3287 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
3291 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3292 return (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS
3297 u32 vendor_and_model_id;
3301 int t4_get_flash_params(struct adapter *adapter)
3304 * Table for non-Numonix supported flash parts. Numonix parts are left
3305 * to the preexisting well-tested code. All flash parts have 64KB
3308 static struct flash_desc supported_flash[] = {
3309 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
3316 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
3318 ret = sf1_read(adapter, 3, 0, 1, &info);
3319 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3323 for (i = 0; i < ARRAY_SIZE(supported_flash); ++i)
3324 if (supported_flash[i].vendor_and_model_id == info) {
3325 adapter->params.sf_size = supported_flash[i].size_mb;
3326 adapter->params.sf_nsec =
3327 adapter->params.sf_size / SF_SEC_SIZE;
3331 if ((info & 0xff) != 0x20) /* not a Numonix flash */
3333 info >>= 16; /* log2 of size */
3334 if (info >= 0x14 && info < 0x18)
3335 adapter->params.sf_nsec = 1 << (info - 16);
3336 else if (info == 0x18)
3337 adapter->params.sf_nsec = 64;
3340 adapter->params.sf_size = 1 << info;
3343 * We should reject adapters with FLASHes which are too small. So, emit
3346 if (adapter->params.sf_size < FLASH_MIN_SIZE) {
3347 dev_warn(adapter, "WARNING!!! FLASH size %#x < %#x!!!\n",
3348 adapter->params.sf_size, FLASH_MIN_SIZE);
3354 static void set_pcie_completion_timeout(struct adapter *adapter,
3360 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
3362 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
3365 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
3370 * t4_prep_adapter - prepare SW and HW for operation
3371 * @adapter: the adapter
3373 * Initialize adapter SW state for the various HW modules, set initial
3374 * values for some adapter tunables, take PHYs out of reset, and
3375 * initialize the MDIO interface.
3377 int t4_prep_adapter(struct adapter *adapter)
3382 ret = t4_wait_dev_ready(adapter);
3386 pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
3387 adapter->params.pci.device_id = adapter->pdev->id.device_id;
3388 adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
3391 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
3392 * ADAPTER (VERSION << 4 | REVISION)
3394 ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
3395 adapter->params.chip = 0;
3398 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3399 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
3400 adapter->params.arch.mps_tcam_size =
3401 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3402 adapter->params.arch.mps_rplc_size = 128;
3403 adapter->params.arch.nchan = NCHAN;
3404 adapter->params.arch.vfcount = 128;
3407 dev_err(adapter, "%s: Device %d is not supported\n",
3408 __func__, adapter->params.pci.device_id);
3412 adapter->params.pci.vpd_cap_addr =
3413 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
3415 ret = t4_get_flash_params(adapter);
3419 adapter->params.cim_la_size = CIMLA_SIZE;
3421 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3424 * Default port and clock for debugging in case we can't reach FW.
3426 adapter->params.nports = 1;
3427 adapter->params.portvec = 1;
3428 adapter->params.vpd.cclk = 50000;
3430 /* Set pci completion timeout value to 4 seconds. */
3431 set_pcie_completion_timeout(adapter, 0xd);
3436 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
3437 * @adapter: the adapter
3438 * @qid: the Queue ID
3439 * @qtype: the Ingress or Egress type for @qid
3440 * @pbar2_qoffset: BAR2 Queue Offset
3441 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
3443 * Returns the BAR2 SGE Queue Registers information associated with the
3444 * indicated Absolute Queue ID. These are passed back in return value
3445 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
3446 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
3448 * This may return an error which indicates that BAR2 SGE Queue
3449 * registers aren't available. If an error is not returned, then the
3450 * following values are returned:
3452 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
3453 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
3455 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
3456 * require the "Inferred Queue ID" ability may be used. E.g. the
3457 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
3458 * then these "Inferred Queue ID" register may not be used.
3460 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
3461 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
3462 unsigned int *pbar2_qid)
3464 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
3465 u64 bar2_page_offset, bar2_qoffset;
3466 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
3469 * T4 doesn't support BAR2 SGE Queue registers.
3471 if (is_t4(adapter->params.chip))
3475 * Get our SGE Page Size parameters.
3477 page_shift = adapter->params.sge.hps + 10;
3478 page_size = 1 << page_shift;
3481 * Get the right Queues per Page parameters for our Queue.
3483 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
3484 adapter->params.sge.eq_qpp :
3485 adapter->params.sge.iq_qpp);
3486 qpp_mask = (1 << qpp_shift) - 1;
3489 * Calculate the basics of the BAR2 SGE Queue register area:
3490 * o The BAR2 page the Queue registers will be in.
3491 * o The BAR2 Queue ID.
3492 * o The BAR2 Queue ID Offset into the BAR2 page.
3494 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
3495 bar2_qid = qid & qpp_mask;
3496 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
3499 * If the BAR2 Queue ID Offset is less than the Page Size, then the
3500 * hardware will infer the Absolute Queue ID simply from the writes to
3501 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
3502 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
3503 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
3504 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
3505 * from the BAR2 Page and BAR2 Queue ID.
3507 * One important censequence of this is that some BAR2 SGE registers
3508 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
3509 * there. But other registers synthesize the SGE Queue ID purely
3510 * from the writes to the registers -- the Write Combined Doorbell
3511 * Buffer is a good example. These BAR2 SGE Registers are only
3512 * available for those BAR2 SGE Register areas where the SGE Absolute
3513 * Queue ID can be inferred from simple writes.
3515 bar2_qoffset = bar2_page_offset;
3516 bar2_qinferred = (bar2_qid_offset < page_size);
3517 if (bar2_qinferred) {
3518 bar2_qoffset += bar2_qid_offset;
3522 *pbar2_qoffset = bar2_qoffset;
3523 *pbar2_qid = bar2_qid;
3528 * t4_init_sge_params - initialize adap->params.sge
3529 * @adapter: the adapter
3531 * Initialize various fields of the adapter's SGE Parameters structure.
3533 int t4_init_sge_params(struct adapter *adapter)
3535 struct sge_params *sge_params = &adapter->params.sge;
3537 unsigned int s_hps, s_qpp;
3540 * Extract the SGE Page Size for our PF.
3542 hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
3543 s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
3545 sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
3548 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
3550 s_qpp = (S_QUEUESPERPAGEPF0 +
3551 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
3552 qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
3553 sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
3554 qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
3555 sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
3561 * t4_init_tp_params - initialize adap->params.tp
3562 * @adap: the adapter
3564 * Initialize various fields of the adapter's TP Parameters structure.
3566 int t4_init_tp_params(struct adapter *adap)
3571 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
3572 adap->params.tp.tre = G_TIMERRESOLUTION(v);
3573 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
3575 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
3576 for (chan = 0; chan < NCHAN; chan++)
3577 adap->params.tp.tx_modq[chan] = chan;
3580 * Cache the adapter's Compressed Filter Mode and global Incress
3583 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
3584 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
3585 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
3586 &adap->params.tp.ingress_config, 1,
3587 A_TP_INGRESS_CONFIG);
3590 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
3591 * shift positions of several elements of the Compressed Filter Tuple
3592 * for this adapter which we need frequently ...
3594 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
3595 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
3596 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
3597 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
3601 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
3602 * represents the presense of an Outer VLAN instead of a VNIC ID.
3604 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
3605 adap->params.tp.vnic_shift = -1;
3611 * t4_filter_field_shift - calculate filter field shift
3612 * @adap: the adapter
3613 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
3615 * Return the shift position of a filter field within the Compressed
3616 * Filter Tuple. The filter field is specified via its selection bit
3617 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
3619 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
3621 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
3625 if ((filter_mode & filter_sel) == 0)
3628 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
3629 switch (filter_mode & sel) {
3631 field_shift += W_FT_FCOE;
3634 field_shift += W_FT_PORT;
3637 field_shift += W_FT_VNIC_ID;
3640 field_shift += W_FT_VLAN;
3643 field_shift += W_FT_TOS;
3646 field_shift += W_FT_PROTOCOL;
3649 field_shift += W_FT_ETHERTYPE;
3652 field_shift += W_FT_MACMATCH;
3655 field_shift += W_FT_MPSHITTYPE;
3657 case F_FRAGMENTATION:
3658 field_shift += W_FT_FRAGMENTATION;
3665 int t4_init_rss_mode(struct adapter *adap, int mbox)
3668 struct fw_rss_vi_config_cmd rvc;
3670 memset(&rvc, 0, sizeof(rvc));
3672 for_each_port(adap, i) {
3673 struct port_info *p = adap2pinfo(adap, i);
3675 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
3676 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3677 V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
3678 rvc.retval_len16 = htonl(FW_LEN16(rvc));
3679 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
3682 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
3687 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
3691 struct fw_port_cmd c;
3693 memset(&c, 0, sizeof(c));
3695 for_each_port(adap, i) {
3696 unsigned int rss_size = 0;
3697 struct port_info *p = adap2pinfo(adap, i);
3699 while ((adap->params.portvec & (1 << j)) == 0)
3702 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3703 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3704 V_FW_PORT_CMD_PORTID(j));
3705 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
3706 FW_PORT_ACTION_GET_PORT_INFO) |
3708 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3712 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
3718 p->rss_size = rss_size;
3719 t4_os_set_hw_addr(adap, i, addr);
3721 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
3722 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
3723 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
3724 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
3725 p->mod_type = FW_PORT_MOD_TYPE_NA;
3727 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));