4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <netinet/in.h>
36 #include <rte_interrupts.h>
38 #include <rte_debug.h>
40 #include <rte_atomic.h>
41 #include <rte_branch_prediction.h>
42 #include <rte_memory.h>
43 #include <rte_tailq.h>
45 #include <rte_alarm.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev_driver.h>
48 #include <rte_malloc.h>
49 #include <rte_random.h>
51 #include <rte_byteorder.h>
55 #include "t4_regs_values.h"
56 #include "t4fw_interface.h"
58 static void init_link_config(struct link_config *lc, unsigned int pcaps,
62 * t4_read_mtu_tbl - returns the values in the HW path MTU table
64 * @mtus: where to store the MTU values
65 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
67 * Reads the HW path MTU table.
69 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
74 for (i = 0; i < NMTUS; ++i) {
75 t4_write_reg(adap, A_TP_MTU_TABLE,
76 V_MTUINDEX(0xff) | V_MTUVALUE(i));
77 v = t4_read_reg(adap, A_TP_MTU_TABLE);
78 mtus[i] = G_MTUVALUE(v);
80 mtu_log[i] = G_MTUWIDTH(v);
85 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
87 * @addr: the indirect TP register address
88 * @mask: specifies the field within the register to modify
89 * @val: new value for the field
91 * Sets a field of an indirect TP register to the given value.
93 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
94 unsigned int mask, unsigned int val)
96 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
97 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
98 t4_write_reg(adap, A_TP_PIO_DATA, val);
101 /* The minimum additive increment value for the congestion control table */
102 #define CC_MIN_INCR 2U
105 * t4_load_mtus - write the MTU and congestion control HW tables
107 * @mtus: the values for the MTU table
108 * @alpha: the values for the congestion control alpha parameter
109 * @beta: the values for the congestion control beta parameter
111 * Write the HW MTU table with the supplied MTUs and the high-speed
112 * congestion control table with the supplied alpha, beta, and MTUs.
113 * We write the two tables together because the additive increments
114 * depend on the MTUs.
116 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
117 const unsigned short *alpha, const unsigned short *beta)
119 static const unsigned int avg_pkts[NCCTRL_WIN] = {
120 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
121 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
122 28672, 40960, 57344, 81920, 114688, 163840, 229376
127 for (i = 0; i < NMTUS; ++i) {
128 unsigned int mtu = mtus[i];
129 unsigned int log2 = cxgbe_fls(mtu);
131 if (!(mtu & ((1 << log2) >> 2))) /* round */
133 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
134 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
136 for (w = 0; w < NCCTRL_WIN; ++w) {
139 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
142 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
143 (w << 16) | (beta[w] << 13) | inc);
149 * t4_wait_op_done_val - wait until an operation is completed
150 * @adapter: the adapter performing the operation
151 * @reg: the register to check for completion
152 * @mask: a single-bit field within @reg that indicates completion
153 * @polarity: the value of the field when the operation is completed
154 * @attempts: number of check iterations
155 * @delay: delay in usecs between iterations
156 * @valp: where to store the value of the register at completion time
158 * Wait until an operation is completed by checking a bit in a register
159 * up to @attempts times. If @valp is not NULL the value of the register
160 * at the time it indicated completion is stored there. Returns 0 if the
161 * operation completes and -EAGAIN otherwise.
163 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
164 int polarity, int attempts, int delay, u32 *valp)
167 u32 val = t4_read_reg(adapter, reg);
169 if (!!(val & mask) == polarity) {
182 * t4_set_reg_field - set a register field to a value
183 * @adapter: the adapter to program
184 * @addr: the register address
185 * @mask: specifies the portion of the register to modify
186 * @val: the new value for the register field
188 * Sets a register field specified by the supplied mask to the
191 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
194 u32 v = t4_read_reg(adapter, addr) & ~mask;
196 t4_write_reg(adapter, addr, v | val);
197 (void)t4_read_reg(adapter, addr); /* flush */
201 * t4_read_indirect - read indirectly addressed registers
203 * @addr_reg: register holding the indirect address
204 * @data_reg: register holding the value of the indirect register
205 * @vals: where the read register values are stored
206 * @nregs: how many indirect registers to read
207 * @start_idx: index of first indirect register to read
209 * Reads registers that are accessed indirectly through an address/data
212 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
213 unsigned int data_reg, u32 *vals, unsigned int nregs,
214 unsigned int start_idx)
217 t4_write_reg(adap, addr_reg, start_idx);
218 *vals++ = t4_read_reg(adap, data_reg);
224 * t4_write_indirect - write indirectly addressed registers
226 * @addr_reg: register holding the indirect addresses
227 * @data_reg: register holding the value for the indirect registers
228 * @vals: values to write
229 * @nregs: how many indirect registers to write
230 * @start_idx: address of first indirect register to write
232 * Writes a sequential block of registers that are accessed indirectly
233 * through an address/data register pair.
235 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
236 unsigned int data_reg, const u32 *vals,
237 unsigned int nregs, unsigned int start_idx)
240 t4_write_reg(adap, addr_reg, start_idx++);
241 t4_write_reg(adap, data_reg, *vals++);
246 * t4_report_fw_error - report firmware error
249 * The adapter firmware can indicate error conditions to the host.
250 * If the firmware has indicated an error, print out the reason for
251 * the firmware error.
253 static void t4_report_fw_error(struct adapter *adap)
255 static const char * const reason[] = {
256 "Crash", /* PCIE_FW_EVAL_CRASH */
257 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
258 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
259 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
260 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
261 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
262 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
263 "Reserved", /* reserved */
267 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
268 if (pcie_fw & F_PCIE_FW_ERR)
269 pr_err("%s: Firmware reports adapter error: %s\n",
270 __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
274 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
276 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
279 for ( ; nflit; nflit--, mbox_addr += 8)
280 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
284 * Handle a FW assertion reported in a mailbox.
286 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
288 struct fw_debug_cmd asrt;
290 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
291 pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
292 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
293 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
296 #define X_CIM_PF_NOACCESS 0xeeeeeeee
299 * If the Host OS Driver needs locking arround accesses to the mailbox, this
300 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
302 /* makes single-statement usage a bit cleaner ... */
303 #ifdef T4_OS_NEEDS_MBOX_LOCKING
304 #define T4_OS_MBOX_LOCKING(x) x
306 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
310 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
312 * @mbox: index of the mailbox to use
313 * @cmd: the command to write
314 * @size: command length in bytes
315 * @rpl: where to optionally store the reply
316 * @sleep_ok: if true we may sleep while awaiting command completion
317 * @timeout: time to wait for command to finish before timing out
318 * (negative implies @sleep_ok=false)
320 * Sends the given command to FW through the selected mailbox and waits
321 * for the FW to execute the command. If @rpl is not %NULL it is used to
322 * store the FW's reply to the command. The command and its optional
323 * reply are of the same length. Some FW commands like RESET and
324 * INITIALIZE can take a considerable amount of time to execute.
325 * @sleep_ok determines whether we may sleep while awaiting the response.
326 * If sleeping is allowed we use progressive backoff otherwise we spin.
327 * Note that passing in a negative @timeout is an alternate mechanism
328 * for specifying @sleep_ok=false. This is useful when a higher level
329 * interface allows for specification of @timeout but not @sleep_ok ...
331 * Returns 0 on success or a negative errno on failure. A
332 * failure can happen either because we are not able to execute the
333 * command or FW executes it but signals an error. In the latter case
334 * the return value is the error code indicated by FW (negated).
336 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
337 const void __attribute__((__may_alias__)) *cmd,
338 int size, void *rpl, bool sleep_ok, int timeout)
341 * We delay in small increments at first in an effort to maintain
342 * responsiveness for simple, fast executing commands but then back
343 * off to larger delays to a maximum retry delay.
345 static const int delay[] = {
346 1, 1, 3, 5, 10, 10, 20, 50, 100
352 unsigned int delay_idx;
353 __be64 *temp = (__be64 *)malloc(size * sizeof(char));
355 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
356 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
358 struct mbox_entry entry;
364 if ((size & 15) || size > MBOX_LEN) {
370 memcpy(p, (const __be64 *)cmd, size);
373 * If we have a negative timeout, that implies that we can't sleep.
380 #ifdef T4_OS_NEEDS_MBOX_LOCKING
382 * Queue ourselves onto the mailbox access list. When our entry is at
383 * the front of the list, we have rights to access the mailbox. So we
384 * wait [for a while] till we're at the front [or bail out with an
387 t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
392 for (i = 0; ; i += ms) {
394 * If we've waited too long, return a busy indication. This
395 * really ought to be based on our initial position in the
396 * mailbox access list but this is a start. We very rarely
397 * contend on access to the mailbox ... Also check for a
398 * firmware error which we'll report as a device error.
400 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
401 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
402 t4_os_atomic_list_del(&entry, &adap->mbox_list,
404 t4_report_fw_error(adap);
406 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
410 * If we're at the head, break out and start the mailbox
413 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
417 * Delay for a bit before checking again ...
420 ms = delay[delay_idx]; /* last element may repeat */
421 if (delay_idx < ARRAY_SIZE(delay) - 1)
428 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
431 * Attempt to gain access to the mailbox.
433 for (i = 0; i < 4; i++) {
434 ctl = t4_read_reg(adap, ctl_reg);
436 if (v != X_MBOWNER_NONE)
441 * If we were unable to gain access, dequeue ourselves from the
442 * mailbox atomic access list and report the error to our caller.
444 if (v != X_MBOWNER_PL) {
445 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
448 t4_report_fw_error(adap);
450 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
454 * If we gain ownership of the mailbox and there's a "valid" message
455 * in it, this is likely an asynchronous error message from the
456 * firmware. So we'll report that and then proceed on with attempting
457 * to issue our own command ... which may well fail if the error
458 * presaged the firmware crashing ...
460 if (ctl & F_MBMSGVALID) {
461 dev_err(adap, "found VALID command in mbox %u: "
462 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
463 (unsigned long long)t4_read_reg64(adap, data_reg),
464 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
465 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
466 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
467 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
468 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
469 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
470 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
474 * Copy in the new mailbox command and send it on its way ...
476 for (i = 0; i < size; i += 8, p++)
477 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
479 CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
480 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
481 (unsigned long long)t4_read_reg64(adap, data_reg),
482 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
483 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
484 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
485 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
486 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
487 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
488 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
490 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
491 t4_read_reg(adap, ctl_reg); /* flush write */
497 * Loop waiting for the reply; bail out if we time out or the firmware
500 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
501 for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
503 ms = delay[delay_idx]; /* last element may repeat */
504 if (delay_idx < ARRAY_SIZE(delay) - 1)
511 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
512 v = t4_read_reg(adap, ctl_reg);
513 if (v == X_CIM_PF_NOACCESS)
515 if (G_MBOWNER(v) == X_MBOWNER_PL) {
516 if (!(v & F_MBMSGVALID)) {
517 t4_write_reg(adap, ctl_reg,
518 V_MBOWNER(X_MBOWNER_NONE));
522 CXGBE_DEBUG_MBOX(adap,
523 "%s: mbox %u: %016llx %016llx %016llx %016llx "
524 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
525 (unsigned long long)t4_read_reg64(adap, data_reg),
526 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
527 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
528 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
529 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
530 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
531 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
532 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
534 CXGBE_DEBUG_MBOX(adap,
535 "command %#x completed in %d ms (%ssleeping)\n",
537 i + ms, sleep_ok ? "" : "non-");
539 res = t4_read_reg64(adap, data_reg);
540 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
541 fw_asrt(adap, data_reg);
542 res = V_FW_CMD_RETVAL(EIO);
544 get_mbox_rpl(adap, rpl, size / 8, data_reg);
546 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
548 t4_os_atomic_list_del(&entry, &adap->mbox_list,
551 return -G_FW_CMD_RETVAL((int)res);
556 * We timed out waiting for a reply to our mailbox command. Report
557 * the error and also check to see if the firmware reported any
560 dev_err(adap, "command %#x in mailbox %d timed out\n",
561 *(const u8 *)cmd, mbox);
562 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
565 t4_report_fw_error(adap);
567 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
570 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
571 void *rpl, bool sleep_ok)
573 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
578 * t4_get_regs_len - return the size of the chips register set
579 * @adapter: the adapter
581 * Returns the size of the chip's BAR0 register space.
583 unsigned int t4_get_regs_len(struct adapter *adapter)
585 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
587 switch (chip_version) {
590 return T5_REGMAP_SIZE;
594 "Unsupported chip version %d\n", chip_version);
599 * t4_get_regs - read chip registers into provided buffer
601 * @buf: register buffer
602 * @buf_size: size (in bytes) of register buffer
604 * If the provided register buffer isn't large enough for the chip's
605 * full register range, the register dump will be truncated to the
606 * register buffer's size.
608 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
610 static const unsigned int t5_reg_ranges[] = {
1385 static const unsigned int t6_reg_ranges[] = {
1946 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1947 const unsigned int *reg_ranges;
1948 int reg_ranges_size, range;
1949 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1951 /* Select the right set of register ranges to dump depending on the
1952 * adapter chip type.
1954 switch (chip_version) {
1956 reg_ranges = t5_reg_ranges;
1957 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1961 reg_ranges = t6_reg_ranges;
1962 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1967 "Unsupported chip version %d\n", chip_version);
1971 /* Clear the register buffer and insert the appropriate register
1972 * values selected by the above register ranges.
1974 memset(buf, 0, buf_size);
1975 for (range = 0; range < reg_ranges_size; range += 2) {
1976 unsigned int reg = reg_ranges[range];
1977 unsigned int last_reg = reg_ranges[range + 1];
1978 u32 *bufp = (u32 *)((char *)buf + reg);
1980 /* Iterate across the register range filling in the register
1981 * buffer but don't write past the end of the register buffer.
1983 while (reg <= last_reg && bufp < buf_end) {
1984 *bufp++ = t4_read_reg(adap, reg);
1990 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1991 #define EEPROM_DELAY 10 /* 10us per poll spin */
1992 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
1994 #define EEPROM_STAT_ADDR 0x7bfc
1997 * Small utility function to wait till any outstanding VPD Access is complete.
1998 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1999 * VPD Access in flight. This allows us to handle the problem of having a
2000 * previous VPD Access time out and prevent an attempt to inject a new VPD
2001 * Request before any in-flight VPD request has completed.
2003 static int t4_seeprom_wait(struct adapter *adapter)
2005 unsigned int base = adapter->params.pci.vpd_cap_addr;
2008 /* If no VPD Access is in flight, we can just return success right
2011 if (!adapter->vpd_busy)
2014 /* Poll the VPD Capability Address/Flag register waiting for it
2015 * to indicate that the operation is complete.
2017 max_poll = EEPROM_MAX_POLL;
2021 udelay(EEPROM_DELAY);
2022 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2024 /* If the operation is complete, mark the VPD as no longer
2025 * busy and return success.
2027 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2028 adapter->vpd_busy = 0;
2031 } while (--max_poll);
2033 /* Failure! Note that we leave the VPD Busy status set in order to
2034 * avoid pushing a new VPD Access request into the VPD Capability till
2035 * the current operation eventually succeeds. It's a bug to issue a
2036 * new request when an existing request is in flight and will result
2037 * in corrupt hardware state.
2043 * t4_seeprom_read - read a serial EEPROM location
2044 * @adapter: adapter to read
2045 * @addr: EEPROM virtual address
2046 * @data: where to store the read data
2048 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2049 * VPD capability. Note that this function must be called with a virtual
2052 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2054 unsigned int base = adapter->params.pci.vpd_cap_addr;
2057 /* VPD Accesses must alway be 4-byte aligned!
2059 if (addr >= EEPROMVSIZE || (addr & 3))
2062 /* Wait for any previous operation which may still be in flight to
2065 ret = t4_seeprom_wait(adapter);
2067 dev_err(adapter, "VPD still busy from previous operation\n");
2071 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2072 * for our request to complete. If it doesn't complete, note the
2073 * error and return it to our caller. Note that we do not reset the
2076 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2077 adapter->vpd_busy = 1;
2078 adapter->vpd_flag = PCI_VPD_ADDR_F;
2079 ret = t4_seeprom_wait(adapter);
2081 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2085 /* Grab the returned data, swizzle it into our endianness and
2088 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2089 *data = le32_to_cpu(*data);
2094 * t4_seeprom_write - write a serial EEPROM location
2095 * @adapter: adapter to write
2096 * @addr: virtual EEPROM address
2097 * @data: value to write
2099 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2100 * VPD capability. Note that this function must be called with a virtual
2103 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2105 unsigned int base = adapter->params.pci.vpd_cap_addr;
2110 /* VPD Accesses must alway be 4-byte aligned!
2112 if (addr >= EEPROMVSIZE || (addr & 3))
2115 /* Wait for any previous operation which may still be in flight to
2118 ret = t4_seeprom_wait(adapter);
2120 dev_err(adapter, "VPD still busy from previous operation\n");
2124 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2125 * for our request to complete. If it doesn't complete, note the
2126 * error and return it to our caller. Note that we do not reset the
2129 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2131 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2132 (u16)addr | PCI_VPD_ADDR_F);
2133 adapter->vpd_busy = 1;
2134 adapter->vpd_flag = 0;
2135 ret = t4_seeprom_wait(adapter);
2137 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2141 /* Reset PCI_VPD_DATA register after a transaction and wait for our
2142 * request to complete. If it doesn't complete, return error.
2144 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2145 max_poll = EEPROM_MAX_POLL;
2147 udelay(EEPROM_DELAY);
2148 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2149 } while ((stats_reg & 0x1) && --max_poll);
2153 /* Return success! */
2158 * t4_seeprom_wp - enable/disable EEPROM write protection
2159 * @adapter: the adapter
2160 * @enable: whether to enable or disable write protection
2162 * Enables or disables write protection on the serial EEPROM.
2164 int t4_seeprom_wp(struct adapter *adapter, int enable)
2166 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2170 * t4_fw_tp_pio_rw - Access TP PIO through LDST
2171 * @adap: the adapter
2172 * @vals: where the indirect register values are stored/written
2173 * @nregs: how many indirect registers to read/write
2174 * @start_idx: index of first indirect register to read/write
2175 * @rw: Read (1) or Write (0)
2177 * Access TP PIO registers through LDST
2179 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
2180 unsigned int start_index, unsigned int rw)
2182 int cmd = FW_LDST_ADDRSPC_TP_PIO;
2183 struct fw_ldst_cmd c;
2187 for (i = 0 ; i < nregs; i++) {
2188 memset(&c, 0, sizeof(c));
2189 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
2191 (rw ? F_FW_CMD_READ :
2193 V_FW_LDST_CMD_ADDRSPACE(cmd));
2194 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
2196 c.u.addrval.addr = cpu_to_be32(start_index + i);
2197 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
2198 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2201 vals[i] = be32_to_cpu(c.u.addrval.val);
2207 * t4_write_rss_key - program one of the RSS keys
2208 * @adap: the adapter
2209 * @key: 10-entry array holding the 320-bit RSS key
2210 * @idx: which RSS key to write
2212 * Writes one of the RSS keys with the given 320-bit value. If @idx is
2213 * 0..15 the corresponding entry in the RSS key table is written,
2214 * otherwise the global RSS key is written.
2216 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
2218 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
2219 u8 rss_key_addr_cnt = 16;
2221 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
2222 * allows access to key addresses 16-63 by using KeyWrAddrX
2223 * as index[5:4](upper 2) into key table
2225 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
2226 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
2227 rss_key_addr_cnt = 32;
2229 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
2231 if (idx >= 0 && idx < rss_key_addr_cnt) {
2232 if (rss_key_addr_cnt > 16)
2233 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2234 V_KEYWRADDRX(idx >> 4) |
2235 V_T6_VFWRADDR(idx) | F_KEYWREN);
2237 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2238 V_KEYWRADDR(idx) | F_KEYWREN);
2243 * t4_config_rss_range - configure a portion of the RSS mapping table
2244 * @adapter: the adapter
2245 * @mbox: mbox to use for the FW command
2246 * @viid: virtual interface whose RSS subtable is to be written
2247 * @start: start entry in the table to write
2248 * @n: how many table entries to write
2249 * @rspq: values for the "response queue" (Ingress Queue) lookup table
2250 * @nrspq: number of values in @rspq
2252 * Programs the selected part of the VI's RSS mapping table with the
2253 * provided values. If @nrspq < @n the supplied values are used repeatedly
2254 * until the full table range is populated.
2256 * The caller must ensure the values in @rspq are in the range allowed for
2259 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2260 int start, int n, const u16 *rspq, unsigned int nrspq)
2263 const u16 *rsp = rspq;
2264 const u16 *rsp_end = rspq + nrspq;
2265 struct fw_rss_ind_tbl_cmd cmd;
2267 memset(&cmd, 0, sizeof(cmd));
2268 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2269 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2270 V_FW_RSS_IND_TBL_CMD_VIID(viid));
2271 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2274 * Each firmware RSS command can accommodate up to 32 RSS Ingress
2275 * Queue Identifiers. These Ingress Queue IDs are packed three to
2276 * a 32-bit word as 10-bit values with the upper remaining 2 bits
2280 int nq = min(n, 32);
2282 __be32 *qp = &cmd.iq0_to_iq2;
2285 * Set up the firmware RSS command header to send the next
2286 * "nq" Ingress Queue IDs to the firmware.
2288 cmd.niqid = cpu_to_be16(nq);
2289 cmd.startidx = cpu_to_be16(start);
2292 * "nq" more done for the start of the next loop.
2298 * While there are still Ingress Queue IDs to stuff into the
2299 * current firmware RSS command, retrieve them from the
2300 * Ingress Queue ID array and insert them into the command.
2304 * Grab up to the next 3 Ingress Queue IDs (wrapping
2305 * around the Ingress Queue ID array if necessary) and
2306 * insert them into the firmware RSS command at the
2307 * current 3-tuple position within the commad.
2311 int nqbuf = min(3, nq);
2317 while (nqbuf && nq_packed < 32) {
2324 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2325 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2326 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2330 * Send this portion of the RRS table update to the firmware;
2331 * bail out on any errors.
2333 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2342 * t4_config_vi_rss - configure per VI RSS settings
2343 * @adapter: the adapter
2344 * @mbox: mbox to use for the FW command
2347 * @defq: id of the default RSS queue for the VI.
2349 * Configures VI-specific RSS properties.
2351 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2352 unsigned int flags, unsigned int defq)
2354 struct fw_rss_vi_config_cmd c;
2356 memset(&c, 0, sizeof(c));
2357 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2358 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2359 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2360 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2361 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2362 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2363 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2367 * init_cong_ctrl - initialize congestion control parameters
2368 * @a: the alpha values for congestion control
2369 * @b: the beta values for congestion control
2371 * Initialize the congestion control parameters.
2373 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2377 for (i = 0; i < 9; i++) {
2431 #define INIT_CMD(var, cmd, rd_wr) do { \
2432 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2433 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2434 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2437 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2439 u32 cclk_param, cclk_val;
2443 * Ask firmware for the Core Clock since it knows how to translate the
2444 * Reference Clock ('V2') VPD field into a Core Clock value ...
2446 cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2447 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2448 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2449 1, &cclk_param, &cclk_val);
2451 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2457 dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2461 /* serial flash and firmware constants and flash config file constants */
2463 SF_ATTEMPTS = 10, /* max retries for SF operations */
2465 /* flash command opcodes */
2466 SF_PROG_PAGE = 2, /* program page */
2467 SF_WR_DISABLE = 4, /* disable writes */
2468 SF_RD_STATUS = 5, /* read status register */
2469 SF_WR_ENABLE = 6, /* enable writes */
2470 SF_RD_DATA_FAST = 0xb, /* read flash */
2471 SF_RD_ID = 0x9f, /* read ID */
2472 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2476 * sf1_read - read data from the serial flash
2477 * @adapter: the adapter
2478 * @byte_cnt: number of bytes to read
2479 * @cont: whether another operation will be chained
2480 * @lock: whether to lock SF for PL access only
2481 * @valp: where to store the read data
2483 * Reads up to 4 bytes of data from the serial flash. The location of
2484 * the read needs to be specified prior to calling this by issuing the
2485 * appropriate commands to the serial flash.
2487 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2488 int lock, u32 *valp)
2492 if (!byte_cnt || byte_cnt > 4)
2494 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2496 t4_write_reg(adapter, A_SF_OP,
2497 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2498 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2500 *valp = t4_read_reg(adapter, A_SF_DATA);
2505 * sf1_write - write data to the serial flash
2506 * @adapter: the adapter
2507 * @byte_cnt: number of bytes to write
2508 * @cont: whether another operation will be chained
2509 * @lock: whether to lock SF for PL access only
2510 * @val: value to write
2512 * Writes up to 4 bytes of data to the serial flash. The location of
2513 * the write needs to be specified prior to calling this by issuing the
2514 * appropriate commands to the serial flash.
2516 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2519 if (!byte_cnt || byte_cnt > 4)
2521 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2523 t4_write_reg(adapter, A_SF_DATA, val);
2524 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2525 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2526 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2530 * t4_read_flash - read words from serial flash
2531 * @adapter: the adapter
2532 * @addr: the start address for the read
2533 * @nwords: how many 32-bit words to read
2534 * @data: where to store the read data
2535 * @byte_oriented: whether to store data as bytes or as words
2537 * Read the specified number of 32-bit words from the serial flash.
2538 * If @byte_oriented is set the read data is stored as a byte array
2539 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2540 * natural endianness.
2542 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2543 unsigned int nwords, u32 *data, int byte_oriented)
2547 if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2551 addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2553 ret = sf1_write(adapter, 4, 1, 0, addr);
2557 ret = sf1_read(adapter, 1, 1, 0, data);
2561 for ( ; nwords; nwords--, data++) {
2562 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2564 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
2568 *data = cpu_to_be32(*data);
2574 * t4_get_exprom_version - return the Expansion ROM version (if any)
2575 * @adapter: the adapter
2576 * @vers: where to place the version
2578 * Reads the Expansion ROM header from FLASH and returns the version
2579 * number (if present) through the @vers return value pointer. We return
2580 * this in the Firmware Version Format since it's convenient. Return
2581 * 0 on success, -ENOENT if no Expansion ROM is present.
2583 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2585 struct exprom_header {
2586 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2587 unsigned char hdr_ver[4]; /* Expansion ROM version */
2589 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2593 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2594 ARRAY_SIZE(exprom_header_buf),
2595 exprom_header_buf, 0);
2599 hdr = (struct exprom_header *)exprom_header_buf;
2600 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2603 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2604 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2605 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2606 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2611 * t4_get_fw_version - read the firmware version
2612 * @adapter: the adapter
2613 * @vers: where to place the version
2615 * Reads the FW version from flash.
2617 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2619 return t4_read_flash(adapter, FLASH_FW_START +
2620 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2624 * t4_get_bs_version - read the firmware bootstrap version
2625 * @adapter: the adapter
2626 * @vers: where to place the version
2628 * Reads the FW Bootstrap version from flash.
2630 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2632 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2633 offsetof(struct fw_hdr, fw_ver), 1,
2638 * t4_get_tp_version - read the TP microcode version
2639 * @adapter: the adapter
2640 * @vers: where to place the version
2642 * Reads the TP microcode version from flash.
2644 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2646 return t4_read_flash(adapter, FLASH_FW_START +
2647 offsetof(struct fw_hdr, tp_microcode_ver),
2652 * t4_get_version_info - extract various chip/firmware version information
2653 * @adapter: the adapter
2655 * Reads various chip/firmware version numbers and stores them into the
2656 * adapter Adapter Parameters structure. If any of the efforts fails
2657 * the first failure will be returned, but all of the version numbers
2660 int t4_get_version_info(struct adapter *adapter)
2664 #define FIRST_RET(__getvinfo) \
2666 int __ret = __getvinfo; \
2667 if (__ret && !ret) \
2671 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2672 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2673 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2674 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2682 * t4_dump_version_info - dump all of the adapter configuration IDs
2683 * @adapter: the adapter
2685 * Dumps all of the various bits of adapter configuration version/revision
2686 * IDs information. This is typically called at some point after
2687 * t4_get_version_info() has been called.
2689 void t4_dump_version_info(struct adapter *adapter)
2692 * Device information.
2694 dev_info(adapter, "Chelsio rev %d\n",
2695 CHELSIO_CHIP_RELEASE(adapter->params.chip));
2700 if (!adapter->params.fw_vers)
2701 dev_warn(adapter, "No firmware loaded\n");
2703 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2704 G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2705 G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2706 G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2707 G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2710 * Bootstrap Firmware Version.
2712 if (!adapter->params.bs_vers)
2713 dev_warn(adapter, "No bootstrap loaded\n");
2715 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2716 G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2717 G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2718 G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2719 G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2722 * TP Microcode Version.
2724 if (!adapter->params.tp_vers)
2725 dev_warn(adapter, "No TP Microcode loaded\n");
2727 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2728 G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2729 G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2730 G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2731 G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2734 * Expansion ROM version.
2736 if (!adapter->params.er_vers)
2737 dev_info(adapter, "No Expansion ROM loaded\n");
2739 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2740 G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2741 G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2742 G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2743 G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2746 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
2750 * t4_link_l1cfg - apply link configuration to MAC/PHY
2751 * @phy: the PHY to setup
2752 * @mac: the MAC to setup
2753 * @lc: the requested link configuration
2755 * Set up a port's MAC and PHY according to a desired link configuration.
2756 * - If the PHY can auto-negotiate first decide what to advertise, then
2757 * enable/disable auto-negotiation as desired, and reset.
2758 * - If the PHY does not auto-negotiate just reset it.
2759 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2760 * otherwise do it later based on the outcome of auto-negotiation.
2762 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2763 struct link_config *lc)
2765 struct fw_port_cmd c;
2766 unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
2767 unsigned int fc, fec;
2771 if (lc->requested_fc & PAUSE_RX)
2772 fc |= FW_PORT_CAP_FC_RX;
2773 if (lc->requested_fc & PAUSE_TX)
2774 fc |= FW_PORT_CAP_FC_TX;
2777 if (lc->requested_fec & FEC_RS)
2778 fec |= FW_PORT_CAP_FEC_RS;
2779 if (lc->requested_fec & FEC_BASER_RS)
2780 fec |= FW_PORT_CAP_FEC_BASER_RS;
2781 if (lc->requested_fec & FEC_RESERVED)
2782 fec |= FW_PORT_CAP_FEC_RESERVED;
2784 memset(&c, 0, sizeof(c));
2785 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2786 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2787 V_FW_PORT_CMD_PORTID(port));
2789 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2792 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2793 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2795 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2796 lc->fec = lc->requested_fec;
2797 } else if (lc->autoneg == AUTONEG_DISABLE) {
2798 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
2800 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2801 lc->fec = lc->requested_fec;
2803 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | fec | mdi);
2806 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2810 * t4_flash_cfg_addr - return the address of the flash configuration file
2811 * @adapter: the adapter
2813 * Return the address within the flash where the Firmware Configuration
2814 * File is stored, or an error if the device FLASH is too small to contain
2815 * a Firmware Configuration File.
2817 int t4_flash_cfg_addr(struct adapter *adapter)
2820 * If the device FLASH isn't large enough to hold a Firmware
2821 * Configuration File, return an error.
2823 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2826 return FLASH_CFG_START;
2829 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2832 * t4_intr_enable - enable interrupts
2833 * @adapter: the adapter whose interrupts should be enabled
2835 * Enable PF-specific interrupts for the calling function and the top-level
2836 * interrupt concentrator for global interrupts. Interrupts are already
2837 * enabled at each module, here we just enable the roots of the interrupt
2840 * Note: this function should be called only when the driver manages
2841 * non PF-specific interrupts from the various HW modules. Only one PCI
2842 * function at a time should be doing this.
2844 void t4_intr_enable(struct adapter *adapter)
2847 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2848 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2849 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2851 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2852 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2853 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2854 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2855 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2856 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2857 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2858 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2859 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2860 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2861 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2865 * t4_intr_disable - disable interrupts
2866 * @adapter: the adapter whose interrupts should be disabled
2868 * Disable interrupts. We only disable the top-level interrupt
2869 * concentrators. The caller must be a PCI function managing global
2872 void t4_intr_disable(struct adapter *adapter)
2874 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2875 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2876 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2878 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2879 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2883 * t4_get_port_type_description - return Port Type string description
2884 * @port_type: firmware Port Type enumeration
2886 const char *t4_get_port_type_description(enum fw_port_type port_type)
2888 static const char * const port_type_description[] = {
2913 if (port_type < ARRAY_SIZE(port_type_description))
2914 return port_type_description[port_type];
2919 * t4_get_mps_bg_map - return the buffer groups associated with a port
2920 * @adap: the adapter
2921 * @pidx: the port index
2923 * Returns a bitmap indicating which MPS buffer groups are associated
2924 * with the given port. Bit i is set if buffer group i is used by the
2927 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
2929 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2930 unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
2933 if (pidx >= nports) {
2934 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
2939 switch (chip_version) {
2944 case 2: return 3 << (2 * pidx);
2945 case 4: return 1 << pidx;
2951 case 2: return 1 << (2 * pidx);
2956 dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
2957 chip_version, nports);
2962 * t4_get_tp_ch_map - return TP ingress channels associated with a port
2963 * @adapter: the adapter
2964 * @pidx: the port index
2966 * Returns a bitmap indicating which TP Ingress Channels are associated with
2967 * a given Port. Bit i is set if TP Ingress Channel i is used by the Port.
2969 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
2971 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
2972 unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
2975 if (pidx >= nports) {
2976 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
2981 switch (chip_version) {
2984 /* Note that this happens to be the same values as the MPS
2985 * Buffer Group Map for these Chips. But we replicate the code
2986 * here because they're really separate concepts.
2990 case 2: return 3 << (2 * pidx);
2991 case 4: return 1 << pidx;
2997 case 2: return 1 << pidx;
3002 dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
3003 chip_version, nports);
3008 * t4_get_port_stats - collect port statistics
3009 * @adap: the adapter
3010 * @idx: the port index
3011 * @p: the stats structure to fill
3013 * Collect statistics related to the given port from HW.
3015 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
3017 u32 bgmap = t4_get_mps_bg_map(adap, idx);
3018 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
3020 #define GET_STAT(name) \
3021 t4_read_reg64(adap, \
3022 (is_t4(adap->params.chip) ? \
3023 PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
3024 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
3025 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
3027 p->tx_octets = GET_STAT(TX_PORT_BYTES);
3028 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
3029 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
3030 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
3031 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
3032 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
3033 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
3034 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
3035 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
3036 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
3037 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
3038 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
3039 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
3040 p->tx_drop = GET_STAT(TX_PORT_DROP);
3041 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
3042 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
3043 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
3044 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
3045 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
3046 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
3047 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
3048 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
3049 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
3051 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3052 if (stat_ctl & F_COUNTPAUSESTATTX) {
3053 p->tx_frames -= p->tx_pause;
3054 p->tx_octets -= p->tx_pause * 64;
3056 if (stat_ctl & F_COUNTPAUSEMCTX)
3057 p->tx_mcast_frames -= p->tx_pause;
3060 p->rx_octets = GET_STAT(RX_PORT_BYTES);
3061 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
3062 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
3063 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
3064 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
3065 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
3066 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
3067 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
3068 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
3069 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
3070 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
3071 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
3072 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
3073 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
3074 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
3075 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
3076 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3077 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
3078 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
3079 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
3080 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
3081 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
3082 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
3083 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
3084 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
3085 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
3086 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
3088 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3089 if (stat_ctl & F_COUNTPAUSESTATRX) {
3090 p->rx_frames -= p->rx_pause;
3091 p->rx_octets -= p->rx_pause * 64;
3093 if (stat_ctl & F_COUNTPAUSEMCRX)
3094 p->rx_mcast_frames -= p->rx_pause;
3097 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3098 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3099 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3100 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3101 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3102 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3103 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3104 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3111 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3112 * @adap: The adapter
3114 * @stats: Current stats to fill
3115 * @offset: Previous stats snapshot
3117 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3118 struct port_stats *stats,
3119 struct port_stats *offset)
3124 t4_get_port_stats(adap, idx, stats);
3125 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3126 i < (sizeof(struct port_stats) / sizeof(u64));
3132 * t4_clr_port_stats - clear port statistics
3133 * @adap: the adapter
3134 * @idx: the port index
3136 * Clear HW statistics for the given port.
3138 void t4_clr_port_stats(struct adapter *adap, int idx)
3141 u32 bgmap = t4_get_mps_bg_map(adap, idx);
3144 if (is_t4(adap->params.chip))
3145 port_base_addr = PORT_BASE(idx);
3147 port_base_addr = T5_PORT_BASE(idx);
3149 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3150 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3151 t4_write_reg(adap, port_base_addr + i, 0);
3152 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3153 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3154 t4_write_reg(adap, port_base_addr + i, 0);
3155 for (i = 0; i < 4; i++)
3156 if (bgmap & (1 << i)) {
3158 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3161 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3167 * t4_fw_hello - establish communication with FW
3168 * @adap: the adapter
3169 * @mbox: mailbox to use for the FW command
3170 * @evt_mbox: mailbox to receive async FW events
3171 * @master: specifies the caller's willingness to be the device master
3172 * @state: returns the current device state (if non-NULL)
3174 * Issues a command to establish communication with FW. Returns either
3175 * an error (negative integer) or the mailbox of the Master PF.
3177 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3178 enum dev_master master, enum dev_state *state)
3181 struct fw_hello_cmd c;
3183 unsigned int master_mbox;
3184 int retries = FW_CMD_HELLO_RETRIES;
3187 memset(&c, 0, sizeof(c));
3188 INIT_CMD(c, HELLO, WRITE);
3189 c.err_to_clearinit = cpu_to_be32(
3190 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3191 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3192 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3193 M_FW_HELLO_CMD_MBMASTER) |
3194 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3195 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3196 F_FW_HELLO_CMD_CLEARINIT);
3199 * Issue the HELLO command to the firmware. If it's not successful
3200 * but indicates that we got a "busy" or "timeout" condition, retry
3201 * the HELLO until we exhaust our retry limit. If we do exceed our
3202 * retry limit, check to see if the firmware left us any error
3203 * information and report that if so ...
3205 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3206 if (ret != FW_SUCCESS) {
3207 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3209 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3210 t4_report_fw_error(adap);
3214 v = be32_to_cpu(c.err_to_clearinit);
3215 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3217 if (v & F_FW_HELLO_CMD_ERR)
3218 *state = DEV_STATE_ERR;
3219 else if (v & F_FW_HELLO_CMD_INIT)
3220 *state = DEV_STATE_INIT;
3222 *state = DEV_STATE_UNINIT;
3226 * If we're not the Master PF then we need to wait around for the
3227 * Master PF Driver to finish setting up the adapter.
3229 * Note that we also do this wait if we're a non-Master-capable PF and
3230 * there is no current Master PF; a Master PF may show up momentarily
3231 * and we wouldn't want to fail pointlessly. (This can happen when an
3232 * OS loads lots of different drivers rapidly at the same time). In
3233 * this case, the Master PF returned by the firmware will be
3234 * M_PCIE_FW_MASTER so the test below will work ...
3236 if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3237 master_mbox != mbox) {
3238 int waiting = FW_CMD_HELLO_TIMEOUT;
3241 * Wait for the firmware to either indicate an error or
3242 * initialized state. If we see either of these we bail out
3243 * and report the issue to the caller. If we exhaust the
3244 * "hello timeout" and we haven't exhausted our retries, try
3245 * again. Otherwise bail with a timeout error.
3254 * If neither Error nor Initialialized are indicated
3255 * by the firmware keep waiting till we exaust our
3256 * timeout ... and then retry if we haven't exhausted
3259 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3260 if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3271 * We either have an Error or Initialized condition
3272 * report errors preferentially.
3275 if (pcie_fw & F_PCIE_FW_ERR)
3276 *state = DEV_STATE_ERR;
3277 else if (pcie_fw & F_PCIE_FW_INIT)
3278 *state = DEV_STATE_INIT;
3282 * If we arrived before a Master PF was selected and
3283 * there's not a valid Master PF, grab its identity
3286 if (master_mbox == M_PCIE_FW_MASTER &&
3287 (pcie_fw & F_PCIE_FW_MASTER_VLD))
3288 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3297 * t4_fw_bye - end communication with FW
3298 * @adap: the adapter
3299 * @mbox: mailbox to use for the FW command
3301 * Issues a command to terminate communication with FW.
3303 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3305 struct fw_bye_cmd c;
3307 memset(&c, 0, sizeof(c));
3308 INIT_CMD(c, BYE, WRITE);
3309 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3313 * t4_fw_reset - issue a reset to FW
3314 * @adap: the adapter
3315 * @mbox: mailbox to use for the FW command
3316 * @reset: specifies the type of reset to perform
3318 * Issues a reset command of the specified type to FW.
3320 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3322 struct fw_reset_cmd c;
3324 memset(&c, 0, sizeof(c));
3325 INIT_CMD(c, RESET, WRITE);
3326 c.val = cpu_to_be32(reset);
3327 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3331 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3332 * @adap: the adapter
3333 * @mbox: mailbox to use for the FW RESET command (if desired)
3334 * @force: force uP into RESET even if FW RESET command fails
3336 * Issues a RESET command to firmware (if desired) with a HALT indication
3337 * and then puts the microprocessor into RESET state. The RESET command
3338 * will only be issued if a legitimate mailbox is provided (mbox <=
3339 * M_PCIE_FW_MASTER).
3341 * This is generally used in order for the host to safely manipulate the
3342 * adapter without fear of conflicting with whatever the firmware might
3343 * be doing. The only way out of this state is to RESTART the firmware
3346 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3351 * If a legitimate mailbox is provided, issue a RESET command
3352 * with a HALT indication.
3354 if (mbox <= M_PCIE_FW_MASTER) {
3355 struct fw_reset_cmd c;
3357 memset(&c, 0, sizeof(c));
3358 INIT_CMD(c, RESET, WRITE);
3359 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3360 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3361 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3365 * Normally we won't complete the operation if the firmware RESET
3366 * command fails but if our caller insists we'll go ahead and put the
3367 * uP into RESET. This can be useful if the firmware is hung or even
3368 * missing ... We'll have to take the risk of putting the uP into
3369 * RESET without the cooperation of firmware in that case.
3371 * We also force the firmware's HALT flag to be on in case we bypassed
3372 * the firmware RESET command above or we're dealing with old firmware
3373 * which doesn't have the HALT capability. This will serve as a flag
3374 * for the incoming firmware to know that it's coming out of a HALT
3375 * rather than a RESET ... if it's new enough to understand that ...
3377 if (ret == 0 || force) {
3378 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3379 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3384 * And we always return the result of the firmware RESET command
3385 * even when we force the uP into RESET ...
3391 * t4_fw_restart - restart the firmware by taking the uP out of RESET
3392 * @adap: the adapter
3393 * @mbox: mailbox to use for the FW RESET command (if desired)
3394 * @reset: if we want to do a RESET to restart things
3396 * Restart firmware previously halted by t4_fw_halt(). On successful
3397 * return the previous PF Master remains as the new PF Master and there
3398 * is no need to issue a new HELLO command, etc.
3400 * We do this in two ways:
3402 * 1. If we're dealing with newer firmware we'll simply want to take
3403 * the chip's microprocessor out of RESET. This will cause the
3404 * firmware to start up from its start vector. And then we'll loop
3405 * until the firmware indicates it's started again (PCIE_FW.HALT
3406 * reset to 0) or we timeout.
3408 * 2. If we're dealing with older firmware then we'll need to RESET
3409 * the chip since older firmware won't recognize the PCIE_FW.HALT
3410 * flag and automatically RESET itself on startup.
3412 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3416 * Since we're directing the RESET instead of the firmware
3417 * doing it automatically, we need to clear the PCIE_FW.HALT
3420 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3423 * If we've been given a valid mailbox, first try to get the
3424 * firmware to do the RESET. If that works, great and we can
3425 * return success. Otherwise, if we haven't been given a
3426 * valid mailbox or the RESET command failed, fall back to
3427 * hitting the chip with a hammer.
3429 if (mbox <= M_PCIE_FW_MASTER) {
3430 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3432 if (t4_fw_reset(adap, mbox,
3433 F_PIORST | F_PIORSTMODE) == 0)
3437 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3442 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3443 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3444 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3455 * t4_fl_pkt_align - return the fl packet alignment
3456 * @adap: the adapter
3458 * T4 has a single field to specify the packing and padding boundary.
3459 * T5 onwards has separate fields for this and hence the alignment for
3460 * next packet offset is maximum of these two.
3462 int t4_fl_pkt_align(struct adapter *adap)
3464 u32 sge_control, sge_control2;
3465 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3467 sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3469 /* T4 uses a single control field to specify both the PCIe Padding and
3470 * Packing Boundary. T5 introduced the ability to specify these
3471 * separately. The actual Ingress Packet Data alignment boundary
3472 * within Packed Buffer Mode is the maximum of these two
3475 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3476 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3478 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3480 ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3482 fl_align = ingpadboundary;
3483 if (!is_t4(adap->params.chip)) {
3484 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3485 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3486 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3487 ingpackboundary = 16;
3489 ingpackboundary = 1 << (ingpackboundary +
3490 X_INGPACKBOUNDARY_SHIFT);
3492 fl_align = max(ingpadboundary, ingpackboundary);
3498 * t4_fixup_host_params_compat - fix up host-dependent parameters
3499 * @adap: the adapter
3500 * @page_size: the host's Base Page Size
3501 * @cache_line_size: the host's Cache Line Size
3502 * @chip_compat: maintain compatibility with designated chip
3504 * Various registers in the chip contain values which are dependent on the
3505 * host's Base Page and Cache Line Sizes. This function will fix all of
3506 * those registers with the appropriate values as passed in ...
3508 * @chip_compat is used to limit the set of changes that are made
3509 * to be compatible with the indicated chip release. This is used by
3510 * drivers to maintain compatibility with chip register settings when
3511 * the drivers haven't [yet] been updated with new chip support.
3513 int t4_fixup_host_params_compat(struct adapter *adap,
3514 unsigned int page_size,
3515 unsigned int cache_line_size,
3516 enum chip_type chip_compat)
3518 unsigned int page_shift = cxgbe_fls(page_size) - 1;
3519 unsigned int sge_hps = page_shift - 10;
3520 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3521 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3522 unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3524 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3525 V_HOSTPAGESIZEPF0(sge_hps) |
3526 V_HOSTPAGESIZEPF1(sge_hps) |
3527 V_HOSTPAGESIZEPF2(sge_hps) |
3528 V_HOSTPAGESIZEPF3(sge_hps) |
3529 V_HOSTPAGESIZEPF4(sge_hps) |
3530 V_HOSTPAGESIZEPF5(sge_hps) |
3531 V_HOSTPAGESIZEPF6(sge_hps) |
3532 V_HOSTPAGESIZEPF7(sge_hps));
3534 if (is_t4(adap->params.chip) || is_t4(chip_compat))
3535 t4_set_reg_field(adap, A_SGE_CONTROL,
3536 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3537 F_EGRSTATUSPAGESIZE,
3538 V_INGPADBOUNDARY(fl_align_log -
3539 X_INGPADBOUNDARY_SHIFT) |
3540 V_EGRSTATUSPAGESIZE(stat_len != 64));
3542 unsigned int pack_align;
3543 unsigned int ingpad, ingpack;
3544 unsigned int pcie_cap;
3547 * T5 introduced the separation of the Free List Padding and
3548 * Packing Boundaries. Thus, we can select a smaller Padding
3549 * Boundary to avoid uselessly chewing up PCIe Link and Memory
3550 * Bandwidth, and use a Packing Boundary which is large enough
3551 * to avoid false sharing between CPUs, etc.
3553 * For the PCI Link, the smaller the Padding Boundary the
3554 * better. For the Memory Controller, a smaller Padding
3555 * Boundary is better until we cross under the Memory Line
3556 * Size (the minimum unit of transfer to/from Memory). If we
3557 * have a Padding Boundary which is smaller than the Memory
3558 * Line Size, that'll involve a Read-Modify-Write cycle on the
3559 * Memory Controller which is never good.
3562 /* We want the Packing Boundary to be based on the Cache Line
3563 * Size in order to help avoid False Sharing performance
3564 * issues between CPUs, etc. We also want the Packing
3565 * Boundary to incorporate the PCI-E Maximum Payload Size. We
3566 * get best performance when the Packing Boundary is a
3567 * multiple of the Maximum Payload Size.
3569 pack_align = fl_align;
3570 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3572 unsigned int mps, mps_log;
3575 /* The PCIe Device Control Maximum Payload Size field
3576 * [bits 7:5] encodes sizes as powers of 2 starting at
3579 t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3581 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3583 if (mps > pack_align)
3588 * N.B. T5 has a different interpretation of the "0" value for
3589 * the Packing Boundary. This corresponds to 16 bytes instead
3590 * of the expected 32 bytes. We never have a Packing Boundary
3591 * less than 32 bytes so we can't use that special value but
3592 * on the other hand, if we wanted 32 bytes, the best we can
3593 * really do is 64 bytes ...
3595 if (pack_align <= 16) {
3596 ingpack = X_INGPACKBOUNDARY_16B;
3598 } else if (pack_align == 32) {
3599 ingpack = X_INGPACKBOUNDARY_64B;
3602 unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3604 ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3605 fl_align = pack_align;
3608 /* Use the smallest Ingress Padding which isn't smaller than
3609 * the Memory Controller Read/Write Size. We'll take that as
3610 * being 8 bytes since we don't know of any system with a
3611 * wider Memory Controller Bus Width.
3613 if (is_t5(adap->params.chip))
3614 ingpad = X_INGPADBOUNDARY_32B;
3616 ingpad = X_T6_INGPADBOUNDARY_8B;
3617 t4_set_reg_field(adap, A_SGE_CONTROL,
3618 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3619 F_EGRSTATUSPAGESIZE,
3620 V_INGPADBOUNDARY(ingpad) |
3621 V_EGRSTATUSPAGESIZE(stat_len != 64));
3622 t4_set_reg_field(adap, A_SGE_CONTROL2,
3623 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3624 V_INGPACKBOUNDARY(ingpack));
3628 * Adjust various SGE Free List Host Buffer Sizes.
3630 * The first four entries are:
3634 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3635 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3637 * For the single-MTU buffers in unpacked mode we need to include
3638 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3639 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3640 * Padding boundary. All of these are accommodated in the Factory
3641 * Default Firmware Configuration File but we need to adjust it for
3642 * this host's cache line size.
3644 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3645 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3646 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3648 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3649 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3652 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3658 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3659 * @adap: the adapter
3660 * @page_size: the host's Base Page Size
3661 * @cache_line_size: the host's Cache Line Size
3663 * Various registers in T4 contain values which are dependent on the
3664 * host's Base Page and Cache Line Sizes. This function will fix all of
3665 * those registers with the appropriate values as passed in ...
3667 * This routine makes changes which are compatible with T4 chips.
3669 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3670 unsigned int cache_line_size)
3672 return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3677 * t4_fw_initialize - ask FW to initialize the device
3678 * @adap: the adapter
3679 * @mbox: mailbox to use for the FW command
3681 * Issues a command to FW to partially initialize the device. This
3682 * performs initialization that generally doesn't depend on user input.
3684 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3686 struct fw_initialize_cmd c;
3688 memset(&c, 0, sizeof(c));
3689 INIT_CMD(c, INITIALIZE, WRITE);
3690 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3694 * t4_query_params_rw - query FW or device parameters
3695 * @adap: the adapter
3696 * @mbox: mailbox to use for the FW command
3699 * @nparams: the number of parameters
3700 * @params: the parameter names
3701 * @val: the parameter values
3702 * @rw: Write and read flag
3704 * Reads the value of FW or device parameters. Up to 7 parameters can be
3707 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3708 unsigned int pf, unsigned int vf,
3709 unsigned int nparams, const u32 *params,
3714 struct fw_params_cmd c;
3715 __be32 *p = &c.param[0].mnem;
3720 memset(&c, 0, sizeof(c));
3721 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3722 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3723 V_FW_PARAMS_CMD_PFN(pf) |
3724 V_FW_PARAMS_CMD_VFN(vf));
3725 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3727 for (i = 0; i < nparams; i++) {
3728 *p++ = cpu_to_be32(*params++);
3730 *p = cpu_to_be32(*(val + i));
3734 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3736 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3737 *val++ = be32_to_cpu(*p);
3741 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3742 unsigned int vf, unsigned int nparams, const u32 *params,
3745 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3749 * t4_set_params_timeout - sets FW or device parameters
3750 * @adap: the adapter
3751 * @mbox: mailbox to use for the FW command
3754 * @nparams: the number of parameters
3755 * @params: the parameter names
3756 * @val: the parameter values
3757 * @timeout: the timeout time
3759 * Sets the value of FW or device parameters. Up to 7 parameters can be
3760 * specified at once.
3762 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3763 unsigned int pf, unsigned int vf,
3764 unsigned int nparams, const u32 *params,
3765 const u32 *val, int timeout)
3767 struct fw_params_cmd c;
3768 __be32 *p = &c.param[0].mnem;
3773 memset(&c, 0, sizeof(c));
3774 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3775 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3776 V_FW_PARAMS_CMD_PFN(pf) |
3777 V_FW_PARAMS_CMD_VFN(vf));
3778 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3781 *p++ = cpu_to_be32(*params++);
3782 *p++ = cpu_to_be32(*val++);
3785 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3788 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3789 unsigned int vf, unsigned int nparams, const u32 *params,
3792 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3793 FW_CMD_MAX_TIMEOUT);
3797 * t4_alloc_vi_func - allocate a virtual interface
3798 * @adap: the adapter
3799 * @mbox: mailbox to use for the FW command
3800 * @port: physical port associated with the VI
3801 * @pf: the PF owning the VI
3802 * @vf: the VF owning the VI
3803 * @nmac: number of MAC addresses needed (1 to 5)
3804 * @mac: the MAC addresses of the VI
3805 * @rss_size: size of RSS table slice associated with this VI
3806 * @portfunc: which Port Application Function MAC Address is desired
3807 * @idstype: Intrusion Detection Type
3809 * Allocates a virtual interface for the given physical port. If @mac is
3810 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3811 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3812 * stored consecutively so the space needed is @nmac * 6 bytes.
3813 * Returns a negative error number or the non-negative VI id.
3815 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3816 unsigned int port, unsigned int pf, unsigned int vf,
3817 unsigned int nmac, u8 *mac, unsigned int *rss_size,
3818 unsigned int portfunc, unsigned int idstype)
3823 memset(&c, 0, sizeof(c));
3824 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3825 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3826 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3827 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3828 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3829 V_FW_VI_CMD_FUNC(portfunc));
3830 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3833 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3838 memcpy(mac, c.mac, sizeof(c.mac));
3841 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3844 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3847 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3850 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3855 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3856 return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3860 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3861 * @adap: the adapter
3862 * @mbox: mailbox to use for the FW command
3863 * @port: physical port associated with the VI
3864 * @pf: the PF owning the VI
3865 * @vf: the VF owning the VI
3866 * @nmac: number of MAC addresses needed (1 to 5)
3867 * @mac: the MAC addresses of the VI
3868 * @rss_size: size of RSS table slice associated with this VI
3870 * Backwards compatible and convieniance routine to allocate a Virtual
3871 * Interface with a Ethernet Port Application Function and Intrustion
3872 * Detection System disabled.
3874 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3875 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3876 unsigned int *rss_size)
3878 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3883 * t4_free_vi - free a virtual interface
3884 * @adap: the adapter
3885 * @mbox: mailbox to use for the FW command
3886 * @pf: the PF owning the VI
3887 * @vf: the VF owning the VI
3888 * @viid: virtual interface identifiler
3890 * Free a previously allocated virtual interface.
3892 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3893 unsigned int vf, unsigned int viid)
3897 memset(&c, 0, sizeof(c));
3898 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3899 F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
3900 V_FW_VI_CMD_VFN(vf));
3901 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
3902 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
3904 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3908 * t4_set_rxmode - set Rx properties of a virtual interface
3909 * @adap: the adapter
3910 * @mbox: mailbox to use for the FW command
3912 * @mtu: the new MTU or -1
3913 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3914 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3915 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3916 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
3918 * @sleep_ok: if true we may sleep while awaiting command completion
3920 * Sets Rx properties of a virtual interface.
3922 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3923 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3926 struct fw_vi_rxmode_cmd c;
3928 /* convert to FW values */
3930 mtu = M_FW_VI_RXMODE_CMD_MTU;
3932 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
3934 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
3936 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
3938 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
3940 memset(&c, 0, sizeof(c));
3941 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
3942 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3943 V_FW_VI_RXMODE_CMD_VIID(viid));
3944 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3945 c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
3946 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3947 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3948 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3949 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3950 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3954 * t4_change_mac - modifies the exact-match filter for a MAC address
3955 * @adap: the adapter
3956 * @mbox: mailbox to use for the FW command
3958 * @idx: index of existing filter for old value of MAC address, or -1
3959 * @addr: the new MAC address value
3960 * @persist: whether a new MAC allocation should be persistent
3961 * @add_smt: if true also add the address to the HW SMT
3963 * Modifies an exact-match filter and sets it to the new MAC address if
3964 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
3965 * latter case the address is added persistently if @persist is %true.
3967 * Note that in general it is not possible to modify the value of a given
3968 * filter so the generic way to modify an address filter is to free the one
3969 * being used by the old address value and allocate a new filter for the
3970 * new address value.
3972 * Returns a negative error number or the index of the filter with the new
3973 * MAC value. Note that this index may differ from @idx.
3975 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3976 int idx, const u8 *addr, bool persist, bool add_smt)
3979 struct fw_vi_mac_cmd c;
3980 struct fw_vi_mac_exact *p = c.u.exact;
3981 int max_mac_addr = adap->params.arch.mps_tcam_size;
3983 if (idx < 0) /* new allocation */
3984 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3985 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3987 memset(&c, 0, sizeof(c));
3988 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3989 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3990 V_FW_VI_MAC_CMD_VIID(viid));
3991 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3992 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3993 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3994 V_FW_VI_MAC_CMD_IDX(idx));
3995 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3997 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3999 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
4000 if (ret >= max_mac_addr)
4007 * t4_enable_vi_params - enable/disable a virtual interface
4008 * @adap: the adapter
4009 * @mbox: mailbox to use for the FW command
4011 * @rx_en: 1=enable Rx, 0=disable Rx
4012 * @tx_en: 1=enable Tx, 0=disable Tx
4013 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
4015 * Enables/disables a virtual interface. Note that setting DCB Enable
4016 * only makes sense when enabling a Virtual Interface ...
4018 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
4019 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
4021 struct fw_vi_enable_cmd c;
4023 memset(&c, 0, sizeof(c));
4024 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
4025 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4026 V_FW_VI_ENABLE_CMD_VIID(viid));
4027 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
4028 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
4029 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
4031 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
4035 * t4_enable_vi - enable/disable a virtual interface
4036 * @adap: the adapter
4037 * @mbox: mailbox to use for the FW command
4039 * @rx_en: 1=enable Rx, 0=disable Rx
4040 * @tx_en: 1=enable Tx, 0=disable Tx
4042 * Enables/disables a virtual interface. Note that setting DCB Enable
4043 * only makes sense when enabling a Virtual Interface ...
4045 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
4046 bool rx_en, bool tx_en)
4048 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
4052 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
4053 * @adap: the adapter
4054 * @mbox: mailbox to use for the FW command
4055 * @start: %true to enable the queues, %false to disable them
4056 * @pf: the PF owning the queues
4057 * @vf: the VF owning the queues
4058 * @iqid: ingress queue id
4059 * @fl0id: FL0 queue id or 0xffff if no attached FL0
4060 * @fl1id: FL1 queue id or 0xffff if no attached FL1
4062 * Starts or stops an ingress queue and its associated FLs, if any.
4064 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
4065 unsigned int pf, unsigned int vf, unsigned int iqid,
4066 unsigned int fl0id, unsigned int fl1id)
4070 memset(&c, 0, sizeof(c));
4071 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4072 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4073 V_FW_IQ_CMD_VFN(vf));
4074 c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4075 V_FW_IQ_CMD_IQSTOP(!start) |
4077 c.iqid = cpu_to_be16(iqid);
4078 c.fl0id = cpu_to_be16(fl0id);
4079 c.fl1id = cpu_to_be16(fl1id);
4080 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4084 * t4_iq_free - free an ingress queue and its FLs
4085 * @adap: the adapter
4086 * @mbox: mailbox to use for the FW command
4087 * @pf: the PF owning the queues
4088 * @vf: the VF owning the queues
4089 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4090 * @iqid: ingress queue id
4091 * @fl0id: FL0 queue id or 0xffff if no attached FL0
4092 * @fl1id: FL1 queue id or 0xffff if no attached FL1
4094 * Frees an ingress queue and its associated FLs, if any.
4096 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4097 unsigned int vf, unsigned int iqtype, unsigned int iqid,
4098 unsigned int fl0id, unsigned int fl1id)
4102 memset(&c, 0, sizeof(c));
4103 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4104 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4105 V_FW_IQ_CMD_VFN(vf));
4106 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4107 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4108 c.iqid = cpu_to_be16(iqid);
4109 c.fl0id = cpu_to_be16(fl0id);
4110 c.fl1id = cpu_to_be16(fl1id);
4111 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4115 * t4_eth_eq_free - free an Ethernet egress queue
4116 * @adap: the adapter
4117 * @mbox: mailbox to use for the FW command
4118 * @pf: the PF owning the queue
4119 * @vf: the VF owning the queue
4120 * @eqid: egress queue id
4122 * Frees an Ethernet egress queue.
4124 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4125 unsigned int vf, unsigned int eqid)
4127 struct fw_eq_eth_cmd c;
4129 memset(&c, 0, sizeof(c));
4130 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4131 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4132 V_FW_EQ_ETH_CMD_PFN(pf) |
4133 V_FW_EQ_ETH_CMD_VFN(vf));
4134 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4135 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4136 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4140 * t4_handle_fw_rpl - process a FW reply message
4141 * @adap: the adapter
4142 * @rpl: start of the FW message
4144 * Processes a FW message, such as link state change messages.
4146 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4148 u8 opcode = *(const u8 *)rpl;
4151 * This might be a port command ... this simplifies the following
4152 * conditionals ... We can get away with pre-dereferencing
4153 * action_to_len16 because it's in the first 16 bytes and all messages
4154 * will be at least that long.
4156 const struct fw_port_cmd *p = (const void *)rpl;
4157 unsigned int action =
4158 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4160 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
4161 /* link/module state change message */
4162 unsigned int speed = 0, fc = 0, i;
4163 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4164 struct port_info *pi = NULL;
4165 struct link_config *lc;
4166 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
4167 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
4168 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
4170 if (stat & F_FW_PORT_CMD_RXPAUSE)
4172 if (stat & F_FW_PORT_CMD_TXPAUSE)
4174 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4175 speed = ETH_SPEED_NUM_100M;
4176 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4177 speed = ETH_SPEED_NUM_1G;
4178 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4179 speed = ETH_SPEED_NUM_10G;
4180 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4181 speed = ETH_SPEED_NUM_25G;
4182 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4183 speed = ETH_SPEED_NUM_40G;
4184 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4185 speed = ETH_SPEED_NUM_100G;
4187 for_each_port(adap, i) {
4188 pi = adap2pinfo(adap, i);
4189 if (pi->tx_chan == chan)
4194 if (mod != pi->mod_type) {
4196 t4_os_portmod_changed(adap, i);
4198 if (link_ok != lc->link_ok || speed != lc->speed ||
4199 fc != lc->fc) { /* something changed */
4200 if (!link_ok && lc->link_ok) {
4201 static const char * const reason[] = {
4204 "Auto-negotiation Failure",
4206 "Insufficient Airflow",
4207 "Unable To Determine Reason",
4208 "No RX Signal Detected",
4211 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
4213 dev_warn(adap, "Port %d link down, reason: %s\n",
4216 lc->link_ok = link_ok;
4219 lc->supported = be16_to_cpu(p->u.info.pcap);
4222 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4228 void t4_reset_link_config(struct adapter *adap, int idx)
4230 struct port_info *pi = adap2pinfo(adap, idx);
4231 struct link_config *lc = &pi->link_cfg;
4234 lc->requested_speed = 0;
4235 lc->requested_fc = 0;
4241 * init_link_config - initialize a link's SW state
4242 * @lc: structure holding the link state
4243 * @pcaps: link Port Capabilities
4244 * @acaps: link current Advertised Port Capabilities
4246 * Initializes the SW state maintained for each link, including the link's
4247 * capabilities and default speed/flow-control/autonegotiation settings.
4249 static void init_link_config(struct link_config *lc, unsigned int pcaps,
4254 lc->supported = pcaps;
4255 lc->requested_speed = 0;
4257 lc->requested_fc = 0;
4261 * For Forward Error Control, we default to whatever the Firmware
4262 * tells us the Link is currently advertising.
4265 if (acaps & FW_PORT_CAP_FEC_RS)
4267 if (acaps & FW_PORT_CAP_FEC_BASER_RS)
4268 fec |= FEC_BASER_RS;
4269 if (acaps & FW_PORT_CAP_FEC_RESERVED)
4270 fec |= FEC_RESERVED;
4271 lc->requested_fec = fec;
4274 if (lc->supported & FW_PORT_CAP_ANEG) {
4275 lc->advertising = lc->supported & ADVERT_MASK;
4276 lc->autoneg = AUTONEG_ENABLE;
4278 lc->advertising = 0;
4279 lc->autoneg = AUTONEG_DISABLE;
4284 * t4_wait_dev_ready - wait till to reads of registers work
4286 * Right after the device is RESET is can take a small amount of time
4287 * for it to respond to register reads. Until then, all reads will
4288 * return either 0xff...ff or 0xee...ee. Return an error if reads
4289 * don't work within a reasonable time frame.
4291 static int t4_wait_dev_ready(struct adapter *adapter)
4295 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4297 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4301 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4302 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4305 dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4311 u32 vendor_and_model_id;
4315 int t4_get_flash_params(struct adapter *adapter)
4318 * Table for non-Numonix supported flash parts. Numonix parts are left
4319 * to the preexisting well-tested code. All flash parts have 64KB
4322 static struct flash_desc supported_flash[] = {
4323 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
4328 unsigned int part, manufacturer;
4329 unsigned int density, size;
4332 * Issue a Read ID Command to the Flash part. We decode supported
4333 * Flash parts and their sizes from this. There's a newer Query
4334 * Command which can retrieve detailed geometry information but
4335 * many Flash parts don't support it.
4337 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4339 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4340 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
4344 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4345 if (supported_flash[part].vendor_and_model_id == flashid) {
4346 adapter->params.sf_size =
4347 supported_flash[part].size_mb;
4348 adapter->params.sf_nsec =
4349 adapter->params.sf_size / SF_SEC_SIZE;
4354 manufacturer = flashid & 0xff;
4355 switch (manufacturer) {
4356 case 0x20: { /* Micron/Numonix */
4358 * This Density -> Size decoding table is taken from Micron
4361 density = (flashid >> 16) & 0xff;
4364 size = 1 << 20; /* 1MB */
4367 size = 1 << 21; /* 2MB */
4370 size = 1 << 22; /* 4MB */
4373 size = 1 << 23; /* 8MB */
4376 size = 1 << 24; /* 16MB */
4379 size = 1 << 25; /* 32MB */
4382 size = 1 << 26; /* 64MB */
4385 size = 1 << 27; /* 128MB */
4388 size = 1 << 28; /* 256MB */
4391 dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4396 adapter->params.sf_size = size;
4397 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4401 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4407 * We should reject adapters with FLASHes which are too small. So, emit
4410 if (adapter->params.sf_size < FLASH_MIN_SIZE)
4411 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4412 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4417 static void set_pcie_completion_timeout(struct adapter *adapter,
4423 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4425 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4428 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4433 * t4_get_chip_type - Determine chip type from device ID
4434 * @adap: the adapter
4435 * @ver: adapter version
4437 int t4_get_chip_type(struct adapter *adap, int ver)
4439 enum chip_type chip = 0;
4440 u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4442 /* Retrieve adapter's device ID */
4445 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4448 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4451 dev_err(adap, "Device %d is not supported\n",
4452 adap->params.pci.device_id);
4460 * t4_prep_adapter - prepare SW and HW for operation
4461 * @adapter: the adapter
4463 * Initialize adapter SW state for the various HW modules, set initial
4464 * values for some adapter tunables, take PHYs out of reset, and
4465 * initialize the MDIO interface.
4467 int t4_prep_adapter(struct adapter *adapter)
4472 ret = t4_wait_dev_ready(adapter);
4476 pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4477 adapter->params.pci.device_id = adapter->pdev->id.device_id;
4478 adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4481 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4482 * ADAPTER (VERSION << 4 | REVISION)
4484 ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4485 adapter->params.chip = 0;
4488 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4489 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4490 adapter->params.arch.mps_tcam_size =
4491 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4492 adapter->params.arch.mps_rplc_size = 128;
4493 adapter->params.arch.nchan = NCHAN;
4494 adapter->params.arch.vfcount = 128;
4497 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4498 adapter->params.arch.sge_fl_db = 0;
4499 adapter->params.arch.mps_tcam_size =
4500 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4501 adapter->params.arch.mps_rplc_size = 256;
4502 adapter->params.arch.nchan = 2;
4503 adapter->params.arch.vfcount = 256;
4506 dev_err(adapter, "%s: Device %d is not supported\n",
4507 __func__, adapter->params.pci.device_id);
4511 adapter->params.pci.vpd_cap_addr =
4512 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4514 ret = t4_get_flash_params(adapter);
4516 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4521 adapter->params.cim_la_size = CIMLA_SIZE;
4523 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4526 * Default port and clock for debugging in case we can't reach FW.
4528 adapter->params.nports = 1;
4529 adapter->params.portvec = 1;
4530 adapter->params.vpd.cclk = 50000;
4532 /* Set pci completion timeout value to 4 seconds. */
4533 set_pcie_completion_timeout(adapter, 0xd);
4538 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4539 * @adapter: the adapter
4540 * @qid: the Queue ID
4541 * @qtype: the Ingress or Egress type for @qid
4542 * @pbar2_qoffset: BAR2 Queue Offset
4543 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4545 * Returns the BAR2 SGE Queue Registers information associated with the
4546 * indicated Absolute Queue ID. These are passed back in return value
4547 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4548 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4550 * This may return an error which indicates that BAR2 SGE Queue
4551 * registers aren't available. If an error is not returned, then the
4552 * following values are returned:
4554 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4555 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4557 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4558 * require the "Inferred Queue ID" ability may be used. E.g. the
4559 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4560 * then these "Inferred Queue ID" register may not be used.
4562 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4563 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4564 unsigned int *pbar2_qid)
4566 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4567 u64 bar2_page_offset, bar2_qoffset;
4568 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4571 * T4 doesn't support BAR2 SGE Queue registers.
4573 if (is_t4(adapter->params.chip))
4577 * Get our SGE Page Size parameters.
4579 page_shift = adapter->params.sge.hps + 10;
4580 page_size = 1 << page_shift;
4583 * Get the right Queues per Page parameters for our Queue.
4585 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4586 adapter->params.sge.eq_qpp :
4587 adapter->params.sge.iq_qpp);
4588 qpp_mask = (1 << qpp_shift) - 1;
4591 * Calculate the basics of the BAR2 SGE Queue register area:
4592 * o The BAR2 page the Queue registers will be in.
4593 * o The BAR2 Queue ID.
4594 * o The BAR2 Queue ID Offset into the BAR2 page.
4596 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4597 bar2_qid = qid & qpp_mask;
4598 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4601 * If the BAR2 Queue ID Offset is less than the Page Size, then the
4602 * hardware will infer the Absolute Queue ID simply from the writes to
4603 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4604 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
4605 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4606 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4607 * from the BAR2 Page and BAR2 Queue ID.
4609 * One important censequence of this is that some BAR2 SGE registers
4610 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4611 * there. But other registers synthesize the SGE Queue ID purely
4612 * from the writes to the registers -- the Write Combined Doorbell
4613 * Buffer is a good example. These BAR2 SGE Registers are only
4614 * available for those BAR2 SGE Register areas where the SGE Absolute
4615 * Queue ID can be inferred from simple writes.
4617 bar2_qoffset = bar2_page_offset;
4618 bar2_qinferred = (bar2_qid_offset < page_size);
4619 if (bar2_qinferred) {
4620 bar2_qoffset += bar2_qid_offset;
4624 *pbar2_qoffset = bar2_qoffset;
4625 *pbar2_qid = bar2_qid;
4630 * t4_init_sge_params - initialize adap->params.sge
4631 * @adapter: the adapter
4633 * Initialize various fields of the adapter's SGE Parameters structure.
4635 int t4_init_sge_params(struct adapter *adapter)
4637 struct sge_params *sge_params = &adapter->params.sge;
4639 unsigned int s_hps, s_qpp;
4642 * Extract the SGE Page Size for our PF.
4644 hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4645 s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4647 sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4650 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4652 s_qpp = (S_QUEUESPERPAGEPF0 +
4653 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4654 qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4655 sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4656 qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4657 sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4663 * t4_init_tp_params - initialize adap->params.tp
4664 * @adap: the adapter
4666 * Initialize various fields of the adapter's TP Parameters structure.
4668 int t4_init_tp_params(struct adapter *adap)
4673 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4674 adap->params.tp.tre = G_TIMERRESOLUTION(v);
4675 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4677 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4678 for (chan = 0; chan < NCHAN; chan++)
4679 adap->params.tp.tx_modq[chan] = chan;
4682 * Cache the adapter's Compressed Filter Mode and global Incress
4685 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4686 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4687 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4688 &adap->params.tp.ingress_config, 1,
4689 A_TP_INGRESS_CONFIG);
4691 /* For T6, cache the adapter's compressed error vector
4692 * and passing outer header info for encapsulated packets.
4694 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4695 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
4696 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
4700 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4701 * shift positions of several elements of the Compressed Filter Tuple
4702 * for this adapter which we need frequently ...
4704 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4705 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4706 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4707 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4711 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4712 * represents the presense of an Outer VLAN instead of a VNIC ID.
4714 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4715 adap->params.tp.vnic_shift = -1;
4721 * t4_filter_field_shift - calculate filter field shift
4722 * @adap: the adapter
4723 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4725 * Return the shift position of a filter field within the Compressed
4726 * Filter Tuple. The filter field is specified via its selection bit
4727 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
4729 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4731 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4735 if ((filter_mode & filter_sel) == 0)
4738 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4739 switch (filter_mode & sel) {
4741 field_shift += W_FT_FCOE;
4744 field_shift += W_FT_PORT;
4747 field_shift += W_FT_VNIC_ID;
4750 field_shift += W_FT_VLAN;
4753 field_shift += W_FT_TOS;
4756 field_shift += W_FT_PROTOCOL;
4759 field_shift += W_FT_ETHERTYPE;
4762 field_shift += W_FT_MACMATCH;
4765 field_shift += W_FT_MPSHITTYPE;
4767 case F_FRAGMENTATION:
4768 field_shift += W_FT_FRAGMENTATION;
4775 int t4_init_rss_mode(struct adapter *adap, int mbox)
4778 struct fw_rss_vi_config_cmd rvc;
4780 memset(&rvc, 0, sizeof(rvc));
4782 for_each_port(adap, i) {
4783 struct port_info *p = adap2pinfo(adap, i);
4785 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4786 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4787 V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4788 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4789 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4792 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4797 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4801 struct fw_port_cmd c;
4803 memset(&c, 0, sizeof(c));
4805 for_each_port(adap, i) {
4806 unsigned int rss_size = 0;
4807 struct port_info *p = adap2pinfo(adap, i);
4809 while ((adap->params.portvec & (1 << j)) == 0)
4812 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4813 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4814 V_FW_PORT_CMD_PORTID(j));
4815 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4816 FW_PORT_ACTION_GET_PORT_INFO) |
4818 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4822 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4828 p->rss_size = rss_size;
4829 t4_os_set_hw_addr(adap, i, addr);
4831 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
4832 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
4833 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
4834 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
4835 p->mod_type = FW_PORT_MOD_TYPE_NA;
4837 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
4838 be16_to_cpu(c.u.info.acap));