drivers/net/cxgbe/base/t4_hw.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <netinet/in.h>
  35
  36 #include <rte_interrupts.h>
  37 #include <rte_log.h>
  38 #include <rte_debug.h>
  39 #include <rte_pci.h>
  40 #include <rte_atomic.h>
  41 #include <rte_branch_prediction.h>
  42 #include <rte_memory.h>
  43 #include <rte_tailq.h>
  44 #include <rte_eal.h>
  45 #include <rte_alarm.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev_driver.h>
  48 #include <rte_malloc.h>
  49 #include <rte_random.h>
  50 #include <rte_dev.h>
  51 #include <rte_byteorder.h>
  52
  53 #include "common.h"
  54 #include "t4_regs.h"
  55 #include "t4_regs_values.h"
  56 #include "t4fw_interface.h"
  57
  58 /**
  59  * t4_read_mtu_tbl - returns the values in the HW path MTU table
  60  * @adap: the adapter
  61  * @mtus: where to store the MTU values
  62  * @mtu_log: where to store the MTU base-2 log (may be %NULL)
  63  *
  64  * Reads the HW path MTU table.
  65  */
  66 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
  67 {
  68         u32 v;
  69         int i;
  70
  71         for (i = 0; i < NMTUS; ++i) {
  72                 t4_write_reg(adap, A_TP_MTU_TABLE,
  73                              V_MTUINDEX(0xff) | V_MTUVALUE(i));
  74                 v = t4_read_reg(adap, A_TP_MTU_TABLE);
  75                 mtus[i] = G_MTUVALUE(v);
  76                 if (mtu_log)
  77                         mtu_log[i] = G_MTUWIDTH(v);
  78         }
  79 }
  80
  81 /**
  82  * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
  83  * @adap: the adapter
  84  * @addr: the indirect TP register address
  85  * @mask: specifies the field within the register to modify
  86  * @val: new value for the field
  87  *
  88  * Sets a field of an indirect TP register to the given value.
  89  */
  90 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
  91                             unsigned int mask, unsigned int val)
  92 {
  93         t4_write_reg(adap, A_TP_PIO_ADDR, addr);
  94         val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
  95         t4_write_reg(adap, A_TP_PIO_DATA, val);
  96 }
  97
  98 /* The minimum additive increment value for the congestion control table */
  99 #define CC_MIN_INCR 2U
 100
 101 /**
 102  * t4_load_mtus - write the MTU and congestion control HW tables
 103  * @adap: the adapter
 104  * @mtus: the values for the MTU table
 105  * @alpha: the values for the congestion control alpha parameter
 106  * @beta: the values for the congestion control beta parameter
 107  *
 108  * Write the HW MTU table with the supplied MTUs and the high-speed
 109  * congestion control table with the supplied alpha, beta, and MTUs.
 110  * We write the two tables together because the additive increments
 111  * depend on the MTUs.
 112  */
 113 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
 114                   const unsigned short *alpha, const unsigned short *beta)
 115 {
 116         static const unsigned int avg_pkts[NCCTRL_WIN] = {
 117                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
 118                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
 119                 28672, 40960, 57344, 81920, 114688, 163840, 229376
 120         };
 121
 122         unsigned int i, w;
 123
 124         for (i = 0; i < NMTUS; ++i) {
 125                 unsigned int mtu = mtus[i];
 126                 unsigned int log2 = cxgbe_fls(mtu);
 127
 128                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
 129                         log2--;
 130                 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
 131                              V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
 132
 133                 for (w = 0; w < NCCTRL_WIN; ++w) {
 134                         unsigned int inc;
 135
 136                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
 137                                   CC_MIN_INCR);
 138
 139                         t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
 140                                      (w << 16) | (beta[w] << 13) | inc);
 141                 }
 142         }
 143 }
 144
 145 /**
 146  * t4_wait_op_done_val - wait until an operation is completed
 147  * @adapter: the adapter performing the operation
 148  * @reg: the register to check for completion
 149  * @mask: a single-bit field within @reg that indicates completion
 150  * @polarity: the value of the field when the operation is completed
 151  * @attempts: number of check iterations
 152  * @delay: delay in usecs between iterations
 153  * @valp: where to store the value of the register at completion time
 154  *
 155  * Wait until an operation is completed by checking a bit in a register
 156  * up to @attempts times.  If @valp is not NULL the value of the register
 157  * at the time it indicated completion is stored there.  Returns 0 if the
 158  * operation completes and -EAGAIN otherwise.
 159  */
 160 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 161                         int polarity, int attempts, int delay, u32 *valp)
 162 {
 163         while (1) {
 164                 u32 val = t4_read_reg(adapter, reg);
 165
 166                 if (!!(val & mask) == polarity) {
 167                         if (valp)
 168                                 *valp = val;
 169                         return 0;
 170                 }
 171                 if (--attempts == 0)
 172                         return -EAGAIN;
 173                 if (delay)
 174                         udelay(delay);
 175         }
 176 }
 177
 178 /**
 179  * t4_set_reg_field - set a register field to a value
 180  * @adapter: the adapter to program
 181  * @addr: the register address
 182  * @mask: specifies the portion of the register to modify
 183  * @val: the new value for the register field
 184  *
 185  * Sets a register field specified by the supplied mask to the
 186  * given value.
 187  */
 188 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
 189                       u32 val)
 190 {
 191         u32 v = t4_read_reg(adapter, addr) & ~mask;
 192
 193         t4_write_reg(adapter, addr, v | val);
 194         (void)t4_read_reg(adapter, addr);      /* flush */
 195 }
 196
 197 /**
 198  * t4_read_indirect - read indirectly addressed registers
 199  * @adap: the adapter
 200  * @addr_reg: register holding the indirect address
 201  * @data_reg: register holding the value of the indirect register
 202  * @vals: where the read register values are stored
 203  * @nregs: how many indirect registers to read
 204  * @start_idx: index of first indirect register to read
 205  *
 206  * Reads registers that are accessed indirectly through an address/data
 207  * register pair.
 208  */
 209 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 210                       unsigned int data_reg, u32 *vals, unsigned int nregs,
 211                       unsigned int start_idx)
 212 {
 213         while (nregs--) {
 214                 t4_write_reg(adap, addr_reg, start_idx);
 215                 *vals++ = t4_read_reg(adap, data_reg);
 216                 start_idx++;
 217         }
 218 }
 219
 220 /**
 221  * t4_write_indirect - write indirectly addressed registers
 222  * @adap: the adapter
 223  * @addr_reg: register holding the indirect addresses
 224  * @data_reg: register holding the value for the indirect registers
 225  * @vals: values to write
 226  * @nregs: how many indirect registers to write
 227  * @start_idx: address of first indirect register to write
 228  *
 229  * Writes a sequential block of registers that are accessed indirectly
 230  * through an address/data register pair.
 231  */
 232 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 233                        unsigned int data_reg, const u32 *vals,
 234                        unsigned int nregs, unsigned int start_idx)
 235 {
 236         while (nregs--) {
 237                 t4_write_reg(adap, addr_reg, start_idx++);
 238                 t4_write_reg(adap, data_reg, *vals++);
 239         }
 240 }
 241
 242 /**
 243  * t4_report_fw_error - report firmware error
 244  * @adap: the adapter
 245  *
 246  * The adapter firmware can indicate error conditions to the host.
 247  * If the firmware has indicated an error, print out the reason for
 248  * the firmware error.
 249  */
 250 static void t4_report_fw_error(struct adapter *adap)
 251 {
 252         static const char * const reason[] = {
 253                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 254                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 255                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 256                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 257                 "Unexpected Event",     /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 258                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 259                 "Device Shutdown",      /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 260                 "Reserved",                     /* reserved */
 261         };
 262         u32 pcie_fw;
 263
 264         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 265         if (pcie_fw & F_PCIE_FW_ERR)
 266                 pr_err("%s: Firmware reports adapter error: %s\n",
 267                        __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
 268 }
 269
 270 /*
 271  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 272  */
 273 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 274                          u32 mbox_addr)
 275 {
 276         for ( ; nflit; nflit--, mbox_addr += 8)
 277                 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
 278 }
 279
 280 /*
 281  * Handle a FW assertion reported in a mailbox.
 282  */
 283 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 284 {
 285         struct fw_debug_cmd asrt;
 286
 287         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 288         pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 289                 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 290                 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 291 }
 292
 293 #define X_CIM_PF_NOACCESS 0xeeeeeeee
 294
 295 /*
 296  * If the Host OS Driver needs locking arround accesses to the mailbox, this
 297  * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
 298  */
 299 /* makes single-statement usage a bit cleaner ... */
 300 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 301 #define T4_OS_MBOX_LOCKING(x) x
 302 #else
 303 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
 304 #endif
 305
 306 /**
 307  * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 308  * @adap: the adapter
 309  * @mbox: index of the mailbox to use
 310  * @cmd: the command to write
 311  * @size: command length in bytes
 312  * @rpl: where to optionally store the reply
 313  * @sleep_ok: if true we may sleep while awaiting command completion
 314  * @timeout: time to wait for command to finish before timing out
 315  *           (negative implies @sleep_ok=false)
 316  *
 317  * Sends the given command to FW through the selected mailbox and waits
 318  * for the FW to execute the command.  If @rpl is not %NULL it is used to
 319  * store the FW's reply to the command.  The command and its optional
 320  * reply are of the same length.  Some FW commands like RESET and
 321  * INITIALIZE can take a considerable amount of time to execute.
 322  * @sleep_ok determines whether we may sleep while awaiting the response.
 323  * If sleeping is allowed we use progressive backoff otherwise we spin.
 324  * Note that passing in a negative @timeout is an alternate mechanism
 325  * for specifying @sleep_ok=false.  This is useful when a higher level
 326  * interface allows for specification of @timeout but not @sleep_ok ...
 327  *
 328  * Returns 0 on success or a negative errno on failure.  A
 329  * failure can happen either because we are not able to execute the
 330  * command or FW executes it but signals an error.  In the latter case
 331  * the return value is the error code indicated by FW (negated).
 332  */
 333 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
 334                             const void __attribute__((__may_alias__)) *cmd,
 335                             int size, void *rpl, bool sleep_ok, int timeout)
 336 {
 337         /*
 338          * We delay in small increments at first in an effort to maintain
 339          * responsiveness for simple, fast executing commands but then back
 340          * off to larger delays to a maximum retry delay.
 341          */
 342         static const int delay[] = {
 343                 1, 1, 3, 5, 10, 10, 20, 50, 100
 344         };
 345
 346         u32 v;
 347         u64 res;
 348         int i, ms;
 349         unsigned int delay_idx;
 350         __be64 *temp = (__be64 *)malloc(size * sizeof(char));
 351         __be64 *p = temp;
 352         u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
 353         u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
 354         u32 ctl;
 355         struct mbox_entry entry;
 356         u32 pcie_fw = 0;
 357
 358         if (!temp)
 359                 return -ENOMEM;
 360
 361         if ((size & 15) || size > MBOX_LEN) {
 362                 free(temp);
 363                 return -EINVAL;
 364         }
 365
 366         bzero(p, size);
 367         memcpy(p, (const __be64 *)cmd, size);
 368
 369         /*
 370          * If we have a negative timeout, that implies that we can't sleep.
 371          */
 372         if (timeout < 0) {
 373                 sleep_ok = false;
 374                 timeout = -timeout;
 375         }
 376
 377 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 378         /*
 379          * Queue ourselves onto the mailbox access list.  When our entry is at
 380          * the front of the list, we have rights to access the mailbox.  So we
 381          * wait [for a while] till we're at the front [or bail out with an
 382          * EBUSY] ...
 383          */
 384         t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
 385
 386         delay_idx = 0;
 387         ms = delay[0];
 388
 389         for (i = 0; ; i += ms) {
 390                 /*
 391                  * If we've waited too long, return a busy indication.  This
 392                  * really ought to be based on our initial position in the
 393                  * mailbox access list but this is a start.  We very rarely
 394                  * contend on access to the mailbox ...  Also check for a
 395                  * firmware error which we'll report as a device error.
 396                  */
 397                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 398                 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
 399                         t4_os_atomic_list_del(&entry, &adap->mbox_list,
 400                                               &adap->mbox_lock);
 401                         t4_report_fw_error(adap);
 402                         free(temp);
 403                         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
 404                 }
 405
 406                 /*
 407                  * If we're at the head, break out and start the mailbox
 408                  * protocol.
 409                  */
 410                 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
 411                         break;
 412
 413                 /*
 414                  * Delay for a bit before checking again ...
 415                  */
 416                 if (sleep_ok) {
 417                         ms = delay[delay_idx];  /* last element may repeat */
 418                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 419                                 delay_idx++;
 420                         msleep(ms);
 421                 } else {
 422                         rte_delay_ms(ms);
 423                 }
 424         }
 425 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
 426
 427         /*
 428          * Attempt to gain access to the mailbox.
 429          */
 430         for (i = 0; i < 4; i++) {
 431                 ctl = t4_read_reg(adap, ctl_reg);
 432                 v = G_MBOWNER(ctl);
 433                 if (v != X_MBOWNER_NONE)
 434                         break;
 435         }
 436
 437         /*
 438          * If we were unable to gain access, dequeue ourselves from the
 439          * mailbox atomic access list and report the error to our caller.
 440          */
 441         if (v != X_MBOWNER_PL) {
 442                 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 443                                                          &adap->mbox_list,
 444                                                          &adap->mbox_lock));
 445                 t4_report_fw_error(adap);
 446                 free(temp);
 447                 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
 448         }
 449
 450         /*
 451          * If we gain ownership of the mailbox and there's a "valid" message
 452          * in it, this is likely an asynchronous error message from the
 453          * firmware.  So we'll report that and then proceed on with attempting
 454          * to issue our own command ... which may well fail if the error
 455          * presaged the firmware crashing ...
 456          */
 457         if (ctl & F_MBMSGVALID) {
 458                 dev_err(adap, "found VALID command in mbox %u: "
 459                         "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 460                         (unsigned long long)t4_read_reg64(adap, data_reg),
 461                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 462                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 463                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 464                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 465                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 466                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 467                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 468         }
 469
 470         /*
 471          * Copy in the new mailbox command and send it on its way ...
 472          */
 473         for (i = 0; i < size; i += 8, p++)
 474                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
 475
 476         CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
 477                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 478                         (unsigned long long)t4_read_reg64(adap, data_reg),
 479                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 480                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 481                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 482                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 483                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 484                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 485                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 486
 487         t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
 488         t4_read_reg(adap, ctl_reg);          /* flush write */
 489
 490         delay_idx = 0;
 491         ms = delay[0];
 492
 493         /*
 494          * Loop waiting for the reply; bail out if we time out or the firmware
 495          * reports an error.
 496          */
 497         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 498         for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
 499                 if (sleep_ok) {
 500                         ms = delay[delay_idx];  /* last element may repeat */
 501                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 502                                 delay_idx++;
 503                         msleep(ms);
 504                 } else {
 505                         msleep(ms);
 506                 }
 507
 508                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 509                 v = t4_read_reg(adap, ctl_reg);
 510                 if (v == X_CIM_PF_NOACCESS)
 511                         continue;
 512                 if (G_MBOWNER(v) == X_MBOWNER_PL) {
 513                         if (!(v & F_MBMSGVALID)) {
 514                                 t4_write_reg(adap, ctl_reg,
 515                                              V_MBOWNER(X_MBOWNER_NONE));
 516                                 continue;
 517                         }
 518
 519                         CXGBE_DEBUG_MBOX(adap,
 520                         "%s: mbox %u: %016llx %016llx %016llx %016llx "
 521                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 522                         (unsigned long long)t4_read_reg64(adap, data_reg),
 523                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 524                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 525                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 526                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 527                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 528                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 529                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 530
 531                         CXGBE_DEBUG_MBOX(adap,
 532                                 "command %#x completed in %d ms (%ssleeping)\n",
 533                                 *(const u8 *)cmd,
 534                                 i + ms, sleep_ok ? "" : "non-");
 535
 536                         res = t4_read_reg64(adap, data_reg);
 537                         if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
 538                                 fw_asrt(adap, data_reg);
 539                                 res = V_FW_CMD_RETVAL(EIO);
 540                         } else if (rpl) {
 541                                 get_mbox_rpl(adap, rpl, size / 8, data_reg);
 542                         }
 543                         t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
 544                         T4_OS_MBOX_LOCKING(
 545                                 t4_os_atomic_list_del(&entry, &adap->mbox_list,
 546                                                       &adap->mbox_lock));
 547                         free(temp);
 548                         return -G_FW_CMD_RETVAL((int)res);
 549                 }
 550         }
 551
 552         /*
 553          * We timed out waiting for a reply to our mailbox command.  Report
 554          * the error and also check to see if the firmware reported any
 555          * errors ...
 556          */
 557         dev_err(adap, "command %#x in mailbox %d timed out\n",
 558                 *(const u8 *)cmd, mbox);
 559         T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 560                                                  &adap->mbox_list,
 561                                                  &adap->mbox_lock));
 562         t4_report_fw_error(adap);
 563         free(temp);
 564         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
 565 }
 566
 567 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 568                     void *rpl, bool sleep_ok)
 569 {
 570         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 571                                        FW_CMD_MAX_TIMEOUT);
 572 }
 573
 574 /**
 575  * t4_get_regs_len - return the size of the chips register set
 576  * @adapter: the adapter
 577  *
 578  * Returns the size of the chip's BAR0 register space.
 579  */
 580 unsigned int t4_get_regs_len(struct adapter *adapter)
 581 {
 582         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 583
 584         switch (chip_version) {
 585         case CHELSIO_T5:
 586         case CHELSIO_T6:
 587                 return T5_REGMAP_SIZE;
 588         }
 589
 590         dev_err(adapter,
 591                 "Unsupported chip version %d\n", chip_version);
 592         return 0;
 593 }
 594
 595 /**
 596  * t4_get_regs - read chip registers into provided buffer
 597  * @adap: the adapter
 598  * @buf: register buffer
 599  * @buf_size: size (in bytes) of register buffer
 600  *
 601  * If the provided register buffer isn't large enough for the chip's
 602  * full register range, the register dump will be truncated to the
 603  * register buffer's size.
 604  */
 605 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 606 {
 607         static const unsigned int t5_reg_ranges[] = {
 608                 0x1008, 0x10c0,
 609                 0x10cc, 0x10f8,
 610                 0x1100, 0x1100,
 611                 0x110c, 0x1148,
 612                 0x1180, 0x1184,
 613                 0x1190, 0x1194,
 614                 0x11a0, 0x11a4,
 615                 0x11b0, 0x11b4,
 616                 0x11fc, 0x123c,
 617                 0x1280, 0x173c,
 618                 0x1800, 0x18fc,
 619                 0x3000, 0x3028,
 620                 0x3060, 0x30b0,
 621                 0x30b8, 0x30d8,
 622                 0x30e0, 0x30fc,
 623                 0x3140, 0x357c,
 624                 0x35a8, 0x35cc,
 625                 0x35ec, 0x35ec,
 626                 0x3600, 0x5624,
 627                 0x56cc, 0x56ec,
 628                 0x56f4, 0x5720,
 629                 0x5728, 0x575c,
 630                 0x580c, 0x5814,
 631                 0x5890, 0x589c,
 632                 0x58a4, 0x58ac,
 633                 0x58b8, 0x58bc,
 634                 0x5940, 0x59c8,
 635                 0x59d0, 0x59dc,
 636                 0x59fc, 0x5a18,
 637                 0x5a60, 0x5a70,
 638                 0x5a80, 0x5a9c,
 639                 0x5b94, 0x5bfc,
 640                 0x6000, 0x6020,
 641                 0x6028, 0x6040,
 642                 0x6058, 0x609c,
 643                 0x60a8, 0x614c,
 644                 0x7700, 0x7798,
 645                 0x77c0, 0x78fc,
 646                 0x7b00, 0x7b58,
 647                 0x7b60, 0x7b84,
 648                 0x7b8c, 0x7c54,
 649                 0x7d00, 0x7d38,
 650                 0x7d40, 0x7d80,
 651                 0x7d8c, 0x7ddc,
 652                 0x7de4, 0x7e04,
 653                 0x7e10, 0x7e1c,
 654                 0x7e24, 0x7e38,
 655                 0x7e40, 0x7e44,
 656                 0x7e4c, 0x7e78,
 657                 0x7e80, 0x7edc,
 658                 0x7ee8, 0x7efc,
 659                 0x8dc0, 0x8de0,
 660                 0x8df8, 0x8e04,
 661                 0x8e10, 0x8e84,
 662                 0x8ea0, 0x8f84,
 663                 0x8fc0, 0x9058,
 664                 0x9060, 0x9060,
 665                 0x9068, 0x90f8,
 666                 0x9400, 0x9408,
 667                 0x9410, 0x9470,
 668                 0x9600, 0x9600,
 669                 0x9608, 0x9638,
 670                 0x9640, 0x96f4,
 671                 0x9800, 0x9808,
 672                 0x9820, 0x983c,
 673                 0x9850, 0x9864,
 674                 0x9c00, 0x9c6c,
 675                 0x9c80, 0x9cec,
 676                 0x9d00, 0x9d6c,
 677                 0x9d80, 0x9dec,
 678                 0x9e00, 0x9e6c,
 679                 0x9e80, 0x9eec,
 680                 0x9f00, 0x9f6c,
 681                 0x9f80, 0xa020,
 682                 0xd004, 0xd004,
 683                 0xd010, 0xd03c,
 684                 0xdfc0, 0xdfe0,
 685                 0xe000, 0x1106c,
 686                 0x11074, 0x11088,
 687                 0x1109c, 0x1117c,
 688                 0x11190, 0x11204,
 689                 0x19040, 0x1906c,
 690                 0x19078, 0x19080,
 691                 0x1908c, 0x190e8,
 692                 0x190f0, 0x190f8,
 693                 0x19100, 0x19110,
 694                 0x19120, 0x19124,
 695                 0x19150, 0x19194,
 696                 0x1919c, 0x191b0,
 697                 0x191d0, 0x191e8,
 698                 0x19238, 0x19290,
 699                 0x193f8, 0x19428,
 700                 0x19430, 0x19444,
 701                 0x1944c, 0x1946c,
 702                 0x19474, 0x19474,
 703                 0x19490, 0x194cc,
 704                 0x194f0, 0x194f8,
 705                 0x19c00, 0x19c08,
 706                 0x19c10, 0x19c60,
 707                 0x19c94, 0x19ce4,
 708                 0x19cf0, 0x19d40,
 709                 0x19d50, 0x19d94,
 710                 0x19da0, 0x19de8,
 711                 0x19df0, 0x19e10,
 712                 0x19e50, 0x19e90,
 713                 0x19ea0, 0x19f24,
 714                 0x19f34, 0x19f34,
 715                 0x19f40, 0x19f50,
 716                 0x19f90, 0x19fb4,
 717                 0x19fc4, 0x19fe4,
 718                 0x1a000, 0x1a004,
 719                 0x1a010, 0x1a06c,
 720                 0x1a0b0, 0x1a0e4,
 721                 0x1a0ec, 0x1a0f8,
 722                 0x1a100, 0x1a108,
 723                 0x1a114, 0x1a120,
 724                 0x1a128, 0x1a130,
 725                 0x1a138, 0x1a138,
 726                 0x1a190, 0x1a1c4,
 727                 0x1a1fc, 0x1a1fc,
 728                 0x1e008, 0x1e00c,
 729                 0x1e040, 0x1e044,
 730                 0x1e04c, 0x1e04c,
 731                 0x1e284, 0x1e290,
 732                 0x1e2c0, 0x1e2c0,
 733                 0x1e2e0, 0x1e2e0,
 734                 0x1e300, 0x1e384,
 735                 0x1e3c0, 0x1e3c8,
 736                 0x1e408, 0x1e40c,
 737                 0x1e440, 0x1e444,
 738                 0x1e44c, 0x1e44c,
 739                 0x1e684, 0x1e690,
 740                 0x1e6c0, 0x1e6c0,
 741                 0x1e6e0, 0x1e6e0,
 742                 0x1e700, 0x1e784,
 743                 0x1e7c0, 0x1e7c8,
 744                 0x1e808, 0x1e80c,
 745                 0x1e840, 0x1e844,
 746                 0x1e84c, 0x1e84c,
 747                 0x1ea84, 0x1ea90,
 748                 0x1eac0, 0x1eac0,
 749                 0x1eae0, 0x1eae0,
 750                 0x1eb00, 0x1eb84,
 751                 0x1ebc0, 0x1ebc8,
 752                 0x1ec08, 0x1ec0c,
 753                 0x1ec40, 0x1ec44,
 754                 0x1ec4c, 0x1ec4c,
 755                 0x1ee84, 0x1ee90,
 756                 0x1eec0, 0x1eec0,
 757                 0x1eee0, 0x1eee0,
 758                 0x1ef00, 0x1ef84,
 759                 0x1efc0, 0x1efc8,
 760                 0x1f008, 0x1f00c,
 761                 0x1f040, 0x1f044,
 762                 0x1f04c, 0x1f04c,
 763                 0x1f284, 0x1f290,
 764                 0x1f2c0, 0x1f2c0,
 765                 0x1f2e0, 0x1f2e0,
 766                 0x1f300, 0x1f384,
 767                 0x1f3c0, 0x1f3c8,
 768                 0x1f408, 0x1f40c,
 769                 0x1f440, 0x1f444,
 770                 0x1f44c, 0x1f44c,
 771                 0x1f684, 0x1f690,
 772                 0x1f6c0, 0x1f6c0,
 773                 0x1f6e0, 0x1f6e0,
 774                 0x1f700, 0x1f784,
 775                 0x1f7c0, 0x1f7c8,
 776                 0x1f808, 0x1f80c,
 777                 0x1f840, 0x1f844,
 778                 0x1f84c, 0x1f84c,
 779                 0x1fa84, 0x1fa90,
 780                 0x1fac0, 0x1fac0,
 781                 0x1fae0, 0x1fae0,
 782                 0x1fb00, 0x1fb84,
 783                 0x1fbc0, 0x1fbc8,
 784                 0x1fc08, 0x1fc0c,
 785                 0x1fc40, 0x1fc44,
 786                 0x1fc4c, 0x1fc4c,
 787                 0x1fe84, 0x1fe90,
 788                 0x1fec0, 0x1fec0,
 789                 0x1fee0, 0x1fee0,
 790                 0x1ff00, 0x1ff84,
 791                 0x1ffc0, 0x1ffc8,
 792                 0x30000, 0x30030,
 793                 0x30038, 0x30038,
 794                 0x30040, 0x30040,
 795                 0x30100, 0x30144,
 796                 0x30190, 0x301a0,
 797                 0x301a8, 0x301b8,
 798                 0x301c4, 0x301c8,
 799                 0x301d0, 0x301d0,
 800                 0x30200, 0x30318,
 801                 0x30400, 0x304b4,
 802                 0x304c0, 0x3052c,
 803                 0x30540, 0x3061c,
 804                 0x30800, 0x30828,
 805                 0x30834, 0x30834,
 806                 0x308c0, 0x30908,
 807                 0x30910, 0x309ac,
 808                 0x30a00, 0x30a14,
 809                 0x30a1c, 0x30a2c,
 810                 0x30a44, 0x30a50,
 811                 0x30a74, 0x30a74,
 812                 0x30a7c, 0x30afc,
 813                 0x30b08, 0x30c24,
 814                 0x30d00, 0x30d00,
 815                 0x30d08, 0x30d14,
 816                 0x30d1c, 0x30d20,
 817                 0x30d3c, 0x30d3c,
 818                 0x30d48, 0x30d50,
 819                 0x31200, 0x3120c,
 820                 0x31220, 0x31220,
 821                 0x31240, 0x31240,
 822                 0x31600, 0x3160c,
 823                 0x31a00, 0x31a1c,
 824                 0x31e00, 0x31e20,
 825                 0x31e38, 0x31e3c,
 826                 0x31e80, 0x31e80,
 827                 0x31e88, 0x31ea8,
 828                 0x31eb0, 0x31eb4,
 829                 0x31ec8, 0x31ed4,
 830                 0x31fb8, 0x32004,
 831                 0x32200, 0x32200,
 832                 0x32208, 0x32240,
 833                 0x32248, 0x32280,
 834                 0x32288, 0x322c0,
 835                 0x322c8, 0x322fc,
 836                 0x32600, 0x32630,
 837                 0x32a00, 0x32abc,
 838                 0x32b00, 0x32b10,
 839                 0x32b20, 0x32b30,
 840                 0x32b40, 0x32b50,
 841                 0x32b60, 0x32b70,
 842                 0x33000, 0x33028,
 843                 0x33030, 0x33048,
 844                 0x33060, 0x33068,
 845                 0x33070, 0x3309c,
 846                 0x330f0, 0x33128,
 847                 0x33130, 0x33148,
 848                 0x33160, 0x33168,
 849                 0x33170, 0x3319c,
 850                 0x331f0, 0x33238,
 851                 0x33240, 0x33240,
 852                 0x33248, 0x33250,
 853                 0x3325c, 0x33264,
 854                 0x33270, 0x332b8,
 855                 0x332c0, 0x332e4,
 856                 0x332f8, 0x33338,
 857                 0x33340, 0x33340,
 858                 0x33348, 0x33350,
 859                 0x3335c, 0x33364,
 860                 0x33370, 0x333b8,
 861                 0x333c0, 0x333e4,
 862                 0x333f8, 0x33428,
 863                 0x33430, 0x33448,
 864                 0x33460, 0x33468,
 865                 0x33470, 0x3349c,
 866                 0x334f0, 0x33528,
 867                 0x33530, 0x33548,
 868                 0x33560, 0x33568,
 869                 0x33570, 0x3359c,
 870                 0x335f0, 0x33638,
 871                 0x33640, 0x33640,
 872                 0x33648, 0x33650,
 873                 0x3365c, 0x33664,
 874                 0x33670, 0x336b8,
 875                 0x336c0, 0x336e4,
 876                 0x336f8, 0x33738,
 877                 0x33740, 0x33740,
 878                 0x33748, 0x33750,
 879                 0x3375c, 0x33764,
 880                 0x33770, 0x337b8,
 881                 0x337c0, 0x337e4,
 882                 0x337f8, 0x337fc,
 883                 0x33814, 0x33814,
 884                 0x3382c, 0x3382c,
 885                 0x33880, 0x3388c,
 886                 0x338e8, 0x338ec,
 887                 0x33900, 0x33928,
 888                 0x33930, 0x33948,
 889                 0x33960, 0x33968,
 890                 0x33970, 0x3399c,
 891                 0x339f0, 0x33a38,
 892                 0x33a40, 0x33a40,
 893                 0x33a48, 0x33a50,
 894                 0x33a5c, 0x33a64,
 895                 0x33a70, 0x33ab8,
 896                 0x33ac0, 0x33ae4,
 897                 0x33af8, 0x33b10,
 898                 0x33b28, 0x33b28,
 899                 0x33b3c, 0x33b50,
 900                 0x33bf0, 0x33c10,
 901                 0x33c28, 0x33c28,
 902                 0x33c3c, 0x33c50,
 903                 0x33cf0, 0x33cfc,
 904                 0x34000, 0x34030,
 905                 0x34038, 0x34038,
 906                 0x34040, 0x34040,
 907                 0x34100, 0x34144,
 908                 0x34190, 0x341a0,
 909                 0x341a8, 0x341b8,
 910                 0x341c4, 0x341c8,
 911                 0x341d0, 0x341d0,
 912                 0x34200, 0x34318,
 913                 0x34400, 0x344b4,
 914                 0x344c0, 0x3452c,
 915                 0x34540, 0x3461c,
 916                 0x34800, 0x34828,
 917                 0x34834, 0x34834,
 918                 0x348c0, 0x34908,
 919                 0x34910, 0x349ac,
 920                 0x34a00, 0x34a14,
 921                 0x34a1c, 0x34a2c,
 922                 0x34a44, 0x34a50,
 923                 0x34a74, 0x34a74,
 924                 0x34a7c, 0x34afc,
 925                 0x34b08, 0x34c24,
 926                 0x34d00, 0x34d00,
 927                 0x34d08, 0x34d14,
 928                 0x34d1c, 0x34d20,
 929                 0x34d3c, 0x34d3c,
 930                 0x34d48, 0x34d50,
 931                 0x35200, 0x3520c,
 932                 0x35220, 0x35220,
 933                 0x35240, 0x35240,
 934                 0x35600, 0x3560c,
 935                 0x35a00, 0x35a1c,
 936                 0x35e00, 0x35e20,
 937                 0x35e38, 0x35e3c,
 938                 0x35e80, 0x35e80,
 939                 0x35e88, 0x35ea8,
 940                 0x35eb0, 0x35eb4,
 941                 0x35ec8, 0x35ed4,
 942                 0x35fb8, 0x36004,
 943                 0x36200, 0x36200,
 944                 0x36208, 0x36240,
 945                 0x36248, 0x36280,
 946                 0x36288, 0x362c0,
 947                 0x362c8, 0x362fc,
 948                 0x36600, 0x36630,
 949                 0x36a00, 0x36abc,
 950                 0x36b00, 0x36b10,
 951                 0x36b20, 0x36b30,
 952                 0x36b40, 0x36b50,
 953                 0x36b60, 0x36b70,
 954                 0x37000, 0x37028,
 955                 0x37030, 0x37048,
 956                 0x37060, 0x37068,
 957                 0x37070, 0x3709c,
 958                 0x370f0, 0x37128,
 959                 0x37130, 0x37148,
 960                 0x37160, 0x37168,
 961                 0x37170, 0x3719c,
 962                 0x371f0, 0x37238,
 963                 0x37240, 0x37240,
 964                 0x37248, 0x37250,
 965                 0x3725c, 0x37264,
 966                 0x37270, 0x372b8,
 967                 0x372c0, 0x372e4,
 968                 0x372f8, 0x37338,
 969                 0x37340, 0x37340,
 970                 0x37348, 0x37350,
 971                 0x3735c, 0x37364,
 972                 0x37370, 0x373b8,
 973                 0x373c0, 0x373e4,
 974                 0x373f8, 0x37428,
 975                 0x37430, 0x37448,
 976                 0x37460, 0x37468,
 977                 0x37470, 0x3749c,
 978                 0x374f0, 0x37528,
 979                 0x37530, 0x37548,
 980                 0x37560, 0x37568,
 981                 0x37570, 0x3759c,
 982                 0x375f0, 0x37638,
 983                 0x37640, 0x37640,
 984                 0x37648, 0x37650,
 985                 0x3765c, 0x37664,
 986                 0x37670, 0x376b8,
 987                 0x376c0, 0x376e4,
 988                 0x376f8, 0x37738,
 989                 0x37740, 0x37740,
 990                 0x37748, 0x37750,
 991                 0x3775c, 0x37764,
 992                 0x37770, 0x377b8,
 993                 0x377c0, 0x377e4,
 994                 0x377f8, 0x377fc,
 995                 0x37814, 0x37814,
 996                 0x3782c, 0x3782c,
 997                 0x37880, 0x3788c,
 998                 0x378e8, 0x378ec,
 999                 0x37900, 0x37928,
1000                 0x37930, 0x37948,
1001                 0x37960, 0x37968,
1002                 0x37970, 0x3799c,
1003                 0x379f0, 0x37a38,
1004                 0x37a40, 0x37a40,
1005                 0x37a48, 0x37a50,
1006                 0x37a5c, 0x37a64,
1007                 0x37a70, 0x37ab8,
1008                 0x37ac0, 0x37ae4,
1009                 0x37af8, 0x37b10,
1010                 0x37b28, 0x37b28,
1011                 0x37b3c, 0x37b50,
1012                 0x37bf0, 0x37c10,
1013                 0x37c28, 0x37c28,
1014                 0x37c3c, 0x37c50,
1015                 0x37cf0, 0x37cfc,
1016                 0x38000, 0x38030,
1017                 0x38038, 0x38038,
1018                 0x38040, 0x38040,
1019                 0x38100, 0x38144,
1020                 0x38190, 0x381a0,
1021                 0x381a8, 0x381b8,
1022                 0x381c4, 0x381c8,
1023                 0x381d0, 0x381d0,
1024                 0x38200, 0x38318,
1025                 0x38400, 0x384b4,
1026                 0x384c0, 0x3852c,
1027                 0x38540, 0x3861c,
1028                 0x38800, 0x38828,
1029                 0x38834, 0x38834,
1030                 0x388c0, 0x38908,
1031                 0x38910, 0x389ac,
1032                 0x38a00, 0x38a14,
1033                 0x38a1c, 0x38a2c,
1034                 0x38a44, 0x38a50,
1035                 0x38a74, 0x38a74,
1036                 0x38a7c, 0x38afc,
1037                 0x38b08, 0x38c24,
1038                 0x38d00, 0x38d00,
1039                 0x38d08, 0x38d14,
1040                 0x38d1c, 0x38d20,
1041                 0x38d3c, 0x38d3c,
1042                 0x38d48, 0x38d50,
1043                 0x39200, 0x3920c,
1044                 0x39220, 0x39220,
1045                 0x39240, 0x39240,
1046                 0x39600, 0x3960c,
1047                 0x39a00, 0x39a1c,
1048                 0x39e00, 0x39e20,
1049                 0x39e38, 0x39e3c,
1050                 0x39e80, 0x39e80,
1051                 0x39e88, 0x39ea8,
1052                 0x39eb0, 0x39eb4,
1053                 0x39ec8, 0x39ed4,
1054                 0x39fb8, 0x3a004,
1055                 0x3a200, 0x3a200,
1056                 0x3a208, 0x3a240,
1057                 0x3a248, 0x3a280,
1058                 0x3a288, 0x3a2c0,
1059                 0x3a2c8, 0x3a2fc,
1060                 0x3a600, 0x3a630,
1061                 0x3aa00, 0x3aabc,
1062                 0x3ab00, 0x3ab10,
1063                 0x3ab20, 0x3ab30,
1064                 0x3ab40, 0x3ab50,
1065                 0x3ab60, 0x3ab70,
1066                 0x3b000, 0x3b028,
1067                 0x3b030, 0x3b048,
1068                 0x3b060, 0x3b068,
1069                 0x3b070, 0x3b09c,
1070                 0x3b0f0, 0x3b128,
1071                 0x3b130, 0x3b148,
1072                 0x3b160, 0x3b168,
1073                 0x3b170, 0x3b19c,
1074                 0x3b1f0, 0x3b238,
1075                 0x3b240, 0x3b240,
1076                 0x3b248, 0x3b250,
1077                 0x3b25c, 0x3b264,
1078                 0x3b270, 0x3b2b8,
1079                 0x3b2c0, 0x3b2e4,
1080                 0x3b2f8, 0x3b338,
1081                 0x3b340, 0x3b340,
1082                 0x3b348, 0x3b350,
1083                 0x3b35c, 0x3b364,
1084                 0x3b370, 0x3b3b8,
1085                 0x3b3c0, 0x3b3e4,
1086                 0x3b3f8, 0x3b428,
1087                 0x3b430, 0x3b448,
1088                 0x3b460, 0x3b468,
1089                 0x3b470, 0x3b49c,
1090                 0x3b4f0, 0x3b528,
1091                 0x3b530, 0x3b548,
1092                 0x3b560, 0x3b568,
1093                 0x3b570, 0x3b59c,
1094                 0x3b5f0, 0x3b638,
1095                 0x3b640, 0x3b640,
1096                 0x3b648, 0x3b650,
1097                 0x3b65c, 0x3b664,
1098                 0x3b670, 0x3b6b8,
1099                 0x3b6c0, 0x3b6e4,
1100                 0x3b6f8, 0x3b738,
1101                 0x3b740, 0x3b740,
1102                 0x3b748, 0x3b750,
1103                 0x3b75c, 0x3b764,
1104                 0x3b770, 0x3b7b8,
1105                 0x3b7c0, 0x3b7e4,
1106                 0x3b7f8, 0x3b7fc,
1107                 0x3b814, 0x3b814,
1108                 0x3b82c, 0x3b82c,
1109                 0x3b880, 0x3b88c,
1110                 0x3b8e8, 0x3b8ec,
1111                 0x3b900, 0x3b928,
1112                 0x3b930, 0x3b948,
1113                 0x3b960, 0x3b968,
1114                 0x3b970, 0x3b99c,
1115                 0x3b9f0, 0x3ba38,
1116                 0x3ba40, 0x3ba40,
1117                 0x3ba48, 0x3ba50,
1118                 0x3ba5c, 0x3ba64,
1119                 0x3ba70, 0x3bab8,
1120                 0x3bac0, 0x3bae4,
1121                 0x3baf8, 0x3bb10,
1122                 0x3bb28, 0x3bb28,
1123                 0x3bb3c, 0x3bb50,
1124                 0x3bbf0, 0x3bc10,
1125                 0x3bc28, 0x3bc28,
1126                 0x3bc3c, 0x3bc50,
1127                 0x3bcf0, 0x3bcfc,
1128                 0x3c000, 0x3c030,
1129                 0x3c038, 0x3c038,
1130                 0x3c040, 0x3c040,
1131                 0x3c100, 0x3c144,
1132                 0x3c190, 0x3c1a0,
1133                 0x3c1a8, 0x3c1b8,
1134                 0x3c1c4, 0x3c1c8,
1135                 0x3c1d0, 0x3c1d0,
1136                 0x3c200, 0x3c318,
1137                 0x3c400, 0x3c4b4,
1138                 0x3c4c0, 0x3c52c,
1139                 0x3c540, 0x3c61c,
1140                 0x3c800, 0x3c828,
1141                 0x3c834, 0x3c834,
1142                 0x3c8c0, 0x3c908,
1143                 0x3c910, 0x3c9ac,
1144                 0x3ca00, 0x3ca14,
1145                 0x3ca1c, 0x3ca2c,
1146                 0x3ca44, 0x3ca50,
1147                 0x3ca74, 0x3ca74,
1148                 0x3ca7c, 0x3cafc,
1149                 0x3cb08, 0x3cc24,
1150                 0x3cd00, 0x3cd00,
1151                 0x3cd08, 0x3cd14,
1152                 0x3cd1c, 0x3cd20,
1153                 0x3cd3c, 0x3cd3c,
1154                 0x3cd48, 0x3cd50,
1155                 0x3d200, 0x3d20c,
1156                 0x3d220, 0x3d220,
1157                 0x3d240, 0x3d240,
1158                 0x3d600, 0x3d60c,
1159                 0x3da00, 0x3da1c,
1160                 0x3de00, 0x3de20,
1161                 0x3de38, 0x3de3c,
1162                 0x3de80, 0x3de80,
1163                 0x3de88, 0x3dea8,
1164                 0x3deb0, 0x3deb4,
1165                 0x3dec8, 0x3ded4,
1166                 0x3dfb8, 0x3e004,
1167                 0x3e200, 0x3e200,
1168                 0x3e208, 0x3e240,
1169                 0x3e248, 0x3e280,
1170                 0x3e288, 0x3e2c0,
1171                 0x3e2c8, 0x3e2fc,
1172                 0x3e600, 0x3e630,
1173                 0x3ea00, 0x3eabc,
1174                 0x3eb00, 0x3eb10,
1175                 0x3eb20, 0x3eb30,
1176                 0x3eb40, 0x3eb50,
1177                 0x3eb60, 0x3eb70,
1178                 0x3f000, 0x3f028,
1179                 0x3f030, 0x3f048,
1180                 0x3f060, 0x3f068,
1181                 0x3f070, 0x3f09c,
1182                 0x3f0f0, 0x3f128,
1183                 0x3f130, 0x3f148,
1184                 0x3f160, 0x3f168,
1185                 0x3f170, 0x3f19c,
1186                 0x3f1f0, 0x3f238,
1187                 0x3f240, 0x3f240,
1188                 0x3f248, 0x3f250,
1189                 0x3f25c, 0x3f264,
1190                 0x3f270, 0x3f2b8,
1191                 0x3f2c0, 0x3f2e4,
1192                 0x3f2f8, 0x3f338,
1193                 0x3f340, 0x3f340,
1194                 0x3f348, 0x3f350,
1195                 0x3f35c, 0x3f364,
1196                 0x3f370, 0x3f3b8,
1197                 0x3f3c0, 0x3f3e4,
1198                 0x3f3f8, 0x3f428,
1199                 0x3f430, 0x3f448,
1200                 0x3f460, 0x3f468,
1201                 0x3f470, 0x3f49c,
1202                 0x3f4f0, 0x3f528,
1203                 0x3f530, 0x3f548,
1204                 0x3f560, 0x3f568,
1205                 0x3f570, 0x3f59c,
1206                 0x3f5f0, 0x3f638,
1207                 0x3f640, 0x3f640,
1208                 0x3f648, 0x3f650,
1209                 0x3f65c, 0x3f664,
1210                 0x3f670, 0x3f6b8,
1211                 0x3f6c0, 0x3f6e4,
1212                 0x3f6f8, 0x3f738,
1213                 0x3f740, 0x3f740,
1214                 0x3f748, 0x3f750,
1215                 0x3f75c, 0x3f764,
1216                 0x3f770, 0x3f7b8,
1217                 0x3f7c0, 0x3f7e4,
1218                 0x3f7f8, 0x3f7fc,
1219                 0x3f814, 0x3f814,
1220                 0x3f82c, 0x3f82c,
1221                 0x3f880, 0x3f88c,
1222                 0x3f8e8, 0x3f8ec,
1223                 0x3f900, 0x3f928,
1224                 0x3f930, 0x3f948,
1225                 0x3f960, 0x3f968,
1226                 0x3f970, 0x3f99c,
1227                 0x3f9f0, 0x3fa38,
1228                 0x3fa40, 0x3fa40,
1229                 0x3fa48, 0x3fa50,
1230                 0x3fa5c, 0x3fa64,
1231                 0x3fa70, 0x3fab8,
1232                 0x3fac0, 0x3fae4,
1233                 0x3faf8, 0x3fb10,
1234                 0x3fb28, 0x3fb28,
1235                 0x3fb3c, 0x3fb50,
1236                 0x3fbf0, 0x3fc10,
1237                 0x3fc28, 0x3fc28,
1238                 0x3fc3c, 0x3fc50,
1239                 0x3fcf0, 0x3fcfc,
1240                 0x40000, 0x4000c,
1241                 0x40040, 0x40050,
1242                 0x40060, 0x40068,
1243                 0x4007c, 0x4008c,
1244                 0x40094, 0x400b0,
1245                 0x400c0, 0x40144,
1246                 0x40180, 0x4018c,
1247                 0x40200, 0x40254,
1248                 0x40260, 0x40264,
1249                 0x40270, 0x40288,
1250                 0x40290, 0x40298,
1251                 0x402ac, 0x402c8,
1252                 0x402d0, 0x402e0,
1253                 0x402f0, 0x402f0,
1254                 0x40300, 0x4033c,
1255                 0x403f8, 0x403fc,
1256                 0x41304, 0x413c4,
1257                 0x41400, 0x4140c,
1258                 0x41414, 0x4141c,
1259                 0x41480, 0x414d0,
1260                 0x44000, 0x44054,
1261                 0x4405c, 0x44078,
1262                 0x440c0, 0x44174,
1263                 0x44180, 0x441ac,
1264                 0x441b4, 0x441b8,
1265                 0x441c0, 0x44254,
1266                 0x4425c, 0x44278,
1267                 0x442c0, 0x44374,
1268                 0x44380, 0x443ac,
1269                 0x443b4, 0x443b8,
1270                 0x443c0, 0x44454,
1271                 0x4445c, 0x44478,
1272                 0x444c0, 0x44574,
1273                 0x44580, 0x445ac,
1274                 0x445b4, 0x445b8,
1275                 0x445c0, 0x44654,
1276                 0x4465c, 0x44678,
1277                 0x446c0, 0x44774,
1278                 0x44780, 0x447ac,
1279                 0x447b4, 0x447b8,
1280                 0x447c0, 0x44854,
1281                 0x4485c, 0x44878,
1282                 0x448c0, 0x44974,
1283                 0x44980, 0x449ac,
1284                 0x449b4, 0x449b8,
1285                 0x449c0, 0x449fc,
1286                 0x45000, 0x45004,
1287                 0x45010, 0x45030,
1288                 0x45040, 0x45060,
1289                 0x45068, 0x45068,
1290                 0x45080, 0x45084,
1291                 0x450a0, 0x450b0,
1292                 0x45200, 0x45204,
1293                 0x45210, 0x45230,
1294                 0x45240, 0x45260,
1295                 0x45268, 0x45268,
1296                 0x45280, 0x45284,
1297                 0x452a0, 0x452b0,
1298                 0x460c0, 0x460e4,
1299                 0x47000, 0x4703c,
1300                 0x47044, 0x4708c,
1301                 0x47200, 0x47250,
1302                 0x47400, 0x47408,
1303                 0x47414, 0x47420,
1304                 0x47600, 0x47618,
1305                 0x47800, 0x47814,
1306                 0x48000, 0x4800c,
1307                 0x48040, 0x48050,
1308                 0x48060, 0x48068,
1309                 0x4807c, 0x4808c,
1310                 0x48094, 0x480b0,
1311                 0x480c0, 0x48144,
1312                 0x48180, 0x4818c,
1313                 0x48200, 0x48254,
1314                 0x48260, 0x48264,
1315                 0x48270, 0x48288,
1316                 0x48290, 0x48298,
1317                 0x482ac, 0x482c8,
1318                 0x482d0, 0x482e0,
1319                 0x482f0, 0x482f0,
1320                 0x48300, 0x4833c,
1321                 0x483f8, 0x483fc,
1322                 0x49304, 0x493c4,
1323                 0x49400, 0x4940c,
1324                 0x49414, 0x4941c,
1325                 0x49480, 0x494d0,
1326                 0x4c000, 0x4c054,
1327                 0x4c05c, 0x4c078,
1328                 0x4c0c0, 0x4c174,
1329                 0x4c180, 0x4c1ac,
1330                 0x4c1b4, 0x4c1b8,
1331                 0x4c1c0, 0x4c254,
1332                 0x4c25c, 0x4c278,
1333                 0x4c2c0, 0x4c374,
1334                 0x4c380, 0x4c3ac,
1335                 0x4c3b4, 0x4c3b8,
1336                 0x4c3c0, 0x4c454,
1337                 0x4c45c, 0x4c478,
1338                 0x4c4c0, 0x4c574,
1339                 0x4c580, 0x4c5ac,
1340                 0x4c5b4, 0x4c5b8,
1341                 0x4c5c0, 0x4c654,
1342                 0x4c65c, 0x4c678,
1343                 0x4c6c0, 0x4c774,
1344                 0x4c780, 0x4c7ac,
1345                 0x4c7b4, 0x4c7b8,
1346                 0x4c7c0, 0x4c854,
1347                 0x4c85c, 0x4c878,
1348                 0x4c8c0, 0x4c974,
1349                 0x4c980, 0x4c9ac,
1350                 0x4c9b4, 0x4c9b8,
1351                 0x4c9c0, 0x4c9fc,
1352                 0x4d000, 0x4d004,
1353                 0x4d010, 0x4d030,
1354                 0x4d040, 0x4d060,
1355                 0x4d068, 0x4d068,
1356                 0x4d080, 0x4d084,
1357                 0x4d0a0, 0x4d0b0,
1358                 0x4d200, 0x4d204,
1359                 0x4d210, 0x4d230,
1360                 0x4d240, 0x4d260,
1361                 0x4d268, 0x4d268,
1362                 0x4d280, 0x4d284,
1363                 0x4d2a0, 0x4d2b0,
1364                 0x4e0c0, 0x4e0e4,
1365                 0x4f000, 0x4f03c,
1366                 0x4f044, 0x4f08c,
1367                 0x4f200, 0x4f250,
1368                 0x4f400, 0x4f408,
1369                 0x4f414, 0x4f420,
1370                 0x4f600, 0x4f618,
1371                 0x4f800, 0x4f814,
1372                 0x50000, 0x50084,
1373                 0x50090, 0x500cc,
1374                 0x50400, 0x50400,
1375                 0x50800, 0x50884,
1376                 0x50890, 0x508cc,
1377                 0x50c00, 0x50c00,
1378                 0x51000, 0x5101c,
1379                 0x51300, 0x51308,
1380         };
1381
1382         static const unsigned int t6_reg_ranges[] = {
1383                 0x1008, 0x101c,
1384                 0x1024, 0x10a8,
1385                 0x10b4, 0x10f8,
1386                 0x1100, 0x1114,
1387                 0x111c, 0x112c,
1388                 0x1138, 0x113c,
1389                 0x1144, 0x114c,
1390                 0x1180, 0x1184,
1391                 0x1190, 0x1194,
1392                 0x11a0, 0x11a4,
1393                 0x11b0, 0x11b4,
1394                 0x11fc, 0x1274,
1395                 0x1280, 0x133c,
1396                 0x1800, 0x18fc,
1397                 0x3000, 0x302c,
1398                 0x3060, 0x30b0,
1399                 0x30b8, 0x30d8,
1400                 0x30e0, 0x30fc,
1401                 0x3140, 0x357c,
1402                 0x35a8, 0x35cc,
1403                 0x35ec, 0x35ec,
1404                 0x3600, 0x5624,
1405                 0x56cc, 0x56ec,
1406                 0x56f4, 0x5720,
1407                 0x5728, 0x575c,
1408                 0x580c, 0x5814,
1409                 0x5890, 0x589c,
1410                 0x58a4, 0x58ac,
1411                 0x58b8, 0x58bc,
1412                 0x5940, 0x595c,
1413                 0x5980, 0x598c,
1414                 0x59b0, 0x59c8,
1415                 0x59d0, 0x59dc,
1416                 0x59fc, 0x5a18,
1417                 0x5a60, 0x5a6c,
1418                 0x5a80, 0x5a8c,
1419                 0x5a94, 0x5a9c,
1420                 0x5b94, 0x5bfc,
1421                 0x5c10, 0x5e48,
1422                 0x5e50, 0x5e94,
1423                 0x5ea0, 0x5eb0,
1424                 0x5ec0, 0x5ec0,
1425                 0x5ec8, 0x5ed0,
1426                 0x5ee0, 0x5ee0,
1427                 0x5ef0, 0x5ef0,
1428                 0x5f00, 0x5f00,
1429                 0x6000, 0x6020,
1430                 0x6028, 0x6040,
1431                 0x6058, 0x609c,
1432                 0x60a8, 0x619c,
1433                 0x7700, 0x7798,
1434                 0x77c0, 0x7880,
1435                 0x78cc, 0x78fc,
1436                 0x7b00, 0x7b58,
1437                 0x7b60, 0x7b84,
1438                 0x7b8c, 0x7c54,
1439                 0x7d00, 0x7d38,
1440                 0x7d40, 0x7d84,
1441                 0x7d8c, 0x7ddc,
1442                 0x7de4, 0x7e04,
1443                 0x7e10, 0x7e1c,
1444                 0x7e24, 0x7e38,
1445                 0x7e40, 0x7e44,
1446                 0x7e4c, 0x7e78,
1447                 0x7e80, 0x7edc,
1448                 0x7ee8, 0x7efc,
1449                 0x8dc0, 0x8de4,
1450                 0x8df8, 0x8e04,
1451                 0x8e10, 0x8e84,
1452                 0x8ea0, 0x8f88,
1453                 0x8fb8, 0x9058,
1454                 0x9060, 0x9060,
1455                 0x9068, 0x90f8,
1456                 0x9100, 0x9124,
1457                 0x9400, 0x9470,
1458                 0x9600, 0x9600,
1459                 0x9608, 0x9638,
1460                 0x9640, 0x9704,
1461                 0x9710, 0x971c,
1462                 0x9800, 0x9808,
1463                 0x9820, 0x983c,
1464                 0x9850, 0x9864,
1465                 0x9c00, 0x9c6c,
1466                 0x9c80, 0x9cec,
1467                 0x9d00, 0x9d6c,
1468                 0x9d80, 0x9dec,
1469                 0x9e00, 0x9e6c,
1470                 0x9e80, 0x9eec,
1471                 0x9f00, 0x9f6c,
1472                 0x9f80, 0xa020,
1473                 0xd004, 0xd03c,
1474                 0xd100, 0xd118,
1475                 0xd200, 0xd214,
1476                 0xd220, 0xd234,
1477                 0xd240, 0xd254,
1478                 0xd260, 0xd274,
1479                 0xd280, 0xd294,
1480                 0xd2a0, 0xd2b4,
1481                 0xd2c0, 0xd2d4,
1482                 0xd2e0, 0xd2f4,
1483                 0xd300, 0xd31c,
1484                 0xdfc0, 0xdfe0,
1485                 0xe000, 0xf008,
1486                 0xf010, 0xf018,
1487                 0xf020, 0xf028,
1488                 0x11000, 0x11014,
1489                 0x11048, 0x1106c,
1490                 0x11074, 0x11088,
1491                 0x11098, 0x11120,
1492                 0x1112c, 0x1117c,
1493                 0x11190, 0x112e0,
1494                 0x11300, 0x1130c,
1495                 0x12000, 0x1206c,
1496                 0x19040, 0x1906c,
1497                 0x19078, 0x19080,
1498                 0x1908c, 0x190e8,
1499                 0x190f0, 0x190f8,
1500                 0x19100, 0x19110,
1501                 0x19120, 0x19124,
1502                 0x19150, 0x19194,
1503                 0x1919c, 0x191b0,
1504                 0x191d0, 0x191e8,
1505                 0x19238, 0x19290,
1506                 0x192a4, 0x192b0,
1507                 0x192bc, 0x192bc,
1508                 0x19348, 0x1934c,
1509                 0x193f8, 0x19418,
1510                 0x19420, 0x19428,
1511                 0x19430, 0x19444,
1512                 0x1944c, 0x1946c,
1513                 0x19474, 0x19474,
1514                 0x19490, 0x194cc,
1515                 0x194f0, 0x194f8,
1516                 0x19c00, 0x19c48,
1517                 0x19c50, 0x19c80,
1518                 0x19c94, 0x19c98,
1519                 0x19ca0, 0x19cbc,
1520                 0x19ce4, 0x19ce4,
1521                 0x19cf0, 0x19cf8,
1522                 0x19d00, 0x19d28,
1523                 0x19d50, 0x19d78,
1524                 0x19d94, 0x19d98,
1525                 0x19da0, 0x19dc8,
1526                 0x19df0, 0x19e10,
1527                 0x19e50, 0x19e6c,
1528                 0x19ea0, 0x19ebc,
1529                 0x19ec4, 0x19ef4,
1530                 0x19f04, 0x19f2c,
1531                 0x19f34, 0x19f34,
1532                 0x19f40, 0x19f50,
1533                 0x19f90, 0x19fac,
1534                 0x19fc4, 0x19fc8,
1535                 0x19fd0, 0x19fe4,
1536                 0x1a000, 0x1a004,
1537                 0x1a010, 0x1a06c,
1538                 0x1a0b0, 0x1a0e4,
1539                 0x1a0ec, 0x1a0f8,
1540                 0x1a100, 0x1a108,
1541                 0x1a114, 0x1a120,
1542                 0x1a128, 0x1a130,
1543                 0x1a138, 0x1a138,
1544                 0x1a190, 0x1a1c4,
1545                 0x1a1fc, 0x1a1fc,
1546                 0x1e008, 0x1e00c,
1547                 0x1e040, 0x1e044,
1548                 0x1e04c, 0x1e04c,
1549                 0x1e284, 0x1e290,
1550                 0x1e2c0, 0x1e2c0,
1551                 0x1e2e0, 0x1e2e0,
1552                 0x1e300, 0x1e384,
1553                 0x1e3c0, 0x1e3c8,
1554                 0x1e408, 0x1e40c,
1555                 0x1e440, 0x1e444,
1556                 0x1e44c, 0x1e44c,
1557                 0x1e684, 0x1e690,
1558                 0x1e6c0, 0x1e6c0,
1559                 0x1e6e0, 0x1e6e0,
1560                 0x1e700, 0x1e784,
1561                 0x1e7c0, 0x1e7c8,
1562                 0x1e808, 0x1e80c,
1563                 0x1e840, 0x1e844,
1564                 0x1e84c, 0x1e84c,
1565                 0x1ea84, 0x1ea90,
1566                 0x1eac0, 0x1eac0,
1567                 0x1eae0, 0x1eae0,
1568                 0x1eb00, 0x1eb84,
1569                 0x1ebc0, 0x1ebc8,
1570                 0x1ec08, 0x1ec0c,
1571                 0x1ec40, 0x1ec44,
1572                 0x1ec4c, 0x1ec4c,
1573                 0x1ee84, 0x1ee90,
1574                 0x1eec0, 0x1eec0,
1575                 0x1eee0, 0x1eee0,
1576                 0x1ef00, 0x1ef84,
1577                 0x1efc0, 0x1efc8,
1578                 0x1f008, 0x1f00c,
1579                 0x1f040, 0x1f044,
1580                 0x1f04c, 0x1f04c,
1581                 0x1f284, 0x1f290,
1582                 0x1f2c0, 0x1f2c0,
1583                 0x1f2e0, 0x1f2e0,
1584                 0x1f300, 0x1f384,
1585                 0x1f3c0, 0x1f3c8,
1586                 0x1f408, 0x1f40c,
1587                 0x1f440, 0x1f444,
1588                 0x1f44c, 0x1f44c,
1589                 0x1f684, 0x1f690,
1590                 0x1f6c0, 0x1f6c0,
1591                 0x1f6e0, 0x1f6e0,
1592                 0x1f700, 0x1f784,
1593                 0x1f7c0, 0x1f7c8,
1594                 0x1f808, 0x1f80c,
1595                 0x1f840, 0x1f844,
1596                 0x1f84c, 0x1f84c,
1597                 0x1fa84, 0x1fa90,
1598                 0x1fac0, 0x1fac0,
1599                 0x1fae0, 0x1fae0,
1600                 0x1fb00, 0x1fb84,
1601                 0x1fbc0, 0x1fbc8,
1602                 0x1fc08, 0x1fc0c,
1603                 0x1fc40, 0x1fc44,
1604                 0x1fc4c, 0x1fc4c,
1605                 0x1fe84, 0x1fe90,
1606                 0x1fec0, 0x1fec0,
1607                 0x1fee0, 0x1fee0,
1608                 0x1ff00, 0x1ff84,
1609                 0x1ffc0, 0x1ffc8,
1610                 0x30000, 0x30030,
1611                 0x30100, 0x30168,
1612                 0x30190, 0x301a0,
1613                 0x301a8, 0x301b8,
1614                 0x301c4, 0x301c8,
1615                 0x301d0, 0x301d0,
1616                 0x30200, 0x30320,
1617                 0x30400, 0x304b4,
1618                 0x304c0, 0x3052c,
1619                 0x30540, 0x3061c,
1620                 0x30800, 0x308a0,
1621                 0x308c0, 0x30908,
1622                 0x30910, 0x309b8,
1623                 0x30a00, 0x30a04,
1624                 0x30a0c, 0x30a14,
1625                 0x30a1c, 0x30a2c,
1626                 0x30a44, 0x30a50,
1627                 0x30a74, 0x30a74,
1628                 0x30a7c, 0x30afc,
1629                 0x30b08, 0x30c24,
1630                 0x30d00, 0x30d14,
1631                 0x30d1c, 0x30d3c,
1632                 0x30d44, 0x30d4c,
1633                 0x30d54, 0x30d74,
1634                 0x30d7c, 0x30d7c,
1635                 0x30de0, 0x30de0,
1636                 0x30e00, 0x30ed4,
1637                 0x30f00, 0x30fa4,
1638                 0x30fc0, 0x30fc4,
1639                 0x31000, 0x31004,
1640                 0x31080, 0x310fc,
1641                 0x31208, 0x31220,
1642                 0x3123c, 0x31254,
1643                 0x31300, 0x31300,
1644                 0x31308, 0x3131c,
1645                 0x31338, 0x3133c,
1646                 0x31380, 0x31380,
1647                 0x31388, 0x313a8,
1648                 0x313b4, 0x313b4,
1649                 0x31400, 0x31420,
1650                 0x31438, 0x3143c,
1651                 0x31480, 0x31480,
1652                 0x314a8, 0x314a8,
1653                 0x314b0, 0x314b4,
1654                 0x314c8, 0x314d4,
1655                 0x31a40, 0x31a4c,
1656                 0x31af0, 0x31b20,
1657                 0x31b38, 0x31b3c,
1658                 0x31b80, 0x31b80,
1659                 0x31ba8, 0x31ba8,
1660                 0x31bb0, 0x31bb4,
1661                 0x31bc8, 0x31bd4,
1662                 0x32140, 0x3218c,
1663                 0x321f0, 0x321f4,
1664                 0x32200, 0x32200,
1665                 0x32218, 0x32218,
1666                 0x32400, 0x32400,
1667                 0x32408, 0x3241c,
1668                 0x32618, 0x32620,
1669                 0x32664, 0x32664,
1670                 0x326a8, 0x326a8,
1671                 0x326ec, 0x326ec,
1672                 0x32a00, 0x32abc,
1673                 0x32b00, 0x32b38,
1674                 0x32b20, 0x32b38,
1675                 0x32b40, 0x32b58,
1676                 0x32b60, 0x32b78,
1677                 0x32c00, 0x32c00,
1678                 0x32c08, 0x32c3c,
1679                 0x33000, 0x3302c,
1680                 0x33034, 0x33050,
1681                 0x33058, 0x33058,
1682                 0x33060, 0x3308c,
1683                 0x3309c, 0x330ac,
1684                 0x330c0, 0x330c0,
1685                 0x330c8, 0x330d0,
1686                 0x330d8, 0x330e0,
1687                 0x330ec, 0x3312c,
1688                 0x33134, 0x33150,
1689                 0x33158, 0x33158,
1690                 0x33160, 0x3318c,
1691                 0x3319c, 0x331ac,
1692                 0x331c0, 0x331c0,
1693                 0x331c8, 0x331d0,
1694                 0x331d8, 0x331e0,
1695                 0x331ec, 0x33290,
1696                 0x33298, 0x332c4,
1697                 0x332e4, 0x33390,
1698                 0x33398, 0x333c4,
1699                 0x333e4, 0x3342c,
1700                 0x33434, 0x33450,
1701                 0x33458, 0x33458,
1702                 0x33460, 0x3348c,
1703                 0x3349c, 0x334ac,
1704                 0x334c0, 0x334c0,
1705                 0x334c8, 0x334d0,
1706                 0x334d8, 0x334e0,
1707                 0x334ec, 0x3352c,
1708                 0x33534, 0x33550,
1709                 0x33558, 0x33558,
1710                 0x33560, 0x3358c,
1711                 0x3359c, 0x335ac,
1712                 0x335c0, 0x335c0,
1713                 0x335c8, 0x335d0,
1714                 0x335d8, 0x335e0,
1715                 0x335ec, 0x33690,
1716                 0x33698, 0x336c4,
1717                 0x336e4, 0x33790,
1718                 0x33798, 0x337c4,
1719                 0x337e4, 0x337fc,
1720                 0x33814, 0x33814,
1721                 0x33854, 0x33868,
1722                 0x33880, 0x3388c,
1723                 0x338c0, 0x338d0,
1724                 0x338e8, 0x338ec,
1725                 0x33900, 0x3392c,
1726                 0x33934, 0x33950,
1727                 0x33958, 0x33958,
1728                 0x33960, 0x3398c,
1729                 0x3399c, 0x339ac,
1730                 0x339c0, 0x339c0,
1731                 0x339c8, 0x339d0,
1732                 0x339d8, 0x339e0,
1733                 0x339ec, 0x33a90,
1734                 0x33a98, 0x33ac4,
1735                 0x33ae4, 0x33b10,
1736                 0x33b24, 0x33b28,
1737                 0x33b38, 0x33b50,
1738                 0x33bf0, 0x33c10,
1739                 0x33c24, 0x33c28,
1740                 0x33c38, 0x33c50,
1741                 0x33cf0, 0x33cfc,
1742                 0x34000, 0x34030,
1743                 0x34100, 0x34168,
1744                 0x34190, 0x341a0,
1745                 0x341a8, 0x341b8,
1746                 0x341c4, 0x341c8,
1747                 0x341d0, 0x341d0,
1748                 0x34200, 0x34320,
1749                 0x34400, 0x344b4,
1750                 0x344c0, 0x3452c,
1751                 0x34540, 0x3461c,
1752                 0x34800, 0x348a0,
1753                 0x348c0, 0x34908,
1754                 0x34910, 0x349b8,
1755                 0x34a00, 0x34a04,
1756                 0x34a0c, 0x34a14,
1757                 0x34a1c, 0x34a2c,
1758                 0x34a44, 0x34a50,
1759                 0x34a74, 0x34a74,
1760                 0x34a7c, 0x34afc,
1761                 0x34b08, 0x34c24,
1762                 0x34d00, 0x34d14,
1763                 0x34d1c, 0x34d3c,
1764                 0x34d44, 0x34d4c,
1765                 0x34d54, 0x34d74,
1766                 0x34d7c, 0x34d7c,
1767                 0x34de0, 0x34de0,
1768                 0x34e00, 0x34ed4,
1769                 0x34f00, 0x34fa4,
1770                 0x34fc0, 0x34fc4,
1771                 0x35000, 0x35004,
1772                 0x35080, 0x350fc,
1773                 0x35208, 0x35220,
1774                 0x3523c, 0x35254,
1775                 0x35300, 0x35300,
1776                 0x35308, 0x3531c,
1777                 0x35338, 0x3533c,
1778                 0x35380, 0x35380,
1779                 0x35388, 0x353a8,
1780                 0x353b4, 0x353b4,
1781                 0x35400, 0x35420,
1782                 0x35438, 0x3543c,
1783                 0x35480, 0x35480,
1784                 0x354a8, 0x354a8,
1785                 0x354b0, 0x354b4,
1786                 0x354c8, 0x354d4,
1787                 0x35a40, 0x35a4c,
1788                 0x35af0, 0x35b20,
1789                 0x35b38, 0x35b3c,
1790                 0x35b80, 0x35b80,
1791                 0x35ba8, 0x35ba8,
1792                 0x35bb0, 0x35bb4,
1793                 0x35bc8, 0x35bd4,
1794                 0x36140, 0x3618c,
1795                 0x361f0, 0x361f4,
1796                 0x36200, 0x36200,
1797                 0x36218, 0x36218,
1798                 0x36400, 0x36400,
1799                 0x36408, 0x3641c,
1800                 0x36618, 0x36620,
1801                 0x36664, 0x36664,
1802                 0x366a8, 0x366a8,
1803                 0x366ec, 0x366ec,
1804                 0x36a00, 0x36abc,
1805                 0x36b00, 0x36b38,
1806                 0x36b20, 0x36b38,
1807                 0x36b40, 0x36b58,
1808                 0x36b60, 0x36b78,
1809                 0x36c00, 0x36c00,
1810                 0x36c08, 0x36c3c,
1811                 0x37000, 0x3702c,
1812                 0x37034, 0x37050,
1813                 0x37058, 0x37058,
1814                 0x37060, 0x3708c,
1815                 0x3709c, 0x370ac,
1816                 0x370c0, 0x370c0,
1817                 0x370c8, 0x370d0,
1818                 0x370d8, 0x370e0,
1819                 0x370ec, 0x3712c,
1820                 0x37134, 0x37150,
1821                 0x37158, 0x37158,
1822                 0x37160, 0x3718c,
1823                 0x3719c, 0x371ac,
1824                 0x371c0, 0x371c0,
1825                 0x371c8, 0x371d0,
1826                 0x371d8, 0x371e0,
1827                 0x371ec, 0x37290,
1828                 0x37298, 0x372c4,
1829                 0x372e4, 0x37390,
1830                 0x37398, 0x373c4,
1831                 0x373e4, 0x3742c,
1832                 0x37434, 0x37450,
1833                 0x37458, 0x37458,
1834                 0x37460, 0x3748c,
1835                 0x3749c, 0x374ac,
1836                 0x374c0, 0x374c0,
1837                 0x374c8, 0x374d0,
1838                 0x374d8, 0x374e0,
1839                 0x374ec, 0x3752c,
1840                 0x37534, 0x37550,
1841                 0x37558, 0x37558,
1842                 0x37560, 0x3758c,
1843                 0x3759c, 0x375ac,
1844                 0x375c0, 0x375c0,
1845                 0x375c8, 0x375d0,
1846                 0x375d8, 0x375e0,
1847                 0x375ec, 0x37690,
1848                 0x37698, 0x376c4,
1849                 0x376e4, 0x37790,
1850                 0x37798, 0x377c4,
1851                 0x377e4, 0x377fc,
1852                 0x37814, 0x37814,
1853                 0x37854, 0x37868,
1854                 0x37880, 0x3788c,
1855                 0x378c0, 0x378d0,
1856                 0x378e8, 0x378ec,
1857                 0x37900, 0x3792c,
1858                 0x37934, 0x37950,
1859                 0x37958, 0x37958,
1860                 0x37960, 0x3798c,
1861                 0x3799c, 0x379ac,
1862                 0x379c0, 0x379c0,
1863                 0x379c8, 0x379d0,
1864                 0x379d8, 0x379e0,
1865                 0x379ec, 0x37a90,
1866                 0x37a98, 0x37ac4,
1867                 0x37ae4, 0x37b10,
1868                 0x37b24, 0x37b28,
1869                 0x37b38, 0x37b50,
1870                 0x37bf0, 0x37c10,
1871                 0x37c24, 0x37c28,
1872                 0x37c38, 0x37c50,
1873                 0x37cf0, 0x37cfc,
1874                 0x40040, 0x40040,
1875                 0x40080, 0x40084,
1876                 0x40100, 0x40100,
1877                 0x40140, 0x401bc,
1878                 0x40200, 0x40214,
1879                 0x40228, 0x40228,
1880                 0x40240, 0x40258,
1881                 0x40280, 0x40280,
1882                 0x40304, 0x40304,
1883                 0x40330, 0x4033c,
1884                 0x41304, 0x413c8,
1885                 0x413d0, 0x413dc,
1886                 0x413f0, 0x413f0,
1887                 0x41400, 0x4140c,
1888                 0x41414, 0x4141c,
1889                 0x41480, 0x414d0,
1890                 0x44000, 0x4407c,
1891                 0x440c0, 0x441ac,
1892                 0x441b4, 0x4427c,
1893                 0x442c0, 0x443ac,
1894                 0x443b4, 0x4447c,
1895                 0x444c0, 0x445ac,
1896                 0x445b4, 0x4467c,
1897                 0x446c0, 0x447ac,
1898                 0x447b4, 0x4487c,
1899                 0x448c0, 0x449ac,
1900                 0x449b4, 0x44a7c,
1901                 0x44ac0, 0x44bac,
1902                 0x44bb4, 0x44c7c,
1903                 0x44cc0, 0x44dac,
1904                 0x44db4, 0x44e7c,
1905                 0x44ec0, 0x44fac,
1906                 0x44fb4, 0x4507c,
1907                 0x450c0, 0x451ac,
1908                 0x451b4, 0x451fc,
1909                 0x45800, 0x45804,
1910                 0x45810, 0x45830,
1911                 0x45840, 0x45860,
1912                 0x45868, 0x45868,
1913                 0x45880, 0x45884,
1914                 0x458a0, 0x458b0,
1915                 0x45a00, 0x45a04,
1916                 0x45a10, 0x45a30,
1917                 0x45a40, 0x45a60,
1918                 0x45a68, 0x45a68,
1919                 0x45a80, 0x45a84,
1920                 0x45aa0, 0x45ab0,
1921                 0x460c0, 0x460e4,
1922                 0x47000, 0x4703c,
1923                 0x47044, 0x4708c,
1924                 0x47200, 0x47250,
1925                 0x47400, 0x47408,
1926                 0x47414, 0x47420,
1927                 0x47600, 0x47618,
1928                 0x47800, 0x47814,
1929                 0x47820, 0x4782c,
1930                 0x50000, 0x50084,
1931                 0x50090, 0x500cc,
1932                 0x50300, 0x50384,
1933                 0x50400, 0x50400,
1934                 0x50800, 0x50884,
1935                 0x50890, 0x508cc,
1936                 0x50b00, 0x50b84,
1937                 0x50c00, 0x50c00,
1938                 0x51000, 0x51020,
1939                 0x51028, 0x510b0,
1940                 0x51300, 0x51324,
1941         };
1942
1943         u32 *buf_end = (u32 *)((char *)buf + buf_size);
1944         const unsigned int *reg_ranges;
1945         int reg_ranges_size, range;
1946         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1947
1948         /* Select the right set of register ranges to dump depending on the
1949          * adapter chip type.
1950          */
1951         switch (chip_version) {
1952         case CHELSIO_T5:
1953                 reg_ranges = t5_reg_ranges;
1954                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1955                 break;
1956
1957         case CHELSIO_T6:
1958                 reg_ranges = t6_reg_ranges;
1959                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1960                 break;
1961
1962         default:
1963                 dev_err(adap,
1964                         "Unsupported chip version %d\n", chip_version);
1965                 return;
1966         }
1967
1968         /* Clear the register buffer and insert the appropriate register
1969          * values selected by the above register ranges.
1970          */
1971         memset(buf, 0, buf_size);
1972         for (range = 0; range < reg_ranges_size; range += 2) {
1973                 unsigned int reg = reg_ranges[range];
1974                 unsigned int last_reg = reg_ranges[range + 1];
1975                 u32 *bufp = (u32 *)((char *)buf + reg);
1976
1977                 /* Iterate across the register range filling in the register
1978                  * buffer but don't write past the end of the register buffer.
1979                  */
1980                 while (reg <= last_reg && bufp < buf_end) {
1981                         *bufp++ = t4_read_reg(adap, reg);
1982                         reg += sizeof(u32);
1983                 }
1984         }
1985 }
1986
1987 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1988 #define EEPROM_DELAY            10              /* 10us per poll spin */
1989 #define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
1990
1991 #define EEPROM_STAT_ADDR        0x7bfc
1992
1993 /**
1994  * Small utility function to wait till any outstanding VPD Access is complete.
1995  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1996  * VPD Access in flight.  This allows us to handle the problem of having a
1997  * previous VPD Access time out and prevent an attempt to inject a new VPD
1998  * Request before any in-flight VPD request has completed.
1999  */
2000 static int t4_seeprom_wait(struct adapter *adapter)
2001 {
2002         unsigned int base = adapter->params.pci.vpd_cap_addr;
2003         int max_poll;
2004
2005         /* If no VPD Access is in flight, we can just return success right
2006          * away.
2007          */
2008         if (!adapter->vpd_busy)
2009                 return 0;
2010
2011         /* Poll the VPD Capability Address/Flag register waiting for it
2012          * to indicate that the operation is complete.
2013          */
2014         max_poll = EEPROM_MAX_POLL;
2015         do {
2016                 u16 val;
2017
2018                 udelay(EEPROM_DELAY);
2019                 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2020
2021                 /* If the operation is complete, mark the VPD as no longer
2022                  * busy and return success.
2023                  */
2024                 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2025                         adapter->vpd_busy = 0;
2026                         return 0;
2027                 }
2028         } while (--max_poll);
2029
2030         /* Failure!  Note that we leave the VPD Busy status set in order to
2031          * avoid pushing a new VPD Access request into the VPD Capability till
2032          * the current operation eventually succeeds.  It's a bug to issue a
2033          * new request when an existing request is in flight and will result
2034          * in corrupt hardware state.
2035          */
2036         return -ETIMEDOUT;
2037 }
2038
2039 /**
2040  * t4_seeprom_read - read a serial EEPROM location
2041  * @adapter: adapter to read
2042  * @addr: EEPROM virtual address
2043  * @data: where to store the read data
2044  *
2045  * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2046  * VPD capability.  Note that this function must be called with a virtual
2047  * address.
2048  */
2049 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2050 {
2051         unsigned int base = adapter->params.pci.vpd_cap_addr;
2052         int ret;
2053
2054         /* VPD Accesses must alway be 4-byte aligned!
2055          */
2056         if (addr >= EEPROMVSIZE || (addr & 3))
2057                 return -EINVAL;
2058
2059         /* Wait for any previous operation which may still be in flight to
2060          * complete.
2061          */
2062         ret = t4_seeprom_wait(adapter);
2063         if (ret) {
2064                 dev_err(adapter, "VPD still busy from previous operation\n");
2065                 return ret;
2066         }
2067
2068         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2069          * for our request to complete.  If it doesn't complete, note the
2070          * error and return it to our caller.  Note that we do not reset the
2071          * VPD Busy status!
2072          */
2073         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2074         adapter->vpd_busy = 1;
2075         adapter->vpd_flag = PCI_VPD_ADDR_F;
2076         ret = t4_seeprom_wait(adapter);
2077         if (ret) {
2078                 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2079                 return ret;
2080         }
2081
2082         /* Grab the returned data, swizzle it into our endianness and
2083          * return success.
2084          */
2085         t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2086         *data = le32_to_cpu(*data);
2087         return 0;
2088 }
2089
2090 /**
2091  * t4_seeprom_write - write a serial EEPROM location
2092  * @adapter: adapter to write
2093  * @addr: virtual EEPROM address
2094  * @data: value to write
2095  *
2096  * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2097  * VPD capability.  Note that this function must be called with a virtual
2098  * address.
2099  */
2100 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2101 {
2102         unsigned int base = adapter->params.pci.vpd_cap_addr;
2103         int ret;
2104         u32 stats_reg = 0;
2105         int max_poll;
2106
2107         /* VPD Accesses must alway be 4-byte aligned!
2108          */
2109         if (addr >= EEPROMVSIZE || (addr & 3))
2110                 return -EINVAL;
2111
2112         /* Wait for any previous operation which may still be in flight to
2113          * complete.
2114          */
2115         ret = t4_seeprom_wait(adapter);
2116         if (ret) {
2117                 dev_err(adapter, "VPD still busy from previous operation\n");
2118                 return ret;
2119         }
2120
2121         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2122          * for our request to complete.  If it doesn't complete, note the
2123          * error and return it to our caller.  Note that we do not reset the
2124          * VPD Busy status!
2125          */
2126         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2127                              cpu_to_le32(data));
2128         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2129                              (u16)addr | PCI_VPD_ADDR_F);
2130         adapter->vpd_busy = 1;
2131         adapter->vpd_flag = 0;
2132         ret = t4_seeprom_wait(adapter);
2133         if (ret) {
2134                 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2135                 return ret;
2136         }
2137
2138         /* Reset PCI_VPD_DATA register after a transaction and wait for our
2139          * request to complete. If it doesn't complete, return error.
2140          */
2141         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2142         max_poll = EEPROM_MAX_POLL;
2143         do {
2144                 udelay(EEPROM_DELAY);
2145                 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2146         } while ((stats_reg & 0x1) && --max_poll);
2147         if (!max_poll)
2148                 return -ETIMEDOUT;
2149
2150         /* Return success! */
2151         return 0;
2152 }
2153
2154 /**
2155  * t4_seeprom_wp - enable/disable EEPROM write protection
2156  * @adapter: the adapter
2157  * @enable: whether to enable or disable write protection
2158  *
2159  * Enables or disables write protection on the serial EEPROM.
2160  */
2161 int t4_seeprom_wp(struct adapter *adapter, int enable)
2162 {
2163         return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2164 }
2165
2166 /**
2167  * t4_fw_tp_pio_rw - Access TP PIO through LDST
2168  * @adap: the adapter
2169  * @vals: where the indirect register values are stored/written
2170  * @nregs: how many indirect registers to read/write
2171  * @start_idx: index of first indirect register to read/write
2172  * @rw: Read (1) or Write (0)
2173  *
2174  * Access TP PIO registers through LDST
2175  */
2176 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
2177                      unsigned int start_index, unsigned int rw)
2178 {
2179         int cmd = FW_LDST_ADDRSPC_TP_PIO;
2180         struct fw_ldst_cmd c;
2181         unsigned int i;
2182         int ret;
2183
2184         for (i = 0 ; i < nregs; i++) {
2185                 memset(&c, 0, sizeof(c));
2186                 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
2187                                                 F_FW_CMD_REQUEST |
2188                                                 (rw ? F_FW_CMD_READ :
2189                                                       F_FW_CMD_WRITE) |
2190                                                 V_FW_LDST_CMD_ADDRSPACE(cmd));
2191                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
2192
2193                 c.u.addrval.addr = cpu_to_be32(start_index + i);
2194                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
2195                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2196                 if (ret == 0) {
2197                         if (rw)
2198                                 vals[i] = be32_to_cpu(c.u.addrval.val);
2199                 }
2200         }
2201 }
2202
2203 /**
2204  * t4_read_rss_key - read the global RSS key
2205  * @adap: the adapter
2206  * @key: 10-entry array holding the 320-bit RSS key
2207  *
2208  * Reads the global 320-bit RSS key.
2209  */
2210 void t4_read_rss_key(struct adapter *adap, u32 *key)
2211 {
2212         t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 1);
2213 }
2214
2215 /**
2216  * t4_write_rss_key - program one of the RSS keys
2217  * @adap: the adapter
2218  * @key: 10-entry array holding the 320-bit RSS key
2219  * @idx: which RSS key to write
2220  *
2221  * Writes one of the RSS keys with the given 320-bit value.  If @idx is
2222  * 0..15 the corresponding entry in the RSS key table is written,
2223  * otherwise the global RSS key is written.
2224  */
2225 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
2226 {
2227         u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
2228         u8 rss_key_addr_cnt = 16;
2229
2230         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
2231          * allows access to key addresses 16-63 by using KeyWrAddrX
2232          * as index[5:4](upper 2) into key table
2233          */
2234         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
2235             (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
2236                 rss_key_addr_cnt = 32;
2237
2238         t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
2239
2240         if (idx >= 0 && idx < rss_key_addr_cnt) {
2241                 if (rss_key_addr_cnt > 16)
2242                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2243                                      V_KEYWRADDRX(idx >> 4) |
2244                                      V_T6_VFWRADDR(idx) | F_KEYWREN);
2245                 else
2246                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2247                                      V_KEYWRADDR(idx) | F_KEYWREN);
2248         }
2249 }
2250
2251 /**
2252  * t4_config_rss_range - configure a portion of the RSS mapping table
2253  * @adapter: the adapter
2254  * @mbox: mbox to use for the FW command
2255  * @viid: virtual interface whose RSS subtable is to be written
2256  * @start: start entry in the table to write
2257  * @n: how many table entries to write
2258  * @rspq: values for the "response queue" (Ingress Queue) lookup table
2259  * @nrspq: number of values in @rspq
2260  *
2261  * Programs the selected part of the VI's RSS mapping table with the
2262  * provided values.  If @nrspq < @n the supplied values are used repeatedly
2263  * until the full table range is populated.
2264  *
2265  * The caller must ensure the values in @rspq are in the range allowed for
2266  * @viid.
2267  */
2268 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2269                         int start, int n, const u16 *rspq, unsigned int nrspq)
2270 {
2271         int ret;
2272         const u16 *rsp = rspq;
2273         const u16 *rsp_end = rspq + nrspq;
2274         struct fw_rss_ind_tbl_cmd cmd;
2275
2276         memset(&cmd, 0, sizeof(cmd));
2277         cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2278                                      F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2279                                      V_FW_RSS_IND_TBL_CMD_VIID(viid));
2280         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2281
2282         /*
2283          * Each firmware RSS command can accommodate up to 32 RSS Ingress
2284          * Queue Identifiers.  These Ingress Queue IDs are packed three to
2285          * a 32-bit word as 10-bit values with the upper remaining 2 bits
2286          * reserved.
2287          */
2288         while (n > 0) {
2289                 int nq = min(n, 32);
2290                 int nq_packed = 0;
2291                 __be32 *qp = &cmd.iq0_to_iq2;
2292
2293                 /*
2294                  * Set up the firmware RSS command header to send the next
2295                  * "nq" Ingress Queue IDs to the firmware.
2296                  */
2297                 cmd.niqid = cpu_to_be16(nq);
2298                 cmd.startidx = cpu_to_be16(start);
2299
2300                 /*
2301                  * "nq" more done for the start of the next loop.
2302                  */
2303                 start += nq;
2304                 n -= nq;
2305
2306                 /*
2307                  * While there are still Ingress Queue IDs to stuff into the
2308                  * current firmware RSS command, retrieve them from the
2309                  * Ingress Queue ID array and insert them into the command.
2310                  */
2311                 while (nq > 0) {
2312                         /*
2313                          * Grab up to the next 3 Ingress Queue IDs (wrapping
2314                          * around the Ingress Queue ID array if necessary) and
2315                          * insert them into the firmware RSS command at the
2316                          * current 3-tuple position within the commad.
2317                          */
2318                         u16 qbuf[3];
2319                         u16 *qbp = qbuf;
2320                         int nqbuf = min(3, nq);
2321
2322                         nq -= nqbuf;
2323                         qbuf[0] = 0;
2324                         qbuf[1] = 0;
2325                         qbuf[2] = 0;
2326                         while (nqbuf && nq_packed < 32) {
2327                                 nqbuf--;
2328                                 nq_packed++;
2329                                 *qbp++ = *rsp++;
2330                                 if (rsp >= rsp_end)
2331                                         rsp = rspq;
2332                         }
2333                         *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2334                                             V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2335                                             V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2336                 }
2337
2338                 /*
2339                  * Send this portion of the RRS table update to the firmware;
2340                  * bail out on any errors.
2341                  */
2342                 if (is_pf4(adapter))
2343                         ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd),
2344                                          NULL);
2345                 else
2346                         ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
2347                 if (ret)
2348                         return ret;
2349         }
2350
2351         return 0;
2352 }
2353
2354 /**
2355  * t4_config_vi_rss - configure per VI RSS settings
2356  * @adapter: the adapter
2357  * @mbox: mbox to use for the FW command
2358  * @viid: the VI id
2359  * @flags: RSS flags
2360  * @defq: id of the default RSS queue for the VI.
2361  *
2362  * Configures VI-specific RSS properties.
2363  */
2364 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2365                      unsigned int flags, unsigned int defq)
2366 {
2367         struct fw_rss_vi_config_cmd c;
2368
2369         memset(&c, 0, sizeof(c));
2370         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2371                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2372                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2373         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2374         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2375                         V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2376         if (is_pf4(adapter))
2377                 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2378         else
2379                 return t4vf_wr_mbox(adapter, &c, sizeof(c), NULL);
2380 }
2381
2382 /**
2383  * t4_read_config_vi_rss - read the configured per VI RSS settings
2384  * @adapter: the adapter
2385  * @mbox: mbox to use for the FW command
2386  * @viid: the VI id
2387  * @flags: where to place the configured flags
2388  * @defq: where to place the id of the default RSS queue for the VI.
2389  *
2390  * Read configured VI-specific RSS properties.
2391  */
2392 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2393                           u64 *flags, unsigned int *defq)
2394 {
2395         struct fw_rss_vi_config_cmd c;
2396         unsigned int result;
2397         int ret;
2398
2399         memset(&c, 0, sizeof(c));
2400         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2401                                    F_FW_CMD_REQUEST | F_FW_CMD_READ |
2402                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2403         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2404         ret = t4_wr_mbox(adapter, mbox, &c, sizeof(c), &c);
2405         if (!ret) {
2406                 result = be32_to_cpu(c.u.basicvirtual.defaultq_to_udpen);
2407                 if (defq)
2408                         *defq = G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(result);
2409                 if (flags)
2410                         *flags = result & M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ;
2411         }
2412
2413         return ret;
2414 }
2415
2416 /**
2417  * init_cong_ctrl - initialize congestion control parameters
2418  * @a: the alpha values for congestion control
2419  * @b: the beta values for congestion control
2420  *
2421  * Initialize the congestion control parameters.
2422  */
2423 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2424 {
2425         int i;
2426
2427         for (i = 0; i < 9; i++) {
2428                 a[i] = 1;
2429                 b[i] = 0;
2430         }
2431
2432         a[9] = 2;
2433         a[10] = 3;
2434         a[11] = 4;
2435         a[12] = 5;
2436         a[13] = 6;
2437         a[14] = 7;
2438         a[15] = 8;
2439         a[16] = 9;
2440         a[17] = 10;
2441         a[18] = 14;
2442         a[19] = 17;
2443         a[20] = 21;
2444         a[21] = 25;
2445         a[22] = 30;
2446         a[23] = 35;
2447         a[24] = 45;
2448         a[25] = 60;
2449         a[26] = 80;
2450         a[27] = 100;
2451         a[28] = 200;
2452         a[29] = 300;
2453         a[30] = 400;
2454         a[31] = 500;
2455
2456         b[9] = 1;
2457         b[10] = 1;
2458         b[11] = 2;
2459         b[12] = 2;
2460         b[13] = 3;
2461         b[14] = 3;
2462         b[15] = 3;
2463         b[16] = 3;
2464         b[17] = 4;
2465         b[18] = 4;
2466         b[19] = 4;
2467         b[20] = 4;
2468         b[21] = 4;
2469         b[22] = 5;
2470         b[23] = 5;
2471         b[24] = 5;
2472         b[25] = 5;
2473         b[26] = 5;
2474         b[27] = 5;
2475         b[28] = 6;
2476         b[29] = 6;
2477         b[30] = 7;
2478         b[31] = 7;
2479 }
2480
2481 #define INIT_CMD(var, cmd, rd_wr) do { \
2482         (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2483                         F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2484         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2485 } while (0)
2486
2487 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2488 {
2489         u32 cclk_param, cclk_val;
2490         int ret;
2491
2492         /*
2493          * Ask firmware for the Core Clock since it knows how to translate the
2494          * Reference Clock ('V2') VPD field into a Core Clock value ...
2495          */
2496         cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2497                       V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2498         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2499                               1, &cclk_param, &cclk_val);
2500         if (ret) {
2501                 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2502                         __func__, ret);
2503                 return ret;
2504         }
2505
2506         p->cclk = cclk_val;
2507         dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2508         return 0;
2509 }
2510
2511 /* serial flash and firmware constants and flash config file constants */
2512 enum {
2513         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2514
2515         /* flash command opcodes */
2516         SF_PROG_PAGE    = 2,          /* program page */
2517         SF_WR_DISABLE   = 4,          /* disable writes */
2518         SF_RD_STATUS    = 5,          /* read status register */
2519         SF_WR_ENABLE    = 6,          /* enable writes */
2520         SF_RD_DATA_FAST = 0xb,        /* read flash */
2521         SF_RD_ID        = 0x9f,       /* read ID */
2522         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2523 };
2524
2525 /**
2526  * sf1_read - read data from the serial flash
2527  * @adapter: the adapter
2528  * @byte_cnt: number of bytes to read
2529  * @cont: whether another operation will be chained
2530  * @lock: whether to lock SF for PL access only
2531  * @valp: where to store the read data
2532  *
2533  * Reads up to 4 bytes of data from the serial flash.  The location of
2534  * the read needs to be specified prior to calling this by issuing the
2535  * appropriate commands to the serial flash.
2536  */
2537 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2538                     int lock, u32 *valp)
2539 {
2540         int ret;
2541
2542         if (!byte_cnt || byte_cnt > 4)
2543                 return -EINVAL;
2544         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2545                 return -EBUSY;
2546         t4_write_reg(adapter, A_SF_OP,
2547                      V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2548         ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2549         if (!ret)
2550                 *valp = t4_read_reg(adapter, A_SF_DATA);
2551         return ret;
2552 }
2553
2554 /**
2555  * sf1_write - write data to the serial flash
2556  * @adapter: the adapter
2557  * @byte_cnt: number of bytes to write
2558  * @cont: whether another operation will be chained
2559  * @lock: whether to lock SF for PL access only
2560  * @val: value to write
2561  *
2562  * Writes up to 4 bytes of data to the serial flash.  The location of
2563  * the write needs to be specified prior to calling this by issuing the
2564  * appropriate commands to the serial flash.
2565  */
2566 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2567                      int lock, u32 val)
2568 {
2569         if (!byte_cnt || byte_cnt > 4)
2570                 return -EINVAL;
2571         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2572                 return -EBUSY;
2573         t4_write_reg(adapter, A_SF_DATA, val);
2574         t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2575                      V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2576         return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2577 }
2578
2579 /**
2580  * t4_read_flash - read words from serial flash
2581  * @adapter: the adapter
2582  * @addr: the start address for the read
2583  * @nwords: how many 32-bit words to read
2584  * @data: where to store the read data
2585  * @byte_oriented: whether to store data as bytes or as words
2586  *
2587  * Read the specified number of 32-bit words from the serial flash.
2588  * If @byte_oriented is set the read data is stored as a byte array
2589  * (i.e., big-endian), otherwise as 32-bit words in the platform's
2590  * natural endianness.
2591  */
2592 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2593                   unsigned int nwords, u32 *data, int byte_oriented)
2594 {
2595         int ret;
2596
2597         if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2598             (addr & 3))
2599                 return -EINVAL;
2600
2601         addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2602
2603         ret = sf1_write(adapter, 4, 1, 0, addr);
2604         if (ret != 0)
2605                 return ret;
2606
2607         ret = sf1_read(adapter, 1, 1, 0, data);
2608         if (ret != 0)
2609                 return ret;
2610
2611         for ( ; nwords; nwords--, data++) {
2612                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2613                 if (nwords == 1)
2614                         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
2615                 if (ret)
2616                         return ret;
2617                 if (byte_oriented)
2618                         *data = cpu_to_be32(*data);
2619         }
2620         return 0;
2621 }
2622
2623 /**
2624  * t4_get_exprom_version - return the Expansion ROM version (if any)
2625  * @adapter: the adapter
2626  * @vers: where to place the version
2627  *
2628  * Reads the Expansion ROM header from FLASH and returns the version
2629  * number (if present) through the @vers return value pointer.  We return
2630  * this in the Firmware Version Format since it's convenient.  Return
2631  * 0 on success, -ENOENT if no Expansion ROM is present.
2632  */
2633 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2634 {
2635         struct exprom_header {
2636                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
2637                 unsigned char hdr_ver[4];       /* Expansion ROM version */
2638         } *hdr;
2639         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2640                                            sizeof(u32))];
2641         int ret;
2642
2643         ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2644                             ARRAY_SIZE(exprom_header_buf),
2645                             exprom_header_buf, 0);
2646         if (ret)
2647                 return ret;
2648
2649         hdr = (struct exprom_header *)exprom_header_buf;
2650         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2651                 return -ENOENT;
2652
2653         *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2654                  V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2655                  V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2656                  V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2657         return 0;
2658 }
2659
2660 /**
2661  * t4_get_fw_version - read the firmware version
2662  * @adapter: the adapter
2663  * @vers: where to place the version
2664  *
2665  * Reads the FW version from flash.
2666  */
2667 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2668 {
2669         return t4_read_flash(adapter, FLASH_FW_START +
2670                              offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2671 }
2672
2673 /**
2674  *     t4_get_bs_version - read the firmware bootstrap version
2675  *     @adapter: the adapter
2676  *     @vers: where to place the version
2677  *
2678  *     Reads the FW Bootstrap version from flash.
2679  */
2680 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2681 {
2682         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2683                              offsetof(struct fw_hdr, fw_ver), 1,
2684                              vers, 0);
2685 }
2686
2687 /**
2688  * t4_get_tp_version - read the TP microcode version
2689  * @adapter: the adapter
2690  * @vers: where to place the version
2691  *
2692  * Reads the TP microcode version from flash.
2693  */
2694 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2695 {
2696         return t4_read_flash(adapter, FLASH_FW_START +
2697                              offsetof(struct fw_hdr, tp_microcode_ver),
2698                              1, vers, 0);
2699 }
2700
2701 /**
2702  * t4_get_version_info - extract various chip/firmware version information
2703  * @adapter: the adapter
2704  *
2705  * Reads various chip/firmware version numbers and stores them into the
2706  * adapter Adapter Parameters structure.  If any of the efforts fails
2707  * the first failure will be returned, but all of the version numbers
2708  * will be read.
2709  */
2710 int t4_get_version_info(struct adapter *adapter)
2711 {
2712         int ret = 0;
2713
2714 #define FIRST_RET(__getvinfo) \
2715         do { \
2716                 int __ret = __getvinfo; \
2717                 if (__ret && !ret) \
2718                         ret = __ret; \
2719         } while (0)
2720
2721         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2722         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2723         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2724         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2725
2726 #undef FIRST_RET
2727
2728         return ret;
2729 }
2730
2731 /**
2732  * t4_dump_version_info - dump all of the adapter configuration IDs
2733  * @adapter: the adapter
2734  *
2735  * Dumps all of the various bits of adapter configuration version/revision
2736  * IDs information.  This is typically called at some point after
2737  * t4_get_version_info() has been called.
2738  */
2739 void t4_dump_version_info(struct adapter *adapter)
2740 {
2741         /**
2742          * Device information.
2743          */
2744         dev_info(adapter, "Chelsio rev %d\n",
2745                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
2746
2747         /**
2748          * Firmware Version.
2749          */
2750         if (!adapter->params.fw_vers)
2751                 dev_warn(adapter, "No firmware loaded\n");
2752         else
2753                 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2754                          G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2755                          G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2756                          G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2757                          G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2758
2759         /**
2760          * Bootstrap Firmware Version.
2761          */
2762         if (!adapter->params.bs_vers)
2763                 dev_warn(adapter, "No bootstrap loaded\n");
2764         else
2765                 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2766                          G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2767                          G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2768                          G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2769                          G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2770
2771         /**
2772          * TP Microcode Version.
2773          */
2774         if (!adapter->params.tp_vers)
2775                 dev_warn(adapter, "No TP Microcode loaded\n");
2776         else
2777                 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2778                          G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2779                          G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2780                          G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2781                          G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2782
2783         /**
2784          * Expansion ROM version.
2785          */
2786         if (!adapter->params.er_vers)
2787                 dev_info(adapter, "No Expansion ROM loaded\n");
2788         else
2789                 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2790                          G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2791                          G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2792                          G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2793                          G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2794 }
2795
2796 #define ADVERT_MASK (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) | \
2797                      FW_PORT_CAP32_ANEG)
2798 /**
2799  *     fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
2800  *     @caps16: a 16-bit Port Capabilities value
2801  *
2802  *     Returns the equivalent 32-bit Port Capabilities value.
2803  */
2804 fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
2805 {
2806         fw_port_cap32_t caps32 = 0;
2807
2808 #define CAP16_TO_CAP32(__cap) \
2809         do { \
2810                 if (caps16 & FW_PORT_CAP_##__cap) \
2811                         caps32 |= FW_PORT_CAP32_##__cap; \
2812         } while (0)
2813
2814         CAP16_TO_CAP32(SPEED_100M);
2815         CAP16_TO_CAP32(SPEED_1G);
2816         CAP16_TO_CAP32(SPEED_25G);
2817         CAP16_TO_CAP32(SPEED_10G);
2818         CAP16_TO_CAP32(SPEED_40G);
2819         CAP16_TO_CAP32(SPEED_100G);
2820         CAP16_TO_CAP32(FC_RX);
2821         CAP16_TO_CAP32(FC_TX);
2822         CAP16_TO_CAP32(ANEG);
2823         CAP16_TO_CAP32(MDIX);
2824         CAP16_TO_CAP32(MDIAUTO);
2825         CAP16_TO_CAP32(FEC_RS);
2826         CAP16_TO_CAP32(FEC_BASER_RS);
2827         CAP16_TO_CAP32(802_3_PAUSE);
2828         CAP16_TO_CAP32(802_3_ASM_DIR);
2829
2830 #undef CAP16_TO_CAP32
2831
2832         return caps32;
2833 }
2834
2835 /**
2836  *     fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
2837  *     @caps32: a 32-bit Port Capabilities value
2838  *
2839  *     Returns the equivalent 16-bit Port Capabilities value.  Note that
2840  *     not all 32-bit Port Capabilities can be represented in the 16-bit
2841  *     Port Capabilities and some fields/values may not make it.
2842  */
2843 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
2844 {
2845         fw_port_cap16_t caps16 = 0;
2846
2847 #define CAP32_TO_CAP16(__cap) \
2848         do { \
2849                 if (caps32 & FW_PORT_CAP32_##__cap) \
2850                         caps16 |= FW_PORT_CAP_##__cap; \
2851         } while (0)
2852
2853         CAP32_TO_CAP16(SPEED_100M);
2854         CAP32_TO_CAP16(SPEED_1G);
2855         CAP32_TO_CAP16(SPEED_10G);
2856         CAP32_TO_CAP16(SPEED_25G);
2857         CAP32_TO_CAP16(SPEED_40G);
2858         CAP32_TO_CAP16(SPEED_100G);
2859         CAP32_TO_CAP16(FC_RX);
2860         CAP32_TO_CAP16(FC_TX);
2861         CAP32_TO_CAP16(802_3_PAUSE);
2862         CAP32_TO_CAP16(802_3_ASM_DIR);
2863         CAP32_TO_CAP16(ANEG);
2864         CAP32_TO_CAP16(MDIX);
2865         CAP32_TO_CAP16(MDIAUTO);
2866         CAP32_TO_CAP16(FEC_RS);
2867         CAP32_TO_CAP16(FEC_BASER_RS);
2868
2869 #undef CAP32_TO_CAP16
2870
2871         return caps16;
2872 }
2873
2874 /* Translate Firmware Pause specification to Common Code */
2875 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
2876 {
2877         enum cc_pause cc_pause = 0;
2878
2879         if (fw_pause & FW_PORT_CAP32_FC_RX)
2880                 cc_pause |= PAUSE_RX;
2881         if (fw_pause & FW_PORT_CAP32_FC_TX)
2882                 cc_pause |= PAUSE_TX;
2883
2884         return cc_pause;
2885 }
2886
2887 /* Translate Common Code Pause Frame specification into Firmware */
2888 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
2889 {
2890         fw_port_cap32_t fw_pause = 0;
2891
2892         if (cc_pause & PAUSE_RX)
2893                 fw_pause |= FW_PORT_CAP32_FC_RX;
2894         if (cc_pause & PAUSE_TX)
2895                 fw_pause |= FW_PORT_CAP32_FC_TX;
2896
2897         return fw_pause;
2898 }
2899
2900 /* Translate Firmware Forward Error Correction specification to Common Code */
2901 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
2902 {
2903         enum cc_fec cc_fec = 0;
2904
2905         if (fw_fec & FW_PORT_CAP32_FEC_RS)
2906                 cc_fec |= FEC_RS;
2907         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
2908                 cc_fec |= FEC_BASER_RS;
2909
2910         return cc_fec;
2911 }
2912
2913 /* Translate Common Code Forward Error Correction specification to Firmware */
2914 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
2915 {
2916         fw_port_cap32_t fw_fec = 0;
2917
2918         if (cc_fec & FEC_RS)
2919                 fw_fec |= FW_PORT_CAP32_FEC_RS;
2920         if (cc_fec & FEC_BASER_RS)
2921                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
2922
2923         return fw_fec;
2924 }
2925
2926 /**
2927  * t4_link_l1cfg - apply link configuration to MAC/PHY
2928  * @adapter: the adapter
2929  * @mbox: the Firmware Mailbox to use
2930  * @port: the Port ID
2931  * @lc: the Port's Link Configuration
2932  *
2933  * Set up a port's MAC and PHY according to a desired link configuration.
2934  * - If the PHY can auto-negotiate first decide what to advertise, then
2935  *   enable/disable auto-negotiation as desired, and reset.
2936  * - If the PHY does not auto-negotiate just reset it.
2937  * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2938  *   otherwise do it later based on the outcome of auto-negotiation.
2939  */
2940 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2941                   struct link_config *lc)
2942 {
2943         unsigned int fw_mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
2944         unsigned int fw_caps = adap->params.fw_caps_support;
2945         fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
2946         struct fw_port_cmd cmd;
2947
2948         lc->link_ok = 0;
2949
2950         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
2951
2952         /* Convert Common Code Forward Error Control settings into the
2953          * Firmware's API.  If the current Requested FEC has "Automatic"
2954          * (IEEE 802.3) specified, then we use whatever the Firmware
2955          * sent us as part of it's IEEE 802.3-based interpratation of
2956          * the Transceiver Module EPROM FEC parameters.  Otherwise we
2957          * use whatever is in the current Requested FEC settings.
2958          */
2959         if (lc->requested_fec & FEC_AUTO)
2960                 cc_fec = lc->auto_fec;
2961         else
2962                 cc_fec = lc->requested_fec;
2963         fw_fec = cc_to_fwcap_fec(cc_fec);
2964
2965         /* Figure out what our Requested Port Capabilities are going to be.
2966          */
2967         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
2968                 rcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
2969                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2970                 lc->fec = cc_fec;
2971         } else if (lc->autoneg == AUTONEG_DISABLE) {
2972                 rcap = lc->requested_speed | fw_fc | fw_fec | fw_mdi;
2973                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2974                 lc->fec = cc_fec;
2975         } else {
2976                 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
2977         }
2978
2979         /* And send that on to the Firmware ...
2980          */
2981         memset(&cmd, 0, sizeof(cmd));
2982         cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2983                                        F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2984                                        V_FW_PORT_CMD_PORTID(port));
2985         cmd.action_to_len16 =
2986                 cpu_to_be32(V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16 ?
2987                                                  FW_PORT_ACTION_L1_CFG :
2988                                                  FW_PORT_ACTION_L1_CFG32) |
2989                             FW_LEN16(cmd));
2990
2991         if (fw_caps == FW_CAPS16)
2992                 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
2993         else
2994                 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
2995
2996         return t4_wr_mbox(adap, mbox, &cmd, sizeof(cmd), NULL);
2997 }
2998
2999 /**
3000  * t4_flash_cfg_addr - return the address of the flash configuration file
3001  * @adapter: the adapter
3002  *
3003  * Return the address within the flash where the Firmware Configuration
3004  * File is stored, or an error if the device FLASH is too small to contain
3005  * a Firmware Configuration File.
3006  */
3007 int t4_flash_cfg_addr(struct adapter *adapter)
3008 {
3009         /*
3010          * If the device FLASH isn't large enough to hold a Firmware
3011          * Configuration File, return an error.
3012          */
3013         if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3014                 return -ENOSPC;
3015
3016         return FLASH_CFG_START;
3017 }
3018
3019 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
3020
3021 /**
3022  * t4_intr_enable - enable interrupts
3023  * @adapter: the adapter whose interrupts should be enabled
3024  *
3025  * Enable PF-specific interrupts for the calling function and the top-level
3026  * interrupt concentrator for global interrupts.  Interrupts are already
3027  * enabled at each module, here we just enable the roots of the interrupt
3028  * hierarchies.
3029  *
3030  * Note: this function should be called only when the driver manages
3031  * non PF-specific interrupts from the various HW modules.  Only one PCI
3032  * function at a time should be doing this.
3033  */
3034 void t4_intr_enable(struct adapter *adapter)
3035 {
3036         u32 val = 0;
3037         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3038         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
3039                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
3040
3041         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3042                 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
3043         t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
3044                      F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
3045                      F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
3046                      F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
3047                      F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
3048                      F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
3049                      F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
3050         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
3051         t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
3052 }
3053
3054 /**
3055  * t4_intr_disable - disable interrupts
3056  * @adapter: the adapter whose interrupts should be disabled
3057  *
3058  * Disable interrupts.  We only disable the top-level interrupt
3059  * concentrators.  The caller must be a PCI function managing global
3060  * interrupts.
3061  */
3062 void t4_intr_disable(struct adapter *adapter)
3063 {
3064         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3065         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
3066                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
3067
3068         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
3069         t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
3070 }
3071
3072 /**
3073  * t4_get_port_type_description - return Port Type string description
3074  * @port_type: firmware Port Type enumeration
3075  */
3076 const char *t4_get_port_type_description(enum fw_port_type port_type)
3077 {
3078         static const char * const port_type_description[] = {
3079                 "Fiber_XFI",
3080                 "Fiber_XAUI",
3081                 "BT_SGMII",
3082                 "BT_XFI",
3083                 "BT_XAUI",
3084                 "KX4",
3085                 "CX4",
3086                 "KX",
3087                 "KR",
3088                 "SFP",
3089                 "BP_AP",
3090                 "BP4_AP",
3091                 "QSFP_10G",
3092                 "QSA",
3093                 "QSFP",
3094                 "BP40_BA",
3095                 "KR4_100G",
3096                 "CR4_QSFP",
3097                 "CR_QSFP",
3098                 "CR2_QSFP",
3099                 "SFP28",
3100                 "KR_SFP28",
3101         };
3102
3103         if (port_type < ARRAY_SIZE(port_type_description))
3104                 return port_type_description[port_type];
3105         return "UNKNOWN";
3106 }
3107
3108 /**
3109  * t4_get_mps_bg_map - return the buffer groups associated with a port
3110  * @adap: the adapter
3111  * @pidx: the port index
3112  *
3113  * Returns a bitmap indicating which MPS buffer groups are associated
3114  * with the given port.  Bit i is set if buffer group i is used by the
3115  * port.
3116  */
3117 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
3118 {
3119         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3120         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
3121                                                           A_MPS_CMN_CTL));
3122
3123         if (pidx >= nports) {
3124                 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
3125                          pidx, nports);
3126                 return 0;
3127         }
3128
3129         switch (chip_version) {
3130         case CHELSIO_T4:
3131         case CHELSIO_T5:
3132                 switch (nports) {
3133                 case 1: return 0xf;
3134                 case 2: return 3 << (2 * pidx);
3135                 case 4: return 1 << pidx;
3136                 }
3137                 break;
3138
3139         case CHELSIO_T6:
3140                 switch (nports) {
3141                 case 2: return 1 << (2 * pidx);
3142                 }
3143                 break;
3144         }
3145
3146         dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
3147                 chip_version, nports);
3148         return 0;
3149 }
3150
3151 /**
3152  * t4_get_tp_ch_map - return TP ingress channels associated with a port
3153  * @adapter: the adapter
3154  * @pidx: the port index
3155  *
3156  * Returns a bitmap indicating which TP Ingress Channels are associated with
3157  * a given Port.  Bit i is set if TP Ingress Channel i is used by the Port.
3158  */
3159 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
3160 {
3161         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
3162         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
3163                                                           A_MPS_CMN_CTL));
3164
3165         if (pidx >= nports) {
3166                 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
3167                          pidx, nports);
3168                 return 0;
3169         }
3170
3171         switch (chip_version) {
3172         case CHELSIO_T4:
3173         case CHELSIO_T5:
3174                 /* Note that this happens to be the same values as the MPS
3175                  * Buffer Group Map for these Chips.  But we replicate the code
3176                  * here because they're really separate concepts.
3177                  */
3178                 switch (nports) {
3179                 case 1: return 0xf;
3180                 case 2: return 3 << (2 * pidx);
3181                 case 4: return 1 << pidx;
3182                 }
3183                 break;
3184
3185         case CHELSIO_T6:
3186                 switch (nports) {
3187                 case 2: return 1 << pidx;
3188                 }
3189                 break;
3190         }
3191
3192         dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
3193                 chip_version, nports);
3194         return 0;
3195 }
3196
3197 /**
3198  * t4_get_port_stats - collect port statistics
3199  * @adap: the adapter
3200  * @idx: the port index
3201  * @p: the stats structure to fill
3202  *
3203  * Collect statistics related to the given port from HW.
3204  */
3205 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
3206 {
3207         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3208         u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
3209
3210 #define GET_STAT(name) \
3211         t4_read_reg64(adap, \
3212                       (is_t4(adap->params.chip) ? \
3213                        PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
3214                        T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
3215 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
3216
3217         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
3218         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
3219         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
3220         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
3221         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
3222         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
3223         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
3224         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
3225         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
3226         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
3227         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
3228         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
3229         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
3230         p->tx_drop             = GET_STAT(TX_PORT_DROP);
3231         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
3232         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
3233         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
3234         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
3235         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
3236         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
3237         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
3238         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
3239         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
3240
3241         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3242                 if (stat_ctl & F_COUNTPAUSESTATTX) {
3243                         p->tx_frames -= p->tx_pause;
3244                         p->tx_octets -= p->tx_pause * 64;
3245                 }
3246                 if (stat_ctl & F_COUNTPAUSEMCTX)
3247                         p->tx_mcast_frames -= p->tx_pause;
3248         }
3249
3250         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
3251         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
3252         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
3253         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
3254         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
3255         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
3256         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
3257         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
3258         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
3259         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
3260         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
3261         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
3262         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
3263         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
3264         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
3265         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
3266         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3267         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
3268         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
3269         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
3270         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
3271         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
3272         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
3273         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
3274         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
3275         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
3276         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
3277
3278         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3279                 if (stat_ctl & F_COUNTPAUSESTATRX) {
3280                         p->rx_frames -= p->rx_pause;
3281                         p->rx_octets -= p->rx_pause * 64;
3282                 }
3283                 if (stat_ctl & F_COUNTPAUSEMCRX)
3284                         p->rx_mcast_frames -= p->rx_pause;
3285         }
3286
3287         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3288         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3289         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3290         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3291         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3292         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3293         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3294         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3295
3296 #undef GET_STAT
3297 #undef GET_STAT_COM
3298 }
3299
3300 /**
3301  * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3302  * @adap: The adapter
3303  * @idx: The port
3304  * @stats: Current stats to fill
3305  * @offset: Previous stats snapshot
3306  */
3307 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3308                               struct port_stats *stats,
3309                               struct port_stats *offset)
3310 {
3311         u64 *s, *o;
3312         unsigned int i;
3313
3314         t4_get_port_stats(adap, idx, stats);
3315         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3316              i < (sizeof(struct port_stats) / sizeof(u64));
3317              i++, s++, o++)
3318                 *s -= *o;
3319 }
3320
3321 /**
3322  * t4_clr_port_stats - clear port statistics
3323  * @adap: the adapter
3324  * @idx: the port index
3325  *
3326  * Clear HW statistics for the given port.
3327  */
3328 void t4_clr_port_stats(struct adapter *adap, int idx)
3329 {
3330         unsigned int i;
3331         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3332         u32 port_base_addr;
3333
3334         if (is_t4(adap->params.chip))
3335                 port_base_addr = PORT_BASE(idx);
3336         else
3337                 port_base_addr = T5_PORT_BASE(idx);
3338
3339         for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3340              i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3341                 t4_write_reg(adap, port_base_addr + i, 0);
3342         for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3343              i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3344                 t4_write_reg(adap, port_base_addr + i, 0);
3345         for (i = 0; i < 4; i++)
3346                 if (bgmap & (1 << i)) {
3347                         t4_write_reg(adap,
3348                                      A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3349                                      i * 8, 0);
3350                         t4_write_reg(adap,
3351                                      A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3352                                      i * 8, 0);
3353                 }
3354 }
3355
3356 /**
3357  * t4_fw_hello - establish communication with FW
3358  * @adap: the adapter
3359  * @mbox: mailbox to use for the FW command
3360  * @evt_mbox: mailbox to receive async FW events
3361  * @master: specifies the caller's willingness to be the device master
3362  * @state: returns the current device state (if non-NULL)
3363  *
3364  * Issues a command to establish communication with FW.  Returns either
3365  * an error (negative integer) or the mailbox of the Master PF.
3366  */
3367 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3368                 enum dev_master master, enum dev_state *state)
3369 {
3370         int ret;
3371         struct fw_hello_cmd c;
3372         u32 v;
3373         unsigned int master_mbox;
3374         int retries = FW_CMD_HELLO_RETRIES;
3375
3376 retry:
3377         memset(&c, 0, sizeof(c));
3378         INIT_CMD(c, HELLO, WRITE);
3379         c.err_to_clearinit = cpu_to_be32(
3380                         V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3381                         V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3382                         V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3383                                                 M_FW_HELLO_CMD_MBMASTER) |
3384                         V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3385                         V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3386                         F_FW_HELLO_CMD_CLEARINIT);
3387
3388         /*
3389          * Issue the HELLO command to the firmware.  If it's not successful
3390          * but indicates that we got a "busy" or "timeout" condition, retry
3391          * the HELLO until we exhaust our retry limit.  If we do exceed our
3392          * retry limit, check to see if the firmware left us any error
3393          * information and report that if so ...
3394          */
3395         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3396         if (ret != FW_SUCCESS) {
3397                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3398                         goto retry;
3399                 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3400                         t4_report_fw_error(adap);
3401                 return ret;
3402         }
3403
3404         v = be32_to_cpu(c.err_to_clearinit);
3405         master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3406         if (state) {
3407                 if (v & F_FW_HELLO_CMD_ERR)
3408                         *state = DEV_STATE_ERR;
3409                 else if (v & F_FW_HELLO_CMD_INIT)
3410                         *state = DEV_STATE_INIT;
3411                 else
3412                         *state = DEV_STATE_UNINIT;
3413         }
3414
3415         /*
3416          * If we're not the Master PF then we need to wait around for the
3417          * Master PF Driver to finish setting up the adapter.
3418          *
3419          * Note that we also do this wait if we're a non-Master-capable PF and
3420          * there is no current Master PF; a Master PF may show up momentarily
3421          * and we wouldn't want to fail pointlessly.  (This can happen when an
3422          * OS loads lots of different drivers rapidly at the same time).  In
3423          * this case, the Master PF returned by the firmware will be
3424          * M_PCIE_FW_MASTER so the test below will work ...
3425          */
3426         if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3427             master_mbox != mbox) {
3428                 int waiting = FW_CMD_HELLO_TIMEOUT;
3429
3430                 /*
3431                  * Wait for the firmware to either indicate an error or
3432                  * initialized state.  If we see either of these we bail out
3433                  * and report the issue to the caller.  If we exhaust the
3434                  * "hello timeout" and we haven't exhausted our retries, try
3435                  * again.  Otherwise bail with a timeout error.
3436                  */
3437                 for (;;) {
3438                         u32 pcie_fw;
3439
3440                         msleep(50);
3441                         waiting -= 50;
3442
3443                         /*
3444                          * If neither Error nor Initialialized are indicated
3445                          * by the firmware keep waiting till we exaust our
3446                          * timeout ... and then retry if we haven't exhausted
3447                          * our retries ...
3448                          */
3449                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3450                         if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3451                                 if (waiting <= 0) {
3452                                         if (retries-- > 0)
3453                                                 goto retry;
3454
3455                                         return -ETIMEDOUT;
3456                                 }
3457                                 continue;
3458                         }
3459
3460                         /*
3461                          * We either have an Error or Initialized condition
3462                          * report errors preferentially.
3463                          */
3464                         if (state) {
3465                                 if (pcie_fw & F_PCIE_FW_ERR)
3466                                         *state = DEV_STATE_ERR;
3467                                 else if (pcie_fw & F_PCIE_FW_INIT)
3468                                         *state = DEV_STATE_INIT;
3469                         }
3470
3471                         /*
3472                          * If we arrived before a Master PF was selected and
3473                          * there's not a valid Master PF, grab its identity
3474                          * for our caller.
3475                          */
3476                         if (master_mbox == M_PCIE_FW_MASTER &&
3477                             (pcie_fw & F_PCIE_FW_MASTER_VLD))
3478                                 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3479                         break;
3480                 }
3481         }
3482
3483         return master_mbox;
3484 }
3485
3486 /**
3487  * t4_fw_bye - end communication with FW
3488  * @adap: the adapter
3489  * @mbox: mailbox to use for the FW command
3490  *
3491  * Issues a command to terminate communication with FW.
3492  */
3493 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3494 {
3495         struct fw_bye_cmd c;
3496
3497         memset(&c, 0, sizeof(c));
3498         INIT_CMD(c, BYE, WRITE);
3499         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3500 }
3501
3502 /**
3503  * t4_fw_reset - issue a reset to FW
3504  * @adap: the adapter
3505  * @mbox: mailbox to use for the FW command
3506  * @reset: specifies the type of reset to perform
3507  *
3508  * Issues a reset command of the specified type to FW.
3509  */
3510 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3511 {
3512         struct fw_reset_cmd c;
3513
3514         memset(&c, 0, sizeof(c));
3515         INIT_CMD(c, RESET, WRITE);
3516         c.val = cpu_to_be32(reset);
3517         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3518 }
3519
3520 /**
3521  * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3522  * @adap: the adapter
3523  * @mbox: mailbox to use for the FW RESET command (if desired)
3524  * @force: force uP into RESET even if FW RESET command fails
3525  *
3526  * Issues a RESET command to firmware (if desired) with a HALT indication
3527  * and then puts the microprocessor into RESET state.  The RESET command
3528  * will only be issued if a legitimate mailbox is provided (mbox <=
3529  * M_PCIE_FW_MASTER).
3530  *
3531  * This is generally used in order for the host to safely manipulate the
3532  * adapter without fear of conflicting with whatever the firmware might
3533  * be doing.  The only way out of this state is to RESTART the firmware
3534  * ...
3535  */
3536 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3537 {
3538         int ret = 0;
3539
3540         /*
3541          * If a legitimate mailbox is provided, issue a RESET command
3542          * with a HALT indication.
3543          */
3544         if (mbox <= M_PCIE_FW_MASTER) {
3545                 struct fw_reset_cmd c;
3546
3547                 memset(&c, 0, sizeof(c));
3548                 INIT_CMD(c, RESET, WRITE);
3549                 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3550                 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3551                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3552         }
3553
3554         /*
3555          * Normally we won't complete the operation if the firmware RESET
3556          * command fails but if our caller insists we'll go ahead and put the
3557          * uP into RESET.  This can be useful if the firmware is hung or even
3558          * missing ...  We'll have to take the risk of putting the uP into
3559          * RESET without the cooperation of firmware in that case.
3560          *
3561          * We also force the firmware's HALT flag to be on in case we bypassed
3562          * the firmware RESET command above or we're dealing with old firmware
3563          * which doesn't have the HALT capability.  This will serve as a flag
3564          * for the incoming firmware to know that it's coming out of a HALT
3565          * rather than a RESET ... if it's new enough to understand that ...
3566          */
3567         if (ret == 0 || force) {
3568                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3569                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3570                                  F_PCIE_FW_HALT);
3571         }
3572
3573         /*
3574          * And we always return the result of the firmware RESET command
3575          * even when we force the uP into RESET ...
3576          */
3577         return ret;
3578 }
3579
3580 /**
3581  * t4_fw_restart - restart the firmware by taking the uP out of RESET
3582  * @adap: the adapter
3583  * @mbox: mailbox to use for the FW RESET command (if desired)
3584  * @reset: if we want to do a RESET to restart things
3585  *
3586  * Restart firmware previously halted by t4_fw_halt().  On successful
3587  * return the previous PF Master remains as the new PF Master and there
3588  * is no need to issue a new HELLO command, etc.
3589  *
3590  * We do this in two ways:
3591  *
3592  * 1. If we're dealing with newer firmware we'll simply want to take
3593  *    the chip's microprocessor out of RESET.  This will cause the
3594  *    firmware to start up from its start vector.  And then we'll loop
3595  *    until the firmware indicates it's started again (PCIE_FW.HALT
3596  *    reset to 0) or we timeout.
3597  *
3598  * 2. If we're dealing with older firmware then we'll need to RESET
3599  *    the chip since older firmware won't recognize the PCIE_FW.HALT
3600  *    flag and automatically RESET itself on startup.
3601  */
3602 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3603 {
3604         if (reset) {
3605                 /*
3606                  * Since we're directing the RESET instead of the firmware
3607                  * doing it automatically, we need to clear the PCIE_FW.HALT
3608                  * bit.
3609                  */
3610                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3611
3612                 /*
3613                  * If we've been given a valid mailbox, first try to get the
3614                  * firmware to do the RESET.  If that works, great and we can
3615                  * return success.  Otherwise, if we haven't been given a
3616                  * valid mailbox or the RESET command failed, fall back to
3617                  * hitting the chip with a hammer.
3618                  */
3619                 if (mbox <= M_PCIE_FW_MASTER) {
3620                         t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3621                         msleep(100);
3622                         if (t4_fw_reset(adap, mbox,
3623                                         F_PIORST | F_PIORSTMODE) == 0)
3624                                 return 0;
3625                 }
3626
3627                 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3628                 msleep(2000);
3629         } else {
3630                 int ms;
3631
3632                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3633                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3634                         if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3635                                 return FW_SUCCESS;
3636                         msleep(100);
3637                         ms += 100;
3638                 }
3639                 return -ETIMEDOUT;
3640         }
3641         return 0;
3642 }
3643
3644 /**
3645  * t4_fl_pkt_align - return the fl packet alignment
3646  * @adap: the adapter
3647  *
3648  * T4 has a single field to specify the packing and padding boundary.
3649  * T5 onwards has separate fields for this and hence the alignment for
3650  * next packet offset is maximum of these two.
3651  */
3652 int t4_fl_pkt_align(struct adapter *adap)
3653 {
3654         u32 sge_control, sge_control2;
3655         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3656
3657         sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3658
3659         /* T4 uses a single control field to specify both the PCIe Padding and
3660          * Packing Boundary.  T5 introduced the ability to specify these
3661          * separately.  The actual Ingress Packet Data alignment boundary
3662          * within Packed Buffer Mode is the maximum of these two
3663          * specifications.
3664          */
3665         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3666                 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3667         else
3668                 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3669
3670         ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3671
3672         fl_align = ingpadboundary;
3673         if (!is_t4(adap->params.chip)) {
3674                 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3675                 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3676                 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3677                         ingpackboundary = 16;
3678                 else
3679                         ingpackboundary = 1 << (ingpackboundary +
3680                                         X_INGPACKBOUNDARY_SHIFT);
3681
3682                 fl_align = max(ingpadboundary, ingpackboundary);
3683         }
3684         return fl_align;
3685 }
3686
3687 /**
3688  * t4_fixup_host_params_compat - fix up host-dependent parameters
3689  * @adap: the adapter
3690  * @page_size: the host's Base Page Size
3691  * @cache_line_size: the host's Cache Line Size
3692  * @chip_compat: maintain compatibility with designated chip
3693  *
3694  * Various registers in the chip contain values which are dependent on the
3695  * host's Base Page and Cache Line Sizes.  This function will fix all of
3696  * those registers with the appropriate values as passed in ...
3697  *
3698  * @chip_compat is used to limit the set of changes that are made
3699  * to be compatible with the indicated chip release.  This is used by
3700  * drivers to maintain compatibility with chip register settings when
3701  * the drivers haven't [yet] been updated with new chip support.
3702  */
3703 int t4_fixup_host_params_compat(struct adapter *adap,
3704                                 unsigned int page_size,
3705                                 unsigned int cache_line_size,
3706                                 enum chip_type chip_compat)
3707 {
3708         unsigned int page_shift = cxgbe_fls(page_size) - 1;
3709         unsigned int sge_hps = page_shift - 10;
3710         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3711         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3712         unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3713
3714         t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3715                      V_HOSTPAGESIZEPF0(sge_hps) |
3716                      V_HOSTPAGESIZEPF1(sge_hps) |
3717                      V_HOSTPAGESIZEPF2(sge_hps) |
3718                      V_HOSTPAGESIZEPF3(sge_hps) |
3719                      V_HOSTPAGESIZEPF4(sge_hps) |
3720                      V_HOSTPAGESIZEPF5(sge_hps) |
3721                      V_HOSTPAGESIZEPF6(sge_hps) |
3722                      V_HOSTPAGESIZEPF7(sge_hps));
3723
3724         if (is_t4(adap->params.chip) || is_t4(chip_compat))
3725                 t4_set_reg_field(adap, A_SGE_CONTROL,
3726                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3727                                  F_EGRSTATUSPAGESIZE,
3728                                  V_INGPADBOUNDARY(fl_align_log -
3729                                                   X_INGPADBOUNDARY_SHIFT) |
3730                                 V_EGRSTATUSPAGESIZE(stat_len != 64));
3731         else {
3732                 unsigned int pack_align;
3733                 unsigned int ingpad, ingpack;
3734                 unsigned int pcie_cap;
3735
3736                 /*
3737                  * T5 introduced the separation of the Free List Padding and
3738                  * Packing Boundaries.  Thus, we can select a smaller Padding
3739                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
3740                  * Bandwidth, and use a Packing Boundary which is large enough
3741                  * to avoid false sharing between CPUs, etc.
3742                  *
3743                  * For the PCI Link, the smaller the Padding Boundary the
3744                  * better.  For the Memory Controller, a smaller Padding
3745                  * Boundary is better until we cross under the Memory Line
3746                  * Size (the minimum unit of transfer to/from Memory).  If we
3747                  * have a Padding Boundary which is smaller than the Memory
3748                  * Line Size, that'll involve a Read-Modify-Write cycle on the
3749                  * Memory Controller which is never good.
3750                  */
3751
3752                 /* We want the Packing Boundary to be based on the Cache Line
3753                  * Size in order to help avoid False Sharing performance
3754                  * issues between CPUs, etc.  We also want the Packing
3755                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
3756                  * get best performance when the Packing Boundary is a
3757                  * multiple of the Maximum Payload Size.
3758                  */
3759                 pack_align = fl_align;
3760                 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3761                 if (pcie_cap) {
3762                         unsigned int mps, mps_log;
3763                         u16 devctl;
3764
3765                         /* The PCIe Device Control Maximum Payload Size field
3766                          * [bits 7:5] encodes sizes as powers of 2 starting at
3767                          * 128 bytes.
3768                          */
3769                         t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3770                                             &devctl);
3771                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3772                         mps = 1 << mps_log;
3773                         if (mps > pack_align)
3774                                 pack_align = mps;
3775                 }
3776
3777                 /*
3778                  * N.B. T5 has a different interpretation of the "0" value for
3779                  * the Packing Boundary.  This corresponds to 16 bytes instead
3780                  * of the expected 32 bytes.  We never have a Packing Boundary
3781                  * less than 32 bytes so we can't use that special value but
3782                  * on the other hand, if we wanted 32 bytes, the best we can
3783                  * really do is 64 bytes ...
3784                  */
3785                 if (pack_align <= 16) {
3786                         ingpack = X_INGPACKBOUNDARY_16B;
3787                         fl_align = 16;
3788                 } else if (pack_align == 32) {
3789                         ingpack = X_INGPACKBOUNDARY_64B;
3790                         fl_align = 64;
3791                 } else {
3792                         unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3793
3794                         ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3795                         fl_align = pack_align;
3796                 }
3797
3798                 /* Use the smallest Ingress Padding which isn't smaller than
3799                  * the Memory Controller Read/Write Size.  We'll take that as
3800                  * being 8 bytes since we don't know of any system with a
3801                  * wider Memory Controller Bus Width.
3802                  */
3803                 if (is_t5(adap->params.chip))
3804                         ingpad = X_INGPADBOUNDARY_32B;
3805                 else
3806                         ingpad = X_T6_INGPADBOUNDARY_8B;
3807                 t4_set_reg_field(adap, A_SGE_CONTROL,
3808                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3809                                  F_EGRSTATUSPAGESIZE,
3810                                  V_INGPADBOUNDARY(ingpad) |
3811                                  V_EGRSTATUSPAGESIZE(stat_len != 64));
3812                 t4_set_reg_field(adap, A_SGE_CONTROL2,
3813                                  V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3814                                  V_INGPACKBOUNDARY(ingpack));
3815         }
3816
3817         /*
3818          * Adjust various SGE Free List Host Buffer Sizes.
3819          *
3820          * The first four entries are:
3821          *
3822          *   0: Host Page Size
3823          *   1: 64KB
3824          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3825          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3826          *
3827          * For the single-MTU buffers in unpacked mode we need to include
3828          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3829          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3830          * Padding boundary.  All of these are accommodated in the Factory
3831          * Default Firmware Configuration File but we need to adjust it for
3832          * this host's cache line size.
3833          */
3834         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3835         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3836                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3837                      & ~(fl_align - 1));
3838         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3839                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3840                      & ~(fl_align - 1));
3841
3842         t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3843
3844         return 0;
3845 }
3846
3847 /**
3848  * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3849  * @adap: the adapter
3850  * @page_size: the host's Base Page Size
3851  * @cache_line_size: the host's Cache Line Size
3852  *
3853  * Various registers in T4 contain values which are dependent on the
3854  * host's Base Page and Cache Line Sizes.  This function will fix all of
3855  * those registers with the appropriate values as passed in ...
3856  *
3857  * This routine makes changes which are compatible with T4 chips.
3858  */
3859 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3860                          unsigned int cache_line_size)
3861 {
3862         return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3863                                            T4_LAST_REV);
3864 }
3865
3866 /**
3867  * t4_fw_initialize - ask FW to initialize the device
3868  * @adap: the adapter
3869  * @mbox: mailbox to use for the FW command
3870  *
3871  * Issues a command to FW to partially initialize the device.  This
3872  * performs initialization that generally doesn't depend on user input.
3873  */
3874 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3875 {
3876         struct fw_initialize_cmd c;
3877
3878         memset(&c, 0, sizeof(c));
3879         INIT_CMD(c, INITIALIZE, WRITE);
3880         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3881 }
3882
3883 /**
3884  * t4_query_params_rw - query FW or device parameters
3885  * @adap: the adapter
3886  * @mbox: mailbox to use for the FW command
3887  * @pf: the PF
3888  * @vf: the VF
3889  * @nparams: the number of parameters
3890  * @params: the parameter names
3891  * @val: the parameter values
3892  * @rw: Write and read flag
3893  *
3894  * Reads the value of FW or device parameters.  Up to 7 parameters can be
3895  * queried at once.
3896  */
3897 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3898                               unsigned int pf, unsigned int vf,
3899                               unsigned int nparams, const u32 *params,
3900                               u32 *val, int rw)
3901 {
3902         unsigned int i;
3903         int ret;
3904         struct fw_params_cmd c;
3905         __be32 *p = &c.param[0].mnem;
3906
3907         if (nparams > 7)
3908                 return -EINVAL;
3909
3910         memset(&c, 0, sizeof(c));
3911         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3912                                   F_FW_CMD_REQUEST | F_FW_CMD_READ |
3913                                   V_FW_PARAMS_CMD_PFN(pf) |
3914                                   V_FW_PARAMS_CMD_VFN(vf));
3915         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3916
3917         for (i = 0; i < nparams; i++) {
3918                 *p++ = cpu_to_be32(*params++);
3919                 if (rw)
3920                         *p = cpu_to_be32(*(val + i));
3921                 p++;
3922         }
3923
3924         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3925         if (ret == 0)
3926                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3927                         *val++ = be32_to_cpu(*p);
3928         return ret;
3929 }
3930
3931 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3932                     unsigned int vf, unsigned int nparams, const u32 *params,
3933                     u32 *val)
3934 {
3935         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3936 }
3937
3938 /**
3939  * t4_set_params_timeout - sets FW or device parameters
3940  * @adap: the adapter
3941  * @mbox: mailbox to use for the FW command
3942  * @pf: the PF
3943  * @vf: the VF
3944  * @nparams: the number of parameters
3945  * @params: the parameter names
3946  * @val: the parameter values
3947  * @timeout: the timeout time
3948  *
3949  * Sets the value of FW or device parameters.  Up to 7 parameters can be
3950  * specified at once.
3951  */
3952 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3953                           unsigned int pf, unsigned int vf,
3954                           unsigned int nparams, const u32 *params,
3955                           const u32 *val, int timeout)
3956 {
3957         struct fw_params_cmd c;
3958         __be32 *p = &c.param[0].mnem;
3959
3960         if (nparams > 7)
3961                 return -EINVAL;
3962
3963         memset(&c, 0, sizeof(c));
3964         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3965                                   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3966                                   V_FW_PARAMS_CMD_PFN(pf) |
3967                                   V_FW_PARAMS_CMD_VFN(vf));
3968         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3969
3970         while (nparams--) {
3971                 *p++ = cpu_to_be32(*params++);
3972                 *p++ = cpu_to_be32(*val++);
3973         }
3974
3975         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3976 }
3977
3978 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3979                   unsigned int vf, unsigned int nparams, const u32 *params,
3980                   const u32 *val)
3981 {
3982         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3983                                      FW_CMD_MAX_TIMEOUT);
3984 }
3985
3986 /**
3987  * t4_alloc_vi_func - allocate a virtual interface
3988  * @adap: the adapter
3989  * @mbox: mailbox to use for the FW command
3990  * @port: physical port associated with the VI
3991  * @pf: the PF owning the VI
3992  * @vf: the VF owning the VI
3993  * @nmac: number of MAC addresses needed (1 to 5)
3994  * @mac: the MAC addresses of the VI
3995  * @rss_size: size of RSS table slice associated with this VI
3996  * @portfunc: which Port Application Function MAC Address is desired
3997  * @idstype: Intrusion Detection Type
3998  *
3999  * Allocates a virtual interface for the given physical port.  If @mac is
4000  * not %NULL it contains the MAC addresses of the VI as assigned by FW.
4001  * @mac should be large enough to hold @nmac Ethernet addresses, they are
4002  * stored consecutively so the space needed is @nmac * 6 bytes.
4003  * Returns a negative error number or the non-negative VI id.
4004  */
4005 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
4006                      unsigned int port, unsigned int pf, unsigned int vf,
4007                      unsigned int nmac, u8 *mac, unsigned int *rss_size,
4008                      unsigned int portfunc, unsigned int idstype)
4009 {
4010         int ret;
4011         struct fw_vi_cmd c;
4012
4013         memset(&c, 0, sizeof(c));
4014         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
4015                                   F_FW_CMD_WRITE | F_FW_CMD_EXEC |
4016                                   V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
4017         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
4018         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
4019                                      V_FW_VI_CMD_FUNC(portfunc));
4020         c.portid_pkd = V_FW_VI_CMD_PORTID(port);
4021         c.nmac = nmac - 1;
4022
4023         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4024         if (ret)
4025                 return ret;
4026
4027         if (mac) {
4028                 memcpy(mac, c.mac, sizeof(c.mac));
4029                 switch (nmac) {
4030                 case 5:
4031                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
4032                         /* FALLTHROUGH */
4033                 case 4:
4034                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
4035                         /* FALLTHROUGH */
4036                 case 3:
4037                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
4038                         /* FALLTHROUGH */
4039                 case 2:
4040                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
4041                         /* FALLTHROUGH */
4042                 }
4043         }
4044         if (rss_size)
4045                 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
4046         return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
4047 }
4048
4049 /**
4050  * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
4051  * @adap: the adapter
4052  * @mbox: mailbox to use for the FW command
4053  * @port: physical port associated with the VI
4054  * @pf: the PF owning the VI
4055  * @vf: the VF owning the VI
4056  * @nmac: number of MAC addresses needed (1 to 5)
4057  * @mac: the MAC addresses of the VI
4058  * @rss_size: size of RSS table slice associated with this VI
4059  *
4060  * Backwards compatible and convieniance routine to allocate a Virtual
4061  * Interface with a Ethernet Port Application Function and Intrustion
4062  * Detection System disabled.
4063  */
4064 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
4065                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
4066                 unsigned int *rss_size)
4067 {
4068         return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
4069                                 FW_VI_FUNC_ETH, 0);
4070 }
4071
4072 /**
4073  * t4_free_vi - free a virtual interface
4074  * @adap: the adapter
4075  * @mbox: mailbox to use for the FW command
4076  * @pf: the PF owning the VI
4077  * @vf: the VF owning the VI
4078  * @viid: virtual interface identifiler
4079  *
4080  * Free a previously allocated virtual interface.
4081  */
4082 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
4083                unsigned int vf, unsigned int viid)
4084 {
4085         struct fw_vi_cmd c;
4086
4087         memset(&c, 0, sizeof(c));
4088         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
4089                                   F_FW_CMD_EXEC);
4090         if (is_pf4(adap))
4091                 c.op_to_vfn |= cpu_to_be32(V_FW_VI_CMD_PFN(pf) |
4092                                            V_FW_VI_CMD_VFN(vf));
4093         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
4094         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
4095
4096         if (is_pf4(adap))
4097                 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4098         else
4099                 return t4vf_wr_mbox(adap, &c, sizeof(c), NULL);
4100 }
4101
4102 /**
4103  * t4_set_rxmode - set Rx properties of a virtual interface
4104  * @adap: the adapter
4105  * @mbox: mailbox to use for the FW command
4106  * @viid: the VI id
4107  * @mtu: the new MTU or -1
4108  * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
4109  * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
4110  * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
4111  * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
4112  *          -1 no change
4113  * @sleep_ok: if true we may sleep while awaiting command completion
4114  *
4115  * Sets Rx properties of a virtual interface.
4116  */
4117 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
4118                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
4119                   bool sleep_ok)
4120 {
4121         struct fw_vi_rxmode_cmd c;
4122
4123         /* convert to FW values */
4124         if (mtu < 0)
4125                 mtu = M_FW_VI_RXMODE_CMD_MTU;
4126         if (promisc < 0)
4127                 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
4128         if (all_multi < 0)
4129                 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
4130         if (bcast < 0)
4131                 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
4132         if (vlanex < 0)
4133                 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
4134
4135         memset(&c, 0, sizeof(c));
4136         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
4137                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4138                                    V_FW_VI_RXMODE_CMD_VIID(viid));
4139         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4140         c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
4141                             V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
4142                             V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
4143                             V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
4144                             V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
4145         if (is_pf4(adap))
4146                 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL,
4147                                        sleep_ok);
4148         else
4149                 return t4vf_wr_mbox(adap, &c, sizeof(c), NULL);
4150 }
4151
4152 /**
4153  * t4_change_mac - modifies the exact-match filter for a MAC address
4154  * @adap: the adapter
4155  * @mbox: mailbox to use for the FW command
4156  * @viid: the VI id
4157  * @idx: index of existing filter for old value of MAC address, or -1
4158  * @addr: the new MAC address value
4159  * @persist: whether a new MAC allocation should be persistent
4160  * @add_smt: if true also add the address to the HW SMT
4161  *
4162  * Modifies an exact-match filter and sets it to the new MAC address if
4163  * @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
4164  * latter case the address is added persistently if @persist is %true.
4165  *
4166  * Note that in general it is not possible to modify the value of a given
4167  * filter so the generic way to modify an address filter is to free the one
4168  * being used by the old address value and allocate a new filter for the
4169  * new address value.
4170  *
4171  * Returns a negative error number or the index of the filter with the new
4172  * MAC value.  Note that this index may differ from @idx.
4173  */
4174 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
4175                   int idx, const u8 *addr, bool persist, bool add_smt)
4176 {
4177         int ret, mode;
4178         struct fw_vi_mac_cmd c;
4179         struct fw_vi_mac_exact *p = c.u.exact;
4180         int max_mac_addr = adap->params.arch.mps_tcam_size;
4181
4182         if (idx < 0)                             /* new allocation */
4183                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
4184         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
4185
4186         memset(&c, 0, sizeof(c));
4187         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
4188                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4189                                    V_FW_VI_MAC_CMD_VIID(viid));
4190         c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
4191         p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
4192                                       V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
4193                                       V_FW_VI_MAC_CMD_IDX(idx));
4194         memcpy(p->macaddr, addr, sizeof(p->macaddr));
4195
4196         if (is_pf4(adap))
4197                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4198         else
4199                 ret = t4vf_wr_mbox(adap, &c, sizeof(c), &c);
4200         if (ret == 0) {
4201                 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
4202                 if (ret >= max_mac_addr)
4203                         ret = -ENOMEM;
4204         }
4205         return ret;
4206 }
4207
4208 /**
4209  * t4_enable_vi_params - enable/disable a virtual interface
4210  * @adap: the adapter
4211  * @mbox: mailbox to use for the FW command
4212  * @viid: the VI id
4213  * @rx_en: 1=enable Rx, 0=disable Rx
4214  * @tx_en: 1=enable Tx, 0=disable Tx
4215  * @dcb_en: 1=enable delivery of Data Center Bridging messages.
4216  *
4217  * Enables/disables a virtual interface.  Note that setting DCB Enable
4218  * only makes sense when enabling a Virtual Interface ...
4219  */
4220 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
4221                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
4222 {
4223         struct fw_vi_enable_cmd c;
4224
4225         memset(&c, 0, sizeof(c));
4226         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
4227                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4228                                    V_FW_VI_ENABLE_CMD_VIID(viid));
4229         c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
4230                                      V_FW_VI_ENABLE_CMD_EEN(tx_en) |
4231                                      V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
4232                                      FW_LEN16(c));
4233         if (is_pf4(adap))
4234                 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
4235         else
4236                 return t4vf_wr_mbox_ns(adap, &c, sizeof(c), NULL);
4237 }
4238
4239 /**
4240  * t4_enable_vi - enable/disable a virtual interface
4241  * @adap: the adapter
4242  * @mbox: mailbox to use for the FW command
4243  * @viid: the VI id
4244  * @rx_en: 1=enable Rx, 0=disable Rx
4245  * @tx_en: 1=enable Tx, 0=disable Tx
4246  *
4247  * Enables/disables a virtual interface.  Note that setting DCB Enable
4248  * only makes sense when enabling a Virtual Interface ...
4249  */
4250 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
4251                  bool rx_en, bool tx_en)
4252 {
4253         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
4254 }
4255
4256 /**
4257  * t4_iq_start_stop - enable/disable an ingress queue and its FLs
4258  * @adap: the adapter
4259  * @mbox: mailbox to use for the FW command
4260  * @start: %true to enable the queues, %false to disable them
4261  * @pf: the PF owning the queues
4262  * @vf: the VF owning the queues
4263  * @iqid: ingress queue id
4264  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4265  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4266  *
4267  * Starts or stops an ingress queue and its associated FLs, if any.
4268  */
4269 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
4270                      unsigned int pf, unsigned int vf, unsigned int iqid,
4271                      unsigned int fl0id, unsigned int fl1id)
4272 {
4273         struct fw_iq_cmd c;
4274
4275         memset(&c, 0, sizeof(c));
4276         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4277                                   F_FW_CMD_EXEC);
4278         c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4279                                        V_FW_IQ_CMD_IQSTOP(!start) |
4280                                        FW_LEN16(c));
4281         c.iqid = cpu_to_be16(iqid);
4282         c.fl0id = cpu_to_be16(fl0id);
4283         c.fl1id = cpu_to_be16(fl1id);
4284         if (is_pf4(adap)) {
4285                 c.op_to_vfn |= cpu_to_be32(V_FW_IQ_CMD_PFN(pf) |
4286                                            V_FW_IQ_CMD_VFN(vf));
4287                 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4288         } else {
4289                 return t4vf_wr_mbox(adap, &c, sizeof(c), NULL);
4290         }
4291 }
4292
4293 /**
4294  * t4_iq_free - free an ingress queue and its FLs
4295  * @adap: the adapter
4296  * @mbox: mailbox to use for the FW command
4297  * @pf: the PF owning the queues
4298  * @vf: the VF owning the queues
4299  * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4300  * @iqid: ingress queue id
4301  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4302  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4303  *
4304  * Frees an ingress queue and its associated FLs, if any.
4305  */
4306 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4307                unsigned int vf, unsigned int iqtype, unsigned int iqid,
4308                unsigned int fl0id, unsigned int fl1id)
4309 {
4310         struct fw_iq_cmd c;
4311
4312         memset(&c, 0, sizeof(c));
4313         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4314                                   F_FW_CMD_EXEC);
4315         if (is_pf4(adap))
4316                 c.op_to_vfn |= cpu_to_be32(V_FW_IQ_CMD_PFN(pf) |
4317                                            V_FW_IQ_CMD_VFN(vf));
4318         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4319         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4320         c.iqid = cpu_to_be16(iqid);
4321         c.fl0id = cpu_to_be16(fl0id);
4322         c.fl1id = cpu_to_be16(fl1id);
4323         if (is_pf4(adap))
4324                 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4325         else
4326                 return t4vf_wr_mbox(adap, &c, sizeof(c), NULL);
4327 }
4328
4329 /**
4330  * t4_eth_eq_free - free an Ethernet egress queue
4331  * @adap: the adapter
4332  * @mbox: mailbox to use for the FW command
4333  * @pf: the PF owning the queue
4334  * @vf: the VF owning the queue
4335  * @eqid: egress queue id
4336  *
4337  * Frees an Ethernet egress queue.
4338  */
4339 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4340                    unsigned int vf, unsigned int eqid)
4341 {
4342         struct fw_eq_eth_cmd c;
4343
4344         memset(&c, 0, sizeof(c));
4345         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4346                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC);
4347         if (is_pf4(adap))
4348                 c.op_to_vfn |= cpu_to_be32(V_FW_IQ_CMD_PFN(pf) |
4349                                            V_FW_IQ_CMD_VFN(vf));
4350         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4351         c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4352         if (is_pf4(adap))
4353                 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4354         else
4355                 return t4vf_wr_mbox(adap, &c, sizeof(c), NULL);
4356 }
4357
4358 /**
4359  * t4_link_down_rc_str - return a string for a Link Down Reason Code
4360  * @link_down_rc: Link Down Reason Code
4361  *
4362  * Returns a string representation of the Link Down Reason Code.
4363  */
4364 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
4365 {
4366         static const char * const reason[] = {
4367                 "Link Down",
4368                 "Remote Fault",
4369                 "Auto-negotiation Failure",
4370                 "Reserved",
4371                 "Insufficient Airflow",
4372                 "Unable To Determine Reason",
4373                 "No RX Signal Detected",
4374                 "Reserved",
4375         };
4376
4377         if (link_down_rc >= ARRAY_SIZE(reason))
4378                 return "Bad Reason Code";
4379
4380         return reason[link_down_rc];
4381 }
4382
4383 /* Return the highest speed set in the port capabilities, in Mb/s. */
4384 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
4385 {
4386 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
4387         do { \
4388                 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
4389                         return __speed; \
4390         } while (0)
4391
4392         TEST_SPEED_RETURN(100G, 100000);
4393         TEST_SPEED_RETURN(50G,   50000);
4394         TEST_SPEED_RETURN(40G,   40000);
4395         TEST_SPEED_RETURN(25G,   25000);
4396         TEST_SPEED_RETURN(10G,   10000);
4397         TEST_SPEED_RETURN(1G,     1000);
4398         TEST_SPEED_RETURN(100M,    100);
4399
4400 #undef TEST_SPEED_RETURN
4401
4402         return 0;
4403 }
4404
4405 /**
4406  * t4_handle_get_port_info - process a FW reply message
4407  * @pi: the port info
4408  * @rpl: start of the FW message
4409  *
4410  * Processes a GET_PORT_INFO FW reply message.
4411  */
4412 static void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
4413 {
4414         const struct fw_port_cmd *cmd = (const void *)rpl;
4415         int action = G_FW_PORT_CMD_ACTION(be32_to_cpu(cmd->action_to_len16));
4416         fw_port_cap32_t pcaps, acaps, linkattr;
4417         struct link_config *lc = &pi->link_cfg;
4418         struct adapter *adapter = pi->adapter;
4419         enum fw_port_module_type mod_type;
4420         enum fw_port_type port_type;
4421         unsigned int speed, fc, fec;
4422         int link_ok, linkdnrc;
4423
4424         /* Extract the various fields from the Port Information message.
4425          */
4426         switch (action) {
4427         case FW_PORT_ACTION_GET_PORT_INFO: {
4428                 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
4429
4430                 link_ok = (lstatus & F_FW_PORT_CMD_LSTATUS) != 0;
4431                 linkdnrc = G_FW_PORT_CMD_LINKDNRC(lstatus);
4432                 port_type = G_FW_PORT_CMD_PTYPE(lstatus);
4433                 mod_type = G_FW_PORT_CMD_MODTYPE(lstatus);
4434                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
4435                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
4436
4437                 /* Unfortunately the format of the Link Status in the old
4438                  * 16-bit Port Information message isn't the same as the
4439                  * 16-bit Port Capabilities bitfield used everywhere else ...
4440                  */
4441                 linkattr = 0;
4442                 if (lstatus & F_FW_PORT_CMD_RXPAUSE)
4443                         linkattr |= FW_PORT_CAP32_FC_RX;
4444                 if (lstatus & F_FW_PORT_CMD_TXPAUSE)
4445                         linkattr |= FW_PORT_CAP32_FC_TX;
4446                 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4447                         linkattr |= FW_PORT_CAP32_SPEED_100M;
4448                 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4449                         linkattr |= FW_PORT_CAP32_SPEED_1G;
4450                 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4451                         linkattr |= FW_PORT_CAP32_SPEED_10G;
4452                 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4453                         linkattr |= FW_PORT_CAP32_SPEED_25G;
4454                 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4455                         linkattr |= FW_PORT_CAP32_SPEED_40G;
4456                 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4457                         linkattr |= FW_PORT_CAP32_SPEED_100G;
4458
4459                 break;
4460                 }
4461
4462         case FW_PORT_ACTION_GET_PORT_INFO32: {
4463                 u32 lstatus32 =
4464                         be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
4465
4466                 link_ok = (lstatus32 & F_FW_PORT_CMD_LSTATUS32) != 0;
4467                 linkdnrc = G_FW_PORT_CMD_LINKDNRC32(lstatus32);
4468                 port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);
4469                 mod_type = G_FW_PORT_CMD_MODTYPE32(lstatus32);
4470                 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
4471                 acaps = be32_to_cpu(cmd->u.info32.acaps32);
4472                 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
4473                 break;
4474                 }
4475
4476         default:
4477                 dev_warn(adapter, "Handle Port Information: Bad Command/Action %#x\n",
4478                          be32_to_cpu(cmd->action_to_len16));
4479                 return;
4480         }
4481
4482         fec = fwcap_to_cc_fec(acaps);
4483
4484         fc = fwcap_to_cc_pause(linkattr);
4485         speed = fwcap_to_speed(linkattr);
4486
4487         if (mod_type != pi->mod_type) {
4488                 lc->auto_fec = fec;
4489                 pi->port_type = port_type;
4490                 pi->mod_type = mod_type;
4491                 t4_os_portmod_changed(adapter, pi->pidx);
4492         }
4493         if (link_ok != lc->link_ok || speed != lc->speed ||
4494             fc != lc->fc || fec != lc->fec) { /* something changed */
4495                 if (!link_ok && lc->link_ok) {
4496                         lc->link_down_rc = linkdnrc;
4497                         dev_warn(adap, "Port %d link down, reason: %s\n",
4498                                  pi->tx_chan, t4_link_down_rc_str(linkdnrc));
4499                 }
4500                 lc->link_ok = link_ok;
4501                 lc->speed = speed;
4502                 lc->fc = fc;
4503                 lc->fec = fec;
4504                 lc->pcaps = pcaps;
4505                 lc->acaps = acaps & ADVERT_MASK;
4506
4507                 if (lc->acaps & FW_PORT_CAP32_ANEG) {
4508                         lc->autoneg = AUTONEG_ENABLE;
4509                 } else {
4510                         /* When Autoneg is disabled, user needs to set
4511                          * single speed.
4512                          * Similar to cxgb4_ethtool.c: set_link_ksettings
4513                          */
4514                         lc->acaps = 0;
4515                         lc->requested_speed = fwcap_to_speed(acaps);
4516                         lc->autoneg = AUTONEG_DISABLE;
4517                 }
4518         }
4519 }
4520
4521 /**
4522  * t4_handle_fw_rpl - process a FW reply message
4523  * @adap: the adapter
4524  * @rpl: start of the FW message
4525  *
4526  * Processes a FW message, such as link state change messages.
4527  */
4528 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4529 {
4530         u8 opcode = *(const u8 *)rpl;
4531
4532         /*
4533          * This might be a port command ... this simplifies the following
4534          * conditionals ...  We can get away with pre-dereferencing
4535          * action_to_len16 because it's in the first 16 bytes and all messages
4536          * will be at least that long.
4537          */
4538         const struct fw_port_cmd *p = (const void *)rpl;
4539         unsigned int action =
4540                 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4541
4542         if (opcode == FW_PORT_CMD &&
4543             (action == FW_PORT_ACTION_GET_PORT_INFO ||
4544              action == FW_PORT_ACTION_GET_PORT_INFO32)) {
4545                 /* link/module state change message */
4546                 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4547                 struct port_info *pi = NULL;
4548                 int i;
4549
4550                 for_each_port(adap, i) {
4551                         pi = adap2pinfo(adap, i);
4552                         if (pi->tx_chan == chan)
4553                                 break;
4554                 }
4555
4556                 t4_handle_get_port_info(pi, rpl);
4557         } else {
4558                 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4559                 return -EINVAL;
4560         }
4561         return 0;
4562 }
4563
4564 void t4_reset_link_config(struct adapter *adap, int idx)
4565 {
4566         struct port_info *pi = adap2pinfo(adap, idx);
4567         struct link_config *lc = &pi->link_cfg;
4568
4569         lc->link_ok = 0;
4570         lc->requested_speed = 0;
4571         lc->requested_fc = 0;
4572         lc->speed = 0;
4573         lc->fc = 0;
4574 }
4575
4576 /**
4577  * init_link_config - initialize a link's SW state
4578  * @lc: structure holding the link state
4579  * @pcaps: link Port Capabilities
4580  * @acaps: link current Advertised Port Capabilities
4581  *
4582  * Initializes the SW state maintained for each link, including the link's
4583  * capabilities and default speed/flow-control/autonegotiation settings.
4584  */
4585 void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
4586                       fw_port_cap32_t acaps)
4587 {
4588         lc->pcaps = pcaps;
4589         lc->requested_speed = 0;
4590         lc->speed = 0;
4591         lc->requested_fc = 0;
4592         lc->fc = 0;
4593
4594         /**
4595          * For Forward Error Control, we default to whatever the Firmware
4596          * tells us the Link is currently advertising.
4597          */
4598         lc->auto_fec = fwcap_to_cc_fec(acaps);
4599         lc->requested_fec = FEC_AUTO;
4600         lc->fec = lc->auto_fec;
4601
4602         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
4603                 lc->acaps = lc->pcaps & ADVERT_MASK;
4604                 lc->autoneg = AUTONEG_ENABLE;
4605                 lc->requested_fc |= PAUSE_AUTONEG;
4606         } else {
4607                 lc->acaps = 0;
4608                 lc->autoneg = AUTONEG_DISABLE;
4609         }
4610 }
4611
4612 /**
4613  * t4_wait_dev_ready - wait till to reads of registers work
4614  *
4615  * Right after the device is RESET is can take a small amount of time
4616  * for it to respond to register reads.  Until then, all reads will
4617  * return either 0xff...ff or 0xee...ee.  Return an error if reads
4618  * don't work within a reasonable time frame.
4619  */
4620 static int t4_wait_dev_ready(struct adapter *adapter)
4621 {
4622         u32 whoami;
4623
4624         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4625
4626         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4627                 return 0;
4628
4629         msleep(500);
4630         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4631         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4632                 return 0;
4633
4634         dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4635                 whoami);
4636         return -EIO;
4637 }
4638
4639 struct flash_desc {
4640         u32 vendor_and_model_id;
4641         u32 size_mb;
4642 };
4643
4644 int t4_get_flash_params(struct adapter *adapter)
4645 {
4646         /*
4647          * Table for non-Numonix supported flash parts.  Numonix parts are left
4648          * to the preexisting well-tested code.  All flash parts have 64KB
4649          * sectors.
4650          */
4651         static struct flash_desc supported_flash[] = {
4652                 { 0x00150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
4653         };
4654
4655         int ret;
4656         u32 flashid = 0;
4657         unsigned int part, manufacturer;
4658         unsigned int density, size;
4659
4660         /**
4661          * Issue a Read ID Command to the Flash part.  We decode supported
4662          * Flash parts and their sizes from this.  There's a newer Query
4663          * Command which can retrieve detailed geometry information but
4664          * many Flash parts don't support it.
4665          */
4666         ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4667         if (!ret)
4668                 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4669         t4_write_reg(adapter, A_SF_OP, 0);               /* unlock SF */
4670         if (ret < 0)
4671                 return ret;
4672
4673         for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4674                 if (supported_flash[part].vendor_and_model_id == flashid) {
4675                         adapter->params.sf_size =
4676                                 supported_flash[part].size_mb;
4677                         adapter->params.sf_nsec =
4678                                 adapter->params.sf_size / SF_SEC_SIZE;
4679                         goto found;
4680                 }
4681         }
4682
4683         manufacturer = flashid & 0xff;
4684         switch (manufacturer) {
4685         case 0x20: { /* Micron/Numonix */
4686                 /**
4687                  * This Density -> Size decoding table is taken from Micron
4688                  * Data Sheets.
4689                  */
4690                 density = (flashid >> 16) & 0xff;
4691                 switch (density) {
4692                 case 0x14:
4693                         size = 1 << 20; /* 1MB */
4694                         break;
4695                 case 0x15:
4696                         size = 1 << 21; /* 2MB */
4697                         break;
4698                 case 0x16:
4699                         size = 1 << 22; /* 4MB */
4700                         break;
4701                 case 0x17:
4702                         size = 1 << 23; /* 8MB */
4703                         break;
4704                 case 0x18:
4705                         size = 1 << 24; /* 16MB */
4706                         break;
4707                 case 0x19:
4708                         size = 1 << 25; /* 32MB */
4709                         break;
4710                 case 0x20:
4711                         size = 1 << 26; /* 64MB */
4712                         break;
4713                 case 0x21:
4714                         size = 1 << 27; /* 128MB */
4715                         break;
4716                 case 0x22:
4717                         size = 1 << 28; /* 256MB */
4718                         break;
4719                 default:
4720                         dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4721                                 flashid, density);
4722                         return -EINVAL;
4723                 }
4724
4725                 adapter->params.sf_size = size;
4726                 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4727                 break;
4728         }
4729         default:
4730                 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4731                 return -EINVAL;
4732         }
4733
4734 found:
4735         /*
4736          * We should reject adapters with FLASHes which are too small. So, emit
4737          * a warning.
4738          */
4739         if (adapter->params.sf_size < FLASH_MIN_SIZE)
4740                 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4741                          flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4742
4743         return 0;
4744 }
4745
4746 static void set_pcie_completion_timeout(struct adapter *adapter,
4747                                         u8 range)
4748 {
4749         u32 pcie_cap;
4750         u16 val;
4751
4752         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4753         if (pcie_cap) {
4754                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4755                 val &= 0xfff0;
4756                 val |= range;
4757                 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4758         }
4759 }
4760
4761 /**
4762  * t4_get_chip_type - Determine chip type from device ID
4763  * @adap: the adapter
4764  * @ver: adapter version
4765  */
4766 int t4_get_chip_type(struct adapter *adap, int ver)
4767 {
4768         enum chip_type chip = 0;
4769         u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4770
4771         /* Retrieve adapter's device ID */
4772         switch (ver) {
4773         case CHELSIO_T5:
4774                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4775                 break;
4776         case CHELSIO_T6:
4777                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4778                 break;
4779         default:
4780                 dev_err(adap, "Device %d is not supported\n",
4781                         adap->params.pci.device_id);
4782                 return -EINVAL;
4783         }
4784
4785         return chip;
4786 }
4787
4788 /**
4789  * t4_prep_adapter - prepare SW and HW for operation
4790  * @adapter: the adapter
4791  *
4792  * Initialize adapter SW state for the various HW modules, set initial
4793  * values for some adapter tunables, take PHYs out of reset, and
4794  * initialize the MDIO interface.
4795  */
4796 int t4_prep_adapter(struct adapter *adapter)
4797 {
4798         int ret, ver;
4799         u32 pl_rev;
4800
4801         ret = t4_wait_dev_ready(adapter);
4802         if (ret < 0)
4803                 return ret;
4804
4805         pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4806         adapter->params.pci.device_id = adapter->pdev->id.device_id;
4807         adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4808
4809         /*
4810          * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4811          * ADAPTER (VERSION << 4 | REVISION)
4812          */
4813         ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4814         adapter->params.chip = 0;
4815         switch (ver) {
4816         case CHELSIO_T5:
4817                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4818                 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4819                 adapter->params.arch.mps_tcam_size =
4820                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4821                 adapter->params.arch.mps_rplc_size = 128;
4822                 adapter->params.arch.nchan = NCHAN;
4823                 adapter->params.arch.vfcount = 128;
4824                 break;
4825         case CHELSIO_T6:
4826                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4827                 adapter->params.arch.sge_fl_db = 0;
4828                 adapter->params.arch.mps_tcam_size =
4829                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4830                 adapter->params.arch.mps_rplc_size = 256;
4831                 adapter->params.arch.nchan = 2;
4832                 adapter->params.arch.vfcount = 256;
4833                 break;
4834         default:
4835                 dev_err(adapter, "%s: Device %d is not supported\n",
4836                         __func__, adapter->params.pci.device_id);
4837                 return -EINVAL;
4838         }
4839
4840         adapter->params.pci.vpd_cap_addr =
4841                 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4842
4843         ret = t4_get_flash_params(adapter);
4844         if (ret < 0) {
4845                 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4846                         -ret);
4847                 return ret;
4848         }
4849
4850         adapter->params.cim_la_size = CIMLA_SIZE;
4851
4852         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4853
4854         /*
4855          * Default port and clock for debugging in case we can't reach FW.
4856          */
4857         adapter->params.nports = 1;
4858         adapter->params.portvec = 1;
4859         adapter->params.vpd.cclk = 50000;
4860
4861         /* Set pci completion timeout value to 4 seconds. */
4862         set_pcie_completion_timeout(adapter, 0xd);
4863         return 0;
4864 }
4865
4866 /**
4867  * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4868  * @adapter: the adapter
4869  * @qid: the Queue ID
4870  * @qtype: the Ingress or Egress type for @qid
4871  * @pbar2_qoffset: BAR2 Queue Offset
4872  * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4873  *
4874  * Returns the BAR2 SGE Queue Registers information associated with the
4875  * indicated Absolute Queue ID.  These are passed back in return value
4876  * pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4877  * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4878  *
4879  * This may return an error which indicates that BAR2 SGE Queue
4880  * registers aren't available.  If an error is not returned, then the
4881  * following values are returned:
4882  *
4883  *   *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4884  *   *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4885  *
4886  * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4887  * require the "Inferred Queue ID" ability may be used.  E.g. the
4888  * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4889  * then these "Inferred Queue ID" register may not be used.
4890  */
4891 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4892                       enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4893                       unsigned int *pbar2_qid)
4894 {
4895         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4896         u64 bar2_page_offset, bar2_qoffset;
4897         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4898
4899         /*
4900          * T4 doesn't support BAR2 SGE Queue registers.
4901          */
4902         if (is_t4(adapter->params.chip))
4903                 return -EINVAL;
4904
4905         /*
4906          * Get our SGE Page Size parameters.
4907          */
4908         page_shift = adapter->params.sge.hps + 10;
4909         page_size = 1 << page_shift;
4910
4911         /*
4912          * Get the right Queues per Page parameters for our Queue.
4913          */
4914         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4915                               adapter->params.sge.eq_qpp :
4916                               adapter->params.sge.iq_qpp);
4917         qpp_mask = (1 << qpp_shift) - 1;
4918
4919         /*
4920          * Calculate the basics of the BAR2 SGE Queue register area:
4921          *  o The BAR2 page the Queue registers will be in.
4922          *  o The BAR2 Queue ID.
4923          *  o The BAR2 Queue ID Offset into the BAR2 page.
4924          */
4925         bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4926         bar2_qid = qid & qpp_mask;
4927         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4928
4929         /*
4930          * If the BAR2 Queue ID Offset is less than the Page Size, then the
4931          * hardware will infer the Absolute Queue ID simply from the writes to
4932          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4933          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
4934          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4935          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4936          * from the BAR2 Page and BAR2 Queue ID.
4937          *
4938          * One important censequence of this is that some BAR2 SGE registers
4939          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4940          * there.  But other registers synthesize the SGE Queue ID purely
4941          * from the writes to the registers -- the Write Combined Doorbell
4942          * Buffer is a good example.  These BAR2 SGE Registers are only
4943          * available for those BAR2 SGE Register areas where the SGE Absolute
4944          * Queue ID can be inferred from simple writes.
4945          */
4946         bar2_qoffset = bar2_page_offset;
4947         bar2_qinferred = (bar2_qid_offset < page_size);
4948         if (bar2_qinferred) {
4949                 bar2_qoffset += bar2_qid_offset;
4950                 bar2_qid = 0;
4951         }
4952
4953         *pbar2_qoffset = bar2_qoffset;
4954         *pbar2_qid = bar2_qid;
4955         return 0;
4956 }
4957
4958 /**
4959  * t4_init_sge_params - initialize adap->params.sge
4960  * @adapter: the adapter
4961  *
4962  * Initialize various fields of the adapter's SGE Parameters structure.
4963  */
4964 int t4_init_sge_params(struct adapter *adapter)
4965 {
4966         struct sge_params *sge_params = &adapter->params.sge;
4967         u32 hps, qpp;
4968         unsigned int s_hps, s_qpp;
4969
4970         /*
4971          * Extract the SGE Page Size for our PF.
4972          */
4973         hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4974         s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4975                  adapter->pf);
4976         sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4977
4978         /*
4979          * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4980          */
4981         s_qpp = (S_QUEUESPERPAGEPF0 +
4982                  (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4983         qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4984         sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4985         qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4986         sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4987
4988         return 0;
4989 }
4990
4991 /**
4992  * t4_init_tp_params - initialize adap->params.tp
4993  * @adap: the adapter
4994  *
4995  * Initialize various fields of the adapter's TP Parameters structure.
4996  */
4997 int t4_init_tp_params(struct adapter *adap)
4998 {
4999         int chan;
5000         u32 v;
5001
5002         v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
5003         adap->params.tp.tre = G_TIMERRESOLUTION(v);
5004         adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
5005
5006         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
5007         for (chan = 0; chan < NCHAN; chan++)
5008                 adap->params.tp.tx_modq[chan] = chan;
5009
5010         /*
5011          * Cache the adapter's Compressed Filter Mode and global Incress
5012          * Configuration.
5013          */
5014         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5015                          &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
5016         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5017                          &adap->params.tp.ingress_config, 1,
5018                          A_TP_INGRESS_CONFIG);
5019
5020         /* For T6, cache the adapter's compressed error vector
5021          * and passing outer header info for encapsulated packets.
5022          */
5023         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
5024                 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
5025                 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
5026         }
5027
5028         /*
5029          * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
5030          * shift positions of several elements of the Compressed Filter Tuple
5031          * for this adapter which we need frequently ...
5032          */
5033         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
5034         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
5035         adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
5036         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
5037                                                                F_PROTOCOL);
5038
5039         /*
5040          * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
5041          * represents the presense of an Outer VLAN instead of a VNIC ID.
5042          */
5043         if ((adap->params.tp.ingress_config & F_VNIC) == 0)
5044                 adap->params.tp.vnic_shift = -1;
5045
5046         return 0;
5047 }
5048
5049 /**
5050  * t4_filter_field_shift - calculate filter field shift
5051  * @adap: the adapter
5052  * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
5053  *
5054  * Return the shift position of a filter field within the Compressed
5055  * Filter Tuple.  The filter field is specified via its selection bit
5056  * within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
5057  */
5058 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
5059 {
5060         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
5061         unsigned int sel;
5062         int field_shift;
5063
5064         if ((filter_mode & filter_sel) == 0)
5065                 return -1;
5066
5067         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
5068                 switch (filter_mode & sel) {
5069                 case F_FCOE:
5070                         field_shift += W_FT_FCOE;
5071                         break;
5072                 case F_PORT:
5073                         field_shift += W_FT_PORT;
5074                         break;
5075                 case F_VNIC_ID:
5076                         field_shift += W_FT_VNIC_ID;
5077                         break;
5078                 case F_VLAN:
5079                         field_shift += W_FT_VLAN;
5080                         break;
5081                 case F_TOS:
5082                         field_shift += W_FT_TOS;
5083                         break;
5084                 case F_PROTOCOL:
5085                         field_shift += W_FT_PROTOCOL;
5086                         break;
5087                 case F_ETHERTYPE:
5088                         field_shift += W_FT_ETHERTYPE;
5089                         break;
5090                 case F_MACMATCH:
5091                         field_shift += W_FT_MACMATCH;
5092                         break;
5093                 case F_MPSHITTYPE:
5094                         field_shift += W_FT_MPSHITTYPE;
5095                         break;
5096                 case F_FRAGMENTATION:
5097                         field_shift += W_FT_FRAGMENTATION;
5098                         break;
5099                 }
5100         }
5101         return field_shift;
5102 }
5103
5104 int t4_init_rss_mode(struct adapter *adap, int mbox)
5105 {
5106         int i, ret;
5107         struct fw_rss_vi_config_cmd rvc;
5108
5109         memset(&rvc, 0, sizeof(rvc));
5110
5111         for_each_port(adap, i) {
5112                 struct port_info *p = adap2pinfo(adap, i);
5113
5114                 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
5115                                        F_FW_CMD_REQUEST | F_FW_CMD_READ |
5116                                        V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
5117                 rvc.retval_len16 = htonl(FW_LEN16(rvc));
5118                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
5119                 if (ret)
5120                         return ret;
5121                 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
5122         }
5123         return 0;
5124 }
5125
5126 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
5127 {
5128         unsigned int fw_caps = adap->params.fw_caps_support;
5129         fw_port_cap32_t pcaps, acaps;
5130         enum fw_port_type port_type;
5131         struct fw_port_cmd cmd;
5132         int ret, i, j = 0;
5133         int mdio_addr;
5134         u32 action;
5135         u8 addr[6];
5136
5137         memset(&cmd, 0, sizeof(cmd));
5138
5139         for_each_port(adap, i) {
5140                 struct port_info *pi = adap2pinfo(adap, i);
5141                 unsigned int rss_size = 0;
5142
5143                 while ((adap->params.portvec & (1 << j)) == 0)
5144                         j++;
5145
5146                 /* If we haven't yet determined whether we're talking to
5147                  * Firmware which knows the new 32-bit Port Capabilities, it's
5148                  * time to find out now.  This will also tell new Firmware to
5149                  * send us Port Status Updates using the new 32-bit Port
5150                  * Capabilities version of the Port Information message.
5151                  */
5152                 if (fw_caps == FW_CAPS_UNKNOWN) {
5153                         u32 param, val, caps;
5154
5155                         caps = FW_PARAMS_PARAM_PFVF_PORT_CAPS32;
5156                         param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) |
5157                                  V_FW_PARAMS_PARAM_X(caps));
5158                         val = 1;
5159                         ret = t4_set_params(adap, mbox, pf, vf, 1, &param,
5160                                             &val);
5161                         fw_caps = ret == 0 ? FW_CAPS32 : FW_CAPS16;
5162                         adap->params.fw_caps_support = fw_caps;
5163                 }
5164
5165                 memset(&cmd, 0, sizeof(cmd));
5166                 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
5167                                                F_FW_CMD_REQUEST |
5168                                                F_FW_CMD_READ |
5169                                                V_FW_PORT_CMD_PORTID(j));
5170                 action = fw_caps == FW_CAPS16 ? FW_PORT_ACTION_GET_PORT_INFO :
5171                                                 FW_PORT_ACTION_GET_PORT_INFO32;
5172                 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
5173                                                   FW_LEN16(cmd));
5174                 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
5175                 if (ret)
5176                         return ret;
5177
5178                 /* Extract the various fields from the Port Information message.
5179                  */
5180                 if (fw_caps == FW_CAPS16) {
5181                         u32 lstatus =
5182                                 be32_to_cpu(cmd.u.info.lstatus_to_modtype);
5183
5184                         port_type = G_FW_PORT_CMD_PTYPE(lstatus);
5185                         mdio_addr = (lstatus & F_FW_PORT_CMD_MDIOCAP) ?
5186                                     (int)G_FW_PORT_CMD_MDIOADDR(lstatus) : -1;
5187                         pcaps = be16_to_cpu(cmd.u.info.pcap);
5188                         acaps = be16_to_cpu(cmd.u.info.acap);
5189                         pcaps = fwcaps16_to_caps32(pcaps);
5190                         acaps = fwcaps16_to_caps32(acaps);
5191                 } else {
5192                         u32 lstatus32 =
5193                                 be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
5194
5195                         port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);
5196                         mdio_addr = (lstatus32 & F_FW_PORT_CMD_MDIOCAP32) ?
5197                                     (int)G_FW_PORT_CMD_MDIOADDR32(lstatus32) :
5198                                     -1;
5199                         pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
5200                         acaps = be32_to_cpu(cmd.u.info32.acaps32);
5201                 }
5202
5203                 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
5204                 if (ret < 0)
5205                         return ret;
5206
5207                 pi->viid = ret;
5208                 pi->tx_chan = j;
5209                 pi->rss_size = rss_size;
5210                 t4_os_set_hw_addr(adap, i, addr);
5211
5212                 pi->port_type = port_type;
5213                 pi->mdio_addr = mdio_addr;
5214                 pi->mod_type = FW_PORT_MOD_TYPE_NA;
5215
5216                 init_link_config(&pi->link_cfg, pcaps, acaps);
5217                 j++;
5218         }
5219         return 0;
5220 }