drivers/net/cxgbe/base/t4_hw.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <netinet/in.h>
   7
   8 #include <rte_interrupts.h>
   9 #include <rte_log.h>
  10 #include <rte_debug.h>
  11 #include <rte_pci.h>
  12 #include <rte_branch_prediction.h>
  13 #include <rte_memory.h>
  14 #include <rte_tailq.h>
  15 #include <rte_eal.h>
  16 #include <rte_alarm.h>
  17 #include <rte_ether.h>
  18 #include <ethdev_driver.h>
  19 #include <rte_malloc.h>
  20 #include <rte_random.h>
  21 #include <rte_dev.h>
  22 #include <rte_byteorder.h>
  23
  24 #include "common.h"
  25 #include "t4_regs.h"
  26 #include "t4_regs_values.h"
  27 #include "t4fw_interface.h"
  28
  29 /**
  30  * t4_read_mtu_tbl - returns the values in the HW path MTU table
  31  * @adap: the adapter
  32  * @mtus: where to store the MTU values
  33  * @mtu_log: where to store the MTU base-2 log (may be %NULL)
  34  *
  35  * Reads the HW path MTU table.
  36  */
  37 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
  38 {
  39         u32 v;
  40         int i;
  41
  42         for (i = 0; i < NMTUS; ++i) {
  43                 t4_write_reg(adap, A_TP_MTU_TABLE,
  44                              V_MTUINDEX(0xff) | V_MTUVALUE(i));
  45                 v = t4_read_reg(adap, A_TP_MTU_TABLE);
  46                 mtus[i] = G_MTUVALUE(v);
  47                 if (mtu_log)
  48                         mtu_log[i] = G_MTUWIDTH(v);
  49         }
  50 }
  51
  52 /**
  53  * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
  54  * @adap: the adapter
  55  * @addr: the indirect TP register address
  56  * @mask: specifies the field within the register to modify
  57  * @val: new value for the field
  58  *
  59  * Sets a field of an indirect TP register to the given value.
  60  */
  61 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
  62                             unsigned int mask, unsigned int val)
  63 {
  64         t4_write_reg(adap, A_TP_PIO_ADDR, addr);
  65         val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
  66         t4_write_reg(adap, A_TP_PIO_DATA, val);
  67 }
  68
  69 /* The minimum additive increment value for the congestion control table */
  70 #define CC_MIN_INCR 2U
  71
  72 /**
  73  * t4_load_mtus - write the MTU and congestion control HW tables
  74  * @adap: the adapter
  75  * @mtus: the values for the MTU table
  76  * @alpha: the values for the congestion control alpha parameter
  77  * @beta: the values for the congestion control beta parameter
  78  *
  79  * Write the HW MTU table with the supplied MTUs and the high-speed
  80  * congestion control table with the supplied alpha, beta, and MTUs.
  81  * We write the two tables together because the additive increments
  82  * depend on the MTUs.
  83  */
  84 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
  85                   const unsigned short *alpha, const unsigned short *beta)
  86 {
  87         static const unsigned int avg_pkts[NCCTRL_WIN] = {
  88                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
  89                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
  90                 28672, 40960, 57344, 81920, 114688, 163840, 229376
  91         };
  92
  93         unsigned int i, w;
  94
  95         for (i = 0; i < NMTUS; ++i) {
  96                 unsigned int mtu = mtus[i];
  97                 unsigned int log2 = cxgbe_fls(mtu);
  98
  99                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
 100                         log2--;
 101                 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
 102                              V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
 103
 104                 for (w = 0; w < NCCTRL_WIN; ++w) {
 105                         unsigned int inc;
 106
 107                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
 108                                   CC_MIN_INCR);
 109
 110                         t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
 111                                      (w << 16) | (beta[w] << 13) | inc);
 112                 }
 113         }
 114 }
 115
 116 /**
 117  * t4_wait_op_done_val - wait until an operation is completed
 118  * @adapter: the adapter performing the operation
 119  * @reg: the register to check for completion
 120  * @mask: a single-bit field within @reg that indicates completion
 121  * @polarity: the value of the field when the operation is completed
 122  * @attempts: number of check iterations
 123  * @delay: delay in usecs between iterations
 124  * @valp: where to store the value of the register at completion time
 125  *
 126  * Wait until an operation is completed by checking a bit in a register
 127  * up to @attempts times.  If @valp is not NULL the value of the register
 128  * at the time it indicated completion is stored there.  Returns 0 if the
 129  * operation completes and -EAGAIN otherwise.
 130  */
 131 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 132                         int polarity, int attempts, int delay, u32 *valp)
 133 {
 134         while (1) {
 135                 u32 val = t4_read_reg(adapter, reg);
 136
 137                 if (!!(val & mask) == polarity) {
 138                         if (valp)
 139                                 *valp = val;
 140                         return 0;
 141                 }
 142                 if (--attempts == 0)
 143                         return -EAGAIN;
 144                 if (delay)
 145                         udelay(delay);
 146         }
 147 }
 148
 149 /**
 150  * t4_set_reg_field - set a register field to a value
 151  * @adapter: the adapter to program
 152  * @addr: the register address
 153  * @mask: specifies the portion of the register to modify
 154  * @val: the new value for the register field
 155  *
 156  * Sets a register field specified by the supplied mask to the
 157  * given value.
 158  */
 159 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
 160                       u32 val)
 161 {
 162         u32 v = t4_read_reg(adapter, addr) & ~mask;
 163
 164         t4_write_reg(adapter, addr, v | val);
 165         (void)t4_read_reg(adapter, addr);      /* flush */
 166 }
 167
 168 /**
 169  * t4_read_indirect - read indirectly addressed registers
 170  * @adap: the adapter
 171  * @addr_reg: register holding the indirect address
 172  * @data_reg: register holding the value of the indirect register
 173  * @vals: where the read register values are stored
 174  * @nregs: how many indirect registers to read
 175  * @start_idx: index of first indirect register to read
 176  *
 177  * Reads registers that are accessed indirectly through an address/data
 178  * register pair.
 179  */
 180 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 181                       unsigned int data_reg, u32 *vals, unsigned int nregs,
 182                       unsigned int start_idx)
 183 {
 184         while (nregs--) {
 185                 t4_write_reg(adap, addr_reg, start_idx);
 186                 *vals++ = t4_read_reg(adap, data_reg);
 187                 start_idx++;
 188         }
 189 }
 190
 191 /**
 192  * t4_write_indirect - write indirectly addressed registers
 193  * @adap: the adapter
 194  * @addr_reg: register holding the indirect addresses
 195  * @data_reg: register holding the value for the indirect registers
 196  * @vals: values to write
 197  * @nregs: how many indirect registers to write
 198  * @start_idx: address of first indirect register to write
 199  *
 200  * Writes a sequential block of registers that are accessed indirectly
 201  * through an address/data register pair.
 202  */
 203 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 204                        unsigned int data_reg, const u32 *vals,
 205                        unsigned int nregs, unsigned int start_idx)
 206 {
 207         while (nregs--) {
 208                 t4_write_reg(adap, addr_reg, start_idx++);
 209                 t4_write_reg(adap, data_reg, *vals++);
 210         }
 211 }
 212
 213 /**
 214  * t4_report_fw_error - report firmware error
 215  * @adap: the adapter
 216  *
 217  * The adapter firmware can indicate error conditions to the host.
 218  * If the firmware has indicated an error, print out the reason for
 219  * the firmware error.
 220  */
 221 static void t4_report_fw_error(struct adapter *adap)
 222 {
 223         static const char * const reason[] = {
 224                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 225                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 226                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 227                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 228                 "Unexpected Event",     /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 229                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 230                 "Device Shutdown",      /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 231                 "Reserved",                     /* reserved */
 232         };
 233         u32 pcie_fw;
 234
 235         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 236         if (pcie_fw & F_PCIE_FW_ERR)
 237                 pr_err("%s: Firmware reports adapter error: %s\n",
 238                        __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
 239 }
 240
 241 /*
 242  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 243  */
 244 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 245                          u32 mbox_addr)
 246 {
 247         for ( ; nflit; nflit--, mbox_addr += 8)
 248                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 249 }
 250
 251 /*
 252  * Handle a FW assertion reported in a mailbox.
 253  */
 254 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 255 {
 256         struct fw_debug_cmd asrt;
 257
 258         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 259         pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 260                 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 261                 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 262 }
 263
 264 #define X_CIM_PF_NOACCESS 0xeeeeeeee
 265
 266 /*
 267  * If the Host OS Driver needs locking arround accesses to the mailbox, this
 268  * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
 269  */
 270 /* makes single-statement usage a bit cleaner ... */
 271 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 272 #define T4_OS_MBOX_LOCKING(x) x
 273 #else
 274 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
 275 #endif
 276
 277 /**
 278  * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 279  * @adap: the adapter
 280  * @mbox: index of the mailbox to use
 281  * @cmd: the command to write
 282  * @size: command length in bytes
 283  * @rpl: where to optionally store the reply
 284  * @sleep_ok: if true we may sleep while awaiting command completion
 285  * @timeout: time to wait for command to finish before timing out
 286  *           (negative implies @sleep_ok=false)
 287  *
 288  * Sends the given command to FW through the selected mailbox and waits
 289  * for the FW to execute the command.  If @rpl is not %NULL it is used to
 290  * store the FW's reply to the command.  The command and its optional
 291  * reply are of the same length.  Some FW commands like RESET and
 292  * INITIALIZE can take a considerable amount of time to execute.
 293  * @sleep_ok determines whether we may sleep while awaiting the response.
 294  * If sleeping is allowed we use progressive backoff otherwise we spin.
 295  * Note that passing in a negative @timeout is an alternate mechanism
 296  * for specifying @sleep_ok=false.  This is useful when a higher level
 297  * interface allows for specification of @timeout but not @sleep_ok ...
 298  *
 299  * Returns 0 on success or a negative errno on failure.  A
 300  * failure can happen either because we are not able to execute the
 301  * command or FW executes it but signals an error.  In the latter case
 302  * the return value is the error code indicated by FW (negated).
 303  */
 304 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
 305                             const void __attribute__((__may_alias__)) *cmd,
 306                             int size, void *rpl, bool sleep_ok, int timeout)
 307 {
 308         /*
 309          * We delay in small increments at first in an effort to maintain
 310          * responsiveness for simple, fast executing commands but then back
 311          * off to larger delays to a maximum retry delay.
 312          */
 313         static const int delay[] = {
 314                 1, 1, 3, 5, 10, 10, 20, 50, 100
 315         };
 316
 317         u32 v;
 318         u64 res;
 319         int i, ms;
 320         unsigned int delay_idx;
 321         __be64 *temp = (__be64 *)malloc(size * sizeof(char));
 322         __be64 *p = temp;
 323         u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
 324         u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
 325         u32 ctl;
 326         struct mbox_entry entry;
 327         u32 pcie_fw = 0;
 328
 329         if (!temp)
 330                 return -ENOMEM;
 331
 332         if ((size & 15) || size > MBOX_LEN) {
 333                 free(temp);
 334                 return -EINVAL;
 335         }
 336
 337         memset(p, 0, size);
 338         memcpy(p, (const __be64 *)cmd, size);
 339
 340         /*
 341          * If we have a negative timeout, that implies that we can't sleep.
 342          */
 343         if (timeout < 0) {
 344                 sleep_ok = false;
 345                 timeout = -timeout;
 346         }
 347
 348 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 349         /*
 350          * Queue ourselves onto the mailbox access list.  When our entry is at
 351          * the front of the list, we have rights to access the mailbox.  So we
 352          * wait [for a while] till we're at the front [or bail out with an
 353          * EBUSY] ...
 354          */
 355         t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
 356
 357         delay_idx = 0;
 358         ms = delay[0];
 359
 360         for (i = 0; ; i += ms) {
 361                 /*
 362                  * If we've waited too long, return a busy indication.  This
 363                  * really ought to be based on our initial position in the
 364                  * mailbox access list but this is a start.  We very rarely
 365                  * contend on access to the mailbox ...  Also check for a
 366                  * firmware error which we'll report as a device error.
 367                  */
 368                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 369                 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
 370                         t4_os_atomic_list_del(&entry, &adap->mbox_list,
 371                                               &adap->mbox_lock);
 372                         t4_report_fw_error(adap);
 373                         free(temp);
 374                         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
 375                 }
 376
 377                 /*
 378                  * If we're at the head, break out and start the mailbox
 379                  * protocol.
 380                  */
 381                 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
 382                         break;
 383
 384                 /*
 385                  * Delay for a bit before checking again ...
 386                  */
 387                 if (sleep_ok) {
 388                         ms = delay[delay_idx];  /* last element may repeat */
 389                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 390                                 delay_idx++;
 391                         msleep(ms);
 392                 } else {
 393                         rte_delay_ms(ms);
 394                 }
 395         }
 396 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
 397
 398         /*
 399          * Attempt to gain access to the mailbox.
 400          */
 401         for (i = 0; i < 4; i++) {
 402                 ctl = t4_read_reg(adap, ctl_reg);
 403                 v = G_MBOWNER(ctl);
 404                 if (v != X_MBOWNER_NONE)
 405                         break;
 406         }
 407
 408         /*
 409          * If we were unable to gain access, dequeue ourselves from the
 410          * mailbox atomic access list and report the error to our caller.
 411          */
 412         if (v != X_MBOWNER_PL) {
 413                 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 414                                                          &adap->mbox_list,
 415                                                          &adap->mbox_lock));
 416                 t4_report_fw_error(adap);
 417                 free(temp);
 418                 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
 419         }
 420
 421         /*
 422          * If we gain ownership of the mailbox and there's a "valid" message
 423          * in it, this is likely an asynchronous error message from the
 424          * firmware.  So we'll report that and then proceed on with attempting
 425          * to issue our own command ... which may well fail if the error
 426          * presaged the firmware crashing ...
 427          */
 428         if (ctl & F_MBMSGVALID) {
 429                 dev_err(adap, "found VALID command in mbox %u: "
 430                         "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 431                         (unsigned long long)t4_read_reg64(adap, data_reg),
 432                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 433                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 434                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 435                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 436                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 437                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 438                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 439         }
 440
 441         /*
 442          * Copy in the new mailbox command and send it on its way ...
 443          */
 444         for (i = 0; i < size; i += 8, p++)
 445                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
 446
 447         CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
 448                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 449                         (unsigned long long)t4_read_reg64(adap, data_reg),
 450                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 451                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 452                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 453                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 454                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 455                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 456                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 457
 458         t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
 459         t4_read_reg(adap, ctl_reg);          /* flush write */
 460
 461         delay_idx = 0;
 462         ms = delay[0];
 463
 464         /*
 465          * Loop waiting for the reply; bail out if we time out or the firmware
 466          * reports an error.
 467          */
 468         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 469         for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
 470                 if (sleep_ok) {
 471                         ms = delay[delay_idx];  /* last element may repeat */
 472                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 473                                 delay_idx++;
 474                         msleep(ms);
 475                 } else {
 476                         msleep(ms);
 477                 }
 478
 479                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 480                 v = t4_read_reg(adap, ctl_reg);
 481                 if (v == X_CIM_PF_NOACCESS)
 482                         continue;
 483                 if (G_MBOWNER(v) == X_MBOWNER_PL) {
 484                         if (!(v & F_MBMSGVALID)) {
 485                                 t4_write_reg(adap, ctl_reg,
 486                                              V_MBOWNER(X_MBOWNER_NONE));
 487                                 continue;
 488                         }
 489
 490                         CXGBE_DEBUG_MBOX(adap,
 491                         "%s: mbox %u: %016llx %016llx %016llx %016llx "
 492                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 493                         (unsigned long long)t4_read_reg64(adap, data_reg),
 494                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 495                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 496                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 497                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 498                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 499                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 500                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 501
 502                         CXGBE_DEBUG_MBOX(adap,
 503                                 "command %#x completed in %d ms (%ssleeping)\n",
 504                                 *(const u8 *)cmd,
 505                                 i + ms, sleep_ok ? "" : "non-");
 506
 507                         res = t4_read_reg64(adap, data_reg);
 508                         if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
 509                                 fw_asrt(adap, data_reg);
 510                                 res = V_FW_CMD_RETVAL(EIO);
 511                         } else if (rpl) {
 512                                 get_mbox_rpl(adap, rpl, size / 8, data_reg);
 513                         }
 514                         t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
 515                         T4_OS_MBOX_LOCKING(
 516                                 t4_os_atomic_list_del(&entry, &adap->mbox_list,
 517                                                       &adap->mbox_lock));
 518                         free(temp);
 519                         return -G_FW_CMD_RETVAL((int)res);
 520                 }
 521         }
 522
 523         /*
 524          * We timed out waiting for a reply to our mailbox command.  Report
 525          * the error and also check to see if the firmware reported any
 526          * errors ...
 527          */
 528         dev_err(adap, "command %#x in mailbox %d timed out\n",
 529                 *(const u8 *)cmd, mbox);
 530         T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 531                                                  &adap->mbox_list,
 532                                                  &adap->mbox_lock));
 533         t4_report_fw_error(adap);
 534         free(temp);
 535         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
 536 }
 537
 538 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 539                     void *rpl, bool sleep_ok)
 540 {
 541         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 542                                        FW_CMD_MAX_TIMEOUT);
 543 }
 544
 545 /**
 546  * t4_get_regs_len - return the size of the chips register set
 547  * @adapter: the adapter
 548  *
 549  * Returns the size of the chip's BAR0 register space.
 550  */
 551 unsigned int t4_get_regs_len(struct adapter *adapter)
 552 {
 553         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 554
 555         switch (chip_version) {
 556         case CHELSIO_T5:
 557         case CHELSIO_T6:
 558                 return T5_REGMAP_SIZE;
 559         }
 560
 561         dev_err(adapter,
 562                 "Unsupported chip version %d\n", chip_version);
 563         return 0;
 564 }
 565
 566 /**
 567  * t4_get_regs - read chip registers into provided buffer
 568  * @adap: the adapter
 569  * @buf: register buffer
 570  * @buf_size: size (in bytes) of register buffer
 571  *
 572  * If the provided register buffer isn't large enough for the chip's
 573  * full register range, the register dump will be truncated to the
 574  * register buffer's size.
 575  */
 576 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 577 {
 578         static const unsigned int t5_reg_ranges[] = {
 579                 0x1008, 0x10c0,
 580                 0x10cc, 0x10f8,
 581                 0x1100, 0x1100,
 582                 0x110c, 0x1148,
 583                 0x1180, 0x1184,
 584                 0x1190, 0x1194,
 585                 0x11a0, 0x11a4,
 586                 0x11b0, 0x11b4,
 587                 0x11fc, 0x123c,
 588                 0x1280, 0x173c,
 589                 0x1800, 0x18fc,
 590                 0x3000, 0x3028,
 591                 0x3060, 0x30b0,
 592                 0x30b8, 0x30d8,
 593                 0x30e0, 0x30fc,
 594                 0x3140, 0x357c,
 595                 0x35a8, 0x35cc,
 596                 0x35ec, 0x35ec,
 597                 0x3600, 0x5624,
 598                 0x56cc, 0x56ec,
 599                 0x56f4, 0x5720,
 600                 0x5728, 0x575c,
 601                 0x580c, 0x5814,
 602                 0x5890, 0x589c,
 603                 0x58a4, 0x58ac,
 604                 0x58b8, 0x58bc,
 605                 0x5940, 0x59c8,
 606                 0x59d0, 0x59dc,
 607                 0x59fc, 0x5a18,
 608                 0x5a60, 0x5a70,
 609                 0x5a80, 0x5a9c,
 610                 0x5b94, 0x5bfc,
 611                 0x6000, 0x6020,
 612                 0x6028, 0x6040,
 613                 0x6058, 0x609c,
 614                 0x60a8, 0x614c,
 615                 0x7700, 0x7798,
 616                 0x77c0, 0x78fc,
 617                 0x7b00, 0x7b58,
 618                 0x7b60, 0x7b84,
 619                 0x7b8c, 0x7c54,
 620                 0x7d00, 0x7d38,
 621                 0x7d40, 0x7d80,
 622                 0x7d8c, 0x7ddc,
 623                 0x7de4, 0x7e04,
 624                 0x7e10, 0x7e1c,
 625                 0x7e24, 0x7e38,
 626                 0x7e40, 0x7e44,
 627                 0x7e4c, 0x7e78,
 628                 0x7e80, 0x7edc,
 629                 0x7ee8, 0x7efc,
 630                 0x8dc0, 0x8de0,
 631                 0x8df8, 0x8e04,
 632                 0x8e10, 0x8e84,
 633                 0x8ea0, 0x8f84,
 634                 0x8fc0, 0x9058,
 635                 0x9060, 0x9060,
 636                 0x9068, 0x90f8,
 637                 0x9400, 0x9408,
 638                 0x9410, 0x9470,
 639                 0x9600, 0x9600,
 640                 0x9608, 0x9638,
 641                 0x9640, 0x96f4,
 642                 0x9800, 0x9808,
 643                 0x9820, 0x983c,
 644                 0x9850, 0x9864,
 645                 0x9c00, 0x9c6c,
 646                 0x9c80, 0x9cec,
 647                 0x9d00, 0x9d6c,
 648                 0x9d80, 0x9dec,
 649                 0x9e00, 0x9e6c,
 650                 0x9e80, 0x9eec,
 651                 0x9f00, 0x9f6c,
 652                 0x9f80, 0xa020,
 653                 0xd004, 0xd004,
 654                 0xd010, 0xd03c,
 655                 0xdfc0, 0xdfe0,
 656                 0xe000, 0x1106c,
 657                 0x11074, 0x11088,
 658                 0x1109c, 0x1117c,
 659                 0x11190, 0x11204,
 660                 0x19040, 0x1906c,
 661                 0x19078, 0x19080,
 662                 0x1908c, 0x190e8,
 663                 0x190f0, 0x190f8,
 664                 0x19100, 0x19110,
 665                 0x19120, 0x19124,
 666                 0x19150, 0x19194,
 667                 0x1919c, 0x191b0,
 668                 0x191d0, 0x191e8,
 669                 0x19238, 0x19290,
 670                 0x193f8, 0x19428,
 671                 0x19430, 0x19444,
 672                 0x1944c, 0x1946c,
 673                 0x19474, 0x19474,
 674                 0x19490, 0x194cc,
 675                 0x194f0, 0x194f8,
 676                 0x19c00, 0x19c08,
 677                 0x19c10, 0x19c60,
 678                 0x19c94, 0x19ce4,
 679                 0x19cf0, 0x19d40,
 680                 0x19d50, 0x19d94,
 681                 0x19da0, 0x19de8,
 682                 0x19df0, 0x19e10,
 683                 0x19e50, 0x19e90,
 684                 0x19ea0, 0x19f24,
 685                 0x19f34, 0x19f34,
 686                 0x19f40, 0x19f50,
 687                 0x19f90, 0x19fb4,
 688                 0x19fc4, 0x19fe4,
 689                 0x1a000, 0x1a004,
 690                 0x1a010, 0x1a06c,
 691                 0x1a0b0, 0x1a0e4,
 692                 0x1a0ec, 0x1a0f8,
 693                 0x1a100, 0x1a108,
 694                 0x1a114, 0x1a120,
 695                 0x1a128, 0x1a130,
 696                 0x1a138, 0x1a138,
 697                 0x1a190, 0x1a1c4,
 698                 0x1a1fc, 0x1a1fc,
 699                 0x1e008, 0x1e00c,
 700                 0x1e040, 0x1e044,
 701                 0x1e04c, 0x1e04c,
 702                 0x1e284, 0x1e290,
 703                 0x1e2c0, 0x1e2c0,
 704                 0x1e2e0, 0x1e2e0,
 705                 0x1e300, 0x1e384,
 706                 0x1e3c0, 0x1e3c8,
 707                 0x1e408, 0x1e40c,
 708                 0x1e440, 0x1e444,
 709                 0x1e44c, 0x1e44c,
 710                 0x1e684, 0x1e690,
 711                 0x1e6c0, 0x1e6c0,
 712                 0x1e6e0, 0x1e6e0,
 713                 0x1e700, 0x1e784,
 714                 0x1e7c0, 0x1e7c8,
 715                 0x1e808, 0x1e80c,
 716                 0x1e840, 0x1e844,
 717                 0x1e84c, 0x1e84c,
 718                 0x1ea84, 0x1ea90,
 719                 0x1eac0, 0x1eac0,
 720                 0x1eae0, 0x1eae0,
 721                 0x1eb00, 0x1eb84,
 722                 0x1ebc0, 0x1ebc8,
 723                 0x1ec08, 0x1ec0c,
 724                 0x1ec40, 0x1ec44,
 725                 0x1ec4c, 0x1ec4c,
 726                 0x1ee84, 0x1ee90,
 727                 0x1eec0, 0x1eec0,
 728                 0x1eee0, 0x1eee0,
 729                 0x1ef00, 0x1ef84,
 730                 0x1efc0, 0x1efc8,
 731                 0x1f008, 0x1f00c,
 732                 0x1f040, 0x1f044,
 733                 0x1f04c, 0x1f04c,
 734                 0x1f284, 0x1f290,
 735                 0x1f2c0, 0x1f2c0,
 736                 0x1f2e0, 0x1f2e0,
 737                 0x1f300, 0x1f384,
 738                 0x1f3c0, 0x1f3c8,
 739                 0x1f408, 0x1f40c,
 740                 0x1f440, 0x1f444,
 741                 0x1f44c, 0x1f44c,
 742                 0x1f684, 0x1f690,
 743                 0x1f6c0, 0x1f6c0,
 744                 0x1f6e0, 0x1f6e0,
 745                 0x1f700, 0x1f784,
 746                 0x1f7c0, 0x1f7c8,
 747                 0x1f808, 0x1f80c,
 748                 0x1f840, 0x1f844,
 749                 0x1f84c, 0x1f84c,
 750                 0x1fa84, 0x1fa90,
 751                 0x1fac0, 0x1fac0,
 752                 0x1fae0, 0x1fae0,
 753                 0x1fb00, 0x1fb84,
 754                 0x1fbc0, 0x1fbc8,
 755                 0x1fc08, 0x1fc0c,
 756                 0x1fc40, 0x1fc44,
 757                 0x1fc4c, 0x1fc4c,
 758                 0x1fe84, 0x1fe90,
 759                 0x1fec0, 0x1fec0,
 760                 0x1fee0, 0x1fee0,
 761                 0x1ff00, 0x1ff84,
 762                 0x1ffc0, 0x1ffc8,
 763                 0x30000, 0x30030,
 764                 0x30038, 0x30038,
 765                 0x30040, 0x30040,
 766                 0x30100, 0x30144,
 767                 0x30190, 0x301a0,
 768                 0x301a8, 0x301b8,
 769                 0x301c4, 0x301c8,
 770                 0x301d0, 0x301d0,
 771                 0x30200, 0x30318,
 772                 0x30400, 0x304b4,
 773                 0x304c0, 0x3052c,
 774                 0x30540, 0x3061c,
 775                 0x30800, 0x30828,
 776                 0x30834, 0x30834,
 777                 0x308c0, 0x30908,
 778                 0x30910, 0x309ac,
 779                 0x30a00, 0x30a14,
 780                 0x30a1c, 0x30a2c,
 781                 0x30a44, 0x30a50,
 782                 0x30a74, 0x30a74,
 783                 0x30a7c, 0x30afc,
 784                 0x30b08, 0x30c24,
 785                 0x30d00, 0x30d00,
 786                 0x30d08, 0x30d14,
 787                 0x30d1c, 0x30d20,
 788                 0x30d3c, 0x30d3c,
 789                 0x30d48, 0x30d50,
 790                 0x31200, 0x3120c,
 791                 0x31220, 0x31220,
 792                 0x31240, 0x31240,
 793                 0x31600, 0x3160c,
 794                 0x31a00, 0x31a1c,
 795                 0x31e00, 0x31e20,
 796                 0x31e38, 0x31e3c,
 797                 0x31e80, 0x31e80,
 798                 0x31e88, 0x31ea8,
 799                 0x31eb0, 0x31eb4,
 800                 0x31ec8, 0x31ed4,
 801                 0x31fb8, 0x32004,
 802                 0x32200, 0x32200,
 803                 0x32208, 0x32240,
 804                 0x32248, 0x32280,
 805                 0x32288, 0x322c0,
 806                 0x322c8, 0x322fc,
 807                 0x32600, 0x32630,
 808                 0x32a00, 0x32abc,
 809                 0x32b00, 0x32b10,
 810                 0x32b20, 0x32b30,
 811                 0x32b40, 0x32b50,
 812                 0x32b60, 0x32b70,
 813                 0x33000, 0x33028,
 814                 0x33030, 0x33048,
 815                 0x33060, 0x33068,
 816                 0x33070, 0x3309c,
 817                 0x330f0, 0x33128,
 818                 0x33130, 0x33148,
 819                 0x33160, 0x33168,
 820                 0x33170, 0x3319c,
 821                 0x331f0, 0x33238,
 822                 0x33240, 0x33240,
 823                 0x33248, 0x33250,
 824                 0x3325c, 0x33264,
 825                 0x33270, 0x332b8,
 826                 0x332c0, 0x332e4,
 827                 0x332f8, 0x33338,
 828                 0x33340, 0x33340,
 829                 0x33348, 0x33350,
 830                 0x3335c, 0x33364,
 831                 0x33370, 0x333b8,
 832                 0x333c0, 0x333e4,
 833                 0x333f8, 0x33428,
 834                 0x33430, 0x33448,
 835                 0x33460, 0x33468,
 836                 0x33470, 0x3349c,
 837                 0x334f0, 0x33528,
 838                 0x33530, 0x33548,
 839                 0x33560, 0x33568,
 840                 0x33570, 0x3359c,
 841                 0x335f0, 0x33638,
 842                 0x33640, 0x33640,
 843                 0x33648, 0x33650,
 844                 0x3365c, 0x33664,
 845                 0x33670, 0x336b8,
 846                 0x336c0, 0x336e4,
 847                 0x336f8, 0x33738,
 848                 0x33740, 0x33740,
 849                 0x33748, 0x33750,
 850                 0x3375c, 0x33764,
 851                 0x33770, 0x337b8,
 852                 0x337c0, 0x337e4,
 853                 0x337f8, 0x337fc,
 854                 0x33814, 0x33814,
 855                 0x3382c, 0x3382c,
 856                 0x33880, 0x3388c,
 857                 0x338e8, 0x338ec,
 858                 0x33900, 0x33928,
 859                 0x33930, 0x33948,
 860                 0x33960, 0x33968,
 861                 0x33970, 0x3399c,
 862                 0x339f0, 0x33a38,
 863                 0x33a40, 0x33a40,
 864                 0x33a48, 0x33a50,
 865                 0x33a5c, 0x33a64,
 866                 0x33a70, 0x33ab8,
 867                 0x33ac0, 0x33ae4,
 868                 0x33af8, 0x33b10,
 869                 0x33b28, 0x33b28,
 870                 0x33b3c, 0x33b50,
 871                 0x33bf0, 0x33c10,
 872                 0x33c28, 0x33c28,
 873                 0x33c3c, 0x33c50,
 874                 0x33cf0, 0x33cfc,
 875                 0x34000, 0x34030,
 876                 0x34038, 0x34038,
 877                 0x34040, 0x34040,
 878                 0x34100, 0x34144,
 879                 0x34190, 0x341a0,
 880                 0x341a8, 0x341b8,
 881                 0x341c4, 0x341c8,
 882                 0x341d0, 0x341d0,
 883                 0x34200, 0x34318,
 884                 0x34400, 0x344b4,
 885                 0x344c0, 0x3452c,
 886                 0x34540, 0x3461c,
 887                 0x34800, 0x34828,
 888                 0x34834, 0x34834,
 889                 0x348c0, 0x34908,
 890                 0x34910, 0x349ac,
 891                 0x34a00, 0x34a14,
 892                 0x34a1c, 0x34a2c,
 893                 0x34a44, 0x34a50,
 894                 0x34a74, 0x34a74,
 895                 0x34a7c, 0x34afc,
 896                 0x34b08, 0x34c24,
 897                 0x34d00, 0x34d00,
 898                 0x34d08, 0x34d14,
 899                 0x34d1c, 0x34d20,
 900                 0x34d3c, 0x34d3c,
 901                 0x34d48, 0x34d50,
 902                 0x35200, 0x3520c,
 903                 0x35220, 0x35220,
 904                 0x35240, 0x35240,
 905                 0x35600, 0x3560c,
 906                 0x35a00, 0x35a1c,
 907                 0x35e00, 0x35e20,
 908                 0x35e38, 0x35e3c,
 909                 0x35e80, 0x35e80,
 910                 0x35e88, 0x35ea8,
 911                 0x35eb0, 0x35eb4,
 912                 0x35ec8, 0x35ed4,
 913                 0x35fb8, 0x36004,
 914                 0x36200, 0x36200,
 915                 0x36208, 0x36240,
 916                 0x36248, 0x36280,
 917                 0x36288, 0x362c0,
 918                 0x362c8, 0x362fc,
 919                 0x36600, 0x36630,
 920                 0x36a00, 0x36abc,
 921                 0x36b00, 0x36b10,
 922                 0x36b20, 0x36b30,
 923                 0x36b40, 0x36b50,
 924                 0x36b60, 0x36b70,
 925                 0x37000, 0x37028,
 926                 0x37030, 0x37048,
 927                 0x37060, 0x37068,
 928                 0x37070, 0x3709c,
 929                 0x370f0, 0x37128,
 930                 0x37130, 0x37148,
 931                 0x37160, 0x37168,
 932                 0x37170, 0x3719c,
 933                 0x371f0, 0x37238,
 934                 0x37240, 0x37240,
 935                 0x37248, 0x37250,
 936                 0x3725c, 0x37264,
 937                 0x37270, 0x372b8,
 938                 0x372c0, 0x372e4,
 939                 0x372f8, 0x37338,
 940                 0x37340, 0x37340,
 941                 0x37348, 0x37350,
 942                 0x3735c, 0x37364,
 943                 0x37370, 0x373b8,
 944                 0x373c0, 0x373e4,
 945                 0x373f8, 0x37428,
 946                 0x37430, 0x37448,
 947                 0x37460, 0x37468,
 948                 0x37470, 0x3749c,
 949                 0x374f0, 0x37528,
 950                 0x37530, 0x37548,
 951                 0x37560, 0x37568,
 952                 0x37570, 0x3759c,
 953                 0x375f0, 0x37638,
 954                 0x37640, 0x37640,
 955                 0x37648, 0x37650,
 956                 0x3765c, 0x37664,
 957                 0x37670, 0x376b8,
 958                 0x376c0, 0x376e4,
 959                 0x376f8, 0x37738,
 960                 0x37740, 0x37740,
 961                 0x37748, 0x37750,
 962                 0x3775c, 0x37764,
 963                 0x37770, 0x377b8,
 964                 0x377c0, 0x377e4,
 965                 0x377f8, 0x377fc,
 966                 0x37814, 0x37814,
 967                 0x3782c, 0x3782c,
 968                 0x37880, 0x3788c,
 969                 0x378e8, 0x378ec,
 970                 0x37900, 0x37928,
 971                 0x37930, 0x37948,
 972                 0x37960, 0x37968,
 973                 0x37970, 0x3799c,
 974                 0x379f0, 0x37a38,
 975                 0x37a40, 0x37a40,
 976                 0x37a48, 0x37a50,
 977                 0x37a5c, 0x37a64,
 978                 0x37a70, 0x37ab8,
 979                 0x37ac0, 0x37ae4,
 980                 0x37af8, 0x37b10,
 981                 0x37b28, 0x37b28,
 982                 0x37b3c, 0x37b50,
 983                 0x37bf0, 0x37c10,
 984                 0x37c28, 0x37c28,
 985                 0x37c3c, 0x37c50,
 986                 0x37cf0, 0x37cfc,
 987                 0x38000, 0x38030,
 988                 0x38038, 0x38038,
 989                 0x38040, 0x38040,
 990                 0x38100, 0x38144,
 991                 0x38190, 0x381a0,
 992                 0x381a8, 0x381b8,
 993                 0x381c4, 0x381c8,
 994                 0x381d0, 0x381d0,
 995                 0x38200, 0x38318,
 996                 0x38400, 0x384b4,
 997                 0x384c0, 0x3852c,
 998                 0x38540, 0x3861c,
 999                 0x38800, 0x38828,
1000                 0x38834, 0x38834,
1001                 0x388c0, 0x38908,
1002                 0x38910, 0x389ac,
1003                 0x38a00, 0x38a14,
1004                 0x38a1c, 0x38a2c,
1005                 0x38a44, 0x38a50,
1006                 0x38a74, 0x38a74,
1007                 0x38a7c, 0x38afc,
1008                 0x38b08, 0x38c24,
1009                 0x38d00, 0x38d00,
1010                 0x38d08, 0x38d14,
1011                 0x38d1c, 0x38d20,
1012                 0x38d3c, 0x38d3c,
1013                 0x38d48, 0x38d50,
1014                 0x39200, 0x3920c,
1015                 0x39220, 0x39220,
1016                 0x39240, 0x39240,
1017                 0x39600, 0x3960c,
1018                 0x39a00, 0x39a1c,
1019                 0x39e00, 0x39e20,
1020                 0x39e38, 0x39e3c,
1021                 0x39e80, 0x39e80,
1022                 0x39e88, 0x39ea8,
1023                 0x39eb0, 0x39eb4,
1024                 0x39ec8, 0x39ed4,
1025                 0x39fb8, 0x3a004,
1026                 0x3a200, 0x3a200,
1027                 0x3a208, 0x3a240,
1028                 0x3a248, 0x3a280,
1029                 0x3a288, 0x3a2c0,
1030                 0x3a2c8, 0x3a2fc,
1031                 0x3a600, 0x3a630,
1032                 0x3aa00, 0x3aabc,
1033                 0x3ab00, 0x3ab10,
1034                 0x3ab20, 0x3ab30,
1035                 0x3ab40, 0x3ab50,
1036                 0x3ab60, 0x3ab70,
1037                 0x3b000, 0x3b028,
1038                 0x3b030, 0x3b048,
1039                 0x3b060, 0x3b068,
1040                 0x3b070, 0x3b09c,
1041                 0x3b0f0, 0x3b128,
1042                 0x3b130, 0x3b148,
1043                 0x3b160, 0x3b168,
1044                 0x3b170, 0x3b19c,
1045                 0x3b1f0, 0x3b238,
1046                 0x3b240, 0x3b240,
1047                 0x3b248, 0x3b250,
1048                 0x3b25c, 0x3b264,
1049                 0x3b270, 0x3b2b8,
1050                 0x3b2c0, 0x3b2e4,
1051                 0x3b2f8, 0x3b338,
1052                 0x3b340, 0x3b340,
1053                 0x3b348, 0x3b350,
1054                 0x3b35c, 0x3b364,
1055                 0x3b370, 0x3b3b8,
1056                 0x3b3c0, 0x3b3e4,
1057                 0x3b3f8, 0x3b428,
1058                 0x3b430, 0x3b448,
1059                 0x3b460, 0x3b468,
1060                 0x3b470, 0x3b49c,
1061                 0x3b4f0, 0x3b528,
1062                 0x3b530, 0x3b548,
1063                 0x3b560, 0x3b568,
1064                 0x3b570, 0x3b59c,
1065                 0x3b5f0, 0x3b638,
1066                 0x3b640, 0x3b640,
1067                 0x3b648, 0x3b650,
1068                 0x3b65c, 0x3b664,
1069                 0x3b670, 0x3b6b8,
1070                 0x3b6c0, 0x3b6e4,
1071                 0x3b6f8, 0x3b738,
1072                 0x3b740, 0x3b740,
1073                 0x3b748, 0x3b750,
1074                 0x3b75c, 0x3b764,
1075                 0x3b770, 0x3b7b8,
1076                 0x3b7c0, 0x3b7e4,
1077                 0x3b7f8, 0x3b7fc,
1078                 0x3b814, 0x3b814,
1079                 0x3b82c, 0x3b82c,
1080                 0x3b880, 0x3b88c,
1081                 0x3b8e8, 0x3b8ec,
1082                 0x3b900, 0x3b928,
1083                 0x3b930, 0x3b948,
1084                 0x3b960, 0x3b968,
1085                 0x3b970, 0x3b99c,
1086                 0x3b9f0, 0x3ba38,
1087                 0x3ba40, 0x3ba40,
1088                 0x3ba48, 0x3ba50,
1089                 0x3ba5c, 0x3ba64,
1090                 0x3ba70, 0x3bab8,
1091                 0x3bac0, 0x3bae4,
1092                 0x3baf8, 0x3bb10,
1093                 0x3bb28, 0x3bb28,
1094                 0x3bb3c, 0x3bb50,
1095                 0x3bbf0, 0x3bc10,
1096                 0x3bc28, 0x3bc28,
1097                 0x3bc3c, 0x3bc50,
1098                 0x3bcf0, 0x3bcfc,
1099                 0x3c000, 0x3c030,
1100                 0x3c038, 0x3c038,
1101                 0x3c040, 0x3c040,
1102                 0x3c100, 0x3c144,
1103                 0x3c190, 0x3c1a0,
1104                 0x3c1a8, 0x3c1b8,
1105                 0x3c1c4, 0x3c1c8,
1106                 0x3c1d0, 0x3c1d0,
1107                 0x3c200, 0x3c318,
1108                 0x3c400, 0x3c4b4,
1109                 0x3c4c0, 0x3c52c,
1110                 0x3c540, 0x3c61c,
1111                 0x3c800, 0x3c828,
1112                 0x3c834, 0x3c834,
1113                 0x3c8c0, 0x3c908,
1114                 0x3c910, 0x3c9ac,
1115                 0x3ca00, 0x3ca14,
1116                 0x3ca1c, 0x3ca2c,
1117                 0x3ca44, 0x3ca50,
1118                 0x3ca74, 0x3ca74,
1119                 0x3ca7c, 0x3cafc,
1120                 0x3cb08, 0x3cc24,
1121                 0x3cd00, 0x3cd00,
1122                 0x3cd08, 0x3cd14,
1123                 0x3cd1c, 0x3cd20,
1124                 0x3cd3c, 0x3cd3c,
1125                 0x3cd48, 0x3cd50,
1126                 0x3d200, 0x3d20c,
1127                 0x3d220, 0x3d220,
1128                 0x3d240, 0x3d240,
1129                 0x3d600, 0x3d60c,
1130                 0x3da00, 0x3da1c,
1131                 0x3de00, 0x3de20,
1132                 0x3de38, 0x3de3c,
1133                 0x3de80, 0x3de80,
1134                 0x3de88, 0x3dea8,
1135                 0x3deb0, 0x3deb4,
1136                 0x3dec8, 0x3ded4,
1137                 0x3dfb8, 0x3e004,
1138                 0x3e200, 0x3e200,
1139                 0x3e208, 0x3e240,
1140                 0x3e248, 0x3e280,
1141                 0x3e288, 0x3e2c0,
1142                 0x3e2c8, 0x3e2fc,
1143                 0x3e600, 0x3e630,
1144                 0x3ea00, 0x3eabc,
1145                 0x3eb00, 0x3eb10,
1146                 0x3eb20, 0x3eb30,
1147                 0x3eb40, 0x3eb50,
1148                 0x3eb60, 0x3eb70,
1149                 0x3f000, 0x3f028,
1150                 0x3f030, 0x3f048,
1151                 0x3f060, 0x3f068,
1152                 0x3f070, 0x3f09c,
1153                 0x3f0f0, 0x3f128,
1154                 0x3f130, 0x3f148,
1155                 0x3f160, 0x3f168,
1156                 0x3f170, 0x3f19c,
1157                 0x3f1f0, 0x3f238,
1158                 0x3f240, 0x3f240,
1159                 0x3f248, 0x3f250,
1160                 0x3f25c, 0x3f264,
1161                 0x3f270, 0x3f2b8,
1162                 0x3f2c0, 0x3f2e4,
1163                 0x3f2f8, 0x3f338,
1164                 0x3f340, 0x3f340,
1165                 0x3f348, 0x3f350,
1166                 0x3f35c, 0x3f364,
1167                 0x3f370, 0x3f3b8,
1168                 0x3f3c0, 0x3f3e4,
1169                 0x3f3f8, 0x3f428,
1170                 0x3f430, 0x3f448,
1171                 0x3f460, 0x3f468,
1172                 0x3f470, 0x3f49c,
1173                 0x3f4f0, 0x3f528,
1174                 0x3f530, 0x3f548,
1175                 0x3f560, 0x3f568,
1176                 0x3f570, 0x3f59c,
1177                 0x3f5f0, 0x3f638,
1178                 0x3f640, 0x3f640,
1179                 0x3f648, 0x3f650,
1180                 0x3f65c, 0x3f664,
1181                 0x3f670, 0x3f6b8,
1182                 0x3f6c0, 0x3f6e4,
1183                 0x3f6f8, 0x3f738,
1184                 0x3f740, 0x3f740,
1185                 0x3f748, 0x3f750,
1186                 0x3f75c, 0x3f764,
1187                 0x3f770, 0x3f7b8,
1188                 0x3f7c0, 0x3f7e4,
1189                 0x3f7f8, 0x3f7fc,
1190                 0x3f814, 0x3f814,
1191                 0x3f82c, 0x3f82c,
1192                 0x3f880, 0x3f88c,
1193                 0x3f8e8, 0x3f8ec,
1194                 0x3f900, 0x3f928,
1195                 0x3f930, 0x3f948,
1196                 0x3f960, 0x3f968,
1197                 0x3f970, 0x3f99c,
1198                 0x3f9f0, 0x3fa38,
1199                 0x3fa40, 0x3fa40,
1200                 0x3fa48, 0x3fa50,
1201                 0x3fa5c, 0x3fa64,
1202                 0x3fa70, 0x3fab8,
1203                 0x3fac0, 0x3fae4,
1204                 0x3faf8, 0x3fb10,
1205                 0x3fb28, 0x3fb28,
1206                 0x3fb3c, 0x3fb50,
1207                 0x3fbf0, 0x3fc10,
1208                 0x3fc28, 0x3fc28,
1209                 0x3fc3c, 0x3fc50,
1210                 0x3fcf0, 0x3fcfc,
1211                 0x40000, 0x4000c,
1212                 0x40040, 0x40050,
1213                 0x40060, 0x40068,
1214                 0x4007c, 0x4008c,
1215                 0x40094, 0x400b0,
1216                 0x400c0, 0x40144,
1217                 0x40180, 0x4018c,
1218                 0x40200, 0x40254,
1219                 0x40260, 0x40264,
1220                 0x40270, 0x40288,
1221                 0x40290, 0x40298,
1222                 0x402ac, 0x402c8,
1223                 0x402d0, 0x402e0,
1224                 0x402f0, 0x402f0,
1225                 0x40300, 0x4033c,
1226                 0x403f8, 0x403fc,
1227                 0x41304, 0x413c4,
1228                 0x41400, 0x4140c,
1229                 0x41414, 0x4141c,
1230                 0x41480, 0x414d0,
1231                 0x44000, 0x44054,
1232                 0x4405c, 0x44078,
1233                 0x440c0, 0x44174,
1234                 0x44180, 0x441ac,
1235                 0x441b4, 0x441b8,
1236                 0x441c0, 0x44254,
1237                 0x4425c, 0x44278,
1238                 0x442c0, 0x44374,
1239                 0x44380, 0x443ac,
1240                 0x443b4, 0x443b8,
1241                 0x443c0, 0x44454,
1242                 0x4445c, 0x44478,
1243                 0x444c0, 0x44574,
1244                 0x44580, 0x445ac,
1245                 0x445b4, 0x445b8,
1246                 0x445c0, 0x44654,
1247                 0x4465c, 0x44678,
1248                 0x446c0, 0x44774,
1249                 0x44780, 0x447ac,
1250                 0x447b4, 0x447b8,
1251                 0x447c0, 0x44854,
1252                 0x4485c, 0x44878,
1253                 0x448c0, 0x44974,
1254                 0x44980, 0x449ac,
1255                 0x449b4, 0x449b8,
1256                 0x449c0, 0x449fc,
1257                 0x45000, 0x45004,
1258                 0x45010, 0x45030,
1259                 0x45040, 0x45060,
1260                 0x45068, 0x45068,
1261                 0x45080, 0x45084,
1262                 0x450a0, 0x450b0,
1263                 0x45200, 0x45204,
1264                 0x45210, 0x45230,
1265                 0x45240, 0x45260,
1266                 0x45268, 0x45268,
1267                 0x45280, 0x45284,
1268                 0x452a0, 0x452b0,
1269                 0x460c0, 0x460e4,
1270                 0x47000, 0x4703c,
1271                 0x47044, 0x4708c,
1272                 0x47200, 0x47250,
1273                 0x47400, 0x47408,
1274                 0x47414, 0x47420,
1275                 0x47600, 0x47618,
1276                 0x47800, 0x47814,
1277                 0x48000, 0x4800c,
1278                 0x48040, 0x48050,
1279                 0x48060, 0x48068,
1280                 0x4807c, 0x4808c,
1281                 0x48094, 0x480b0,
1282                 0x480c0, 0x48144,
1283                 0x48180, 0x4818c,
1284                 0x48200, 0x48254,
1285                 0x48260, 0x48264,
1286                 0x48270, 0x48288,
1287                 0x48290, 0x48298,
1288                 0x482ac, 0x482c8,
1289                 0x482d0, 0x482e0,
1290                 0x482f0, 0x482f0,
1291                 0x48300, 0x4833c,
1292                 0x483f8, 0x483fc,
1293                 0x49304, 0x493c4,
1294                 0x49400, 0x4940c,
1295                 0x49414, 0x4941c,
1296                 0x49480, 0x494d0,
1297                 0x4c000, 0x4c054,
1298                 0x4c05c, 0x4c078,
1299                 0x4c0c0, 0x4c174,
1300                 0x4c180, 0x4c1ac,
1301                 0x4c1b4, 0x4c1b8,
1302                 0x4c1c0, 0x4c254,
1303                 0x4c25c, 0x4c278,
1304                 0x4c2c0, 0x4c374,
1305                 0x4c380, 0x4c3ac,
1306                 0x4c3b4, 0x4c3b8,
1307                 0x4c3c0, 0x4c454,
1308                 0x4c45c, 0x4c478,
1309                 0x4c4c0, 0x4c574,
1310                 0x4c580, 0x4c5ac,
1311                 0x4c5b4, 0x4c5b8,
1312                 0x4c5c0, 0x4c654,
1313                 0x4c65c, 0x4c678,
1314                 0x4c6c0, 0x4c774,
1315                 0x4c780, 0x4c7ac,
1316                 0x4c7b4, 0x4c7b8,
1317                 0x4c7c0, 0x4c854,
1318                 0x4c85c, 0x4c878,
1319                 0x4c8c0, 0x4c974,
1320                 0x4c980, 0x4c9ac,
1321                 0x4c9b4, 0x4c9b8,
1322                 0x4c9c0, 0x4c9fc,
1323                 0x4d000, 0x4d004,
1324                 0x4d010, 0x4d030,
1325                 0x4d040, 0x4d060,
1326                 0x4d068, 0x4d068,
1327                 0x4d080, 0x4d084,
1328                 0x4d0a0, 0x4d0b0,
1329                 0x4d200, 0x4d204,
1330                 0x4d210, 0x4d230,
1331                 0x4d240, 0x4d260,
1332                 0x4d268, 0x4d268,
1333                 0x4d280, 0x4d284,
1334                 0x4d2a0, 0x4d2b0,
1335                 0x4e0c0, 0x4e0e4,
1336                 0x4f000, 0x4f03c,
1337                 0x4f044, 0x4f08c,
1338                 0x4f200, 0x4f250,
1339                 0x4f400, 0x4f408,
1340                 0x4f414, 0x4f420,
1341                 0x4f600, 0x4f618,
1342                 0x4f800, 0x4f814,
1343                 0x50000, 0x50084,
1344                 0x50090, 0x500cc,
1345                 0x50400, 0x50400,
1346                 0x50800, 0x50884,
1347                 0x50890, 0x508cc,
1348                 0x50c00, 0x50c00,
1349                 0x51000, 0x5101c,
1350                 0x51300, 0x51308,
1351         };
1352
1353         static const unsigned int t6_reg_ranges[] = {
1354                 0x1008, 0x101c,
1355                 0x1024, 0x10a8,
1356                 0x10b4, 0x10f8,
1357                 0x1100, 0x1114,
1358                 0x111c, 0x112c,
1359                 0x1138, 0x113c,
1360                 0x1144, 0x114c,
1361                 0x1180, 0x1184,
1362                 0x1190, 0x1194,
1363                 0x11a0, 0x11a4,
1364                 0x11b0, 0x11b4,
1365                 0x11fc, 0x1274,
1366                 0x1280, 0x133c,
1367                 0x1800, 0x18fc,
1368                 0x3000, 0x302c,
1369                 0x3060, 0x30b0,
1370                 0x30b8, 0x30d8,
1371                 0x30e0, 0x30fc,
1372                 0x3140, 0x357c,
1373                 0x35a8, 0x35cc,
1374                 0x35ec, 0x35ec,
1375                 0x3600, 0x5624,
1376                 0x56cc, 0x56ec,
1377                 0x56f4, 0x5720,
1378                 0x5728, 0x575c,
1379                 0x580c, 0x5814,
1380                 0x5890, 0x589c,
1381                 0x58a4, 0x58ac,
1382                 0x58b8, 0x58bc,
1383                 0x5940, 0x595c,
1384                 0x5980, 0x598c,
1385                 0x59b0, 0x59c8,
1386                 0x59d0, 0x59dc,
1387                 0x59fc, 0x5a18,
1388                 0x5a60, 0x5a6c,
1389                 0x5a80, 0x5a8c,
1390                 0x5a94, 0x5a9c,
1391                 0x5b94, 0x5bfc,
1392                 0x5c10, 0x5e48,
1393                 0x5e50, 0x5e94,
1394                 0x5ea0, 0x5eb0,
1395                 0x5ec0, 0x5ec0,
1396                 0x5ec8, 0x5ed0,
1397                 0x5ee0, 0x5ee0,
1398                 0x5ef0, 0x5ef0,
1399                 0x5f00, 0x5f00,
1400                 0x6000, 0x6020,
1401                 0x6028, 0x6040,
1402                 0x6058, 0x609c,
1403                 0x60a8, 0x619c,
1404                 0x7700, 0x7798,
1405                 0x77c0, 0x7880,
1406                 0x78cc, 0x78fc,
1407                 0x7b00, 0x7b58,
1408                 0x7b60, 0x7b84,
1409                 0x7b8c, 0x7c54,
1410                 0x7d00, 0x7d38,
1411                 0x7d40, 0x7d84,
1412                 0x7d8c, 0x7ddc,
1413                 0x7de4, 0x7e04,
1414                 0x7e10, 0x7e1c,
1415                 0x7e24, 0x7e38,
1416                 0x7e40, 0x7e44,
1417                 0x7e4c, 0x7e78,
1418                 0x7e80, 0x7edc,
1419                 0x7ee8, 0x7efc,
1420                 0x8dc0, 0x8de4,
1421                 0x8df8, 0x8e04,
1422                 0x8e10, 0x8e84,
1423                 0x8ea0, 0x8f88,
1424                 0x8fb8, 0x9058,
1425                 0x9060, 0x9060,
1426                 0x9068, 0x90f8,
1427                 0x9100, 0x9124,
1428                 0x9400, 0x9470,
1429                 0x9600, 0x9600,
1430                 0x9608, 0x9638,
1431                 0x9640, 0x9704,
1432                 0x9710, 0x971c,
1433                 0x9800, 0x9808,
1434                 0x9820, 0x983c,
1435                 0x9850, 0x9864,
1436                 0x9c00, 0x9c6c,
1437                 0x9c80, 0x9cec,
1438                 0x9d00, 0x9d6c,
1439                 0x9d80, 0x9dec,
1440                 0x9e00, 0x9e6c,
1441                 0x9e80, 0x9eec,
1442                 0x9f00, 0x9f6c,
1443                 0x9f80, 0xa020,
1444                 0xd004, 0xd03c,
1445                 0xd100, 0xd118,
1446                 0xd200, 0xd214,
1447                 0xd220, 0xd234,
1448                 0xd240, 0xd254,
1449                 0xd260, 0xd274,
1450                 0xd280, 0xd294,
1451                 0xd2a0, 0xd2b4,
1452                 0xd2c0, 0xd2d4,
1453                 0xd2e0, 0xd2f4,
1454                 0xd300, 0xd31c,
1455                 0xdfc0, 0xdfe0,
1456                 0xe000, 0xf008,
1457                 0xf010, 0xf018,
1458                 0xf020, 0xf028,
1459                 0x11000, 0x11014,
1460                 0x11048, 0x1106c,
1461                 0x11074, 0x11088,
1462                 0x11098, 0x11120,
1463                 0x1112c, 0x1117c,
1464                 0x11190, 0x112e0,
1465                 0x11300, 0x1130c,
1466                 0x12000, 0x1206c,
1467                 0x19040, 0x1906c,
1468                 0x19078, 0x19080,
1469                 0x1908c, 0x190e8,
1470                 0x190f0, 0x190f8,
1471                 0x19100, 0x19110,
1472                 0x19120, 0x19124,
1473                 0x19150, 0x19194,
1474                 0x1919c, 0x191b0,
1475                 0x191d0, 0x191e8,
1476                 0x19238, 0x19290,
1477                 0x192a4, 0x192b0,
1478                 0x192bc, 0x192bc,
1479                 0x19348, 0x1934c,
1480                 0x193f8, 0x19418,
1481                 0x19420, 0x19428,
1482                 0x19430, 0x19444,
1483                 0x1944c, 0x1946c,
1484                 0x19474, 0x19474,
1485                 0x19490, 0x194cc,
1486                 0x194f0, 0x194f8,
1487                 0x19c00, 0x19c48,
1488                 0x19c50, 0x19c80,
1489                 0x19c94, 0x19c98,
1490                 0x19ca0, 0x19cbc,
1491                 0x19ce4, 0x19ce4,
1492                 0x19cf0, 0x19cf8,
1493                 0x19d00, 0x19d28,
1494                 0x19d50, 0x19d78,
1495                 0x19d94, 0x19d98,
1496                 0x19da0, 0x19dc8,
1497                 0x19df0, 0x19e10,
1498                 0x19e50, 0x19e6c,
1499                 0x19ea0, 0x19ebc,
1500                 0x19ec4, 0x19ef4,
1501                 0x19f04, 0x19f2c,
1502                 0x19f34, 0x19f34,
1503                 0x19f40, 0x19f50,
1504                 0x19f90, 0x19fac,
1505                 0x19fc4, 0x19fc8,
1506                 0x19fd0, 0x19fe4,
1507                 0x1a000, 0x1a004,
1508                 0x1a010, 0x1a06c,
1509                 0x1a0b0, 0x1a0e4,
1510                 0x1a0ec, 0x1a0f8,
1511                 0x1a100, 0x1a108,
1512                 0x1a114, 0x1a120,
1513                 0x1a128, 0x1a130,
1514                 0x1a138, 0x1a138,
1515                 0x1a190, 0x1a1c4,
1516                 0x1a1fc, 0x1a1fc,
1517                 0x1e008, 0x1e00c,
1518                 0x1e040, 0x1e044,
1519                 0x1e04c, 0x1e04c,
1520                 0x1e284, 0x1e290,
1521                 0x1e2c0, 0x1e2c0,
1522                 0x1e2e0, 0x1e2e0,
1523                 0x1e300, 0x1e384,
1524                 0x1e3c0, 0x1e3c8,
1525                 0x1e408, 0x1e40c,
1526                 0x1e440, 0x1e444,
1527                 0x1e44c, 0x1e44c,
1528                 0x1e684, 0x1e690,
1529                 0x1e6c0, 0x1e6c0,
1530                 0x1e6e0, 0x1e6e0,
1531                 0x1e700, 0x1e784,
1532                 0x1e7c0, 0x1e7c8,
1533                 0x1e808, 0x1e80c,
1534                 0x1e840, 0x1e844,
1535                 0x1e84c, 0x1e84c,
1536                 0x1ea84, 0x1ea90,
1537                 0x1eac0, 0x1eac0,
1538                 0x1eae0, 0x1eae0,
1539                 0x1eb00, 0x1eb84,
1540                 0x1ebc0, 0x1ebc8,
1541                 0x1ec08, 0x1ec0c,
1542                 0x1ec40, 0x1ec44,
1543                 0x1ec4c, 0x1ec4c,
1544                 0x1ee84, 0x1ee90,
1545                 0x1eec0, 0x1eec0,
1546                 0x1eee0, 0x1eee0,
1547                 0x1ef00, 0x1ef84,
1548                 0x1efc0, 0x1efc8,
1549                 0x1f008, 0x1f00c,
1550                 0x1f040, 0x1f044,
1551                 0x1f04c, 0x1f04c,
1552                 0x1f284, 0x1f290,
1553                 0x1f2c0, 0x1f2c0,
1554                 0x1f2e0, 0x1f2e0,
1555                 0x1f300, 0x1f384,
1556                 0x1f3c0, 0x1f3c8,
1557                 0x1f408, 0x1f40c,
1558                 0x1f440, 0x1f444,
1559                 0x1f44c, 0x1f44c,
1560                 0x1f684, 0x1f690,
1561                 0x1f6c0, 0x1f6c0,
1562                 0x1f6e0, 0x1f6e0,
1563                 0x1f700, 0x1f784,
1564                 0x1f7c0, 0x1f7c8,
1565                 0x1f808, 0x1f80c,
1566                 0x1f840, 0x1f844,
1567                 0x1f84c, 0x1f84c,
1568                 0x1fa84, 0x1fa90,
1569                 0x1fac0, 0x1fac0,
1570                 0x1fae0, 0x1fae0,
1571                 0x1fb00, 0x1fb84,
1572                 0x1fbc0, 0x1fbc8,
1573                 0x1fc08, 0x1fc0c,
1574                 0x1fc40, 0x1fc44,
1575                 0x1fc4c, 0x1fc4c,
1576                 0x1fe84, 0x1fe90,
1577                 0x1fec0, 0x1fec0,
1578                 0x1fee0, 0x1fee0,
1579                 0x1ff00, 0x1ff84,
1580                 0x1ffc0, 0x1ffc8,
1581                 0x30000, 0x30030,
1582                 0x30100, 0x30168,
1583                 0x30190, 0x301a0,
1584                 0x301a8, 0x301b8,
1585                 0x301c4, 0x301c8,
1586                 0x301d0, 0x301d0,
1587                 0x30200, 0x30320,
1588                 0x30400, 0x304b4,
1589                 0x304c0, 0x3052c,
1590                 0x30540, 0x3061c,
1591                 0x30800, 0x308a0,
1592                 0x308c0, 0x30908,
1593                 0x30910, 0x309b8,
1594                 0x30a00, 0x30a04,
1595                 0x30a0c, 0x30a14,
1596                 0x30a1c, 0x30a2c,
1597                 0x30a44, 0x30a50,
1598                 0x30a74, 0x30a74,
1599                 0x30a7c, 0x30afc,
1600                 0x30b08, 0x30c24,
1601                 0x30d00, 0x30d14,
1602                 0x30d1c, 0x30d3c,
1603                 0x30d44, 0x30d4c,
1604                 0x30d54, 0x30d74,
1605                 0x30d7c, 0x30d7c,
1606                 0x30de0, 0x30de0,
1607                 0x30e00, 0x30ed4,
1608                 0x30f00, 0x30fa4,
1609                 0x30fc0, 0x30fc4,
1610                 0x31000, 0x31004,
1611                 0x31080, 0x310fc,
1612                 0x31208, 0x31220,
1613                 0x3123c, 0x31254,
1614                 0x31300, 0x31300,
1615                 0x31308, 0x3131c,
1616                 0x31338, 0x3133c,
1617                 0x31380, 0x31380,
1618                 0x31388, 0x313a8,
1619                 0x313b4, 0x313b4,
1620                 0x31400, 0x31420,
1621                 0x31438, 0x3143c,
1622                 0x31480, 0x31480,
1623                 0x314a8, 0x314a8,
1624                 0x314b0, 0x314b4,
1625                 0x314c8, 0x314d4,
1626                 0x31a40, 0x31a4c,
1627                 0x31af0, 0x31b20,
1628                 0x31b38, 0x31b3c,
1629                 0x31b80, 0x31b80,
1630                 0x31ba8, 0x31ba8,
1631                 0x31bb0, 0x31bb4,
1632                 0x31bc8, 0x31bd4,
1633                 0x32140, 0x3218c,
1634                 0x321f0, 0x321f4,
1635                 0x32200, 0x32200,
1636                 0x32218, 0x32218,
1637                 0x32400, 0x32400,
1638                 0x32408, 0x3241c,
1639                 0x32618, 0x32620,
1640                 0x32664, 0x32664,
1641                 0x326a8, 0x326a8,
1642                 0x326ec, 0x326ec,
1643                 0x32a00, 0x32abc,
1644                 0x32b00, 0x32b38,
1645                 0x32b20, 0x32b38,
1646                 0x32b40, 0x32b58,
1647                 0x32b60, 0x32b78,
1648                 0x32c00, 0x32c00,
1649                 0x32c08, 0x32c3c,
1650                 0x33000, 0x3302c,
1651                 0x33034, 0x33050,
1652                 0x33058, 0x33058,
1653                 0x33060, 0x3308c,
1654                 0x3309c, 0x330ac,
1655                 0x330c0, 0x330c0,
1656                 0x330c8, 0x330d0,
1657                 0x330d8, 0x330e0,
1658                 0x330ec, 0x3312c,
1659                 0x33134, 0x33150,
1660                 0x33158, 0x33158,
1661                 0x33160, 0x3318c,
1662                 0x3319c, 0x331ac,
1663                 0x331c0, 0x331c0,
1664                 0x331c8, 0x331d0,
1665                 0x331d8, 0x331e0,
1666                 0x331ec, 0x33290,
1667                 0x33298, 0x332c4,
1668                 0x332e4, 0x33390,
1669                 0x33398, 0x333c4,
1670                 0x333e4, 0x3342c,
1671                 0x33434, 0x33450,
1672                 0x33458, 0x33458,
1673                 0x33460, 0x3348c,
1674                 0x3349c, 0x334ac,
1675                 0x334c0, 0x334c0,
1676                 0x334c8, 0x334d0,
1677                 0x334d8, 0x334e0,
1678                 0x334ec, 0x3352c,
1679                 0x33534, 0x33550,
1680                 0x33558, 0x33558,
1681                 0x33560, 0x3358c,
1682                 0x3359c, 0x335ac,
1683                 0x335c0, 0x335c0,
1684                 0x335c8, 0x335d0,
1685                 0x335d8, 0x335e0,
1686                 0x335ec, 0x33690,
1687                 0x33698, 0x336c4,
1688                 0x336e4, 0x33790,
1689                 0x33798, 0x337c4,
1690                 0x337e4, 0x337fc,
1691                 0x33814, 0x33814,
1692                 0x33854, 0x33868,
1693                 0x33880, 0x3388c,
1694                 0x338c0, 0x338d0,
1695                 0x338e8, 0x338ec,
1696                 0x33900, 0x3392c,
1697                 0x33934, 0x33950,
1698                 0x33958, 0x33958,
1699                 0x33960, 0x3398c,
1700                 0x3399c, 0x339ac,
1701                 0x339c0, 0x339c0,
1702                 0x339c8, 0x339d0,
1703                 0x339d8, 0x339e0,
1704                 0x339ec, 0x33a90,
1705                 0x33a98, 0x33ac4,
1706                 0x33ae4, 0x33b10,
1707                 0x33b24, 0x33b28,
1708                 0x33b38, 0x33b50,
1709                 0x33bf0, 0x33c10,
1710                 0x33c24, 0x33c28,
1711                 0x33c38, 0x33c50,
1712                 0x33cf0, 0x33cfc,
1713                 0x34000, 0x34030,
1714                 0x34100, 0x34168,
1715                 0x34190, 0x341a0,
1716                 0x341a8, 0x341b8,
1717                 0x341c4, 0x341c8,
1718                 0x341d0, 0x341d0,
1719                 0x34200, 0x34320,
1720                 0x34400, 0x344b4,
1721                 0x344c0, 0x3452c,
1722                 0x34540, 0x3461c,
1723                 0x34800, 0x348a0,
1724                 0x348c0, 0x34908,
1725                 0x34910, 0x349b8,
1726                 0x34a00, 0x34a04,
1727                 0x34a0c, 0x34a14,
1728                 0x34a1c, 0x34a2c,
1729                 0x34a44, 0x34a50,
1730                 0x34a74, 0x34a74,
1731                 0x34a7c, 0x34afc,
1732                 0x34b08, 0x34c24,
1733                 0x34d00, 0x34d14,
1734                 0x34d1c, 0x34d3c,
1735                 0x34d44, 0x34d4c,
1736                 0x34d54, 0x34d74,
1737                 0x34d7c, 0x34d7c,
1738                 0x34de0, 0x34de0,
1739                 0x34e00, 0x34ed4,
1740                 0x34f00, 0x34fa4,
1741                 0x34fc0, 0x34fc4,
1742                 0x35000, 0x35004,
1743                 0x35080, 0x350fc,
1744                 0x35208, 0x35220,
1745                 0x3523c, 0x35254,
1746                 0x35300, 0x35300,
1747                 0x35308, 0x3531c,
1748                 0x35338, 0x3533c,
1749                 0x35380, 0x35380,
1750                 0x35388, 0x353a8,
1751                 0x353b4, 0x353b4,
1752                 0x35400, 0x35420,
1753                 0x35438, 0x3543c,
1754                 0x35480, 0x35480,
1755                 0x354a8, 0x354a8,
1756                 0x354b0, 0x354b4,
1757                 0x354c8, 0x354d4,
1758                 0x35a40, 0x35a4c,
1759                 0x35af0, 0x35b20,
1760                 0x35b38, 0x35b3c,
1761                 0x35b80, 0x35b80,
1762                 0x35ba8, 0x35ba8,
1763                 0x35bb0, 0x35bb4,
1764                 0x35bc8, 0x35bd4,
1765                 0x36140, 0x3618c,
1766                 0x361f0, 0x361f4,
1767                 0x36200, 0x36200,
1768                 0x36218, 0x36218,
1769                 0x36400, 0x36400,
1770                 0x36408, 0x3641c,
1771                 0x36618, 0x36620,
1772                 0x36664, 0x36664,
1773                 0x366a8, 0x366a8,
1774                 0x366ec, 0x366ec,
1775                 0x36a00, 0x36abc,
1776                 0x36b00, 0x36b38,
1777                 0x36b20, 0x36b38,
1778                 0x36b40, 0x36b58,
1779                 0x36b60, 0x36b78,
1780                 0x36c00, 0x36c00,
1781                 0x36c08, 0x36c3c,
1782                 0x37000, 0x3702c,
1783                 0x37034, 0x37050,
1784                 0x37058, 0x37058,
1785                 0x37060, 0x3708c,
1786                 0x3709c, 0x370ac,
1787                 0x370c0, 0x370c0,
1788                 0x370c8, 0x370d0,
1789                 0x370d8, 0x370e0,
1790                 0x370ec, 0x3712c,
1791                 0x37134, 0x37150,
1792                 0x37158, 0x37158,
1793                 0x37160, 0x3718c,
1794                 0x3719c, 0x371ac,
1795                 0x371c0, 0x371c0,
1796                 0x371c8, 0x371d0,
1797                 0x371d8, 0x371e0,
1798                 0x371ec, 0x37290,
1799                 0x37298, 0x372c4,
1800                 0x372e4, 0x37390,
1801                 0x37398, 0x373c4,
1802                 0x373e4, 0x3742c,
1803                 0x37434, 0x37450,
1804                 0x37458, 0x37458,
1805                 0x37460, 0x3748c,
1806                 0x3749c, 0x374ac,
1807                 0x374c0, 0x374c0,
1808                 0x374c8, 0x374d0,
1809                 0x374d8, 0x374e0,
1810                 0x374ec, 0x3752c,
1811                 0x37534, 0x37550,
1812                 0x37558, 0x37558,
1813                 0x37560, 0x3758c,
1814                 0x3759c, 0x375ac,
1815                 0x375c0, 0x375c0,
1816                 0x375c8, 0x375d0,
1817                 0x375d8, 0x375e0,
1818                 0x375ec, 0x37690,
1819                 0x37698, 0x376c4,
1820                 0x376e4, 0x37790,
1821                 0x37798, 0x377c4,
1822                 0x377e4, 0x377fc,
1823                 0x37814, 0x37814,
1824                 0x37854, 0x37868,
1825                 0x37880, 0x3788c,
1826                 0x378c0, 0x378d0,
1827                 0x378e8, 0x378ec,
1828                 0x37900, 0x3792c,
1829                 0x37934, 0x37950,
1830                 0x37958, 0x37958,
1831                 0x37960, 0x3798c,
1832                 0x3799c, 0x379ac,
1833                 0x379c0, 0x379c0,
1834                 0x379c8, 0x379d0,
1835                 0x379d8, 0x379e0,
1836                 0x379ec, 0x37a90,
1837                 0x37a98, 0x37ac4,
1838                 0x37ae4, 0x37b10,
1839                 0x37b24, 0x37b28,
1840                 0x37b38, 0x37b50,
1841                 0x37bf0, 0x37c10,
1842                 0x37c24, 0x37c28,
1843                 0x37c38, 0x37c50,
1844                 0x37cf0, 0x37cfc,
1845                 0x40040, 0x40040,
1846                 0x40080, 0x40084,
1847                 0x40100, 0x40100,
1848                 0x40140, 0x401bc,
1849                 0x40200, 0x40214,
1850                 0x40228, 0x40228,
1851                 0x40240, 0x40258,
1852                 0x40280, 0x40280,
1853                 0x40304, 0x40304,
1854                 0x40330, 0x4033c,
1855                 0x41304, 0x413c8,
1856                 0x413d0, 0x413dc,
1857                 0x413f0, 0x413f0,
1858                 0x41400, 0x4140c,
1859                 0x41414, 0x4141c,
1860                 0x41480, 0x414d0,
1861                 0x44000, 0x4407c,
1862                 0x440c0, 0x441ac,
1863                 0x441b4, 0x4427c,
1864                 0x442c0, 0x443ac,
1865                 0x443b4, 0x4447c,
1866                 0x444c0, 0x445ac,
1867                 0x445b4, 0x4467c,
1868                 0x446c0, 0x447ac,
1869                 0x447b4, 0x4487c,
1870                 0x448c0, 0x449ac,
1871                 0x449b4, 0x44a7c,
1872                 0x44ac0, 0x44bac,
1873                 0x44bb4, 0x44c7c,
1874                 0x44cc0, 0x44dac,
1875                 0x44db4, 0x44e7c,
1876                 0x44ec0, 0x44fac,
1877                 0x44fb4, 0x4507c,
1878                 0x450c0, 0x451ac,
1879                 0x451b4, 0x451fc,
1880                 0x45800, 0x45804,
1881                 0x45810, 0x45830,
1882                 0x45840, 0x45860,
1883                 0x45868, 0x45868,
1884                 0x45880, 0x45884,
1885                 0x458a0, 0x458b0,
1886                 0x45a00, 0x45a04,
1887                 0x45a10, 0x45a30,
1888                 0x45a40, 0x45a60,
1889                 0x45a68, 0x45a68,
1890                 0x45a80, 0x45a84,
1891                 0x45aa0, 0x45ab0,
1892                 0x460c0, 0x460e4,
1893                 0x47000, 0x4703c,
1894                 0x47044, 0x4708c,
1895                 0x47200, 0x47250,
1896                 0x47400, 0x47408,
1897                 0x47414, 0x47420,
1898                 0x47600, 0x47618,
1899                 0x47800, 0x47814,
1900                 0x47820, 0x4782c,
1901                 0x50000, 0x50084,
1902                 0x50090, 0x500cc,
1903                 0x50300, 0x50384,
1904                 0x50400, 0x50400,
1905                 0x50800, 0x50884,
1906                 0x50890, 0x508cc,
1907                 0x50b00, 0x50b84,
1908                 0x50c00, 0x50c00,
1909                 0x51000, 0x51020,
1910                 0x51028, 0x510b0,
1911                 0x51300, 0x51324,
1912         };
1913
1914         u32 *buf_end = (u32 *)((char *)buf + buf_size);
1915         const unsigned int *reg_ranges;
1916         int reg_ranges_size, range;
1917         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1918
1919         /* Select the right set of register ranges to dump depending on the
1920          * adapter chip type.
1921          */
1922         switch (chip_version) {
1923         case CHELSIO_T5:
1924                 reg_ranges = t5_reg_ranges;
1925                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1926                 break;
1927
1928         case CHELSIO_T6:
1929                 reg_ranges = t6_reg_ranges;
1930                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1931                 break;
1932
1933         default:
1934                 dev_err(adap,
1935                         "Unsupported chip version %d\n", chip_version);
1936                 return;
1937         }
1938
1939         /* Clear the register buffer and insert the appropriate register
1940          * values selected by the above register ranges.
1941          */
1942         memset(buf, 0, buf_size);
1943         for (range = 0; range < reg_ranges_size; range += 2) {
1944                 unsigned int reg = reg_ranges[range];
1945                 unsigned int last_reg = reg_ranges[range + 1];
1946                 u32 *bufp = (u32 *)((char *)buf + reg);
1947
1948                 /* Iterate across the register range filling in the register
1949                  * buffer but don't write past the end of the register buffer.
1950                  */
1951                 while (reg <= last_reg && bufp < buf_end) {
1952                         *bufp++ = t4_read_reg(adap, reg);
1953                         reg += sizeof(u32);
1954                 }
1955         }
1956 }
1957
1958 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1959 #define EEPROM_DELAY            10              /* 10us per poll spin */
1960 #define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
1961
1962 #define EEPROM_STAT_ADDR        0x7bfc
1963
1964 /**
1965  * Small utility function to wait till any outstanding VPD Access is complete.
1966  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1967  * VPD Access in flight.  This allows us to handle the problem of having a
1968  * previous VPD Access time out and prevent an attempt to inject a new VPD
1969  * Request before any in-flight VPD request has completed.
1970  */
1971 static int t4_seeprom_wait(struct adapter *adapter)
1972 {
1973         unsigned int base = adapter->params.pci.vpd_cap_addr;
1974         int max_poll;
1975
1976         /* If no VPD Access is in flight, we can just return success right
1977          * away.
1978          */
1979         if (!adapter->vpd_busy)
1980                 return 0;
1981
1982         /* Poll the VPD Capability Address/Flag register waiting for it
1983          * to indicate that the operation is complete.
1984          */
1985         max_poll = EEPROM_MAX_POLL;
1986         do {
1987                 u16 val;
1988
1989                 udelay(EEPROM_DELAY);
1990                 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
1991
1992                 /* If the operation is complete, mark the VPD as no longer
1993                  * busy and return success.
1994                  */
1995                 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
1996                         adapter->vpd_busy = 0;
1997                         return 0;
1998                 }
1999         } while (--max_poll);
2000
2001         /* Failure!  Note that we leave the VPD Busy status set in order to
2002          * avoid pushing a new VPD Access request into the VPD Capability till
2003          * the current operation eventually succeeds.  It's a bug to issue a
2004          * new request when an existing request is in flight and will result
2005          * in corrupt hardware state.
2006          */
2007         return -ETIMEDOUT;
2008 }
2009
2010 /**
2011  * t4_seeprom_read - read a serial EEPROM location
2012  * @adapter: adapter to read
2013  * @addr: EEPROM virtual address
2014  * @data: where to store the read data
2015  *
2016  * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2017  * VPD capability.  Note that this function must be called with a virtual
2018  * address.
2019  */
2020 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2021 {
2022         unsigned int base = adapter->params.pci.vpd_cap_addr;
2023         int ret;
2024
2025         /* VPD Accesses must alway be 4-byte aligned!
2026          */
2027         if (addr >= EEPROMVSIZE || (addr & 3))
2028                 return -EINVAL;
2029
2030         /* Wait for any previous operation which may still be in flight to
2031          * complete.
2032          */
2033         ret = t4_seeprom_wait(adapter);
2034         if (ret) {
2035                 dev_err(adapter, "VPD still busy from previous operation\n");
2036                 return ret;
2037         }
2038
2039         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2040          * for our request to complete.  If it doesn't complete, note the
2041          * error and return it to our caller.  Note that we do not reset the
2042          * VPD Busy status!
2043          */
2044         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2045         adapter->vpd_busy = 1;
2046         adapter->vpd_flag = PCI_VPD_ADDR_F;
2047         ret = t4_seeprom_wait(adapter);
2048         if (ret) {
2049                 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2050                 return ret;
2051         }
2052
2053         /* Grab the returned data, swizzle it into our endianness and
2054          * return success.
2055          */
2056         t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2057         *data = le32_to_cpu(*data);
2058         return 0;
2059 }
2060
2061 /**
2062  * t4_seeprom_write - write a serial EEPROM location
2063  * @adapter: adapter to write
2064  * @addr: virtual EEPROM address
2065  * @data: value to write
2066  *
2067  * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2068  * VPD capability.  Note that this function must be called with a virtual
2069  * address.
2070  */
2071 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2072 {
2073         unsigned int base = adapter->params.pci.vpd_cap_addr;
2074         int ret;
2075         u32 stats_reg = 0;
2076         int max_poll;
2077
2078         /* VPD Accesses must alway be 4-byte aligned!
2079          */
2080         if (addr >= EEPROMVSIZE || (addr & 3))
2081                 return -EINVAL;
2082
2083         /* Wait for any previous operation which may still be in flight to
2084          * complete.
2085          */
2086         ret = t4_seeprom_wait(adapter);
2087         if (ret) {
2088                 dev_err(adapter, "VPD still busy from previous operation\n");
2089                 return ret;
2090         }
2091
2092         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2093          * for our request to complete.  If it doesn't complete, note the
2094          * error and return it to our caller.  Note that we do not reset the
2095          * VPD Busy status!
2096          */
2097         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2098                              cpu_to_le32(data));
2099         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2100                              (u16)addr | PCI_VPD_ADDR_F);
2101         adapter->vpd_busy = 1;
2102         adapter->vpd_flag = 0;
2103         ret = t4_seeprom_wait(adapter);
2104         if (ret) {
2105                 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2106                 return ret;
2107         }
2108
2109         /* Reset PCI_VPD_DATA register after a transaction and wait for our
2110          * request to complete. If it doesn't complete, return error.
2111          */
2112         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2113         max_poll = EEPROM_MAX_POLL;
2114         do {
2115                 udelay(EEPROM_DELAY);
2116                 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2117         } while ((stats_reg & 0x1) && --max_poll);
2118         if (!max_poll)
2119                 return -ETIMEDOUT;
2120
2121         /* Return success! */
2122         return 0;
2123 }
2124
2125 /**
2126  * t4_seeprom_wp - enable/disable EEPROM write protection
2127  * @adapter: the adapter
2128  * @enable: whether to enable or disable write protection
2129  *
2130  * Enables or disables write protection on the serial EEPROM.
2131  */
2132 int t4_seeprom_wp(struct adapter *adapter, int enable)
2133 {
2134         return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2135 }
2136
2137 /**
2138  * t4_fw_tp_pio_rw - Access TP PIO through LDST
2139  * @adap: the adapter
2140  * @vals: where the indirect register values are stored/written
2141  * @nregs: how many indirect registers to read/write
2142  * @start_idx: index of first indirect register to read/write
2143  * @rw: Read (1) or Write (0)
2144  *
2145  * Access TP PIO registers through LDST
2146  */
2147 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
2148                      unsigned int start_index, unsigned int rw)
2149 {
2150         int cmd = FW_LDST_ADDRSPC_TP_PIO;
2151         struct fw_ldst_cmd c;
2152         unsigned int i;
2153         int ret;
2154
2155         for (i = 0 ; i < nregs; i++) {
2156                 memset(&c, 0, sizeof(c));
2157                 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
2158                                                 F_FW_CMD_REQUEST |
2159                                                 (rw ? F_FW_CMD_READ :
2160                                                       F_FW_CMD_WRITE) |
2161                                                 V_FW_LDST_CMD_ADDRSPACE(cmd));
2162                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
2163
2164                 c.u.addrval.addr = cpu_to_be32(start_index + i);
2165                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
2166                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2167                 if (ret == 0) {
2168                         if (rw)
2169                                 vals[i] = be32_to_cpu(c.u.addrval.val);
2170                 }
2171         }
2172 }
2173
2174 /**
2175  * t4_read_rss_key - read the global RSS key
2176  * @adap: the adapter
2177  * @key: 10-entry array holding the 320-bit RSS key
2178  *
2179  * Reads the global 320-bit RSS key.
2180  */
2181 void t4_read_rss_key(struct adapter *adap, u32 *key)
2182 {
2183         t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 1);
2184 }
2185
2186 /**
2187  * t4_write_rss_key - program one of the RSS keys
2188  * @adap: the adapter
2189  * @key: 10-entry array holding the 320-bit RSS key
2190  * @idx: which RSS key to write
2191  *
2192  * Writes one of the RSS keys with the given 320-bit value.  If @idx is
2193  * 0..15 the corresponding entry in the RSS key table is written,
2194  * otherwise the global RSS key is written.
2195  */
2196 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
2197 {
2198         u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
2199         u8 rss_key_addr_cnt = 16;
2200
2201         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
2202          * allows access to key addresses 16-63 by using KeyWrAddrX
2203          * as index[5:4](upper 2) into key table
2204          */
2205         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
2206             (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
2207                 rss_key_addr_cnt = 32;
2208
2209         t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
2210
2211         if (idx >= 0 && idx < rss_key_addr_cnt) {
2212                 if (rss_key_addr_cnt > 16)
2213                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2214                                      V_KEYWRADDRX(idx >> 4) |
2215                                      V_T6_VFWRADDR(idx) | F_KEYWREN);
2216                 else
2217                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2218                                      V_KEYWRADDR(idx) | F_KEYWREN);
2219         }
2220 }
2221
2222 /**
2223  * t4_config_rss_range - configure a portion of the RSS mapping table
2224  * @adapter: the adapter
2225  * @mbox: mbox to use for the FW command
2226  * @viid: virtual interface whose RSS subtable is to be written
2227  * @start: start entry in the table to write
2228  * @n: how many table entries to write
2229  * @rspq: values for the "response queue" (Ingress Queue) lookup table
2230  * @nrspq: number of values in @rspq
2231  *
2232  * Programs the selected part of the VI's RSS mapping table with the
2233  * provided values.  If @nrspq < @n the supplied values are used repeatedly
2234  * until the full table range is populated.
2235  *
2236  * The caller must ensure the values in @rspq are in the range allowed for
2237  * @viid.
2238  */
2239 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2240                         int start, int n, const u16 *rspq, unsigned int nrspq)
2241 {
2242         int ret;
2243         const u16 *rsp = rspq;
2244         const u16 *rsp_end = rspq + nrspq;
2245         struct fw_rss_ind_tbl_cmd cmd;
2246
2247         memset(&cmd, 0, sizeof(cmd));
2248         cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2249                                      F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2250                                      V_FW_RSS_IND_TBL_CMD_VIID(viid));
2251         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2252
2253         /*
2254          * Each firmware RSS command can accommodate up to 32 RSS Ingress
2255          * Queue Identifiers.  These Ingress Queue IDs are packed three to
2256          * a 32-bit word as 10-bit values with the upper remaining 2 bits
2257          * reserved.
2258          */
2259         while (n > 0) {
2260                 int nq = min(n, 32);
2261                 int nq_packed = 0;
2262                 __be32 *qp = &cmd.iq0_to_iq2;
2263
2264                 /*
2265                  * Set up the firmware RSS command header to send the next
2266                  * "nq" Ingress Queue IDs to the firmware.
2267                  */
2268                 cmd.niqid = cpu_to_be16(nq);
2269                 cmd.startidx = cpu_to_be16(start);
2270
2271                 /*
2272                  * "nq" more done for the start of the next loop.
2273                  */
2274                 start += nq;
2275                 n -= nq;
2276
2277                 /*
2278                  * While there are still Ingress Queue IDs to stuff into the
2279                  * current firmware RSS command, retrieve them from the
2280                  * Ingress Queue ID array and insert them into the command.
2281                  */
2282                 while (nq > 0) {
2283                         /*
2284                          * Grab up to the next 3 Ingress Queue IDs (wrapping
2285                          * around the Ingress Queue ID array if necessary) and
2286                          * insert them into the firmware RSS command at the
2287                          * current 3-tuple position within the commad.
2288                          */
2289                         u16 qbuf[3];
2290                         u16 *qbp = qbuf;
2291                         int nqbuf = min(3, nq);
2292
2293                         nq -= nqbuf;
2294                         qbuf[0] = 0;
2295                         qbuf[1] = 0;
2296                         qbuf[2] = 0;
2297                         while (nqbuf && nq_packed < 32) {
2298                                 nqbuf--;
2299                                 nq_packed++;
2300                                 *qbp++ = *rsp++;
2301                                 if (rsp >= rsp_end)
2302                                         rsp = rspq;
2303                         }
2304                         *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2305                                             V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2306                                             V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2307                 }
2308
2309                 /*
2310                  * Send this portion of the RRS table update to the firmware;
2311                  * bail out on any errors.
2312                  */
2313                 if (is_pf4(adapter))
2314                         ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd),
2315                                          NULL);
2316                 else
2317                         ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
2318                 if (ret)
2319                         return ret;
2320         }
2321
2322         return 0;
2323 }
2324
2325 /**
2326  * t4_config_vi_rss - configure per VI RSS settings
2327  * @adapter: the adapter
2328  * @mbox: mbox to use for the FW command
2329  * @viid: the VI id
2330  * @flags: RSS flags
2331  * @defq: id of the default RSS queue for the VI.
2332  *
2333  * Configures VI-specific RSS properties.
2334  */
2335 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2336                      unsigned int flags, unsigned int defq)
2337 {
2338         struct fw_rss_vi_config_cmd c;
2339
2340         memset(&c, 0, sizeof(c));
2341         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2342                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2343                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2344         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2345         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2346                         V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2347         if (is_pf4(adapter))
2348                 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2349         else
2350                 return t4vf_wr_mbox(adapter, &c, sizeof(c), NULL);
2351 }
2352
2353 /**
2354  * t4_read_config_vi_rss - read the configured per VI RSS settings
2355  * @adapter: the adapter
2356  * @mbox: mbox to use for the FW command
2357  * @viid: the VI id
2358  * @flags: where to place the configured flags
2359  * @defq: where to place the id of the default RSS queue for the VI.
2360  *
2361  * Read configured VI-specific RSS properties.
2362  */
2363 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2364                           u64 *flags, unsigned int *defq)
2365 {
2366         struct fw_rss_vi_config_cmd c;
2367         unsigned int result;
2368         int ret;
2369
2370         memset(&c, 0, sizeof(c));
2371         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2372                                    F_FW_CMD_REQUEST | F_FW_CMD_READ |
2373                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2374         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2375         ret = t4_wr_mbox(adapter, mbox, &c, sizeof(c), &c);
2376         if (!ret) {
2377                 result = be32_to_cpu(c.u.basicvirtual.defaultq_to_udpen);
2378                 if (defq)
2379                         *defq = G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(result);
2380                 if (flags)
2381                         *flags = result & M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ;
2382         }
2383
2384         return ret;
2385 }
2386
2387 /**
2388  * init_cong_ctrl - initialize congestion control parameters
2389  * @a: the alpha values for congestion control
2390  * @b: the beta values for congestion control
2391  *
2392  * Initialize the congestion control parameters.
2393  */
2394 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2395 {
2396         int i;
2397
2398         for (i = 0; i < 9; i++) {
2399                 a[i] = 1;
2400                 b[i] = 0;
2401         }
2402
2403         a[9] = 2;
2404         a[10] = 3;
2405         a[11] = 4;
2406         a[12] = 5;
2407         a[13] = 6;
2408         a[14] = 7;
2409         a[15] = 8;
2410         a[16] = 9;
2411         a[17] = 10;
2412         a[18] = 14;
2413         a[19] = 17;
2414         a[20] = 21;
2415         a[21] = 25;
2416         a[22] = 30;
2417         a[23] = 35;
2418         a[24] = 45;
2419         a[25] = 60;
2420         a[26] = 80;
2421         a[27] = 100;
2422         a[28] = 200;
2423         a[29] = 300;
2424         a[30] = 400;
2425         a[31] = 500;
2426
2427         b[9] = 1;
2428         b[10] = 1;
2429         b[11] = 2;
2430         b[12] = 2;
2431         b[13] = 3;
2432         b[14] = 3;
2433         b[15] = 3;
2434         b[16] = 3;
2435         b[17] = 4;
2436         b[18] = 4;
2437         b[19] = 4;
2438         b[20] = 4;
2439         b[21] = 4;
2440         b[22] = 5;
2441         b[23] = 5;
2442         b[24] = 5;
2443         b[25] = 5;
2444         b[26] = 5;
2445         b[27] = 5;
2446         b[28] = 6;
2447         b[29] = 6;
2448         b[30] = 7;
2449         b[31] = 7;
2450 }
2451
2452 #define INIT_CMD(var, cmd, rd_wr) do { \
2453         (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2454                         F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2455         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2456 } while (0)
2457
2458 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2459 {
2460         u32 cclk_param, cclk_val;
2461         int ret;
2462
2463         /*
2464          * Ask firmware for the Core Clock since it knows how to translate the
2465          * Reference Clock ('V2') VPD field into a Core Clock value ...
2466          */
2467         cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2468                       V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2469         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2470                               1, &cclk_param, &cclk_val);
2471         if (ret) {
2472                 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2473                         __func__, ret);
2474                 return ret;
2475         }
2476
2477         p->cclk = cclk_val;
2478         dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2479         return 0;
2480 }
2481
2482 /**
2483  * t4_get_pfres - retrieve VF resource limits
2484  * @adapter: the adapter
2485  *
2486  * Retrieves configured resource limits and capabilities for a physical
2487  * function.  The results are stored in @adapter->pfres.
2488  */
2489 int t4_get_pfres(struct adapter *adapter)
2490 {
2491         struct pf_resources *pfres = &adapter->params.pfres;
2492         struct fw_pfvf_cmd cmd, rpl;
2493         u32 word;
2494         int v;
2495
2496         /*
2497          * Execute PFVF Read command to get VF resource limits; bail out early
2498          * with error on command failure.
2499          */
2500         memset(&cmd, 0, sizeof(cmd));
2501         cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) |
2502                                     F_FW_CMD_REQUEST |
2503                                     F_FW_CMD_READ |
2504                                     V_FW_PFVF_CMD_PFN(adapter->pf) |
2505                                     V_FW_PFVF_CMD_VFN(0));
2506         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2507         v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2508         if (v != FW_SUCCESS)
2509                 return v;
2510
2511         /*
2512          * Extract PF resource limits and return success.
2513          */
2514         word = be32_to_cpu(rpl.niqflint_niq);
2515         pfres->niqflint = G_FW_PFVF_CMD_NIQFLINT(word);
2516
2517         word = be32_to_cpu(rpl.type_to_neq);
2518         pfres->neq = G_FW_PFVF_CMD_NEQ(word);
2519
2520         word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2521         pfres->nethctrl = G_FW_PFVF_CMD_NETHCTRL(word);
2522
2523         return 0;
2524 }
2525
2526 /* serial flash and firmware constants and flash config file constants */
2527 enum {
2528         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2529
2530         /* flash command opcodes */
2531         SF_PROG_PAGE    = 2,          /* program page */
2532         SF_WR_DISABLE   = 4,          /* disable writes */
2533         SF_RD_STATUS    = 5,          /* read status register */
2534         SF_WR_ENABLE    = 6,          /* enable writes */
2535         SF_RD_DATA_FAST = 0xb,        /* read flash */
2536         SF_RD_ID        = 0x9f,       /* read ID */
2537         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2538 };
2539
2540 /**
2541  * sf1_read - read data from the serial flash
2542  * @adapter: the adapter
2543  * @byte_cnt: number of bytes to read
2544  * @cont: whether another operation will be chained
2545  * @lock: whether to lock SF for PL access only
2546  * @valp: where to store the read data
2547  *
2548  * Reads up to 4 bytes of data from the serial flash.  The location of
2549  * the read needs to be specified prior to calling this by issuing the
2550  * appropriate commands to the serial flash.
2551  */
2552 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2553                     int lock, u32 *valp)
2554 {
2555         int ret;
2556
2557         if (!byte_cnt || byte_cnt > 4)
2558                 return -EINVAL;
2559         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2560                 return -EBUSY;
2561         t4_write_reg(adapter, A_SF_OP,
2562                      V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2563         ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2564         if (!ret)
2565                 *valp = t4_read_reg(adapter, A_SF_DATA);
2566         return ret;
2567 }
2568
2569 /**
2570  * sf1_write - write data to the serial flash
2571  * @adapter: the adapter
2572  * @byte_cnt: number of bytes to write
2573  * @cont: whether another operation will be chained
2574  * @lock: whether to lock SF for PL access only
2575  * @val: value to write
2576  *
2577  * Writes up to 4 bytes of data to the serial flash.  The location of
2578  * the write needs to be specified prior to calling this by issuing the
2579  * appropriate commands to the serial flash.
2580  */
2581 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2582                      int lock, u32 val)
2583 {
2584         if (!byte_cnt || byte_cnt > 4)
2585                 return -EINVAL;
2586         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2587                 return -EBUSY;
2588         t4_write_reg(adapter, A_SF_DATA, val);
2589         t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2590                      V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2591         return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2592 }
2593
2594 /**
2595  * t4_read_flash - read words from serial flash
2596  * @adapter: the adapter
2597  * @addr: the start address for the read
2598  * @nwords: how many 32-bit words to read
2599  * @data: where to store the read data
2600  * @byte_oriented: whether to store data as bytes or as words
2601  *
2602  * Read the specified number of 32-bit words from the serial flash.
2603  * If @byte_oriented is set the read data is stored as a byte array
2604  * (i.e., big-endian), otherwise as 32-bit words in the platform's
2605  * natural endianness.
2606  */
2607 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2608                   unsigned int nwords, u32 *data, int byte_oriented)
2609 {
2610         int ret;
2611
2612         if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2613             (addr & 3))
2614                 return -EINVAL;
2615
2616         addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2617
2618         ret = sf1_write(adapter, 4, 1, 0, addr);
2619         if (ret != 0)
2620                 return ret;
2621
2622         ret = sf1_read(adapter, 1, 1, 0, data);
2623         if (ret != 0)
2624                 return ret;
2625
2626         for ( ; nwords; nwords--, data++) {
2627                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2628                 if (nwords == 1)
2629                         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
2630                 if (ret)
2631                         return ret;
2632                 if (byte_oriented)
2633                         *data = cpu_to_be32(*data);
2634         }
2635         return 0;
2636 }
2637
2638 /**
2639  * t4_get_exprom_version - return the Expansion ROM version (if any)
2640  * @adapter: the adapter
2641  * @vers: where to place the version
2642  *
2643  * Reads the Expansion ROM header from FLASH and returns the version
2644  * number (if present) through the @vers return value pointer.  We return
2645  * this in the Firmware Version Format since it's convenient.  Return
2646  * 0 on success, -ENOENT if no Expansion ROM is present.
2647  */
2648 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2649 {
2650         struct exprom_header {
2651                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
2652                 unsigned char hdr_ver[4];       /* Expansion ROM version */
2653         } *hdr;
2654         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2655                                            sizeof(u32))];
2656         int ret;
2657
2658         ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2659                             ARRAY_SIZE(exprom_header_buf),
2660                             exprom_header_buf, 0);
2661         if (ret)
2662                 return ret;
2663
2664         hdr = (struct exprom_header *)exprom_header_buf;
2665         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2666                 return -ENOENT;
2667
2668         *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2669                  V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2670                  V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2671                  V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2672         return 0;
2673 }
2674
2675 /**
2676  * t4_get_fw_version - read the firmware version
2677  * @adapter: the adapter
2678  * @vers: where to place the version
2679  *
2680  * Reads the FW version from flash.
2681  */
2682 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2683 {
2684         return t4_read_flash(adapter, FLASH_FW_START +
2685                              offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2686 }
2687
2688 /**
2689  *     t4_get_bs_version - read the firmware bootstrap version
2690  *     @adapter: the adapter
2691  *     @vers: where to place the version
2692  *
2693  *     Reads the FW Bootstrap version from flash.
2694  */
2695 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2696 {
2697         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2698                              offsetof(struct fw_hdr, fw_ver), 1,
2699                              vers, 0);
2700 }
2701
2702 /**
2703  * t4_get_tp_version - read the TP microcode version
2704  * @adapter: the adapter
2705  * @vers: where to place the version
2706  *
2707  * Reads the TP microcode version from flash.
2708  */
2709 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2710 {
2711         return t4_read_flash(adapter, FLASH_FW_START +
2712                              offsetof(struct fw_hdr, tp_microcode_ver),
2713                              1, vers, 0);
2714 }
2715
2716 /**
2717  * t4_get_version_info - extract various chip/firmware version information
2718  * @adapter: the adapter
2719  *
2720  * Reads various chip/firmware version numbers and stores them into the
2721  * adapter Adapter Parameters structure.  If any of the efforts fails
2722  * the first failure will be returned, but all of the version numbers
2723  * will be read.
2724  */
2725 int t4_get_version_info(struct adapter *adapter)
2726 {
2727         int ret = 0;
2728
2729 #define FIRST_RET(__getvinfo) \
2730         do { \
2731                 int __ret = __getvinfo; \
2732                 if (__ret && !ret) \
2733                         ret = __ret; \
2734         } while (0)
2735
2736         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2737         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2738         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2739         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2740
2741 #undef FIRST_RET
2742
2743         return ret;
2744 }
2745
2746 /**
2747  * t4_dump_version_info - dump all of the adapter configuration IDs
2748  * @adapter: the adapter
2749  *
2750  * Dumps all of the various bits of adapter configuration version/revision
2751  * IDs information.  This is typically called at some point after
2752  * t4_get_version_info() has been called.
2753  */
2754 void t4_dump_version_info(struct adapter *adapter)
2755 {
2756         /**
2757          * Device information.
2758          */
2759         dev_info(adapter, "Chelsio rev %d\n",
2760                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
2761
2762         /**
2763          * Firmware Version.
2764          */
2765         if (!adapter->params.fw_vers)
2766                 dev_warn(adapter, "No firmware loaded\n");
2767         else
2768                 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2769                          G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2770                          G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2771                          G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2772                          G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2773
2774         /**
2775          * Bootstrap Firmware Version.
2776          */
2777         if (!adapter->params.bs_vers)
2778                 dev_warn(adapter, "No bootstrap loaded\n");
2779         else
2780                 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2781                          G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2782                          G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2783                          G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2784                          G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2785
2786         /**
2787          * TP Microcode Version.
2788          */
2789         if (!adapter->params.tp_vers)
2790                 dev_warn(adapter, "No TP Microcode loaded\n");
2791         else
2792                 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2793                          G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2794                          G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2795                          G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2796                          G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2797
2798         /**
2799          * Expansion ROM version.
2800          */
2801         if (!adapter->params.er_vers)
2802                 dev_info(adapter, "No Expansion ROM loaded\n");
2803         else
2804                 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2805                          G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2806                          G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2807                          G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2808                          G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2809 }
2810
2811 /**
2812  * t4_link_l1cfg_core - apply link configuration to MAC/PHY
2813  * @pi: the port info
2814  * @caps: link capabilities to configure
2815  * @sleep_ok: if true we may sleep while awaiting command completion
2816  *
2817  * Set up a port's MAC and PHY according to a desired link configuration.
2818  * - If the PHY can auto-negotiate first decide what to advertise, then
2819  *   enable/disable auto-negotiation as desired, and reset.
2820  * - If the PHY does not auto-negotiate just reset it.
2821  * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2822  *   otherwise do it later based on the outcome of auto-negotiation.
2823  */
2824 int t4_link_l1cfg_core(struct port_info *pi, u32 caps, u8 sleep_ok)
2825 {
2826         struct link_config *lc = &pi->link_cfg;
2827         struct adapter *adap = pi->adapter;
2828         struct fw_port_cmd cmd;
2829         int ret;
2830
2831         memset(&cmd, 0, sizeof(cmd));
2832         cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2833                                        F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2834                                        V_FW_PORT_CMD_PORTID(pi->port_id));
2835         cmd.action_to_len16 =
2836                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) |
2837                             FW_LEN16(cmd));
2838
2839         cmd.u.l1cfg32.rcap32 = cpu_to_be32(caps);
2840
2841         if (sleep_ok)
2842                 ret = t4_wr_mbox(adap, adap->mbox, &cmd, sizeof(cmd), NULL);
2843         else
2844                 ret = t4_wr_mbox_ns(adap, adap->mbox, &cmd, sizeof(cmd), NULL);
2845
2846         if (ret == FW_SUCCESS)
2847                 lc->link_caps = caps;
2848         else
2849                 dev_err(adap,
2850                         "Requested Port Capabilities %#x rejected, error %d\n",
2851                         caps, ret);
2852
2853         return ret;
2854 }
2855
2856 /**
2857  * t4_flash_cfg_addr - return the address of the flash configuration file
2858  * @adapter: the adapter
2859  *
2860  * Return the address within the flash where the Firmware Configuration
2861  * File is stored, or an error if the device FLASH is too small to contain
2862  * a Firmware Configuration File.
2863  */
2864 int t4_flash_cfg_addr(struct adapter *adapter)
2865 {
2866         /*
2867          * If the device FLASH isn't large enough to hold a Firmware
2868          * Configuration File, return an error.
2869          */
2870         if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2871                 return -ENOSPC;
2872
2873         return FLASH_CFG_START;
2874 }
2875
2876 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2877
2878 /**
2879  * t4_intr_enable - enable interrupts
2880  * @adapter: the adapter whose interrupts should be enabled
2881  *
2882  * Enable PF-specific interrupts for the calling function and the top-level
2883  * interrupt concentrator for global interrupts.  Interrupts are already
2884  * enabled at each module, here we just enable the roots of the interrupt
2885  * hierarchies.
2886  *
2887  * Note: this function should be called only when the driver manages
2888  * non PF-specific interrupts from the various HW modules.  Only one PCI
2889  * function at a time should be doing this.
2890  */
2891 void t4_intr_enable(struct adapter *adapter)
2892 {
2893         u32 val = 0;
2894         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2895         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2896                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2897
2898         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2899                 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2900         t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2901                      F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2902                      F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2903                      F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2904                      F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2905                      F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2906                      F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2907         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2908         t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2909 }
2910
2911 /**
2912  * t4_intr_disable - disable interrupts
2913  * @adapter: the adapter whose interrupts should be disabled
2914  *
2915  * Disable interrupts.  We only disable the top-level interrupt
2916  * concentrators.  The caller must be a PCI function managing global
2917  * interrupts.
2918  */
2919 void t4_intr_disable(struct adapter *adapter)
2920 {
2921         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2922         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2923                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2924
2925         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2926         t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2927 }
2928
2929 /**
2930  * t4_get_port_type_description - return Port Type string description
2931  * @port_type: firmware Port Type enumeration
2932  */
2933 const char *t4_get_port_type_description(enum fw_port_type port_type)
2934 {
2935         static const char * const port_type_description[] = {
2936                 "Fiber_XFI",
2937                 "Fiber_XAUI",
2938                 "BT_SGMII",
2939                 "BT_XFI",
2940                 "BT_XAUI",
2941                 "KX4",
2942                 "CX4",
2943                 "KX",
2944                 "KR",
2945                 "SFP",
2946                 "BP_AP",
2947                 "BP4_AP",
2948                 "QSFP_10G",
2949                 "QSA",
2950                 "QSFP",
2951                 "BP40_BA",
2952                 "KR4_100G",
2953                 "CR4_QSFP",
2954                 "CR_QSFP",
2955                 "CR2_QSFP",
2956                 "SFP28",
2957                 "KR_SFP28",
2958         };
2959
2960         if (port_type < ARRAY_SIZE(port_type_description))
2961                 return port_type_description[port_type];
2962         return "UNKNOWN";
2963 }
2964
2965 /**
2966  * t4_get_mps_bg_map - return the buffer groups associated with a port
2967  * @adap: the adapter
2968  * @pidx: the port index
2969  *
2970  * Returns a bitmap indicating which MPS buffer groups are associated
2971  * with the given port.  Bit i is set if buffer group i is used by the
2972  * port.
2973  */
2974 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
2975 {
2976         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2977         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
2978                                                           A_MPS_CMN_CTL));
2979
2980         if (pidx >= nports) {
2981                 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
2982                          pidx, nports);
2983                 return 0;
2984         }
2985
2986         switch (chip_version) {
2987         case CHELSIO_T4:
2988         case CHELSIO_T5:
2989                 switch (nports) {
2990                 case 1: return 0xf;
2991                 case 2: return 3 << (2 * pidx);
2992                 case 4: return 1 << pidx;
2993                 }
2994                 break;
2995
2996         case CHELSIO_T6:
2997                 switch (nports) {
2998                 case 2: return 1 << (2 * pidx);
2999                 }
3000                 break;
3001         }
3002
3003         dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
3004                 chip_version, nports);
3005         return 0;
3006 }
3007
3008 /**
3009  * t4_get_tp_ch_map - return TP ingress channels associated with a port
3010  * @adapter: the adapter
3011  * @pidx: the port index
3012  *
3013  * Returns a bitmap indicating which TP Ingress Channels are associated with
3014  * a given Port.  Bit i is set if TP Ingress Channel i is used by the Port.
3015  */
3016 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
3017 {
3018         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
3019         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
3020                                                           A_MPS_CMN_CTL));
3021
3022         if (pidx >= nports) {
3023                 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
3024                          pidx, nports);
3025                 return 0;
3026         }
3027
3028         switch (chip_version) {
3029         case CHELSIO_T4:
3030         case CHELSIO_T5:
3031                 /* Note that this happens to be the same values as the MPS
3032                  * Buffer Group Map for these Chips.  But we replicate the code
3033                  * here because they're really separate concepts.
3034                  */
3035                 switch (nports) {
3036                 case 1: return 0xf;
3037                 case 2: return 3 << (2 * pidx);
3038                 case 4: return 1 << pidx;
3039                 }
3040                 break;
3041
3042         case CHELSIO_T6:
3043                 switch (nports) {
3044                 case 2: return 1 << pidx;
3045                 }
3046                 break;
3047         }
3048
3049         dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
3050                 chip_version, nports);
3051         return 0;
3052 }
3053
3054 /**
3055  * t4_get_port_stats - collect port statistics
3056  * @adap: the adapter
3057  * @idx: the port index
3058  * @p: the stats structure to fill
3059  *
3060  * Collect statistics related to the given port from HW.
3061  */
3062 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
3063 {
3064         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3065         u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
3066
3067 #define GET_STAT(name) \
3068         t4_read_reg64(adap, \
3069                       (is_t4(adap->params.chip) ? \
3070                        PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
3071                        T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
3072 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
3073
3074         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
3075         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
3076         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
3077         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
3078         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
3079         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
3080         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
3081         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
3082         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
3083         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
3084         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
3085         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
3086         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
3087         p->tx_drop             = GET_STAT(TX_PORT_DROP);
3088         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
3089         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
3090         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
3091         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
3092         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
3093         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
3094         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
3095         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
3096         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
3097
3098         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3099                 if (stat_ctl & F_COUNTPAUSESTATTX) {
3100                         p->tx_frames -= p->tx_pause;
3101                         p->tx_octets -= p->tx_pause * 64;
3102                 }
3103                 if (stat_ctl & F_COUNTPAUSEMCTX)
3104                         p->tx_mcast_frames -= p->tx_pause;
3105         }
3106
3107         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
3108         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
3109         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
3110         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
3111         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
3112         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
3113         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
3114         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
3115         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
3116         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
3117         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
3118         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
3119         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
3120         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
3121         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
3122         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
3123         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3124         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
3125         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
3126         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
3127         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
3128         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
3129         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
3130         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
3131         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
3132         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
3133         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
3134
3135         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3136                 if (stat_ctl & F_COUNTPAUSESTATRX) {
3137                         p->rx_frames -= p->rx_pause;
3138                         p->rx_octets -= p->rx_pause * 64;
3139                 }
3140                 if (stat_ctl & F_COUNTPAUSEMCRX)
3141                         p->rx_mcast_frames -= p->rx_pause;
3142         }
3143
3144         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3145         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3146         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3147         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3148         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3149         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3150         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3151         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3152
3153 #undef GET_STAT
3154 #undef GET_STAT_COM
3155 }
3156
3157 /**
3158  * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3159  * @adap: The adapter
3160  * @idx: The port
3161  * @stats: Current stats to fill
3162  * @offset: Previous stats snapshot
3163  */
3164 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3165                               struct port_stats *stats,
3166                               struct port_stats *offset)
3167 {
3168         u64 *s, *o;
3169         unsigned int i;
3170
3171         t4_get_port_stats(adap, idx, stats);
3172         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3173              i < (sizeof(struct port_stats) / sizeof(u64));
3174              i++, s++, o++)
3175                 *s -= *o;
3176 }
3177
3178 /**
3179  * t4_clr_port_stats - clear port statistics
3180  * @adap: the adapter
3181  * @idx: the port index
3182  *
3183  * Clear HW statistics for the given port.
3184  */
3185 void t4_clr_port_stats(struct adapter *adap, int idx)
3186 {
3187         unsigned int i;
3188         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3189         u32 port_base_addr;
3190
3191         if (is_t4(adap->params.chip))
3192                 port_base_addr = PORT_BASE(idx);
3193         else
3194                 port_base_addr = T5_PORT_BASE(idx);
3195
3196         for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3197              i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3198                 t4_write_reg(adap, port_base_addr + i, 0);
3199         for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3200              i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3201                 t4_write_reg(adap, port_base_addr + i, 0);
3202         for (i = 0; i < 4; i++)
3203                 if (bgmap & (1 << i)) {
3204                         t4_write_reg(adap,
3205                                      A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3206                                      i * 8, 0);
3207                         t4_write_reg(adap,
3208                                      A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3209                                      i * 8, 0);
3210                 }
3211 }
3212
3213 /**
3214  * t4_fw_hello - establish communication with FW
3215  * @adap: the adapter
3216  * @mbox: mailbox to use for the FW command
3217  * @evt_mbox: mailbox to receive async FW events
3218  * @master: specifies the caller's willingness to be the device master
3219  * @state: returns the current device state (if non-NULL)
3220  *
3221  * Issues a command to establish communication with FW.  Returns either
3222  * an error (negative integer) or the mailbox of the Master PF.
3223  */
3224 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3225                 enum dev_master master, enum dev_state *state)
3226 {
3227         int ret;
3228         struct fw_hello_cmd c;
3229         u32 v;
3230         unsigned int master_mbox;
3231         int retries = FW_CMD_HELLO_RETRIES;
3232
3233 retry:
3234         memset(&c, 0, sizeof(c));
3235         INIT_CMD(c, HELLO, WRITE);
3236         c.err_to_clearinit = cpu_to_be32(
3237                         V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3238                         V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3239                         V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3240                                                 M_FW_HELLO_CMD_MBMASTER) |
3241                         V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3242                         V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3243                         F_FW_HELLO_CMD_CLEARINIT);
3244
3245         /*
3246          * Issue the HELLO command to the firmware.  If it's not successful
3247          * but indicates that we got a "busy" or "timeout" condition, retry
3248          * the HELLO until we exhaust our retry limit.  If we do exceed our
3249          * retry limit, check to see if the firmware left us any error
3250          * information and report that if so ...
3251          */
3252         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3253         if (ret != FW_SUCCESS) {
3254                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3255                         goto retry;
3256                 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3257                         t4_report_fw_error(adap);
3258                 return ret;
3259         }
3260
3261         v = be32_to_cpu(c.err_to_clearinit);
3262         master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3263         if (state) {
3264                 if (v & F_FW_HELLO_CMD_ERR)
3265                         *state = DEV_STATE_ERR;
3266                 else if (v & F_FW_HELLO_CMD_INIT)
3267                         *state = DEV_STATE_INIT;
3268                 else
3269                         *state = DEV_STATE_UNINIT;
3270         }
3271
3272         /*
3273          * If we're not the Master PF then we need to wait around for the
3274          * Master PF Driver to finish setting up the adapter.
3275          *
3276          * Note that we also do this wait if we're a non-Master-capable PF and
3277          * there is no current Master PF; a Master PF may show up momentarily
3278          * and we wouldn't want to fail pointlessly.  (This can happen when an
3279          * OS loads lots of different drivers rapidly at the same time).  In
3280          * this case, the Master PF returned by the firmware will be
3281          * M_PCIE_FW_MASTER so the test below will work ...
3282          */
3283         if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3284             master_mbox != mbox) {
3285                 int waiting = FW_CMD_HELLO_TIMEOUT;
3286
3287                 /*
3288                  * Wait for the firmware to either indicate an error or
3289                  * initialized state.  If we see either of these we bail out
3290                  * and report the issue to the caller.  If we exhaust the
3291                  * "hello timeout" and we haven't exhausted our retries, try
3292                  * again.  Otherwise bail with a timeout error.
3293                  */
3294                 for (;;) {
3295                         u32 pcie_fw;
3296
3297                         msleep(50);
3298                         waiting -= 50;
3299
3300                         /*
3301                          * If neither Error nor Initialialized are indicated
3302                          * by the firmware keep waiting till we exaust our
3303                          * timeout ... and then retry if we haven't exhausted
3304                          * our retries ...
3305                          */
3306                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3307                         if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3308                                 if (waiting <= 0) {
3309                                         if (retries-- > 0)
3310                                                 goto retry;
3311
3312                                         return -ETIMEDOUT;
3313                                 }
3314                                 continue;
3315                         }
3316
3317                         /*
3318                          * We either have an Error or Initialized condition
3319                          * report errors preferentially.
3320                          */
3321                         if (state) {
3322                                 if (pcie_fw & F_PCIE_FW_ERR)
3323                                         *state = DEV_STATE_ERR;
3324                                 else if (pcie_fw & F_PCIE_FW_INIT)
3325                                         *state = DEV_STATE_INIT;
3326                         }
3327
3328                         /*
3329                          * If we arrived before a Master PF was selected and
3330                          * there's not a valid Master PF, grab its identity
3331                          * for our caller.
3332                          */
3333                         if (master_mbox == M_PCIE_FW_MASTER &&
3334                             (pcie_fw & F_PCIE_FW_MASTER_VLD))
3335                                 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3336                         break;
3337                 }
3338         }
3339
3340         return master_mbox;
3341 }
3342
3343 /**
3344  * t4_fw_bye - end communication with FW
3345  * @adap: the adapter
3346  * @mbox: mailbox to use for the FW command
3347  *
3348  * Issues a command to terminate communication with FW.
3349  */
3350 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3351 {
3352         struct fw_bye_cmd c;
3353
3354         memset(&c, 0, sizeof(c));
3355         INIT_CMD(c, BYE, WRITE);
3356         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3357 }
3358
3359 /**
3360  * t4_fw_reset - issue a reset to FW
3361  * @adap: the adapter
3362  * @mbox: mailbox to use for the FW command
3363  * @reset: specifies the type of reset to perform
3364  *
3365  * Issues a reset command of the specified type to FW.
3366  */
3367 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3368 {
3369         struct fw_reset_cmd c;
3370
3371         memset(&c, 0, sizeof(c));
3372         INIT_CMD(c, RESET, WRITE);
3373         c.val = cpu_to_be32(reset);
3374         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3375 }
3376
3377 /**
3378  * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3379  * @adap: the adapter
3380  * @mbox: mailbox to use for the FW RESET command (if desired)
3381  * @force: force uP into RESET even if FW RESET command fails
3382  *
3383  * Issues a RESET command to firmware (if desired) with a HALT indication
3384  * and then puts the microprocessor into RESET state.  The RESET command
3385  * will only be issued if a legitimate mailbox is provided (mbox <=
3386  * M_PCIE_FW_MASTER).
3387  *
3388  * This is generally used in order for the host to safely manipulate the
3389  * adapter without fear of conflicting with whatever the firmware might
3390  * be doing.  The only way out of this state is to RESTART the firmware
3391  * ...
3392  */
3393 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3394 {
3395         int ret = 0;
3396
3397         /*
3398          * If a legitimate mailbox is provided, issue a RESET command
3399          * with a HALT indication.
3400          */
3401         if (mbox <= M_PCIE_FW_MASTER) {
3402                 struct fw_reset_cmd c;
3403
3404                 memset(&c, 0, sizeof(c));
3405                 INIT_CMD(c, RESET, WRITE);
3406                 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3407                 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3408                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3409         }
3410
3411         /*
3412          * Normally we won't complete the operation if the firmware RESET
3413          * command fails but if our caller insists we'll go ahead and put the
3414          * uP into RESET.  This can be useful if the firmware is hung or even
3415          * missing ...  We'll have to take the risk of putting the uP into
3416          * RESET without the cooperation of firmware in that case.
3417          *
3418          * We also force the firmware's HALT flag to be on in case we bypassed
3419          * the firmware RESET command above or we're dealing with old firmware
3420          * which doesn't have the HALT capability.  This will serve as a flag
3421          * for the incoming firmware to know that it's coming out of a HALT
3422          * rather than a RESET ... if it's new enough to understand that ...
3423          */
3424         if (ret == 0 || force) {
3425                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3426                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3427                                  F_PCIE_FW_HALT);
3428         }
3429
3430         /*
3431          * And we always return the result of the firmware RESET command
3432          * even when we force the uP into RESET ...
3433          */
3434         return ret;
3435 }
3436
3437 /**
3438  * t4_fw_restart - restart the firmware by taking the uP out of RESET
3439  * @adap: the adapter
3440  * @mbox: mailbox to use for the FW RESET command (if desired)
3441  * @reset: if we want to do a RESET to restart things
3442  *
3443  * Restart firmware previously halted by t4_fw_halt().  On successful
3444  * return the previous PF Master remains as the new PF Master and there
3445  * is no need to issue a new HELLO command, etc.
3446  *
3447  * We do this in two ways:
3448  *
3449  * 1. If we're dealing with newer firmware we'll simply want to take
3450  *    the chip's microprocessor out of RESET.  This will cause the
3451  *    firmware to start up from its start vector.  And then we'll loop
3452  *    until the firmware indicates it's started again (PCIE_FW.HALT
3453  *    reset to 0) or we timeout.
3454  *
3455  * 2. If we're dealing with older firmware then we'll need to RESET
3456  *    the chip since older firmware won't recognize the PCIE_FW.HALT
3457  *    flag and automatically RESET itself on startup.
3458  */
3459 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3460 {
3461         if (reset) {
3462                 /*
3463                  * Since we're directing the RESET instead of the firmware
3464                  * doing it automatically, we need to clear the PCIE_FW.HALT
3465                  * bit.
3466                  */
3467                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3468
3469                 /*
3470                  * If we've been given a valid mailbox, first try to get the
3471                  * firmware to do the RESET.  If that works, great and we can
3472                  * return success.  Otherwise, if we haven't been given a
3473                  * valid mailbox or the RESET command failed, fall back to
3474                  * hitting the chip with a hammer.
3475                  */
3476                 if (mbox <= M_PCIE_FW_MASTER) {
3477                         t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3478                         msleep(100);
3479                         if (t4_fw_reset(adap, mbox,
3480                                         F_PIORST | F_PIORSTMODE) == 0)
3481                                 return 0;
3482                 }
3483
3484                 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3485                 msleep(2000);
3486         } else {
3487                 int ms;
3488
3489                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3490                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3491                         if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3492                                 return FW_SUCCESS;
3493                         msleep(100);
3494                         ms += 100;
3495                 }
3496                 return -ETIMEDOUT;
3497         }
3498         return 0;
3499 }
3500
3501 /**
3502  * t4_fl_pkt_align - return the fl packet alignment
3503  * @adap: the adapter
3504  *
3505  * T4 has a single field to specify the packing and padding boundary.
3506  * T5 onwards has separate fields for this and hence the alignment for
3507  * next packet offset is maximum of these two.
3508  */
3509 int t4_fl_pkt_align(struct adapter *adap)
3510 {
3511         u32 sge_control, sge_control2;
3512         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3513
3514         sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3515
3516         /* T4 uses a single control field to specify both the PCIe Padding and
3517          * Packing Boundary.  T5 introduced the ability to specify these
3518          * separately.  The actual Ingress Packet Data alignment boundary
3519          * within Packed Buffer Mode is the maximum of these two
3520          * specifications.
3521          */
3522         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3523                 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3524         else
3525                 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3526
3527         ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3528
3529         fl_align = ingpadboundary;
3530         if (!is_t4(adap->params.chip)) {
3531                 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3532                 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3533                 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3534                         ingpackboundary = 16;
3535                 else
3536                         ingpackboundary = 1 << (ingpackboundary +
3537                                         X_INGPACKBOUNDARY_SHIFT);
3538
3539                 fl_align = max(ingpadboundary, ingpackboundary);
3540         }
3541         return fl_align;
3542 }
3543
3544 /**
3545  * t4_fixup_host_params_compat - fix up host-dependent parameters
3546  * @adap: the adapter
3547  * @page_size: the host's Base Page Size
3548  * @cache_line_size: the host's Cache Line Size
3549  * @chip_compat: maintain compatibility with designated chip
3550  *
3551  * Various registers in the chip contain values which are dependent on the
3552  * host's Base Page and Cache Line Sizes.  This function will fix all of
3553  * those registers with the appropriate values as passed in ...
3554  *
3555  * @chip_compat is used to limit the set of changes that are made
3556  * to be compatible with the indicated chip release.  This is used by
3557  * drivers to maintain compatibility with chip register settings when
3558  * the drivers haven't [yet] been updated with new chip support.
3559  */
3560 int t4_fixup_host_params_compat(struct adapter *adap,
3561                                 unsigned int page_size,
3562                                 unsigned int cache_line_size,
3563                                 enum chip_type chip_compat)
3564 {
3565         unsigned int page_shift = cxgbe_fls(page_size) - 1;
3566         unsigned int sge_hps = page_shift - 10;
3567         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3568         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3569         unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3570
3571         t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3572                      V_HOSTPAGESIZEPF0(sge_hps) |
3573                      V_HOSTPAGESIZEPF1(sge_hps) |
3574                      V_HOSTPAGESIZEPF2(sge_hps) |
3575                      V_HOSTPAGESIZEPF3(sge_hps) |
3576                      V_HOSTPAGESIZEPF4(sge_hps) |
3577                      V_HOSTPAGESIZEPF5(sge_hps) |
3578                      V_HOSTPAGESIZEPF6(sge_hps) |
3579                      V_HOSTPAGESIZEPF7(sge_hps));
3580
3581         if (is_t4(adap->params.chip) || is_t4(chip_compat))
3582                 t4_set_reg_field(adap, A_SGE_CONTROL,
3583                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3584                                  F_EGRSTATUSPAGESIZE,
3585                                  V_INGPADBOUNDARY(fl_align_log -
3586                                                   X_INGPADBOUNDARY_SHIFT) |
3587                                 V_EGRSTATUSPAGESIZE(stat_len != 64));
3588         else {
3589                 unsigned int pack_align;
3590                 unsigned int ingpad, ingpack;
3591                 unsigned int pcie_cap;
3592
3593                 /*
3594                  * T5 introduced the separation of the Free List Padding and
3595                  * Packing Boundaries.  Thus, we can select a smaller Padding
3596                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
3597                  * Bandwidth, and use a Packing Boundary which is large enough
3598                  * to avoid false sharing between CPUs, etc.
3599                  *
3600                  * For the PCI Link, the smaller the Padding Boundary the
3601                  * better.  For the Memory Controller, a smaller Padding
3602                  * Boundary is better until we cross under the Memory Line
3603                  * Size (the minimum unit of transfer to/from Memory).  If we
3604                  * have a Padding Boundary which is smaller than the Memory
3605                  * Line Size, that'll involve a Read-Modify-Write cycle on the
3606                  * Memory Controller which is never good.
3607                  */
3608
3609                 /* We want the Packing Boundary to be based on the Cache Line
3610                  * Size in order to help avoid False Sharing performance
3611                  * issues between CPUs, etc.  We also want the Packing
3612                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
3613                  * get best performance when the Packing Boundary is a
3614                  * multiple of the Maximum Payload Size.
3615                  */
3616                 pack_align = fl_align;
3617                 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3618                 if (pcie_cap) {
3619                         unsigned int mps, mps_log;
3620                         u16 devctl;
3621
3622                         /* The PCIe Device Control Maximum Payload Size field
3623                          * [bits 7:5] encodes sizes as powers of 2 starting at
3624                          * 128 bytes.
3625                          */
3626                         t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3627                                             &devctl);
3628                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3629                         mps = 1 << mps_log;
3630                         if (mps > pack_align)
3631                                 pack_align = mps;
3632                 }
3633
3634                 /*
3635                  * N.B. T5 has a different interpretation of the "0" value for
3636                  * the Packing Boundary.  This corresponds to 16 bytes instead
3637                  * of the expected 32 bytes.  We never have a Packing Boundary
3638                  * less than 32 bytes so we can't use that special value but
3639                  * on the other hand, if we wanted 32 bytes, the best we can
3640                  * really do is 64 bytes ...
3641                  */
3642                 if (pack_align <= 16) {
3643                         ingpack = X_INGPACKBOUNDARY_16B;
3644                         fl_align = 16;
3645                 } else if (pack_align == 32) {
3646                         ingpack = X_INGPACKBOUNDARY_64B;
3647                         fl_align = 64;
3648                 } else {
3649                         unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3650
3651                         ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3652                         fl_align = pack_align;
3653                 }
3654
3655                 /* Use the smallest Ingress Padding which isn't smaller than
3656                  * the Memory Controller Read/Write Size.  We'll take that as
3657                  * being 8 bytes since we don't know of any system with a
3658                  * wider Memory Controller Bus Width.
3659                  */
3660                 if (is_t5(adap->params.chip))
3661                         ingpad = X_INGPADBOUNDARY_32B;
3662                 else
3663                         ingpad = X_T6_INGPADBOUNDARY_8B;
3664                 t4_set_reg_field(adap, A_SGE_CONTROL,
3665                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3666                                  F_EGRSTATUSPAGESIZE,
3667                                  V_INGPADBOUNDARY(ingpad) |
3668                                  V_EGRSTATUSPAGESIZE(stat_len != 64));
3669                 t4_set_reg_field(adap, A_SGE_CONTROL2,
3670                                  V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3671                                  V_INGPACKBOUNDARY(ingpack));
3672         }
3673
3674         /*
3675          * Adjust various SGE Free List Host Buffer Sizes.
3676          *
3677          * The first four entries are:
3678          *
3679          *   0: Host Page Size
3680          *   1: 64KB
3681          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3682          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3683          *
3684          * For the single-MTU buffers in unpacked mode we need to include
3685          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3686          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3687          * Padding boundary.  All of these are accommodated in the Factory
3688          * Default Firmware Configuration File but we need to adjust it for
3689          * this host's cache line size.
3690          */
3691         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3692         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3693                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3694                      & ~(fl_align - 1));
3695         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3696                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3697                      & ~(fl_align - 1));
3698
3699         t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3700
3701         return 0;
3702 }
3703
3704 /**
3705  * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3706  * @adap: the adapter
3707  * @page_size: the host's Base Page Size
3708  * @cache_line_size: the host's Cache Line Size
3709  *
3710  * Various registers in T4 contain values which are dependent on the
3711  * host's Base Page and Cache Line Sizes.  This function will fix all of
3712  * those registers with the appropriate values as passed in ...
3713  *
3714  * This routine makes changes which are compatible with T4 chips.
3715  */
3716 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3717                          unsigned int cache_line_size)
3718 {
3719         return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3720                                            T4_LAST_REV);
3721 }
3722
3723 /**
3724  * t4_fw_initialize - ask FW to initialize the device
3725  * @adap: the adapter
3726  * @mbox: mailbox to use for the FW command
3727  *
3728  * Issues a command to FW to partially initialize the device.  This
3729  * performs initialization that generally doesn't depend on user input.
3730  */
3731 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3732 {
3733         struct fw_initialize_cmd c;
3734
3735         memset(&c, 0, sizeof(c));
3736         INIT_CMD(c, INITIALIZE, WRITE);
3737         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3738 }
3739
3740 /**
3741  * t4_query_params_rw - query FW or device parameters
3742  * @adap: the adapter
3743  * @mbox: mailbox to use for the FW command
3744  * @pf: the PF
3745  * @vf: the VF
3746  * @nparams: the number of parameters
3747  * @params: the parameter names
3748  * @val: the parameter values
3749  * @rw: Write and read flag
3750  *
3751  * Reads the value of FW or device parameters.  Up to 7 parameters can be
3752  * queried at once.
3753  */
3754 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3755                               unsigned int pf, unsigned int vf,
3756                               unsigned int nparams, const u32 *params,
3757                               u32 *val, int rw)
3758 {
3759         unsigned int i;
3760         int ret;
3761         struct fw_params_cmd c;
3762         __be32 *p = &c.param[0].mnem;
3763
3764         if (nparams > 7)
3765                 return -EINVAL;
3766
3767         memset(&c, 0, sizeof(c));
3768         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3769                                   F_FW_CMD_REQUEST | F_FW_CMD_READ |
3770                                   V_FW_PARAMS_CMD_PFN(pf) |
3771                                   V_FW_PARAMS_CMD_VFN(vf));
3772         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3773
3774         for (i = 0; i < nparams; i++) {
3775                 *p++ = cpu_to_be32(*params++);
3776                 if (rw)
3777                         *p = cpu_to_be32(*(val + i));
3778                 p++;
3779         }
3780
3781         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3782         if (ret == 0)
3783                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3784                         *val++ = be32_to_cpu(*p);
3785         return ret;
3786 }
3787
3788 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3789                     unsigned int vf, unsigned int nparams, const u32 *params,
3790                     u32 *val)
3791 {
3792         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3793 }
3794
3795 /**
3796  * t4_set_params_timeout - sets FW or device parameters
3797  * @adap: the adapter
3798  * @mbox: mailbox to use for the FW command
3799  * @pf: the PF
3800  * @vf: the VF
3801  * @nparams: the number of parameters
3802  * @params: the parameter names
3803  * @val: the parameter values
3804  * @timeout: the timeout time
3805  *
3806  * Sets the value of FW or device parameters.  Up to 7 parameters can be
3807  * specified at once.
3808  */
3809 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3810                           unsigned int pf, unsigned int vf,
3811                           unsigned int nparams, const u32 *params,
3812                           const u32 *val, int timeout)
3813 {
3814         struct fw_params_cmd c;
3815         __be32 *p = &c.param[0].mnem;
3816
3817         if (nparams > 7)
3818                 return -EINVAL;
3819
3820         memset(&c, 0, sizeof(c));
3821         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3822                                   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3823                                   V_FW_PARAMS_CMD_PFN(pf) |
3824                                   V_FW_PARAMS_CMD_VFN(vf));
3825         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3826
3827         while (nparams--) {
3828                 *p++ = cpu_to_be32(*params++);
3829                 *p++ = cpu_to_be32(*val++);
3830         }
3831
3832         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3833 }
3834
3835 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3836                   unsigned int vf, unsigned int nparams, const u32 *params,
3837                   const u32 *val)
3838 {
3839         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3840                                      FW_CMD_MAX_TIMEOUT);
3841 }
3842
3843 /**
3844  * t4_alloc_vi_func - allocate a virtual interface
3845  * @adap: the adapter
3846  * @mbox: mailbox to use for the FW command
3847  * @port: physical port associated with the VI
3848  * @pf: the PF owning the VI
3849  * @vf: the VF owning the VI
3850  * @nmac: number of MAC addresses needed (1 to 5)
3851  * @mac: the MAC addresses of the VI
3852  * @rss_size: size of RSS table slice associated with this VI
3853  * @portfunc: which Port Application Function MAC Address is desired
3854  * @idstype: Intrusion Detection Type
3855  *
3856  * Allocates a virtual interface for the given physical port.  If @mac is
3857  * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3858  * @mac should be large enough to hold @nmac Ethernet addresses, they are
3859  * stored consecutively so the space needed is @nmac * 6 bytes.
3860  * Returns a negative error number or the non-negative VI id.
3861  */
3862 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3863                      unsigned int port, unsigned int pf, unsigned int vf,
3864                      unsigned int nmac, u8 *mac, unsigned int *rss_size,
3865                      unsigned int portfunc, unsigned int idstype,
3866                      u8 *vivld, u8 *vin)
3867 {
3868         int ret;
3869         struct fw_vi_cmd c;
3870
3871         memset(&c, 0, sizeof(c));
3872         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3873                                   F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3874                                   V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3875         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3876         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3877                                      V_FW_VI_CMD_FUNC(portfunc));
3878         c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3879         c.nmac = nmac - 1;
3880
3881         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3882         if (ret)
3883                 return ret;
3884
3885         if (mac) {
3886                 memcpy(mac, c.mac, sizeof(c.mac));
3887                 switch (nmac) {
3888                 case 5:
3889                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3890                         /* FALLTHROUGH */
3891                 case 4:
3892                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3893                         /* FALLTHROUGH */
3894                 case 3:
3895                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3896                         /* FALLTHROUGH */
3897                 case 2:
3898                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
3899                         /* FALLTHROUGH */
3900                 }
3901         }
3902         if (rss_size)
3903                 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3904         if (vivld)
3905                 *vivld = G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16));
3906         if (vin)
3907                 *vin = G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16));
3908         return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3909 }
3910
3911 /**
3912  * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3913  * @adap: the adapter
3914  * @mbox: mailbox to use for the FW command
3915  * @port: physical port associated with the VI
3916  * @pf: the PF owning the VI
3917  * @vf: the VF owning the VI
3918  * @nmac: number of MAC addresses needed (1 to 5)
3919  * @mac: the MAC addresses of the VI
3920  * @rss_size: size of RSS table slice associated with this VI
3921  *
3922  * Backwards compatible and convieniance routine to allocate a Virtual
3923  * Interface with a Ethernet Port Application Function and Intrustion
3924  * Detection System disabled.
3925  */
3926 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3927                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3928                 unsigned int *rss_size, u8 *vivld, u8 *vin)
3929 {
3930         return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3931                                 FW_VI_FUNC_ETH, 0, vivld, vin);
3932 }
3933
3934 /**
3935  * t4_free_vi - free a virtual interface
3936  * @adap: the adapter
3937  * @mbox: mailbox to use for the FW command
3938  * @pf: the PF owning the VI
3939  * @vf: the VF owning the VI
3940  * @viid: virtual interface identifiler
3941  *
3942  * Free a previously allocated virtual interface.
3943  */
3944 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3945                unsigned int vf, unsigned int viid)
3946 {
3947         struct fw_vi_cmd c;
3948
3949         memset(&c, 0, sizeof(c));
3950         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3951                                   F_FW_CMD_EXEC);
3952         if (is_pf4(adap))
3953                 c.op_to_vfn |= cpu_to_be32(V_FW_VI_CMD_PFN(pf) |
3954                                            V_FW_VI_CMD_VFN(vf));
3955         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
3956         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
3957
3958         if (is_pf4(adap))
3959                 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3960         else
3961                 return t4vf_wr_mbox(adap, &c, sizeof(c), NULL);
3962 }
3963
3964 /**
3965  * t4_set_rxmode - set Rx properties of a virtual interface
3966  * @adap: the adapter
3967  * @mbox: mailbox to use for the FW command
3968  * @viid: the VI id
3969  * @mtu: the new MTU or -1
3970  * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3971  * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3972  * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3973  * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
3974  *          -1 no change
3975  * @sleep_ok: if true we may sleep while awaiting command completion
3976  *
3977  * Sets Rx properties of a virtual interface.
3978  */
3979 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3980                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
3981                   bool sleep_ok)
3982 {
3983         struct fw_vi_rxmode_cmd c;
3984
3985         /* convert to FW values */
3986         if (mtu < 0)
3987                 mtu = M_FW_VI_RXMODE_CMD_MTU;
3988         if (promisc < 0)
3989                 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
3990         if (all_multi < 0)
3991                 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
3992         if (bcast < 0)
3993                 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
3994         if (vlanex < 0)
3995                 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
3996
3997         memset(&c, 0, sizeof(c));
3998         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
3999                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4000                                    V_FW_VI_RXMODE_CMD_VIID(viid));
4001         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4002         c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
4003                             V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
4004                             V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
4005                             V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
4006                             V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
4007         if (is_pf4(adap))
4008                 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL,
4009                                        sleep_ok);
4010         else
4011                 return t4vf_wr_mbox(adap, &c, sizeof(c), NULL);
4012 }
4013
4014 /**
4015  *      t4_alloc_raw_mac_filt - Adds a raw mac entry in mps tcam
4016  *      @adap: the adapter
4017  *      @viid: the VI id
4018  *      @mac: the MAC address
4019  *      @mask: the mask
4020  *      @idx: index at which to add this entry
4021  *      @port_id: the port index
4022  *      @lookup_type: MAC address for inner (1) or outer (0) header
4023  *      @sleep_ok: call is allowed to sleep
4024  *
4025  *      Adds the mac entry at the specified index using raw mac interface.
4026  *
4027  *      Returns a negative error number or the allocated index for this mac.
4028  */
4029 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
4030                           const u8 *addr, const u8 *mask, unsigned int idx,
4031                           u8 lookup_type, u8 port_id, bool sleep_ok)
4032 {
4033         int ret = 0;
4034         struct fw_vi_mac_cmd c;
4035         struct fw_vi_mac_raw *p = &c.u.raw;
4036         u32 val;
4037
4038         memset(&c, 0, sizeof(c));
4039         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
4040                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4041                                    V_FW_VI_MAC_CMD_VIID(viid));
4042         val = V_FW_CMD_LEN16(1) |
4043               V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
4044         c.freemacs_to_len16 = cpu_to_be32(val);
4045
4046         /* Specify that this is an inner mac address */
4047         p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx));
4048
4049         /* Lookup Type. Outer header: 0, Inner header: 1 */
4050         p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
4051                                    V_DATAPORTNUM(port_id));
4052         /* Lookup mask and port mask */
4053         p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
4054                                     V_DATAPORTNUM(M_DATAPORTNUM));
4055
4056         /* Copy the address and the mask */
4057         memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN);
4058         memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN);
4059
4060         ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
4061         if (ret == 0) {
4062                 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd));
4063                 if (ret != (int)idx)
4064                         ret = -ENOMEM;
4065         }
4066
4067         return ret;
4068 }
4069
4070 /**
4071  *      t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
4072  *      @adap: the adapter
4073  *      @viid: the VI id
4074  *      @addr: the MAC address
4075  *      @mask: the mask
4076  *      @idx: index of the entry in mps tcam
4077  *      @lookup_type: MAC address for inner (1) or outer (0) header
4078  *      @port_id: the port index
4079  *      @sleep_ok: call is allowed to sleep
4080  *
4081  *      Removes the mac entry at the specified index using raw mac interface.
4082  *
4083  *      Returns a negative error number on failure.
4084  */
4085 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
4086                          const u8 *addr, const u8 *mask, unsigned int idx,
4087                          u8 lookup_type, u8 port_id, bool sleep_ok)
4088 {
4089         struct fw_vi_mac_cmd c;
4090         struct fw_vi_mac_raw *p = &c.u.raw;
4091         u32 raw;
4092
4093         memset(&c, 0, sizeof(c));
4094         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
4095                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4096                                    V_FW_CMD_EXEC(0) |
4097                                    V_FW_VI_MAC_CMD_VIID(viid));
4098         raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
4099         c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0U) |
4100                                           raw |
4101                                           V_FW_CMD_LEN16(1));
4102
4103         p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) |
4104                                      FW_VI_MAC_ID_BASED_FREE);
4105
4106         /* Lookup Type. Outer header: 0, Inner header: 1 */
4107         p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
4108                                    V_DATAPORTNUM(port_id));
4109         /* Lookup mask and port mask */
4110         p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
4111                                     V_DATAPORTNUM(M_DATAPORTNUM));
4112
4113         /* Copy the address and the mask */
4114         memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN);
4115         memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN);
4116
4117         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
4118 }
4119
4120 /**
4121  * t4_change_mac - modifies the exact-match filter for a MAC address
4122  * @adap: the adapter
4123  * @mbox: mailbox to use for the FW command
4124  * @viid: the VI id
4125  * @idx: index of existing filter for old value of MAC address, or -1
4126  * @addr: the new MAC address value
4127  * @persist: whether a new MAC allocation should be persistent
4128  * @add_smt: if true also add the address to the HW SMT
4129  *
4130  * Modifies an exact-match filter and sets it to the new MAC address if
4131  * @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
4132  * latter case the address is added persistently if @persist is %true.
4133  *
4134  * Note that in general it is not possible to modify the value of a given
4135  * filter so the generic way to modify an address filter is to free the one
4136  * being used by the old address value and allocate a new filter for the
4137  * new address value.
4138  *
4139  * Returns a negative error number or the index of the filter with the new
4140  * MAC value.  Note that this index may differ from @idx.
4141  */
4142 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
4143                   int idx, const u8 *addr, bool persist, bool add_smt)
4144 {
4145         int ret, mode;
4146         struct fw_vi_mac_cmd c;
4147         struct fw_vi_mac_exact *p = c.u.exact;
4148         int max_mac_addr = adap->params.arch.mps_tcam_size;
4149
4150         if (idx < 0)                             /* new allocation */
4151                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
4152         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
4153
4154         memset(&c, 0, sizeof(c));
4155         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
4156                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4157                                    V_FW_VI_MAC_CMD_VIID(viid));
4158         c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
4159         p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
4160                                       V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
4161                                       V_FW_VI_MAC_CMD_IDX(idx));
4162         memcpy(p->macaddr, addr, sizeof(p->macaddr));
4163
4164         if (is_pf4(adap))
4165                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4166         else
4167                 ret = t4vf_wr_mbox(adap, &c, sizeof(c), &c);
4168         if (ret == 0) {
4169                 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
4170                 if (ret >= max_mac_addr)
4171                         ret = -ENOMEM;
4172         }
4173         return ret;
4174 }
4175
4176 /**
4177  * t4_enable_vi_params - enable/disable a virtual interface
4178  * @adap: the adapter
4179  * @mbox: mailbox to use for the FW command
4180  * @viid: the VI id
4181  * @rx_en: 1=enable Rx, 0=disable Rx
4182  * @tx_en: 1=enable Tx, 0=disable Tx
4183  * @dcb_en: 1=enable delivery of Data Center Bridging messages.
4184  *
4185  * Enables/disables a virtual interface.  Note that setting DCB Enable
4186  * only makes sense when enabling a Virtual Interface ...
4187  */
4188 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
4189                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
4190 {
4191         struct fw_vi_enable_cmd c;
4192
4193         memset(&c, 0, sizeof(c));
4194         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
4195                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4196                                    V_FW_VI_ENABLE_CMD_VIID(viid));
4197         c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
4198                                      V_FW_VI_ENABLE_CMD_EEN(tx_en) |
4199                                      V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
4200                                      FW_LEN16(c));
4201         if (is_pf4(adap))
4202                 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
4203         else
4204                 return t4vf_wr_mbox_ns(adap, &c, sizeof(c), NULL);
4205 }
4206
4207 /**
4208  * t4_enable_vi - enable/disable a virtual interface
4209  * @adap: the adapter
4210  * @mbox: mailbox to use for the FW command
4211  * @viid: the VI id
4212  * @rx_en: 1=enable Rx, 0=disable Rx
4213  * @tx_en: 1=enable Tx, 0=disable Tx
4214  *
4215  * Enables/disables a virtual interface.  Note that setting DCB Enable
4216  * only makes sense when enabling a Virtual Interface ...
4217  */
4218 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
4219                  bool rx_en, bool tx_en)
4220 {
4221         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
4222 }
4223
4224 /**
4225  * t4_iq_start_stop - enable/disable an ingress queue and its FLs
4226  * @adap: the adapter
4227  * @mbox: mailbox to use for the FW command
4228  * @start: %true to enable the queues, %false to disable them
4229  * @pf: the PF owning the queues
4230  * @vf: the VF owning the queues
4231  * @iqid: ingress queue id
4232  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4233  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4234  *
4235  * Starts or stops an ingress queue and its associated FLs, if any.
4236  */
4237 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
4238                      unsigned int pf, unsigned int vf, unsigned int iqid,
4239                      unsigned int fl0id, unsigned int fl1id)
4240 {
4241         struct fw_iq_cmd c;
4242
4243         memset(&c, 0, sizeof(c));
4244         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4245                                   F_FW_CMD_EXEC);
4246         c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4247                                        V_FW_IQ_CMD_IQSTOP(!start) |
4248                                        FW_LEN16(c));
4249         c.iqid = cpu_to_be16(iqid);
4250         c.fl0id = cpu_to_be16(fl0id);
4251         c.fl1id = cpu_to_be16(fl1id);
4252         if (is_pf4(adap)) {
4253                 c.op_to_vfn |= cpu_to_be32(V_FW_IQ_CMD_PFN(pf) |
4254                                            V_FW_IQ_CMD_VFN(vf));
4255                 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4256         } else {
4257                 return t4vf_wr_mbox(adap, &c, sizeof(c), NULL);
4258         }
4259 }
4260
4261 /**
4262  * t4_iq_free - free an ingress queue and its FLs
4263  * @adap: the adapter
4264  * @mbox: mailbox to use for the FW command
4265  * @pf: the PF owning the queues
4266  * @vf: the VF owning the queues
4267  * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4268  * @iqid: ingress queue id
4269  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4270  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4271  *
4272  * Frees an ingress queue and its associated FLs, if any.
4273  */
4274 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4275                unsigned int vf, unsigned int iqtype, unsigned int iqid,
4276                unsigned int fl0id, unsigned int fl1id)
4277 {
4278         struct fw_iq_cmd c;
4279
4280         memset(&c, 0, sizeof(c));
4281         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4282                                   F_FW_CMD_EXEC);
4283         if (is_pf4(adap))
4284                 c.op_to_vfn |= cpu_to_be32(V_FW_IQ_CMD_PFN(pf) |
4285                                            V_FW_IQ_CMD_VFN(vf));
4286         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4287         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4288         c.iqid = cpu_to_be16(iqid);
4289         c.fl0id = cpu_to_be16(fl0id);
4290         c.fl1id = cpu_to_be16(fl1id);
4291         if (is_pf4(adap))
4292                 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4293         else
4294                 return t4vf_wr_mbox(adap, &c, sizeof(c), NULL);
4295 }
4296
4297 /**
4298  * t4_eth_eq_free - free an Ethernet egress queue
4299  * @adap: the adapter
4300  * @mbox: mailbox to use for the FW command
4301  * @pf: the PF owning the queue
4302  * @vf: the VF owning the queue
4303  * @eqid: egress queue id
4304  *
4305  * Frees an Ethernet egress queue.
4306  */
4307 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4308                    unsigned int vf, unsigned int eqid)
4309 {
4310         struct fw_eq_eth_cmd c;
4311
4312         memset(&c, 0, sizeof(c));
4313         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4314                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC);
4315         if (is_pf4(adap))
4316                 c.op_to_vfn |= cpu_to_be32(V_FW_IQ_CMD_PFN(pf) |
4317                                            V_FW_IQ_CMD_VFN(vf));
4318         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4319         c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4320         if (is_pf4(adap))
4321                 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4322         else
4323                 return t4vf_wr_mbox(adap, &c, sizeof(c), NULL);
4324 }
4325
4326 /**
4327  * t4_link_down_rc_str - return a string for a Link Down Reason Code
4328  * @link_down_rc: Link Down Reason Code
4329  *
4330  * Returns a string representation of the Link Down Reason Code.
4331  */
4332 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
4333 {
4334         static const char * const reason[] = {
4335                 "Link Down",
4336                 "Remote Fault",
4337                 "Auto-negotiation Failure",
4338                 "Reserved",
4339                 "Insufficient Airflow",
4340                 "Unable To Determine Reason",
4341                 "No RX Signal Detected",
4342                 "Reserved",
4343         };
4344
4345         if (link_down_rc >= ARRAY_SIZE(reason))
4346                 return "Bad Reason Code";
4347
4348         return reason[link_down_rc];
4349 }
4350
4351 static u32 t4_speed_to_fwcap(u32 speed)
4352 {
4353         switch (speed) {
4354         case 100000:
4355                 return FW_PORT_CAP32_SPEED_100G;
4356         case 50000:
4357                 return FW_PORT_CAP32_SPEED_50G;
4358         case 40000:
4359                 return FW_PORT_CAP32_SPEED_40G;
4360         case 25000:
4361                 return FW_PORT_CAP32_SPEED_25G;
4362         case 10000:
4363                 return FW_PORT_CAP32_SPEED_10G;
4364         case 1000:
4365                 return FW_PORT_CAP32_SPEED_1G;
4366         case 100:
4367                 return FW_PORT_CAP32_SPEED_100M;
4368         default:
4369                 break;
4370         }
4371
4372         return 0;
4373 }
4374
4375 /* Return the highest speed set in the port capabilities, in Mb/s. */
4376 unsigned int t4_fwcap_to_speed(u32 caps)
4377 {
4378 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
4379         do { \
4380                 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
4381                         return __speed; \
4382         } while (0)
4383
4384         TEST_SPEED_RETURN(100G, 100000);
4385         TEST_SPEED_RETURN(50G,   50000);
4386         TEST_SPEED_RETURN(40G,   40000);
4387         TEST_SPEED_RETURN(25G,   25000);
4388         TEST_SPEED_RETURN(10G,   10000);
4389         TEST_SPEED_RETURN(1G,     1000);
4390         TEST_SPEED_RETURN(100M,    100);
4391
4392 #undef TEST_SPEED_RETURN
4393
4394         return 0;
4395 }
4396
4397 static void t4_set_link_autoneg_speed(struct port_info *pi, u32 *new_caps)
4398 {
4399         struct link_config *lc = &pi->link_cfg;
4400         u32 caps = *new_caps;
4401
4402         caps &= ~V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED);
4403         caps |= G_FW_PORT_CAP32_SPEED(lc->acaps);
4404
4405         *new_caps = caps;
4406 }
4407
4408 int t4_set_link_speed(struct port_info *pi, u32 speed, u32 *new_caps)
4409 {
4410         u32 fw_speed_cap = t4_speed_to_fwcap(speed);
4411         struct link_config *lc = &pi->link_cfg;
4412         u32 caps = *new_caps;
4413
4414         if (!(lc->pcaps & fw_speed_cap))
4415                 return -EOPNOTSUPP;
4416
4417         caps &= ~V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED);
4418         caps |= fw_speed_cap;
4419
4420         *new_caps = caps;
4421
4422         return 0;
4423 }
4424
4425 int t4_set_link_pause(struct port_info *pi, u8 autoneg, u8 pause_tx,
4426                       u8 pause_rx, u32 *new_caps)
4427 {
4428         struct link_config *lc = &pi->link_cfg;
4429         u32 caps = *new_caps;
4430         u32 max_speed;
4431
4432         max_speed = t4_fwcap_to_speed(lc->link_caps);
4433
4434         if (autoneg) {
4435                 if (!(lc->pcaps & FW_PORT_CAP32_ANEG))
4436                         return -EINVAL;
4437
4438                 caps |= FW_PORT_CAP32_ANEG;
4439                 t4_set_link_autoneg_speed(pi, &caps);
4440         } else {
4441                 if (!max_speed)
4442                         max_speed = t4_fwcap_to_speed(lc->acaps);
4443
4444                 caps &= ~FW_PORT_CAP32_ANEG;
4445                 t4_set_link_speed(pi, max_speed, &caps);
4446         }
4447
4448         if (lc->pcaps & FW_PORT_CAP32_MDIAUTO)
4449                 caps |= V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
4450
4451         caps &= ~V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC);
4452         caps &= ~V_FW_PORT_CAP32_802_3(M_FW_PORT_CAP32_802_3);
4453         if (pause_tx && pause_rx) {
4454                 caps |= FW_PORT_CAP32_FC_TX | FW_PORT_CAP32_FC_RX;
4455                 if (lc->pcaps & FW_PORT_CAP32_802_3_PAUSE)
4456                         caps |= FW_PORT_CAP32_802_3_PAUSE;
4457         } else if (pause_tx) {
4458                 caps |= FW_PORT_CAP32_FC_TX;
4459                 if (lc->pcaps & FW_PORT_CAP32_802_3_ASM_DIR)
4460                         caps |= FW_PORT_CAP32_802_3_ASM_DIR;
4461         } else if (pause_rx) {
4462                 caps |= FW_PORT_CAP32_FC_RX;
4463                 if (lc->pcaps & FW_PORT_CAP32_802_3_PAUSE)
4464                         caps |= FW_PORT_CAP32_802_3_PAUSE;
4465
4466                 if (lc->pcaps & FW_PORT_CAP32_802_3_ASM_DIR)
4467                         caps |= FW_PORT_CAP32_802_3_ASM_DIR;
4468         }
4469
4470         *new_caps = caps;
4471
4472         return 0;
4473 }
4474
4475 int t4_set_link_fec(struct port_info *pi, u8 fec_rs, u8 fec_baser,
4476                     u8 fec_none, u32 *new_caps)
4477 {
4478         struct link_config *lc = &pi->link_cfg;
4479         u32 max_speed, caps = *new_caps;
4480
4481         if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
4482                 return -EOPNOTSUPP;
4483
4484         /* Link might be down. In that case consider the max
4485          * speed advertised
4486          */
4487         max_speed = t4_fwcap_to_speed(lc->link_caps);
4488         if (!max_speed)
4489                 max_speed = t4_fwcap_to_speed(lc->acaps);
4490
4491         caps &= ~V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC);
4492         if (fec_rs) {
4493                 switch (max_speed) {
4494                 case 100000:
4495                 case 25000:
4496                         caps |= FW_PORT_CAP32_FEC_RS;
4497                         break;
4498                 default:
4499                         return -EOPNOTSUPP;
4500                 }
4501         }
4502
4503         if (fec_baser) {
4504                 switch (max_speed) {
4505                 case 50000:
4506                 case 25000:
4507                         caps |= FW_PORT_CAP32_FEC_BASER_RS;
4508                         break;
4509                 default:
4510                         return -EOPNOTSUPP;
4511                 }
4512         }
4513
4514         if (fec_none)
4515                 caps |= FW_PORT_CAP32_FEC_NO_FEC;
4516
4517         if (!(caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) {
4518                 /* No explicit encoding is requested.
4519                  * So, default back to AUTO.
4520                  */
4521                 switch (max_speed) {
4522                 case 100000:
4523                         caps |= FW_PORT_CAP32_FEC_RS |
4524                                 FW_PORT_CAP32_FEC_NO_FEC;
4525                         break;
4526                 case 50000:
4527                         caps |= FW_PORT_CAP32_FEC_BASER_RS |
4528                                 FW_PORT_CAP32_FEC_NO_FEC;
4529                         break;
4530                 case 25000:
4531                         caps |= FW_PORT_CAP32_FEC_RS |
4532                                 FW_PORT_CAP32_FEC_BASER_RS |
4533                                 FW_PORT_CAP32_FEC_NO_FEC;
4534                         break;
4535                 default:
4536                         return -EOPNOTSUPP;
4537                 }
4538         }
4539
4540         *new_caps = caps;
4541
4542         return 0;
4543 }
4544
4545 /**
4546  * t4_handle_get_port_info - process a FW reply message
4547  * @pi: the port info
4548  * @rpl: start of the FW message
4549  *
4550  * Processes a GET_PORT_INFO FW reply message.
4551  */
4552 static void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
4553 {
4554         const struct fw_port_cmd *cmd = (const void *)rpl;
4555         u8 link_ok, link_down_rc, mod_type, port_type;
4556         u32 action, pcaps, acaps, link_caps, lstatus;
4557         struct link_config *lc = &pi->link_cfg;
4558         struct adapter *adapter = pi->adapter;
4559         u8 mod_changed = 0;
4560
4561         /* Extract the various fields from the Port Information message.
4562          */
4563         action = be32_to_cpu(cmd->action_to_len16);
4564         if (G_FW_PORT_CMD_ACTION(action) != FW_PORT_ACTION_GET_PORT_INFO32) {
4565                 dev_warn(adapter, "Handle Port Information: Bad Command/Action %#x\n",
4566                          action);
4567                 return;
4568         }
4569
4570         lstatus = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
4571         link_ok = (lstatus & F_FW_PORT_CMD_LSTATUS32) ? 1 : 0;
4572         link_down_rc = G_FW_PORT_CMD_LINKDNRC32(lstatus);
4573         port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus);
4574         mod_type = G_FW_PORT_CMD_MODTYPE32(lstatus);
4575
4576         pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
4577         acaps = be32_to_cpu(cmd->u.info32.acaps32);
4578         link_caps = be32_to_cpu(cmd->u.info32.linkattr32);
4579
4580         if (mod_type != lc->mod_type) {
4581                 t4_init_link_config(pi, pcaps, acaps, lc->mdio_addr,
4582                                     port_type, mod_type);
4583                 t4_os_portmod_changed(adapter, pi->pidx);
4584                 mod_changed = 1;
4585         }
4586         if (link_ok != lc->link_ok || acaps != lc->acaps ||
4587             link_caps != lc->link_caps) { /* something changed */
4588                 if (!link_ok && lc->link_ok) {
4589                         lc->link_down_rc = link_down_rc;
4590                         dev_warn(adap, "Port %d link down, reason: %s\n",
4591                                  pi->port_id,
4592                                  t4_link_down_rc_str(link_down_rc));
4593                 }
4594                 lc->link_ok = link_ok;
4595                 lc->acaps = acaps;
4596                 lc->link_caps = link_caps;
4597                 t4_os_link_changed(adapter, pi->pidx);
4598         }
4599
4600         if (mod_changed) {
4601                 u32 mod_caps = lc->admin_caps;
4602                 int ret;
4603
4604                 ret = t4_link_l1cfg_ns(pi, mod_caps);
4605                 if (ret != FW_SUCCESS)
4606                         dev_warn(adapter,
4607                                  "Attempt to update new Transceiver Module settings %#x failed with error: %d\n",
4608                                  mod_caps, ret);
4609         }
4610 }
4611
4612 /**
4613  * t4_ctrl_eq_free - free a control egress queue
4614  * @adap: the adapter
4615  * @mbox: mailbox to use for the FW command
4616  * @pf: the PF owning the queue
4617  * @vf: the VF owning the queue
4618  * @eqid: egress queue id
4619  *
4620  * Frees a control egress queue.
4621  */
4622 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4623                     unsigned int vf, unsigned int eqid)
4624 {
4625         struct fw_eq_ctrl_cmd c;
4626
4627         memset(&c, 0, sizeof(c));
4628         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
4629                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4630                                   V_FW_EQ_CTRL_CMD_PFN(pf) |
4631                                   V_FW_EQ_CTRL_CMD_VFN(vf));
4632         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
4633         c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
4634         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4635 }
4636
4637 /**
4638  * t4_handle_fw_rpl - process a FW reply message
4639  * @adap: the adapter
4640  * @rpl: start of the FW message
4641  *
4642  * Processes a FW message, such as link state change messages.
4643  */
4644 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4645 {
4646         u8 opcode = *(const u8 *)rpl;
4647
4648         /*
4649          * This might be a port command ... this simplifies the following
4650          * conditionals ...  We can get away with pre-dereferencing
4651          * action_to_len16 because it's in the first 16 bytes and all messages
4652          * will be at least that long.
4653          */
4654         const struct fw_port_cmd *p = (const void *)rpl;
4655         unsigned int action =
4656                 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4657
4658         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO32) {
4659                 /* link/module state change message */
4660                 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4661                 struct port_info *pi = NULL;
4662                 int i;
4663
4664                 for_each_port(adap, i) {
4665                         pi = adap2pinfo(adap, i);
4666                         if (pi->tx_chan == chan)
4667                                 break;
4668                 }
4669
4670                 t4_handle_get_port_info(pi, rpl);
4671         } else {
4672                 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4673                 return -EINVAL;
4674         }
4675         return 0;
4676 }
4677
4678 void t4_reset_link_config(struct adapter *adap, int idx)
4679 {
4680         struct port_info *pi = adap2pinfo(adap, idx);
4681         struct link_config *lc = &pi->link_cfg;
4682
4683         lc->link_ok = 0;
4684         lc->link_down_rc = 0;
4685         lc->link_caps = 0;
4686 }
4687
4688 /**
4689  * t4_init_link_config - initialize a link's SW state
4690  * @pi: the port info
4691  * @pcaps: link Port Capabilities
4692  * @acaps: link current Advertised Port Capabilities
4693  * @mdio_addr : address of the PHY
4694  * @port_type : firmware port type
4695  * @mod_type  : firmware module type
4696  *
4697  * Initializes the SW state maintained for each link, including the link's
4698  * capabilities and default speed/flow-control/autonegotiation settings.
4699  */
4700 void t4_init_link_config(struct port_info *pi, u32 pcaps, u32 acaps,
4701                          u8 mdio_addr, u8 port_type, u8 mod_type)
4702 {
4703         u8 fec_rs = 0, fec_baser = 0, fec_none = 0;
4704         struct link_config *lc = &pi->link_cfg;
4705
4706         lc->pcaps = pcaps;
4707         lc->acaps = acaps;
4708         lc->admin_caps = acaps;
4709         lc->link_caps = 0;
4710
4711         lc->mdio_addr = mdio_addr;
4712         lc->port_type = port_type;
4713         lc->mod_type = mod_type;
4714
4715         lc->link_ok = 0;
4716         lc->link_down_rc = 0;
4717
4718         /* Turn Tx and Rx pause off by default */
4719         lc->admin_caps &= ~V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC);
4720         lc->admin_caps &= ~V_FW_PORT_CAP32_802_3(M_FW_PORT_CAP32_802_3);
4721         if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)
4722                 lc->admin_caps &= ~FW_PORT_CAP32_FORCE_PAUSE;
4723
4724         /* Reset FEC caps to default values */
4725         if (lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) {
4726                 if (lc->acaps & FW_PORT_CAP32_FEC_RS)
4727                         fec_rs = 1;
4728                 else if (lc->acaps & FW_PORT_CAP32_FEC_BASER_RS)
4729                         fec_baser = 1;
4730                 else
4731                         fec_none = 1;
4732
4733                 lc->admin_caps &= ~V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC);
4734                 t4_set_link_fec(pi, fec_rs, fec_baser, fec_none,
4735                                 &lc->admin_caps);
4736         }
4737
4738         if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
4739                 lc->admin_caps &= ~FW_PORT_CAP32_FORCE_FEC;
4740
4741         /* Reset MDI to AUTO */
4742         if (lc->pcaps & FW_PORT_CAP32_MDIAUTO) {
4743                 lc->admin_caps &= ~V_FW_PORT_CAP32_MDI(M_FW_PORT_CAP32_MDI);
4744                 lc->admin_caps |= V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
4745         }
4746 }
4747
4748 /**
4749  * t4_wait_dev_ready - wait till to reads of registers work
4750  *
4751  * Right after the device is RESET is can take a small amount of time
4752  * for it to respond to register reads.  Until then, all reads will
4753  * return either 0xff...ff or 0xee...ee.  Return an error if reads
4754  * don't work within a reasonable time frame.
4755  */
4756 static int t4_wait_dev_ready(struct adapter *adapter)
4757 {
4758         u32 whoami;
4759
4760         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4761
4762         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4763                 return 0;
4764
4765         msleep(500);
4766         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4767         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4768                 return 0;
4769
4770         dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4771                 whoami);
4772         return -EIO;
4773 }
4774
4775 struct flash_desc {
4776         u32 vendor_and_model_id;
4777         u32 size_mb;
4778 };
4779
4780 int t4_get_flash_params(struct adapter *adapter)
4781 {
4782         /*
4783          * Table for non-standard supported Flash parts.  Note, all Flash
4784          * parts must have 64KB sectors.
4785          */
4786         static struct flash_desc supported_flash[] = {
4787                 { 0x00150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
4788         };
4789
4790         int ret;
4791         u32 flashid = 0;
4792         unsigned int part, manufacturer;
4793         unsigned int density, size = 0;
4794
4795         /**
4796          * Issue a Read ID Command to the Flash part.  We decode supported
4797          * Flash parts and their sizes from this.  There's a newer Query
4798          * Command which can retrieve detailed geometry information but
4799          * many Flash parts don't support it.
4800          */
4801         ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4802         if (!ret)
4803                 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4804         t4_write_reg(adapter, A_SF_OP, 0);               /* unlock SF */
4805         if (ret < 0)
4806                 return ret;
4807
4808         /**
4809          * Check to see if it's one of our non-standard supported Flash parts.
4810          */
4811         for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4812                 if (supported_flash[part].vendor_and_model_id == flashid) {
4813                         adapter->params.sf_size =
4814                                 supported_flash[part].size_mb;
4815                         adapter->params.sf_nsec =
4816                                 adapter->params.sf_size / SF_SEC_SIZE;
4817                         goto found;
4818                 }
4819         }
4820
4821         /**
4822          * Decode Flash part size.  The code below looks repetative with
4823          * common encodings, but that's not guaranteed in the JEDEC
4824          * specification for the Read JADEC ID command.  The only thing that
4825          * we're guaranteed by the JADEC specification is where the
4826          * Manufacturer ID is in the returned result.  After that each
4827          * Manufacturer ~could~ encode things completely differently.
4828          * Note, all Flash parts must have 64KB sectors.
4829          */
4830         manufacturer = flashid & 0xff;
4831         switch (manufacturer) {
4832         case 0x20: { /* Micron/Numonix */
4833                 /**
4834                  * This Density -> Size decoding table is taken from Micron
4835                  * Data Sheets.
4836                  */
4837                 density = (flashid >> 16) & 0xff;
4838                 switch (density) {
4839                 case 0x14:
4840                         size = 1 << 20; /* 1MB */
4841                         break;
4842                 case 0x15:
4843                         size = 1 << 21; /* 2MB */
4844                         break;
4845                 case 0x16:
4846                         size = 1 << 22; /* 4MB */
4847                         break;
4848                 case 0x17:
4849                         size = 1 << 23; /* 8MB */
4850                         break;
4851                 case 0x18:
4852                         size = 1 << 24; /* 16MB */
4853                         break;
4854                 case 0x19:
4855                         size = 1 << 25; /* 32MB */
4856                         break;
4857                 case 0x20:
4858                         size = 1 << 26; /* 64MB */
4859                         break;
4860                 case 0x21:
4861                         size = 1 << 27; /* 128MB */
4862                         break;
4863                 case 0x22:
4864                         size = 1 << 28; /* 256MB */
4865                         break;
4866                 }
4867                 break;
4868         }
4869
4870         case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
4871                 /**
4872                  * This Density -> Size decoding table is taken from ISSI
4873                  * Data Sheets.
4874                  */
4875                 density = (flashid >> 16) & 0xff;
4876                 switch (density) {
4877                 case 0x16:
4878                         size = 1 << 25; /* 32MB */
4879                         break;
4880                 case 0x17:
4881                         size = 1 << 26; /* 64MB */
4882                         break;
4883                 }
4884                 break;
4885         }
4886
4887         case 0xc2: { /* Macronix */
4888                 /**
4889                  * This Density -> Size decoding table is taken from Macronix
4890                  * Data Sheets.
4891                  */
4892                 density = (flashid >> 16) & 0xff;
4893                 switch (density) {
4894                 case 0x17:
4895                         size = 1 << 23; /* 8MB */
4896                         break;
4897                 case 0x18:
4898                         size = 1 << 24; /* 16MB */
4899                         break;
4900                 }
4901                 break;
4902         }
4903
4904         case 0xef: { /* Winbond */
4905                 /**
4906                  * This Density -> Size decoding table is taken from Winbond
4907                  * Data Sheets.
4908                  */
4909                 density = (flashid >> 16) & 0xff;
4910                 switch (density) {
4911                 case 0x17:
4912                         size = 1 << 23; /* 8MB */
4913                         break;
4914                 case 0x18:
4915                         size = 1 << 24; /* 16MB */
4916                         break;
4917                 }
4918                 break;
4919         }
4920         }
4921
4922         /* If we didn't recognize the FLASH part, that's no real issue: the
4923          * Hardware/Software contract says that Hardware will _*ALWAYS*_
4924          * use a FLASH part which is at least 4MB in size and has 64KB
4925          * sectors.  The unrecognized FLASH part is likely to be much larger
4926          * than 4MB, but that's all we really need.
4927          */
4928         if (size == 0) {
4929                 dev_warn(adapter,
4930                          "Unknown Flash Part, ID = %#x, assuming 4MB\n",
4931                          flashid);
4932                 size = 1 << 22;
4933         }
4934
4935         /**
4936          * Store decoded Flash size and fall through into vetting code.
4937          */
4938         adapter->params.sf_size = size;
4939         adapter->params.sf_nsec = size / SF_SEC_SIZE;
4940
4941 found:
4942         /*
4943          * We should reject adapters with FLASHes which are too small. So, emit
4944          * a warning.
4945          */
4946         if (adapter->params.sf_size < FLASH_MIN_SIZE)
4947                 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4948                          flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4949
4950         return 0;
4951 }
4952
4953 static void set_pcie_completion_timeout(struct adapter *adapter,
4954                                         u8 range)
4955 {
4956         u32 pcie_cap;
4957         u16 val;
4958
4959         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4960         if (pcie_cap) {
4961                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4962                 val &= 0xfff0;
4963                 val |= range;
4964                 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4965         }
4966 }
4967
4968 /**
4969  * t4_get_chip_type - Determine chip type from device ID
4970  * @adap: the adapter
4971  * @ver: adapter version
4972  */
4973 int t4_get_chip_type(struct adapter *adap, int ver)
4974 {
4975         enum chip_type chip = 0;
4976         u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4977
4978         /* Retrieve adapter's device ID */
4979         switch (ver) {
4980         case CHELSIO_T5:
4981                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4982                 break;
4983         case CHELSIO_T6:
4984                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4985                 break;
4986         default:
4987                 dev_err(adap, "Device %d is not supported\n",
4988                         adap->params.pci.device_id);
4989                 return -EINVAL;
4990         }
4991
4992         return chip;
4993 }
4994
4995 /**
4996  * t4_prep_adapter - prepare SW and HW for operation
4997  * @adapter: the adapter
4998  *
4999  * Initialize adapter SW state for the various HW modules, set initial
5000  * values for some adapter tunables, take PHYs out of reset, and
5001  * initialize the MDIO interface.
5002  */
5003 int t4_prep_adapter(struct adapter *adapter)
5004 {
5005         int ret, ver;
5006         u32 pl_rev;
5007
5008         ret = t4_wait_dev_ready(adapter);
5009         if (ret < 0)
5010                 return ret;
5011
5012         pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
5013         adapter->params.pci.device_id = adapter->pdev->id.device_id;
5014         adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
5015
5016         /*
5017          * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
5018          * ADAPTER (VERSION << 4 | REVISION)
5019          */
5020         ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
5021         adapter->params.chip = 0;
5022         switch (ver) {
5023         case CHELSIO_T5:
5024                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
5025                 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
5026                 adapter->params.arch.mps_tcam_size =
5027                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
5028                 adapter->params.arch.mps_rplc_size = 128;
5029                 adapter->params.arch.nchan = NCHAN;
5030                 adapter->params.arch.vfcount = 128;
5031                 /* Congestion map is for 4 channels so that
5032                  * MPS can have 4 priority per port.
5033                  */
5034                 adapter->params.arch.cng_ch_bits_log = 2;
5035                 break;
5036         case CHELSIO_T6:
5037                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
5038                 adapter->params.arch.sge_fl_db = 0;
5039                 adapter->params.arch.mps_tcam_size =
5040                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
5041                 adapter->params.arch.mps_rplc_size = 256;
5042                 adapter->params.arch.nchan = 2;
5043                 adapter->params.arch.vfcount = 256;
5044                 /* Congestion map is for 2 channels so that
5045                  * MPS can have 8 priority per port.
5046                  */
5047                 adapter->params.arch.cng_ch_bits_log = 3;
5048                 break;
5049         default:
5050                 dev_err(adapter, "%s: Device %d is not supported\n",
5051                         __func__, adapter->params.pci.device_id);
5052                 return -EINVAL;
5053         }
5054
5055         adapter->params.pci.vpd_cap_addr =
5056                 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
5057
5058         ret = t4_get_flash_params(adapter);
5059         if (ret < 0) {
5060                 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
5061                         -ret);
5062                 return ret;
5063         }
5064
5065         adapter->params.cim_la_size = CIMLA_SIZE;
5066
5067         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
5068
5069         /*
5070          * Default port and clock for debugging in case we can't reach FW.
5071          */
5072         adapter->params.nports = 1;
5073         adapter->params.portvec = 1;
5074         adapter->params.vpd.cclk = 50000;
5075
5076         /* Set pci completion timeout value to 4 seconds. */
5077         set_pcie_completion_timeout(adapter, 0xd);
5078         return 0;
5079 }
5080
5081 /**
5082  * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
5083  * @adapter: the adapter
5084  * @qid: the Queue ID
5085  * @qtype: the Ingress or Egress type for @qid
5086  * @pbar2_qoffset: BAR2 Queue Offset
5087  * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
5088  *
5089  * Returns the BAR2 SGE Queue Registers information associated with the
5090  * indicated Absolute Queue ID.  These are passed back in return value
5091  * pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
5092  * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
5093  *
5094  * This may return an error which indicates that BAR2 SGE Queue
5095  * registers aren't available.  If an error is not returned, then the
5096  * following values are returned:
5097  *
5098  *   *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
5099  *   *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
5100  *
5101  * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
5102  * require the "Inferred Queue ID" ability may be used.  E.g. the
5103  * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
5104  * then these "Inferred Queue ID" register may not be used.
5105  */
5106 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
5107                       enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
5108                       unsigned int *pbar2_qid)
5109 {
5110         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
5111         u64 bar2_page_offset, bar2_qoffset;
5112         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
5113
5114         /*
5115          * T4 doesn't support BAR2 SGE Queue registers.
5116          */
5117         if (is_t4(adapter->params.chip))
5118                 return -EINVAL;
5119
5120         /*
5121          * Get our SGE Page Size parameters.
5122          */
5123         page_shift = adapter->params.sge.hps + 10;
5124         page_size = 1 << page_shift;
5125
5126         /*
5127          * Get the right Queues per Page parameters for our Queue.
5128          */
5129         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
5130                               adapter->params.sge.eq_qpp :
5131                               adapter->params.sge.iq_qpp);
5132         qpp_mask = (1 << qpp_shift) - 1;
5133
5134         /*
5135          * Calculate the basics of the BAR2 SGE Queue register area:
5136          *  o The BAR2 page the Queue registers will be in.
5137          *  o The BAR2 Queue ID.
5138          *  o The BAR2 Queue ID Offset into the BAR2 page.
5139          */
5140         bar2_page_offset = ((qid >> qpp_shift) << page_shift);
5141         bar2_qid = qid & qpp_mask;
5142         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
5143
5144         /*
5145          * If the BAR2 Queue ID Offset is less than the Page Size, then the
5146          * hardware will infer the Absolute Queue ID simply from the writes to
5147          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
5148          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
5149          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
5150          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
5151          * from the BAR2 Page and BAR2 Queue ID.
5152          *
5153          * One important censequence of this is that some BAR2 SGE registers
5154          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
5155          * there.  But other registers synthesize the SGE Queue ID purely
5156          * from the writes to the registers -- the Write Combined Doorbell
5157          * Buffer is a good example.  These BAR2 SGE Registers are only
5158          * available for those BAR2 SGE Register areas where the SGE Absolute
5159          * Queue ID can be inferred from simple writes.
5160          */
5161         bar2_qoffset = bar2_page_offset;
5162         bar2_qinferred = (bar2_qid_offset < page_size);
5163         if (bar2_qinferred) {
5164                 bar2_qoffset += bar2_qid_offset;
5165                 bar2_qid = 0;
5166         }
5167
5168         *pbar2_qoffset = bar2_qoffset;
5169         *pbar2_qid = bar2_qid;
5170         return 0;
5171 }
5172
5173 /**
5174  * t4_init_sge_params - initialize adap->params.sge
5175  * @adapter: the adapter
5176  *
5177  * Initialize various fields of the adapter's SGE Parameters structure.
5178  */
5179 int t4_init_sge_params(struct adapter *adapter)
5180 {
5181         struct sge_params *sge_params = &adapter->params.sge;
5182         u32 hps, qpp;
5183         unsigned int s_hps, s_qpp;
5184
5185         /*
5186          * Extract the SGE Page Size for our PF.
5187          */
5188         hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
5189         s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
5190                  adapter->pf);
5191         sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
5192
5193         /*
5194          * Extract the SGE Egress and Ingess Queues Per Page for our PF.
5195          */
5196         s_qpp = (S_QUEUESPERPAGEPF0 +
5197                  (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
5198         qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
5199         sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
5200         qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
5201         sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
5202
5203         return 0;
5204 }
5205
5206 /**
5207  * t4_init_tp_params - initialize adap->params.tp
5208  * @adap: the adapter
5209  *
5210  * Initialize various fields of the adapter's TP Parameters structure.
5211  */
5212 int t4_init_tp_params(struct adapter *adap)
5213 {
5214         int chan, ret;
5215         u32 param, v;
5216
5217         v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
5218         adap->params.tp.tre = G_TIMERRESOLUTION(v);
5219         adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
5220
5221         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
5222         for (chan = 0; chan < NCHAN; chan++)
5223                 adap->params.tp.tx_modq[chan] = chan;
5224
5225         /*
5226          * Cache the adapter's Compressed Filter Mode/Mask and global Ingress
5227          * Configuration.
5228          */
5229         param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5230                  V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
5231                  V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK));
5232
5233         /* Read current value */
5234         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
5235                               1, &param, &v);
5236         if (!ret) {
5237                 dev_info(adap, "Current filter mode/mask 0x%x:0x%x\n",
5238                          G_FW_PARAMS_PARAM_FILTER_MODE(v),
5239                          G_FW_PARAMS_PARAM_FILTER_MASK(v));
5240                 adap->params.tp.vlan_pri_map =
5241                         G_FW_PARAMS_PARAM_FILTER_MODE(v);
5242                 adap->params.tp.filter_mask =
5243                         G_FW_PARAMS_PARAM_FILTER_MASK(v);
5244         } else {
5245                 dev_info(adap,
5246                          "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
5247
5248                 /* In case of older-fw (which doesn't expose the api
5249                  * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
5250                  * the fw api) combination, fall-back to older method of reading
5251                  * the filter mode from indirect-register
5252                  */
5253                 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5254                                  &adap->params.tp.vlan_pri_map, 1,
5255                                  A_TP_VLAN_PRI_MAP);
5256
5257                 /* With the older-fw and newer-driver combination we might run
5258                  * into an issue when user wants to use hash filter region but
5259                  * the filter_mask is zero, in this case filter_mask validation
5260                  * is tough. To avoid that we set the filter_mask same as filter
5261                  * mode, which will behave exactly as the older way of ignoring
5262                  * the filter mask validation.
5263                  */
5264                 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
5265         }
5266
5267         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5268                          &adap->params.tp.ingress_config, 1,
5269                          A_TP_INGRESS_CONFIG);
5270
5271         /* For T6, cache the adapter's compressed error vector
5272          * and passing outer header info for encapsulated packets.
5273          */
5274         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
5275                 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
5276                 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
5277         }
5278
5279         /*
5280          * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
5281          * shift positions of several elements of the Compressed Filter Tuple
5282          * for this adapter which we need frequently ...
5283          */
5284         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
5285         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
5286         adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
5287         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
5288                                                                F_PROTOCOL);
5289         adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
5290                                                                 F_ETHERTYPE);
5291         adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
5292                                                                F_MACMATCH);
5293         adap->params.tp.tos_shift = t4_filter_field_shift(adap, F_TOS);
5294
5295         v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
5296         adap->params.tp.hash_filter_mask = v;
5297         v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
5298         adap->params.tp.hash_filter_mask |= ((u64)v << 32);
5299
5300         return 0;
5301 }
5302
5303 /**
5304  * t4_filter_field_shift - calculate filter field shift
5305  * @adap: the adapter
5306  * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
5307  *
5308  * Return the shift position of a filter field within the Compressed
5309  * Filter Tuple.  The filter field is specified via its selection bit
5310  * within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
5311  */
5312 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
5313 {
5314         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
5315         unsigned int sel;
5316         int field_shift;
5317
5318         if ((filter_mode & filter_sel) == 0)
5319                 return -1;
5320
5321         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
5322                 switch (filter_mode & sel) {
5323                 case F_FCOE:
5324                         field_shift += W_FT_FCOE;
5325                         break;
5326                 case F_PORT:
5327                         field_shift += W_FT_PORT;
5328                         break;
5329                 case F_VNIC_ID:
5330                         field_shift += W_FT_VNIC_ID;
5331                         break;
5332                 case F_VLAN:
5333                         field_shift += W_FT_VLAN;
5334                         break;
5335                 case F_TOS:
5336                         field_shift += W_FT_TOS;
5337                         break;
5338                 case F_PROTOCOL:
5339                         field_shift += W_FT_PROTOCOL;
5340                         break;
5341                 case F_ETHERTYPE:
5342                         field_shift += W_FT_ETHERTYPE;
5343                         break;
5344                 case F_MACMATCH:
5345                         field_shift += W_FT_MACMATCH;
5346                         break;
5347                 case F_MPSHITTYPE:
5348                         field_shift += W_FT_MPSHITTYPE;
5349                         break;
5350                 case F_FRAGMENTATION:
5351                         field_shift += W_FT_FRAGMENTATION;
5352                         break;
5353                 }
5354         }
5355         return field_shift;
5356 }
5357
5358 int t4_init_rss_mode(struct adapter *adap, int mbox)
5359 {
5360         int i, ret;
5361         struct fw_rss_vi_config_cmd rvc;
5362
5363         memset(&rvc, 0, sizeof(rvc));
5364
5365         for_each_port(adap, i) {
5366                 struct port_info *p = adap2pinfo(adap, i);
5367
5368                 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
5369                                        F_FW_CMD_REQUEST | F_FW_CMD_READ |
5370                                        V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
5371                 rvc.retval_len16 = htonl(FW_LEN16(rvc));
5372                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
5373                 if (ret)
5374                         return ret;
5375                 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
5376         }
5377         return 0;
5378 }
5379
5380 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
5381 {
5382         u32 param, val, pcaps, acaps;
5383         enum fw_port_type port_type;
5384         struct fw_port_cmd cmd;
5385         u8 vivld = 0, vin = 0;
5386         int ret, i, j = 0;
5387         int mdio_addr;
5388         u8 addr[6];
5389
5390         param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) |
5391                  V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
5392         val = 1;
5393         ret = t4_set_params(adap, mbox, pf, vf, 1, &param, &val);
5394         if (ret < 0)
5395                 return ret;
5396
5397         memset(&cmd, 0, sizeof(cmd));
5398
5399         for_each_port(adap, i) {
5400                 struct port_info *pi = adap2pinfo(adap, i);
5401                 unsigned int rss_size = 0;
5402                 u32 lstatus32;
5403
5404                 while ((adap->params.portvec & (1 << j)) == 0)
5405                         j++;
5406
5407                 memset(&cmd, 0, sizeof(cmd));
5408                 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
5409                                                F_FW_CMD_REQUEST |
5410                                                F_FW_CMD_READ |
5411                                                V_FW_PORT_CMD_PORTID(j));
5412                 val = FW_PORT_ACTION_GET_PORT_INFO32;
5413                 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(val) |
5414                                                   FW_LEN16(cmd));
5415                 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
5416                 if (ret)
5417                         return ret;
5418
5419                 /* Extract the various fields from the Port Information
5420                  * message.
5421                  */
5422                 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
5423
5424                 port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);
5425                 mdio_addr = (lstatus32 & F_FW_PORT_CMD_MDIOCAP32) ?
5426                             (int)G_FW_PORT_CMD_MDIOADDR32(lstatus32) : -1;
5427                 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
5428                 acaps = be32_to_cpu(cmd.u.info32.acaps32);
5429
5430                 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size,
5431                                   &vivld, &vin);
5432                 if (ret < 0)
5433                         return ret;
5434
5435                 pi->viid = ret;
5436                 pi->tx_chan = j;
5437                 pi->rss_size = rss_size;
5438                 t4_os_set_hw_addr(adap, i, addr);
5439
5440                 /* If fw supports returning the VIN as part of FW_VI_CMD,
5441                  * save the returned values.
5442                  */
5443                 if (adap->params.viid_smt_extn_support) {
5444                         pi->vivld = vivld;
5445                         pi->vin = vin;
5446                 } else {
5447                         /* Retrieve the values from VIID */
5448                         pi->vivld = G_FW_VIID_VIVLD(pi->viid);
5449                         pi->vin =  G_FW_VIID_VIN(pi->viid);
5450                 }
5451
5452                 t4_init_link_config(pi, pcaps, acaps, mdio_addr, port_type,
5453                                     FW_PORT_MOD_TYPE_NA);
5454                 j++;
5455         }
5456         return 0;
5457 }
5458
5459 /**
5460  * t4_memory_rw_addr - read/write adapter memory via PCIE memory window
5461  * @adap: the adapter
5462  * @win: PCI-E Memory Window to use
5463  * @addr: address within adapter memory
5464  * @len: amount of memory to transfer
5465  * @hbuf: host memory buffer
5466  * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
5467  *
5468  * Reads/writes an [almost] arbitrary memory region in the firmware: the
5469  * firmware memory address and host buffer must be aligned on 32-bit
5470  * boudaries; the length may be arbitrary.
5471  *
5472  * NOTES:
5473  *  1. The memory is transferred as a raw byte sequence from/to the
5474  *     firmware's memory.  If this memory contains data structures which
5475  *     contain multi-byte integers, it's the caller's responsibility to
5476  *     perform appropriate byte order conversions.
5477  *
5478  *  2. It is the Caller's responsibility to ensure that no other code
5479  *     uses the specified PCI-E Memory Window while this routine is
5480  *     using it.  This is typically done via the use of OS-specific
5481  *     locks, etc.
5482  */
5483 int t4_memory_rw_addr(struct adapter *adap, int win, u32 addr,
5484                       u32 len, void *hbuf, int dir)
5485 {
5486         u32 pos, offset, resid;
5487         u32 win_pf, mem_reg, mem_aperture, mem_base;
5488         u32 *buf;
5489
5490         /* Argument sanity checks ...*/
5491         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
5492                 return -EINVAL;
5493         buf = (u32 *)hbuf;
5494
5495         /* It's convenient to be able to handle lengths which aren't a
5496          * multiple of 32-bits because we often end up transferring files to
5497          * the firmware.  So we'll handle that by normalizing the length here
5498          * and then handling any residual transfer at the end.
5499          */
5500         resid = len & 0x3;
5501         len -= resid;
5502
5503         /* Each PCI-E Memory Window is programmed with a window size -- or
5504          * "aperture" -- which controls the granularity of its mapping onto
5505          * adapter memory.  We need to grab that aperture in order to know
5506          * how to use the specified window.  The window is also programmed
5507          * with the base address of the Memory Window in BAR0's address
5508          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
5509          * the address is relative to BAR0.
5510          */
5511         mem_reg = t4_read_reg(adap,
5512                               PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
5513                                                   win));
5514         mem_aperture = 1 << (G_WINDOW(mem_reg) + X_WINDOW_SHIFT);
5515         mem_base = G_PCIEOFST(mem_reg) << X_PCIEOFST_SHIFT;
5516
5517         win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->pf);
5518
5519         /* Calculate our initial PCI-E Memory Window Position and Offset into
5520          * that Window.
5521          */
5522         pos = addr & ~(mem_aperture - 1);
5523         offset = addr - pos;
5524
5525         /* Set up initial PCI-E Memory Window to cover the start of our
5526          * transfer.  (Read it back to ensure that changes propagate before we
5527          * attempt to use the new value.)
5528          */
5529         t4_write_reg(adap,
5530                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, win),
5531                      pos | win_pf);
5532         t4_read_reg(adap,
5533                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, win));
5534
5535         /* Transfer data to/from the adapter as long as there's an integral
5536          * number of 32-bit transfers to complete.
5537          *
5538          * A note on Endianness issues:
5539          *
5540          * The "register" reads and writes below from/to the PCI-E Memory
5541          * Window invoke the standard adapter Big-Endian to PCI-E Link
5542          * Little-Endian "swizzel."  As a result, if we have the following
5543          * data in adapter memory:
5544          *
5545          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
5546          *     Address:      i+0  i+1  i+2  i+3
5547          *
5548          * Then a read of the adapter memory via the PCI-E Memory Window
5549          * will yield:
5550          *
5551          *     x = readl(i)
5552          *         31                  0
5553          *         [ b3 | b2 | b1 | b0 ]
5554          *
5555          * If this value is stored into local memory on a Little-Endian system
5556          * it will show up correctly in local memory as:
5557          *
5558          *     ( ..., b0, b1, b2, b3, ... )
5559          *
5560          * But on a Big-Endian system, the store will show up in memory
5561          * incorrectly swizzled as:
5562          *
5563          *     ( ..., b3, b2, b1, b0, ... )
5564          *
5565          * So we need to account for this in the reads and writes to the
5566          * PCI-E Memory Window below by undoing the register read/write
5567          * swizzels.
5568          */
5569         while (len > 0) {
5570                 if (dir == T4_MEMORY_READ)
5571                         *buf++ = le32_to_cpu((__le32)t4_read_reg(adap,
5572                                                                  mem_base +
5573                                                                  offset));
5574                 else
5575                         t4_write_reg(adap, mem_base + offset,
5576                                      (u32)cpu_to_le32(*buf++));
5577                 offset += sizeof(__be32);
5578                 len -= sizeof(__be32);
5579
5580                 /* If we've reached the end of our current window aperture,
5581                  * move the PCI-E Memory Window on to the next.  Note that
5582                  * doing this here after "len" may be 0 allows us to set up
5583                  * the PCI-E Memory Window for a possible final residual
5584                  * transfer below ...
5585                  */
5586                 if (offset == mem_aperture) {
5587                         pos += mem_aperture;
5588                         offset = 0;
5589                         t4_write_reg(adap,
5590                                 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET,
5591                                                     win), pos | win_pf);
5592                         t4_read_reg(adap,
5593                                 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET,
5594                                                     win));
5595                 }
5596         }
5597
5598         /* If the original transfer had a length which wasn't a multiple of
5599          * 32-bits, now's where we need to finish off the transfer of the
5600          * residual amount.  The PCI-E Memory Window has already been moved
5601          * above (if necessary) to cover this final transfer.
5602          */
5603         if (resid) {
5604                 union {
5605                         u32 word;
5606                         char byte[4];
5607                 } last;
5608                 unsigned char *bp;
5609                 int i;
5610
5611                 if (dir == T4_MEMORY_READ) {
5612                         last.word = le32_to_cpu((__le32)t4_read_reg(adap,
5613                                                                     mem_base +
5614                                                                     offset));
5615                         for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
5616                                 bp[i] = last.byte[i];
5617                 } else {
5618                         last.word = *buf;
5619                         for (i = resid; i < 4; i++)
5620                                 last.byte[i] = 0;
5621                         t4_write_reg(adap, mem_base + offset,
5622                                      (u32)cpu_to_le32(last.word));
5623                 }
5624         }
5625
5626         return 0;
5627 }
5628
5629 /**
5630  * t4_memory_rw_mtype -read/write EDC 0, EDC 1 or MC via PCIE memory window
5631  * @adap: the adapter
5632  * @win: PCI-E Memory Window to use
5633  * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
5634  * @maddr: address within indicated memory type
5635  * @len: amount of memory to transfer
5636  * @hbuf: host memory buffer
5637  * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
5638  *
5639  * Reads/writes adapter memory using t4_memory_rw_addr().  This routine
5640  * provides an (memory type, address within memory type) interface.
5641  */
5642 int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr,
5643                        u32 len, void *hbuf, int dir)
5644 {
5645         u32 mtype_offset;
5646         u32 edc_size, mc_size;
5647
5648         /* Offset into the region of memory which is being accessed
5649          * MEM_EDC0 = 0
5650          * MEM_EDC1 = 1
5651          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
5652          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
5653          */
5654         edc_size  = G_EDRAM0_SIZE(t4_read_reg(adap, A_MA_EDRAM0_BAR));
5655         if (mtype != MEM_MC1) {
5656                 mtype_offset = (mtype * (edc_size * 1024 * 1024));
5657         } else {
5658                 mc_size = G_EXT_MEM0_SIZE(t4_read_reg(adap,
5659                                                       A_MA_EXT_MEMORY0_BAR));
5660                 mtype_offset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
5661         }
5662
5663         return t4_memory_rw_addr(adap, win,
5664                                  mtype_offset + maddr, len,
5665                                  hbuf, dir);
5666 }