drivers/net/cxgbe/base/t4_hw.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <netinet/in.h>
  35
  36 #include <rte_interrupts.h>
  37 #include <rte_log.h>
  38 #include <rte_debug.h>
  39 #include <rte_pci.h>
  40 #include <rte_atomic.h>
  41 #include <rte_branch_prediction.h>
  42 #include <rte_memory.h>
  43 #include <rte_memzone.h>
  44 #include <rte_tailq.h>
  45 #include <rte_eal.h>
  46 #include <rte_alarm.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_atomic.h>
  50 #include <rte_malloc.h>
  51 #include <rte_random.h>
  52 #include <rte_dev.h>
  53 #include <rte_byteorder.h>
  54
  55 #include "common.h"
  56 #include "t4_regs.h"
  57 #include "t4_regs_values.h"
  58 #include "t4fw_interface.h"
  59
  60 static void init_link_config(struct link_config *lc, unsigned int caps);
  61
  62 /**
  63  * t4_read_mtu_tbl - returns the values in the HW path MTU table
  64  * @adap: the adapter
  65  * @mtus: where to store the MTU values
  66  * @mtu_log: where to store the MTU base-2 log (may be %NULL)
  67  *
  68  * Reads the HW path MTU table.
  69  */
  70 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
  71 {
  72         u32 v;
  73         int i;
  74
  75         for (i = 0; i < NMTUS; ++i) {
  76                 t4_write_reg(adap, A_TP_MTU_TABLE,
  77                              V_MTUINDEX(0xff) | V_MTUVALUE(i));
  78                 v = t4_read_reg(adap, A_TP_MTU_TABLE);
  79                 mtus[i] = G_MTUVALUE(v);
  80                 if (mtu_log)
  81                         mtu_log[i] = G_MTUWIDTH(v);
  82         }
  83 }
  84
  85 /**
  86  * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
  87  * @adap: the adapter
  88  * @addr: the indirect TP register address
  89  * @mask: specifies the field within the register to modify
  90  * @val: new value for the field
  91  *
  92  * Sets a field of an indirect TP register to the given value.
  93  */
  94 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
  95                             unsigned int mask, unsigned int val)
  96 {
  97         t4_write_reg(adap, A_TP_PIO_ADDR, addr);
  98         val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
  99         t4_write_reg(adap, A_TP_PIO_DATA, val);
 100 }
 101
 102 /* The minimum additive increment value for the congestion control table */
 103 #define CC_MIN_INCR 2U
 104
 105 /**
 106  * t4_load_mtus - write the MTU and congestion control HW tables
 107  * @adap: the adapter
 108  * @mtus: the values for the MTU table
 109  * @alpha: the values for the congestion control alpha parameter
 110  * @beta: the values for the congestion control beta parameter
 111  *
 112  * Write the HW MTU table with the supplied MTUs and the high-speed
 113  * congestion control table with the supplied alpha, beta, and MTUs.
 114  * We write the two tables together because the additive increments
 115  * depend on the MTUs.
 116  */
 117 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
 118                   const unsigned short *alpha, const unsigned short *beta)
 119 {
 120         static const unsigned int avg_pkts[NCCTRL_WIN] = {
 121                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
 122                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
 123                 28672, 40960, 57344, 81920, 114688, 163840, 229376
 124         };
 125
 126         unsigned int i, w;
 127
 128         for (i = 0; i < NMTUS; ++i) {
 129                 unsigned int mtu = mtus[i];
 130                 unsigned int log2 = cxgbe_fls(mtu);
 131
 132                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
 133                         log2--;
 134                 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
 135                              V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
 136
 137                 for (w = 0; w < NCCTRL_WIN; ++w) {
 138                         unsigned int inc;
 139
 140                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
 141                                   CC_MIN_INCR);
 142
 143                         t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
 144                                      (w << 16) | (beta[w] << 13) | inc);
 145                 }
 146         }
 147 }
 148
 149 /**
 150  * t4_wait_op_done_val - wait until an operation is completed
 151  * @adapter: the adapter performing the operation
 152  * @reg: the register to check for completion
 153  * @mask: a single-bit field within @reg that indicates completion
 154  * @polarity: the value of the field when the operation is completed
 155  * @attempts: number of check iterations
 156  * @delay: delay in usecs between iterations
 157  * @valp: where to store the value of the register at completion time
 158  *
 159  * Wait until an operation is completed by checking a bit in a register
 160  * up to @attempts times.  If @valp is not NULL the value of the register
 161  * at the time it indicated completion is stored there.  Returns 0 if the
 162  * operation completes and -EAGAIN otherwise.
 163  */
 164 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 165                         int polarity, int attempts, int delay, u32 *valp)
 166 {
 167         while (1) {
 168                 u32 val = t4_read_reg(adapter, reg);
 169
 170                 if (!!(val & mask) == polarity) {
 171                         if (valp)
 172                                 *valp = val;
 173                         return 0;
 174                 }
 175                 if (--attempts == 0)
 176                         return -EAGAIN;
 177                 if (delay)
 178                         udelay(delay);
 179         }
 180 }
 181
 182 /**
 183  * t4_set_reg_field - set a register field to a value
 184  * @adapter: the adapter to program
 185  * @addr: the register address
 186  * @mask: specifies the portion of the register to modify
 187  * @val: the new value for the register field
 188  *
 189  * Sets a register field specified by the supplied mask to the
 190  * given value.
 191  */
 192 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
 193                       u32 val)
 194 {
 195         u32 v = t4_read_reg(adapter, addr) & ~mask;
 196
 197         t4_write_reg(adapter, addr, v | val);
 198         (void)t4_read_reg(adapter, addr);      /* flush */
 199 }
 200
 201 /**
 202  * t4_read_indirect - read indirectly addressed registers
 203  * @adap: the adapter
 204  * @addr_reg: register holding the indirect address
 205  * @data_reg: register holding the value of the indirect register
 206  * @vals: where the read register values are stored
 207  * @nregs: how many indirect registers to read
 208  * @start_idx: index of first indirect register to read
 209  *
 210  * Reads registers that are accessed indirectly through an address/data
 211  * register pair.
 212  */
 213 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 214                       unsigned int data_reg, u32 *vals, unsigned int nregs,
 215                       unsigned int start_idx)
 216 {
 217         while (nregs--) {
 218                 t4_write_reg(adap, addr_reg, start_idx);
 219                 *vals++ = t4_read_reg(adap, data_reg);
 220                 start_idx++;
 221         }
 222 }
 223
 224 /**
 225  * t4_write_indirect - write indirectly addressed registers
 226  * @adap: the adapter
 227  * @addr_reg: register holding the indirect addresses
 228  * @data_reg: register holding the value for the indirect registers
 229  * @vals: values to write
 230  * @nregs: how many indirect registers to write
 231  * @start_idx: address of first indirect register to write
 232  *
 233  * Writes a sequential block of registers that are accessed indirectly
 234  * through an address/data register pair.
 235  */
 236 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 237                        unsigned int data_reg, const u32 *vals,
 238                        unsigned int nregs, unsigned int start_idx)
 239 {
 240         while (nregs--) {
 241                 t4_write_reg(adap, addr_reg, start_idx++);
 242                 t4_write_reg(adap, data_reg, *vals++);
 243         }
 244 }
 245
 246 /**
 247  * t4_report_fw_error - report firmware error
 248  * @adap: the adapter
 249  *
 250  * The adapter firmware can indicate error conditions to the host.
 251  * If the firmware has indicated an error, print out the reason for
 252  * the firmware error.
 253  */
 254 static void t4_report_fw_error(struct adapter *adap)
 255 {
 256         static const char * const reason[] = {
 257                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 258                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 259                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 260                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 261                 "Unexpected Event",     /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 262                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 263                 "Device Shutdown",      /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 264                 "Reserved",                     /* reserved */
 265         };
 266         u32 pcie_fw;
 267
 268         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 269         if (pcie_fw & F_PCIE_FW_ERR)
 270                 pr_err("%s: Firmware reports adapter error: %s\n",
 271                        __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
 272 }
 273
 274 /*
 275  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 276  */
 277 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 278                          u32 mbox_addr)
 279 {
 280         for ( ; nflit; nflit--, mbox_addr += 8)
 281                 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
 282 }
 283
 284 /*
 285  * Handle a FW assertion reported in a mailbox.
 286  */
 287 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 288 {
 289         struct fw_debug_cmd asrt;
 290
 291         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 292         pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 293                 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 294                 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 295 }
 296
 297 #define X_CIM_PF_NOACCESS 0xeeeeeeee
 298
 299 /*
 300  * If the Host OS Driver needs locking arround accesses to the mailbox, this
 301  * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
 302  */
 303 /* makes single-statement usage a bit cleaner ... */
 304 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 305 #define T4_OS_MBOX_LOCKING(x) x
 306 #else
 307 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
 308 #endif
 309
 310 /**
 311  * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 312  * @adap: the adapter
 313  * @mbox: index of the mailbox to use
 314  * @cmd: the command to write
 315  * @size: command length in bytes
 316  * @rpl: where to optionally store the reply
 317  * @sleep_ok: if true we may sleep while awaiting command completion
 318  * @timeout: time to wait for command to finish before timing out
 319  *           (negative implies @sleep_ok=false)
 320  *
 321  * Sends the given command to FW through the selected mailbox and waits
 322  * for the FW to execute the command.  If @rpl is not %NULL it is used to
 323  * store the FW's reply to the command.  The command and its optional
 324  * reply are of the same length.  Some FW commands like RESET and
 325  * INITIALIZE can take a considerable amount of time to execute.
 326  * @sleep_ok determines whether we may sleep while awaiting the response.
 327  * If sleeping is allowed we use progressive backoff otherwise we spin.
 328  * Note that passing in a negative @timeout is an alternate mechanism
 329  * for specifying @sleep_ok=false.  This is useful when a higher level
 330  * interface allows for specification of @timeout but not @sleep_ok ...
 331  *
 332  * Returns 0 on success or a negative errno on failure.  A
 333  * failure can happen either because we are not able to execute the
 334  * command or FW executes it but signals an error.  In the latter case
 335  * the return value is the error code indicated by FW (negated).
 336  */
 337 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
 338                             const void __attribute__((__may_alias__)) *cmd,
 339                             int size, void *rpl, bool sleep_ok, int timeout)
 340 {
 341         /*
 342          * We delay in small increments at first in an effort to maintain
 343          * responsiveness for simple, fast executing commands but then back
 344          * off to larger delays to a maximum retry delay.
 345          */
 346         static const int delay[] = {
 347                 1, 1, 3, 5, 10, 10, 20, 50, 100
 348         };
 349
 350         u32 v;
 351         u64 res;
 352         int i, ms;
 353         unsigned int delay_idx;
 354         __be64 *temp = (__be64 *)malloc(size * sizeof(char));
 355         __be64 *p = temp;
 356         u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
 357         u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
 358         u32 ctl;
 359         struct mbox_entry entry;
 360         u32 pcie_fw = 0;
 361
 362         if (!temp)
 363                 return -ENOMEM;
 364
 365         if ((size & 15) || size > MBOX_LEN) {
 366                 free(temp);
 367                 return -EINVAL;
 368         }
 369
 370         bzero(p, size);
 371         memcpy(p, (const __be64 *)cmd, size);
 372
 373         /*
 374          * If we have a negative timeout, that implies that we can't sleep.
 375          */
 376         if (timeout < 0) {
 377                 sleep_ok = false;
 378                 timeout = -timeout;
 379         }
 380
 381 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 382         /*
 383          * Queue ourselves onto the mailbox access list.  When our entry is at
 384          * the front of the list, we have rights to access the mailbox.  So we
 385          * wait [for a while] till we're at the front [or bail out with an
 386          * EBUSY] ...
 387          */
 388         t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
 389
 390         delay_idx = 0;
 391         ms = delay[0];
 392
 393         for (i = 0; ; i += ms) {
 394                 /*
 395                  * If we've waited too long, return a busy indication.  This
 396                  * really ought to be based on our initial position in the
 397                  * mailbox access list but this is a start.  We very rarely
 398                  * contend on access to the mailbox ...  Also check for a
 399                  * firmware error which we'll report as a device error.
 400                  */
 401                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 402                 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
 403                         t4_os_atomic_list_del(&entry, &adap->mbox_list,
 404                                               &adap->mbox_lock);
 405                         t4_report_fw_error(adap);
 406                         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
 407                 }
 408
 409                 /*
 410                  * If we're at the head, break out and start the mailbox
 411                  * protocol.
 412                  */
 413                 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
 414                         break;
 415
 416                 /*
 417                  * Delay for a bit before checking again ...
 418                  */
 419                 if (sleep_ok) {
 420                         ms = delay[delay_idx];  /* last element may repeat */
 421                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 422                                 delay_idx++;
 423                         msleep(ms);
 424                 } else {
 425                         rte_delay_ms(ms);
 426                 }
 427         }
 428 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
 429
 430         /*
 431          * Attempt to gain access to the mailbox.
 432          */
 433         for (i = 0; i < 4; i++) {
 434                 ctl = t4_read_reg(adap, ctl_reg);
 435                 v = G_MBOWNER(ctl);
 436                 if (v != X_MBOWNER_NONE)
 437                         break;
 438         }
 439
 440         /*
 441          * If we were unable to gain access, dequeue ourselves from the
 442          * mailbox atomic access list and report the error to our caller.
 443          */
 444         if (v != X_MBOWNER_PL) {
 445                 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 446                                                          &adap->mbox_list,
 447                                                          &adap->mbox_lock));
 448                 t4_report_fw_error(adap);
 449                 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
 450         }
 451
 452         /*
 453          * If we gain ownership of the mailbox and there's a "valid" message
 454          * in it, this is likely an asynchronous error message from the
 455          * firmware.  So we'll report that and then proceed on with attempting
 456          * to issue our own command ... which may well fail if the error
 457          * presaged the firmware crashing ...
 458          */
 459         if (ctl & F_MBMSGVALID) {
 460                 dev_err(adap, "found VALID command in mbox %u: "
 461                         "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 462                         (unsigned long long)t4_read_reg64(adap, data_reg),
 463                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 464                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 465                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 466                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 467                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 468                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 469                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 470         }
 471
 472         /*
 473          * Copy in the new mailbox command and send it on its way ...
 474          */
 475         for (i = 0; i < size; i += 8, p++)
 476                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
 477
 478         CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
 479                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 480                         (unsigned long long)t4_read_reg64(adap, data_reg),
 481                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 482                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 483                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 484                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 485                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 486                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 487                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 488
 489         t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
 490         t4_read_reg(adap, ctl_reg);          /* flush write */
 491
 492         delay_idx = 0;
 493         ms = delay[0];
 494
 495         /*
 496          * Loop waiting for the reply; bail out if we time out or the firmware
 497          * reports an error.
 498          */
 499         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 500         for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
 501                 if (sleep_ok) {
 502                         ms = delay[delay_idx];  /* last element may repeat */
 503                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 504                                 delay_idx++;
 505                         msleep(ms);
 506                 } else {
 507                         msleep(ms);
 508                 }
 509
 510                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 511                 v = t4_read_reg(adap, ctl_reg);
 512                 if (v == X_CIM_PF_NOACCESS)
 513                         continue;
 514                 if (G_MBOWNER(v) == X_MBOWNER_PL) {
 515                         if (!(v & F_MBMSGVALID)) {
 516                                 t4_write_reg(adap, ctl_reg,
 517                                              V_MBOWNER(X_MBOWNER_NONE));
 518                                 continue;
 519                         }
 520
 521                         CXGBE_DEBUG_MBOX(adap,
 522                         "%s: mbox %u: %016llx %016llx %016llx %016llx "
 523                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 524                         (unsigned long long)t4_read_reg64(adap, data_reg),
 525                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 526                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 527                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 528                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 529                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 530                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 531                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 532
 533                         CXGBE_DEBUG_MBOX(adap,
 534                                 "command %#x completed in %d ms (%ssleeping)\n",
 535                                 *(const u8 *)cmd,
 536                                 i + ms, sleep_ok ? "" : "non-");
 537
 538                         res = t4_read_reg64(adap, data_reg);
 539                         if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
 540                                 fw_asrt(adap, data_reg);
 541                                 res = V_FW_CMD_RETVAL(EIO);
 542                         } else if (rpl) {
 543                                 get_mbox_rpl(adap, rpl, size / 8, data_reg);
 544                         }
 545                         t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
 546                         T4_OS_MBOX_LOCKING(
 547                                 t4_os_atomic_list_del(&entry, &adap->mbox_list,
 548                                                       &adap->mbox_lock));
 549                         return -G_FW_CMD_RETVAL((int)res);
 550                 }
 551         }
 552
 553         /*
 554          * We timed out waiting for a reply to our mailbox command.  Report
 555          * the error and also check to see if the firmware reported any
 556          * errors ...
 557          */
 558         dev_err(adap, "command %#x in mailbox %d timed out\n",
 559                 *(const u8 *)cmd, mbox);
 560         T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 561                                                  &adap->mbox_list,
 562                                                  &adap->mbox_lock));
 563         t4_report_fw_error(adap);
 564         free(temp);
 565         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
 566 }
 567
 568 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 569                     void *rpl, bool sleep_ok)
 570 {
 571         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 572                                        FW_CMD_MAX_TIMEOUT);
 573 }
 574
 575 /**
 576  * t4_get_regs_len - return the size of the chips register set
 577  * @adapter: the adapter
 578  *
 579  * Returns the size of the chip's BAR0 register space.
 580  */
 581 unsigned int t4_get_regs_len(struct adapter *adapter)
 582 {
 583         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 584
 585         switch (chip_version) {
 586         case CHELSIO_T5:
 587                 return T5_REGMAP_SIZE;
 588         }
 589
 590         dev_err(adapter,
 591                 "Unsupported chip version %d\n", chip_version);
 592         return 0;
 593 }
 594
 595 /**
 596  * t4_get_regs - read chip registers into provided buffer
 597  * @adap: the adapter
 598  * @buf: register buffer
 599  * @buf_size: size (in bytes) of register buffer
 600  *
 601  * If the provided register buffer isn't large enough for the chip's
 602  * full register range, the register dump will be truncated to the
 603  * register buffer's size.
 604  */
 605 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 606 {
 607         static const unsigned int t5_reg_ranges[] = {
 608                 0x1008, 0x10c0,
 609                 0x10cc, 0x10f8,
 610                 0x1100, 0x1100,
 611                 0x110c, 0x1148,
 612                 0x1180, 0x1184,
 613                 0x1190, 0x1194,
 614                 0x11a0, 0x11a4,
 615                 0x11b0, 0x11b4,
 616                 0x11fc, 0x123c,
 617                 0x1280, 0x173c,
 618                 0x1800, 0x18fc,
 619                 0x3000, 0x3028,
 620                 0x3060, 0x30b0,
 621                 0x30b8, 0x30d8,
 622                 0x30e0, 0x30fc,
 623                 0x3140, 0x357c,
 624                 0x35a8, 0x35cc,
 625                 0x35ec, 0x35ec,
 626                 0x3600, 0x5624,
 627                 0x56cc, 0x56ec,
 628                 0x56f4, 0x5720,
 629                 0x5728, 0x575c,
 630                 0x580c, 0x5814,
 631                 0x5890, 0x589c,
 632                 0x58a4, 0x58ac,
 633                 0x58b8, 0x58bc,
 634                 0x5940, 0x59c8,
 635                 0x59d0, 0x59dc,
 636                 0x59fc, 0x5a18,
 637                 0x5a60, 0x5a70,
 638                 0x5a80, 0x5a9c,
 639                 0x5b94, 0x5bfc,
 640                 0x6000, 0x6020,
 641                 0x6028, 0x6040,
 642                 0x6058, 0x609c,
 643                 0x60a8, 0x614c,
 644                 0x7700, 0x7798,
 645                 0x77c0, 0x78fc,
 646                 0x7b00, 0x7b58,
 647                 0x7b60, 0x7b84,
 648                 0x7b8c, 0x7c54,
 649                 0x7d00, 0x7d38,
 650                 0x7d40, 0x7d80,
 651                 0x7d8c, 0x7ddc,
 652                 0x7de4, 0x7e04,
 653                 0x7e10, 0x7e1c,
 654                 0x7e24, 0x7e38,
 655                 0x7e40, 0x7e44,
 656                 0x7e4c, 0x7e78,
 657                 0x7e80, 0x7edc,
 658                 0x7ee8, 0x7efc,
 659                 0x8dc0, 0x8de0,
 660                 0x8df8, 0x8e04,
 661                 0x8e10, 0x8e84,
 662                 0x8ea0, 0x8f84,
 663                 0x8fc0, 0x9058,
 664                 0x9060, 0x9060,
 665                 0x9068, 0x90f8,
 666                 0x9400, 0x9408,
 667                 0x9410, 0x9470,
 668                 0x9600, 0x9600,
 669                 0x9608, 0x9638,
 670                 0x9640, 0x96f4,
 671                 0x9800, 0x9808,
 672                 0x9820, 0x983c,
 673                 0x9850, 0x9864,
 674                 0x9c00, 0x9c6c,
 675                 0x9c80, 0x9cec,
 676                 0x9d00, 0x9d6c,
 677                 0x9d80, 0x9dec,
 678                 0x9e00, 0x9e6c,
 679                 0x9e80, 0x9eec,
 680                 0x9f00, 0x9f6c,
 681                 0x9f80, 0xa020,
 682                 0xd004, 0xd004,
 683                 0xd010, 0xd03c,
 684                 0xdfc0, 0xdfe0,
 685                 0xe000, 0x1106c,
 686                 0x11074, 0x11088,
 687                 0x1109c, 0x1117c,
 688                 0x11190, 0x11204,
 689                 0x19040, 0x1906c,
 690                 0x19078, 0x19080,
 691                 0x1908c, 0x190e8,
 692                 0x190f0, 0x190f8,
 693                 0x19100, 0x19110,
 694                 0x19120, 0x19124,
 695                 0x19150, 0x19194,
 696                 0x1919c, 0x191b0,
 697                 0x191d0, 0x191e8,
 698                 0x19238, 0x19290,
 699                 0x193f8, 0x19428,
 700                 0x19430, 0x19444,
 701                 0x1944c, 0x1946c,
 702                 0x19474, 0x19474,
 703                 0x19490, 0x194cc,
 704                 0x194f0, 0x194f8,
 705                 0x19c00, 0x19c08,
 706                 0x19c10, 0x19c60,
 707                 0x19c94, 0x19ce4,
 708                 0x19cf0, 0x19d40,
 709                 0x19d50, 0x19d94,
 710                 0x19da0, 0x19de8,
 711                 0x19df0, 0x19e10,
 712                 0x19e50, 0x19e90,
 713                 0x19ea0, 0x19f24,
 714                 0x19f34, 0x19f34,
 715                 0x19f40, 0x19f50,
 716                 0x19f90, 0x19fb4,
 717                 0x19fc4, 0x19fe4,
 718                 0x1a000, 0x1a004,
 719                 0x1a010, 0x1a06c,
 720                 0x1a0b0, 0x1a0e4,
 721                 0x1a0ec, 0x1a0f8,
 722                 0x1a100, 0x1a108,
 723                 0x1a114, 0x1a120,
 724                 0x1a128, 0x1a130,
 725                 0x1a138, 0x1a138,
 726                 0x1a190, 0x1a1c4,
 727                 0x1a1fc, 0x1a1fc,
 728                 0x1e008, 0x1e00c,
 729                 0x1e040, 0x1e044,
 730                 0x1e04c, 0x1e04c,
 731                 0x1e284, 0x1e290,
 732                 0x1e2c0, 0x1e2c0,
 733                 0x1e2e0, 0x1e2e0,
 734                 0x1e300, 0x1e384,
 735                 0x1e3c0, 0x1e3c8,
 736                 0x1e408, 0x1e40c,
 737                 0x1e440, 0x1e444,
 738                 0x1e44c, 0x1e44c,
 739                 0x1e684, 0x1e690,
 740                 0x1e6c0, 0x1e6c0,
 741                 0x1e6e0, 0x1e6e0,
 742                 0x1e700, 0x1e784,
 743                 0x1e7c0, 0x1e7c8,
 744                 0x1e808, 0x1e80c,
 745                 0x1e840, 0x1e844,
 746                 0x1e84c, 0x1e84c,
 747                 0x1ea84, 0x1ea90,
 748                 0x1eac0, 0x1eac0,
 749                 0x1eae0, 0x1eae0,
 750                 0x1eb00, 0x1eb84,
 751                 0x1ebc0, 0x1ebc8,
 752                 0x1ec08, 0x1ec0c,
 753                 0x1ec40, 0x1ec44,
 754                 0x1ec4c, 0x1ec4c,
 755                 0x1ee84, 0x1ee90,
 756                 0x1eec0, 0x1eec0,
 757                 0x1eee0, 0x1eee0,
 758                 0x1ef00, 0x1ef84,
 759                 0x1efc0, 0x1efc8,
 760                 0x1f008, 0x1f00c,
 761                 0x1f040, 0x1f044,
 762                 0x1f04c, 0x1f04c,
 763                 0x1f284, 0x1f290,
 764                 0x1f2c0, 0x1f2c0,
 765                 0x1f2e0, 0x1f2e0,
 766                 0x1f300, 0x1f384,
 767                 0x1f3c0, 0x1f3c8,
 768                 0x1f408, 0x1f40c,
 769                 0x1f440, 0x1f444,
 770                 0x1f44c, 0x1f44c,
 771                 0x1f684, 0x1f690,
 772                 0x1f6c0, 0x1f6c0,
 773                 0x1f6e0, 0x1f6e0,
 774                 0x1f700, 0x1f784,
 775                 0x1f7c0, 0x1f7c8,
 776                 0x1f808, 0x1f80c,
 777                 0x1f840, 0x1f844,
 778                 0x1f84c, 0x1f84c,
 779                 0x1fa84, 0x1fa90,
 780                 0x1fac0, 0x1fac0,
 781                 0x1fae0, 0x1fae0,
 782                 0x1fb00, 0x1fb84,
 783                 0x1fbc0, 0x1fbc8,
 784                 0x1fc08, 0x1fc0c,
 785                 0x1fc40, 0x1fc44,
 786                 0x1fc4c, 0x1fc4c,
 787                 0x1fe84, 0x1fe90,
 788                 0x1fec0, 0x1fec0,
 789                 0x1fee0, 0x1fee0,
 790                 0x1ff00, 0x1ff84,
 791                 0x1ffc0, 0x1ffc8,
 792                 0x30000, 0x30030,
 793                 0x30038, 0x30038,
 794                 0x30040, 0x30040,
 795                 0x30100, 0x30144,
 796                 0x30190, 0x301a0,
 797                 0x301a8, 0x301b8,
 798                 0x301c4, 0x301c8,
 799                 0x301d0, 0x301d0,
 800                 0x30200, 0x30318,
 801                 0x30400, 0x304b4,
 802                 0x304c0, 0x3052c,
 803                 0x30540, 0x3061c,
 804                 0x30800, 0x30828,
 805                 0x30834, 0x30834,
 806                 0x308c0, 0x30908,
 807                 0x30910, 0x309ac,
 808                 0x30a00, 0x30a14,
 809                 0x30a1c, 0x30a2c,
 810                 0x30a44, 0x30a50,
 811                 0x30a74, 0x30a74,
 812                 0x30a7c, 0x30afc,
 813                 0x30b08, 0x30c24,
 814                 0x30d00, 0x30d00,
 815                 0x30d08, 0x30d14,
 816                 0x30d1c, 0x30d20,
 817                 0x30d3c, 0x30d3c,
 818                 0x30d48, 0x30d50,
 819                 0x31200, 0x3120c,
 820                 0x31220, 0x31220,
 821                 0x31240, 0x31240,
 822                 0x31600, 0x3160c,
 823                 0x31a00, 0x31a1c,
 824                 0x31e00, 0x31e20,
 825                 0x31e38, 0x31e3c,
 826                 0x31e80, 0x31e80,
 827                 0x31e88, 0x31ea8,
 828                 0x31eb0, 0x31eb4,
 829                 0x31ec8, 0x31ed4,
 830                 0x31fb8, 0x32004,
 831                 0x32200, 0x32200,
 832                 0x32208, 0x32240,
 833                 0x32248, 0x32280,
 834                 0x32288, 0x322c0,
 835                 0x322c8, 0x322fc,
 836                 0x32600, 0x32630,
 837                 0x32a00, 0x32abc,
 838                 0x32b00, 0x32b10,
 839                 0x32b20, 0x32b30,
 840                 0x32b40, 0x32b50,
 841                 0x32b60, 0x32b70,
 842                 0x33000, 0x33028,
 843                 0x33030, 0x33048,
 844                 0x33060, 0x33068,
 845                 0x33070, 0x3309c,
 846                 0x330f0, 0x33128,
 847                 0x33130, 0x33148,
 848                 0x33160, 0x33168,
 849                 0x33170, 0x3319c,
 850                 0x331f0, 0x33238,
 851                 0x33240, 0x33240,
 852                 0x33248, 0x33250,
 853                 0x3325c, 0x33264,
 854                 0x33270, 0x332b8,
 855                 0x332c0, 0x332e4,
 856                 0x332f8, 0x33338,
 857                 0x33340, 0x33340,
 858                 0x33348, 0x33350,
 859                 0x3335c, 0x33364,
 860                 0x33370, 0x333b8,
 861                 0x333c0, 0x333e4,
 862                 0x333f8, 0x33428,
 863                 0x33430, 0x33448,
 864                 0x33460, 0x33468,
 865                 0x33470, 0x3349c,
 866                 0x334f0, 0x33528,
 867                 0x33530, 0x33548,
 868                 0x33560, 0x33568,
 869                 0x33570, 0x3359c,
 870                 0x335f0, 0x33638,
 871                 0x33640, 0x33640,
 872                 0x33648, 0x33650,
 873                 0x3365c, 0x33664,
 874                 0x33670, 0x336b8,
 875                 0x336c0, 0x336e4,
 876                 0x336f8, 0x33738,
 877                 0x33740, 0x33740,
 878                 0x33748, 0x33750,
 879                 0x3375c, 0x33764,
 880                 0x33770, 0x337b8,
 881                 0x337c0, 0x337e4,
 882                 0x337f8, 0x337fc,
 883                 0x33814, 0x33814,
 884                 0x3382c, 0x3382c,
 885                 0x33880, 0x3388c,
 886                 0x338e8, 0x338ec,
 887                 0x33900, 0x33928,
 888                 0x33930, 0x33948,
 889                 0x33960, 0x33968,
 890                 0x33970, 0x3399c,
 891                 0x339f0, 0x33a38,
 892                 0x33a40, 0x33a40,
 893                 0x33a48, 0x33a50,
 894                 0x33a5c, 0x33a64,
 895                 0x33a70, 0x33ab8,
 896                 0x33ac0, 0x33ae4,
 897                 0x33af8, 0x33b10,
 898                 0x33b28, 0x33b28,
 899                 0x33b3c, 0x33b50,
 900                 0x33bf0, 0x33c10,
 901                 0x33c28, 0x33c28,
 902                 0x33c3c, 0x33c50,
 903                 0x33cf0, 0x33cfc,
 904                 0x34000, 0x34030,
 905                 0x34038, 0x34038,
 906                 0x34040, 0x34040,
 907                 0x34100, 0x34144,
 908                 0x34190, 0x341a0,
 909                 0x341a8, 0x341b8,
 910                 0x341c4, 0x341c8,
 911                 0x341d0, 0x341d0,
 912                 0x34200, 0x34318,
 913                 0x34400, 0x344b4,
 914                 0x344c0, 0x3452c,
 915                 0x34540, 0x3461c,
 916                 0x34800, 0x34828,
 917                 0x34834, 0x34834,
 918                 0x348c0, 0x34908,
 919                 0x34910, 0x349ac,
 920                 0x34a00, 0x34a14,
 921                 0x34a1c, 0x34a2c,
 922                 0x34a44, 0x34a50,
 923                 0x34a74, 0x34a74,
 924                 0x34a7c, 0x34afc,
 925                 0x34b08, 0x34c24,
 926                 0x34d00, 0x34d00,
 927                 0x34d08, 0x34d14,
 928                 0x34d1c, 0x34d20,
 929                 0x34d3c, 0x34d3c,
 930                 0x34d48, 0x34d50,
 931                 0x35200, 0x3520c,
 932                 0x35220, 0x35220,
 933                 0x35240, 0x35240,
 934                 0x35600, 0x3560c,
 935                 0x35a00, 0x35a1c,
 936                 0x35e00, 0x35e20,
 937                 0x35e38, 0x35e3c,
 938                 0x35e80, 0x35e80,
 939                 0x35e88, 0x35ea8,
 940                 0x35eb0, 0x35eb4,
 941                 0x35ec8, 0x35ed4,
 942                 0x35fb8, 0x36004,
 943                 0x36200, 0x36200,
 944                 0x36208, 0x36240,
 945                 0x36248, 0x36280,
 946                 0x36288, 0x362c0,
 947                 0x362c8, 0x362fc,
 948                 0x36600, 0x36630,
 949                 0x36a00, 0x36abc,
 950                 0x36b00, 0x36b10,
 951                 0x36b20, 0x36b30,
 952                 0x36b40, 0x36b50,
 953                 0x36b60, 0x36b70,
 954                 0x37000, 0x37028,
 955                 0x37030, 0x37048,
 956                 0x37060, 0x37068,
 957                 0x37070, 0x3709c,
 958                 0x370f0, 0x37128,
 959                 0x37130, 0x37148,
 960                 0x37160, 0x37168,
 961                 0x37170, 0x3719c,
 962                 0x371f0, 0x37238,
 963                 0x37240, 0x37240,
 964                 0x37248, 0x37250,
 965                 0x3725c, 0x37264,
 966                 0x37270, 0x372b8,
 967                 0x372c0, 0x372e4,
 968                 0x372f8, 0x37338,
 969                 0x37340, 0x37340,
 970                 0x37348, 0x37350,
 971                 0x3735c, 0x37364,
 972                 0x37370, 0x373b8,
 973                 0x373c0, 0x373e4,
 974                 0x373f8, 0x37428,
 975                 0x37430, 0x37448,
 976                 0x37460, 0x37468,
 977                 0x37470, 0x3749c,
 978                 0x374f0, 0x37528,
 979                 0x37530, 0x37548,
 980                 0x37560, 0x37568,
 981                 0x37570, 0x3759c,
 982                 0x375f0, 0x37638,
 983                 0x37640, 0x37640,
 984                 0x37648, 0x37650,
 985                 0x3765c, 0x37664,
 986                 0x37670, 0x376b8,
 987                 0x376c0, 0x376e4,
 988                 0x376f8, 0x37738,
 989                 0x37740, 0x37740,
 990                 0x37748, 0x37750,
 991                 0x3775c, 0x37764,
 992                 0x37770, 0x377b8,
 993                 0x377c0, 0x377e4,
 994                 0x377f8, 0x377fc,
 995                 0x37814, 0x37814,
 996                 0x3782c, 0x3782c,
 997                 0x37880, 0x3788c,
 998                 0x378e8, 0x378ec,
 999                 0x37900, 0x37928,
1000                 0x37930, 0x37948,
1001                 0x37960, 0x37968,
1002                 0x37970, 0x3799c,
1003                 0x379f0, 0x37a38,
1004                 0x37a40, 0x37a40,
1005                 0x37a48, 0x37a50,
1006                 0x37a5c, 0x37a64,
1007                 0x37a70, 0x37ab8,
1008                 0x37ac0, 0x37ae4,
1009                 0x37af8, 0x37b10,
1010                 0x37b28, 0x37b28,
1011                 0x37b3c, 0x37b50,
1012                 0x37bf0, 0x37c10,
1013                 0x37c28, 0x37c28,
1014                 0x37c3c, 0x37c50,
1015                 0x37cf0, 0x37cfc,
1016                 0x38000, 0x38030,
1017                 0x38038, 0x38038,
1018                 0x38040, 0x38040,
1019                 0x38100, 0x38144,
1020                 0x38190, 0x381a0,
1021                 0x381a8, 0x381b8,
1022                 0x381c4, 0x381c8,
1023                 0x381d0, 0x381d0,
1024                 0x38200, 0x38318,
1025                 0x38400, 0x384b4,
1026                 0x384c0, 0x3852c,
1027                 0x38540, 0x3861c,
1028                 0x38800, 0x38828,
1029                 0x38834, 0x38834,
1030                 0x388c0, 0x38908,
1031                 0x38910, 0x389ac,
1032                 0x38a00, 0x38a14,
1033                 0x38a1c, 0x38a2c,
1034                 0x38a44, 0x38a50,
1035                 0x38a74, 0x38a74,
1036                 0x38a7c, 0x38afc,
1037                 0x38b08, 0x38c24,
1038                 0x38d00, 0x38d00,
1039                 0x38d08, 0x38d14,
1040                 0x38d1c, 0x38d20,
1041                 0x38d3c, 0x38d3c,
1042                 0x38d48, 0x38d50,
1043                 0x39200, 0x3920c,
1044                 0x39220, 0x39220,
1045                 0x39240, 0x39240,
1046                 0x39600, 0x3960c,
1047                 0x39a00, 0x39a1c,
1048                 0x39e00, 0x39e20,
1049                 0x39e38, 0x39e3c,
1050                 0x39e80, 0x39e80,
1051                 0x39e88, 0x39ea8,
1052                 0x39eb0, 0x39eb4,
1053                 0x39ec8, 0x39ed4,
1054                 0x39fb8, 0x3a004,
1055                 0x3a200, 0x3a200,
1056                 0x3a208, 0x3a240,
1057                 0x3a248, 0x3a280,
1058                 0x3a288, 0x3a2c0,
1059                 0x3a2c8, 0x3a2fc,
1060                 0x3a600, 0x3a630,
1061                 0x3aa00, 0x3aabc,
1062                 0x3ab00, 0x3ab10,
1063                 0x3ab20, 0x3ab30,
1064                 0x3ab40, 0x3ab50,
1065                 0x3ab60, 0x3ab70,
1066                 0x3b000, 0x3b028,
1067                 0x3b030, 0x3b048,
1068                 0x3b060, 0x3b068,
1069                 0x3b070, 0x3b09c,
1070                 0x3b0f0, 0x3b128,
1071                 0x3b130, 0x3b148,
1072                 0x3b160, 0x3b168,
1073                 0x3b170, 0x3b19c,
1074                 0x3b1f0, 0x3b238,
1075                 0x3b240, 0x3b240,
1076                 0x3b248, 0x3b250,
1077                 0x3b25c, 0x3b264,
1078                 0x3b270, 0x3b2b8,
1079                 0x3b2c0, 0x3b2e4,
1080                 0x3b2f8, 0x3b338,
1081                 0x3b340, 0x3b340,
1082                 0x3b348, 0x3b350,
1083                 0x3b35c, 0x3b364,
1084                 0x3b370, 0x3b3b8,
1085                 0x3b3c0, 0x3b3e4,
1086                 0x3b3f8, 0x3b428,
1087                 0x3b430, 0x3b448,
1088                 0x3b460, 0x3b468,
1089                 0x3b470, 0x3b49c,
1090                 0x3b4f0, 0x3b528,
1091                 0x3b530, 0x3b548,
1092                 0x3b560, 0x3b568,
1093                 0x3b570, 0x3b59c,
1094                 0x3b5f0, 0x3b638,
1095                 0x3b640, 0x3b640,
1096                 0x3b648, 0x3b650,
1097                 0x3b65c, 0x3b664,
1098                 0x3b670, 0x3b6b8,
1099                 0x3b6c0, 0x3b6e4,
1100                 0x3b6f8, 0x3b738,
1101                 0x3b740, 0x3b740,
1102                 0x3b748, 0x3b750,
1103                 0x3b75c, 0x3b764,
1104                 0x3b770, 0x3b7b8,
1105                 0x3b7c0, 0x3b7e4,
1106                 0x3b7f8, 0x3b7fc,
1107                 0x3b814, 0x3b814,
1108                 0x3b82c, 0x3b82c,
1109                 0x3b880, 0x3b88c,
1110                 0x3b8e8, 0x3b8ec,
1111                 0x3b900, 0x3b928,
1112                 0x3b930, 0x3b948,
1113                 0x3b960, 0x3b968,
1114                 0x3b970, 0x3b99c,
1115                 0x3b9f0, 0x3ba38,
1116                 0x3ba40, 0x3ba40,
1117                 0x3ba48, 0x3ba50,
1118                 0x3ba5c, 0x3ba64,
1119                 0x3ba70, 0x3bab8,
1120                 0x3bac0, 0x3bae4,
1121                 0x3baf8, 0x3bb10,
1122                 0x3bb28, 0x3bb28,
1123                 0x3bb3c, 0x3bb50,
1124                 0x3bbf0, 0x3bc10,
1125                 0x3bc28, 0x3bc28,
1126                 0x3bc3c, 0x3bc50,
1127                 0x3bcf0, 0x3bcfc,
1128                 0x3c000, 0x3c030,
1129                 0x3c038, 0x3c038,
1130                 0x3c040, 0x3c040,
1131                 0x3c100, 0x3c144,
1132                 0x3c190, 0x3c1a0,
1133                 0x3c1a8, 0x3c1b8,
1134                 0x3c1c4, 0x3c1c8,
1135                 0x3c1d0, 0x3c1d0,
1136                 0x3c200, 0x3c318,
1137                 0x3c400, 0x3c4b4,
1138                 0x3c4c0, 0x3c52c,
1139                 0x3c540, 0x3c61c,
1140                 0x3c800, 0x3c828,
1141                 0x3c834, 0x3c834,
1142                 0x3c8c0, 0x3c908,
1143                 0x3c910, 0x3c9ac,
1144                 0x3ca00, 0x3ca14,
1145                 0x3ca1c, 0x3ca2c,
1146                 0x3ca44, 0x3ca50,
1147                 0x3ca74, 0x3ca74,
1148                 0x3ca7c, 0x3cafc,
1149                 0x3cb08, 0x3cc24,
1150                 0x3cd00, 0x3cd00,
1151                 0x3cd08, 0x3cd14,
1152                 0x3cd1c, 0x3cd20,
1153                 0x3cd3c, 0x3cd3c,
1154                 0x3cd48, 0x3cd50,
1155                 0x3d200, 0x3d20c,
1156                 0x3d220, 0x3d220,
1157                 0x3d240, 0x3d240,
1158                 0x3d600, 0x3d60c,
1159                 0x3da00, 0x3da1c,
1160                 0x3de00, 0x3de20,
1161                 0x3de38, 0x3de3c,
1162                 0x3de80, 0x3de80,
1163                 0x3de88, 0x3dea8,
1164                 0x3deb0, 0x3deb4,
1165                 0x3dec8, 0x3ded4,
1166                 0x3dfb8, 0x3e004,
1167                 0x3e200, 0x3e200,
1168                 0x3e208, 0x3e240,
1169                 0x3e248, 0x3e280,
1170                 0x3e288, 0x3e2c0,
1171                 0x3e2c8, 0x3e2fc,
1172                 0x3e600, 0x3e630,
1173                 0x3ea00, 0x3eabc,
1174                 0x3eb00, 0x3eb10,
1175                 0x3eb20, 0x3eb30,
1176                 0x3eb40, 0x3eb50,
1177                 0x3eb60, 0x3eb70,
1178                 0x3f000, 0x3f028,
1179                 0x3f030, 0x3f048,
1180                 0x3f060, 0x3f068,
1181                 0x3f070, 0x3f09c,
1182                 0x3f0f0, 0x3f128,
1183                 0x3f130, 0x3f148,
1184                 0x3f160, 0x3f168,
1185                 0x3f170, 0x3f19c,
1186                 0x3f1f0, 0x3f238,
1187                 0x3f240, 0x3f240,
1188                 0x3f248, 0x3f250,
1189                 0x3f25c, 0x3f264,
1190                 0x3f270, 0x3f2b8,
1191                 0x3f2c0, 0x3f2e4,
1192                 0x3f2f8, 0x3f338,
1193                 0x3f340, 0x3f340,
1194                 0x3f348, 0x3f350,
1195                 0x3f35c, 0x3f364,
1196                 0x3f370, 0x3f3b8,
1197                 0x3f3c0, 0x3f3e4,
1198                 0x3f3f8, 0x3f428,
1199                 0x3f430, 0x3f448,
1200                 0x3f460, 0x3f468,
1201                 0x3f470, 0x3f49c,
1202                 0x3f4f0, 0x3f528,
1203                 0x3f530, 0x3f548,
1204                 0x3f560, 0x3f568,
1205                 0x3f570, 0x3f59c,
1206                 0x3f5f0, 0x3f638,
1207                 0x3f640, 0x3f640,
1208                 0x3f648, 0x3f650,
1209                 0x3f65c, 0x3f664,
1210                 0x3f670, 0x3f6b8,
1211                 0x3f6c0, 0x3f6e4,
1212                 0x3f6f8, 0x3f738,
1213                 0x3f740, 0x3f740,
1214                 0x3f748, 0x3f750,
1215                 0x3f75c, 0x3f764,
1216                 0x3f770, 0x3f7b8,
1217                 0x3f7c0, 0x3f7e4,
1218                 0x3f7f8, 0x3f7fc,
1219                 0x3f814, 0x3f814,
1220                 0x3f82c, 0x3f82c,
1221                 0x3f880, 0x3f88c,
1222                 0x3f8e8, 0x3f8ec,
1223                 0x3f900, 0x3f928,
1224                 0x3f930, 0x3f948,
1225                 0x3f960, 0x3f968,
1226                 0x3f970, 0x3f99c,
1227                 0x3f9f0, 0x3fa38,
1228                 0x3fa40, 0x3fa40,
1229                 0x3fa48, 0x3fa50,
1230                 0x3fa5c, 0x3fa64,
1231                 0x3fa70, 0x3fab8,
1232                 0x3fac0, 0x3fae4,
1233                 0x3faf8, 0x3fb10,
1234                 0x3fb28, 0x3fb28,
1235                 0x3fb3c, 0x3fb50,
1236                 0x3fbf0, 0x3fc10,
1237                 0x3fc28, 0x3fc28,
1238                 0x3fc3c, 0x3fc50,
1239                 0x3fcf0, 0x3fcfc,
1240                 0x40000, 0x4000c,
1241                 0x40040, 0x40050,
1242                 0x40060, 0x40068,
1243                 0x4007c, 0x4008c,
1244                 0x40094, 0x400b0,
1245                 0x400c0, 0x40144,
1246                 0x40180, 0x4018c,
1247                 0x40200, 0x40254,
1248                 0x40260, 0x40264,
1249                 0x40270, 0x40288,
1250                 0x40290, 0x40298,
1251                 0x402ac, 0x402c8,
1252                 0x402d0, 0x402e0,
1253                 0x402f0, 0x402f0,
1254                 0x40300, 0x4033c,
1255                 0x403f8, 0x403fc,
1256                 0x41304, 0x413c4,
1257                 0x41400, 0x4140c,
1258                 0x41414, 0x4141c,
1259                 0x41480, 0x414d0,
1260                 0x44000, 0x44054,
1261                 0x4405c, 0x44078,
1262                 0x440c0, 0x44174,
1263                 0x44180, 0x441ac,
1264                 0x441b4, 0x441b8,
1265                 0x441c0, 0x44254,
1266                 0x4425c, 0x44278,
1267                 0x442c0, 0x44374,
1268                 0x44380, 0x443ac,
1269                 0x443b4, 0x443b8,
1270                 0x443c0, 0x44454,
1271                 0x4445c, 0x44478,
1272                 0x444c0, 0x44574,
1273                 0x44580, 0x445ac,
1274                 0x445b4, 0x445b8,
1275                 0x445c0, 0x44654,
1276                 0x4465c, 0x44678,
1277                 0x446c0, 0x44774,
1278                 0x44780, 0x447ac,
1279                 0x447b4, 0x447b8,
1280                 0x447c0, 0x44854,
1281                 0x4485c, 0x44878,
1282                 0x448c0, 0x44974,
1283                 0x44980, 0x449ac,
1284                 0x449b4, 0x449b8,
1285                 0x449c0, 0x449fc,
1286                 0x45000, 0x45004,
1287                 0x45010, 0x45030,
1288                 0x45040, 0x45060,
1289                 0x45068, 0x45068,
1290                 0x45080, 0x45084,
1291                 0x450a0, 0x450b0,
1292                 0x45200, 0x45204,
1293                 0x45210, 0x45230,
1294                 0x45240, 0x45260,
1295                 0x45268, 0x45268,
1296                 0x45280, 0x45284,
1297                 0x452a0, 0x452b0,
1298                 0x460c0, 0x460e4,
1299                 0x47000, 0x4703c,
1300                 0x47044, 0x4708c,
1301                 0x47200, 0x47250,
1302                 0x47400, 0x47408,
1303                 0x47414, 0x47420,
1304                 0x47600, 0x47618,
1305                 0x47800, 0x47814,
1306                 0x48000, 0x4800c,
1307                 0x48040, 0x48050,
1308                 0x48060, 0x48068,
1309                 0x4807c, 0x4808c,
1310                 0x48094, 0x480b0,
1311                 0x480c0, 0x48144,
1312                 0x48180, 0x4818c,
1313                 0x48200, 0x48254,
1314                 0x48260, 0x48264,
1315                 0x48270, 0x48288,
1316                 0x48290, 0x48298,
1317                 0x482ac, 0x482c8,
1318                 0x482d0, 0x482e0,
1319                 0x482f0, 0x482f0,
1320                 0x48300, 0x4833c,
1321                 0x483f8, 0x483fc,
1322                 0x49304, 0x493c4,
1323                 0x49400, 0x4940c,
1324                 0x49414, 0x4941c,
1325                 0x49480, 0x494d0,
1326                 0x4c000, 0x4c054,
1327                 0x4c05c, 0x4c078,
1328                 0x4c0c0, 0x4c174,
1329                 0x4c180, 0x4c1ac,
1330                 0x4c1b4, 0x4c1b8,
1331                 0x4c1c0, 0x4c254,
1332                 0x4c25c, 0x4c278,
1333                 0x4c2c0, 0x4c374,
1334                 0x4c380, 0x4c3ac,
1335                 0x4c3b4, 0x4c3b8,
1336                 0x4c3c0, 0x4c454,
1337                 0x4c45c, 0x4c478,
1338                 0x4c4c0, 0x4c574,
1339                 0x4c580, 0x4c5ac,
1340                 0x4c5b4, 0x4c5b8,
1341                 0x4c5c0, 0x4c654,
1342                 0x4c65c, 0x4c678,
1343                 0x4c6c0, 0x4c774,
1344                 0x4c780, 0x4c7ac,
1345                 0x4c7b4, 0x4c7b8,
1346                 0x4c7c0, 0x4c854,
1347                 0x4c85c, 0x4c878,
1348                 0x4c8c0, 0x4c974,
1349                 0x4c980, 0x4c9ac,
1350                 0x4c9b4, 0x4c9b8,
1351                 0x4c9c0, 0x4c9fc,
1352                 0x4d000, 0x4d004,
1353                 0x4d010, 0x4d030,
1354                 0x4d040, 0x4d060,
1355                 0x4d068, 0x4d068,
1356                 0x4d080, 0x4d084,
1357                 0x4d0a0, 0x4d0b0,
1358                 0x4d200, 0x4d204,
1359                 0x4d210, 0x4d230,
1360                 0x4d240, 0x4d260,
1361                 0x4d268, 0x4d268,
1362                 0x4d280, 0x4d284,
1363                 0x4d2a0, 0x4d2b0,
1364                 0x4e0c0, 0x4e0e4,
1365                 0x4f000, 0x4f03c,
1366                 0x4f044, 0x4f08c,
1367                 0x4f200, 0x4f250,
1368                 0x4f400, 0x4f408,
1369                 0x4f414, 0x4f420,
1370                 0x4f600, 0x4f618,
1371                 0x4f800, 0x4f814,
1372                 0x50000, 0x50084,
1373                 0x50090, 0x500cc,
1374                 0x50400, 0x50400,
1375                 0x50800, 0x50884,
1376                 0x50890, 0x508cc,
1377                 0x50c00, 0x50c00,
1378                 0x51000, 0x5101c,
1379                 0x51300, 0x51308,
1380         };
1381
1382         u32 *buf_end = (u32 *)((char *)buf + buf_size);
1383         const unsigned int *reg_ranges;
1384         int reg_ranges_size, range;
1385         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1386
1387         /* Select the right set of register ranges to dump depending on the
1388          * adapter chip type.
1389          */
1390         switch (chip_version) {
1391         case CHELSIO_T5:
1392                 reg_ranges = t5_reg_ranges;
1393                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1394                 break;
1395
1396         default:
1397                 dev_err(adap,
1398                         "Unsupported chip version %d\n", chip_version);
1399                 return;
1400         }
1401
1402         /* Clear the register buffer and insert the appropriate register
1403          * values selected by the above register ranges.
1404          */
1405         memset(buf, 0, buf_size);
1406         for (range = 0; range < reg_ranges_size; range += 2) {
1407                 unsigned int reg = reg_ranges[range];
1408                 unsigned int last_reg = reg_ranges[range + 1];
1409                 u32 *bufp = (u32 *)((char *)buf + reg);
1410
1411                 /* Iterate across the register range filling in the register
1412                  * buffer but don't write past the end of the register buffer.
1413                  */
1414                 while (reg <= last_reg && bufp < buf_end) {
1415                         *bufp++ = t4_read_reg(adap, reg);
1416                         reg += sizeof(u32);
1417                 }
1418         }
1419 }
1420
1421 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1422 #define EEPROM_DELAY            10              /* 10us per poll spin */
1423 #define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
1424
1425 #define EEPROM_STAT_ADDR        0x7bfc
1426
1427 /**
1428  * Small utility function to wait till any outstanding VPD Access is complete.
1429  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1430  * VPD Access in flight.  This allows us to handle the problem of having a
1431  * previous VPD Access time out and prevent an attempt to inject a new VPD
1432  * Request before any in-flight VPD request has completed.
1433  */
1434 static int t4_seeprom_wait(struct adapter *adapter)
1435 {
1436         unsigned int base = adapter->params.pci.vpd_cap_addr;
1437         int max_poll;
1438
1439         /* If no VPD Access is in flight, we can just return success right
1440          * away.
1441          */
1442         if (!adapter->vpd_busy)
1443                 return 0;
1444
1445         /* Poll the VPD Capability Address/Flag register waiting for it
1446          * to indicate that the operation is complete.
1447          */
1448         max_poll = EEPROM_MAX_POLL;
1449         do {
1450                 u16 val;
1451
1452                 udelay(EEPROM_DELAY);
1453                 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
1454
1455                 /* If the operation is complete, mark the VPD as no longer
1456                  * busy and return success.
1457                  */
1458                 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
1459                         adapter->vpd_busy = 0;
1460                         return 0;
1461                 }
1462         } while (--max_poll);
1463
1464         /* Failure!  Note that we leave the VPD Busy status set in order to
1465          * avoid pushing a new VPD Access request into the VPD Capability till
1466          * the current operation eventually succeeds.  It's a bug to issue a
1467          * new request when an existing request is in flight and will result
1468          * in corrupt hardware state.
1469          */
1470         return -ETIMEDOUT;
1471 }
1472
1473 /**
1474  * t4_seeprom_read - read a serial EEPROM location
1475  * @adapter: adapter to read
1476  * @addr: EEPROM virtual address
1477  * @data: where to store the read data
1478  *
1479  * Read a 32-bit word from a location in serial EEPROM using the card's PCI
1480  * VPD capability.  Note that this function must be called with a virtual
1481  * address.
1482  */
1483 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
1484 {
1485         unsigned int base = adapter->params.pci.vpd_cap_addr;
1486         int ret;
1487
1488         /* VPD Accesses must alway be 4-byte aligned!
1489          */
1490         if (addr >= EEPROMVSIZE || (addr & 3))
1491                 return -EINVAL;
1492
1493         /* Wait for any previous operation which may still be in flight to
1494          * complete.
1495          */
1496         ret = t4_seeprom_wait(adapter);
1497         if (ret) {
1498                 dev_err(adapter, "VPD still busy from previous operation\n");
1499                 return ret;
1500         }
1501
1502         /* Issue our new VPD Read request, mark the VPD as being busy and wait
1503          * for our request to complete.  If it doesn't complete, note the
1504          * error and return it to our caller.  Note that we do not reset the
1505          * VPD Busy status!
1506          */
1507         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
1508         adapter->vpd_busy = 1;
1509         adapter->vpd_flag = PCI_VPD_ADDR_F;
1510         ret = t4_seeprom_wait(adapter);
1511         if (ret) {
1512                 dev_err(adapter, "VPD read of address %#x failed\n", addr);
1513                 return ret;
1514         }
1515
1516         /* Grab the returned data, swizzle it into our endianness and
1517          * return success.
1518          */
1519         t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
1520         *data = le32_to_cpu(*data);
1521         return 0;
1522 }
1523
1524 /**
1525  * t4_seeprom_write - write a serial EEPROM location
1526  * @adapter: adapter to write
1527  * @addr: virtual EEPROM address
1528  * @data: value to write
1529  *
1530  * Write a 32-bit word to a location in serial EEPROM using the card's PCI
1531  * VPD capability.  Note that this function must be called with a virtual
1532  * address.
1533  */
1534 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
1535 {
1536         unsigned int base = adapter->params.pci.vpd_cap_addr;
1537         int ret;
1538         u32 stats_reg = 0;
1539         int max_poll;
1540
1541         /* VPD Accesses must alway be 4-byte aligned!
1542          */
1543         if (addr >= EEPROMVSIZE || (addr & 3))
1544                 return -EINVAL;
1545
1546         /* Wait for any previous operation which may still be in flight to
1547          * complete.
1548          */
1549         ret = t4_seeprom_wait(adapter);
1550         if (ret) {
1551                 dev_err(adapter, "VPD still busy from previous operation\n");
1552                 return ret;
1553         }
1554
1555         /* Issue our new VPD Read request, mark the VPD as being busy and wait
1556          * for our request to complete.  If it doesn't complete, note the
1557          * error and return it to our caller.  Note that we do not reset the
1558          * VPD Busy status!
1559          */
1560         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
1561                              cpu_to_le32(data));
1562         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
1563                              (u16)addr | PCI_VPD_ADDR_F);
1564         adapter->vpd_busy = 1;
1565         adapter->vpd_flag = 0;
1566         ret = t4_seeprom_wait(adapter);
1567         if (ret) {
1568                 dev_err(adapter, "VPD write of address %#x failed\n", addr);
1569                 return ret;
1570         }
1571
1572         /* Reset PCI_VPD_DATA register after a transaction and wait for our
1573          * request to complete. If it doesn't complete, return error.
1574          */
1575         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
1576         max_poll = EEPROM_MAX_POLL;
1577         do {
1578                 udelay(EEPROM_DELAY);
1579                 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
1580         } while ((stats_reg & 0x1) && --max_poll);
1581         if (!max_poll)
1582                 return -ETIMEDOUT;
1583
1584         /* Return success! */
1585         return 0;
1586 }
1587
1588 /**
1589  * t4_seeprom_wp - enable/disable EEPROM write protection
1590  * @adapter: the adapter
1591  * @enable: whether to enable or disable write protection
1592  *
1593  * Enables or disables write protection on the serial EEPROM.
1594  */
1595 int t4_seeprom_wp(struct adapter *adapter, int enable)
1596 {
1597         return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
1598 }
1599
1600 /**
1601  * t4_config_rss_range - configure a portion of the RSS mapping table
1602  * @adapter: the adapter
1603  * @mbox: mbox to use for the FW command
1604  * @viid: virtual interface whose RSS subtable is to be written
1605  * @start: start entry in the table to write
1606  * @n: how many table entries to write
1607  * @rspq: values for the "response queue" (Ingress Queue) lookup table
1608  * @nrspq: number of values in @rspq
1609  *
1610  * Programs the selected part of the VI's RSS mapping table with the
1611  * provided values.  If @nrspq < @n the supplied values are used repeatedly
1612  * until the full table range is populated.
1613  *
1614  * The caller must ensure the values in @rspq are in the range allowed for
1615  * @viid.
1616  */
1617 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1618                         int start, int n, const u16 *rspq, unsigned int nrspq)
1619 {
1620         int ret;
1621         const u16 *rsp = rspq;
1622         const u16 *rsp_end = rspq + nrspq;
1623         struct fw_rss_ind_tbl_cmd cmd;
1624
1625         memset(&cmd, 0, sizeof(cmd));
1626         cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
1627                                      F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
1628                                      V_FW_RSS_IND_TBL_CMD_VIID(viid));
1629         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1630
1631         /*
1632          * Each firmware RSS command can accommodate up to 32 RSS Ingress
1633          * Queue Identifiers.  These Ingress Queue IDs are packed three to
1634          * a 32-bit word as 10-bit values with the upper remaining 2 bits
1635          * reserved.
1636          */
1637         while (n > 0) {
1638                 int nq = min(n, 32);
1639                 int nq_packed = 0;
1640                 __be32 *qp = &cmd.iq0_to_iq2;
1641
1642                 /*
1643                  * Set up the firmware RSS command header to send the next
1644                  * "nq" Ingress Queue IDs to the firmware.
1645                  */
1646                 cmd.niqid = cpu_to_be16(nq);
1647                 cmd.startidx = cpu_to_be16(start);
1648
1649                 /*
1650                  * "nq" more done for the start of the next loop.
1651                  */
1652                 start += nq;
1653                 n -= nq;
1654
1655                 /*
1656                  * While there are still Ingress Queue IDs to stuff into the
1657                  * current firmware RSS command, retrieve them from the
1658                  * Ingress Queue ID array and insert them into the command.
1659                  */
1660                 while (nq > 0) {
1661                         /*
1662                          * Grab up to the next 3 Ingress Queue IDs (wrapping
1663                          * around the Ingress Queue ID array if necessary) and
1664                          * insert them into the firmware RSS command at the
1665                          * current 3-tuple position within the commad.
1666                          */
1667                         u16 qbuf[3];
1668                         u16 *qbp = qbuf;
1669                         int nqbuf = min(3, nq);
1670
1671                         nq -= nqbuf;
1672                         qbuf[0] = 0;
1673                         qbuf[1] = 0;
1674                         qbuf[2] = 0;
1675                         while (nqbuf && nq_packed < 32) {
1676                                 nqbuf--;
1677                                 nq_packed++;
1678                                 *qbp++ = *rsp++;
1679                                 if (rsp >= rsp_end)
1680                                         rsp = rspq;
1681                         }
1682                         *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
1683                                             V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
1684                                             V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
1685                 }
1686
1687                 /*
1688                  * Send this portion of the RRS table update to the firmware;
1689                  * bail out on any errors.
1690                  */
1691                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
1692                 if (ret)
1693                         return ret;
1694         }
1695
1696         return 0;
1697 }
1698
1699 /**
1700  * t4_config_vi_rss - configure per VI RSS settings
1701  * @adapter: the adapter
1702  * @mbox: mbox to use for the FW command
1703  * @viid: the VI id
1704  * @flags: RSS flags
1705  * @defq: id of the default RSS queue for the VI.
1706  *
1707  * Configures VI-specific RSS properties.
1708  */
1709 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1710                      unsigned int flags, unsigned int defq)
1711 {
1712         struct fw_rss_vi_config_cmd c;
1713
1714         memset(&c, 0, sizeof(c));
1715         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
1716                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
1717                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
1718         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
1719         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
1720                         V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
1721         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
1722 }
1723
1724 /**
1725  * init_cong_ctrl - initialize congestion control parameters
1726  * @a: the alpha values for congestion control
1727  * @b: the beta values for congestion control
1728  *
1729  * Initialize the congestion control parameters.
1730  */
1731 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
1732 {
1733         int i;
1734
1735         for (i = 0; i < 9; i++) {
1736                 a[i] = 1;
1737                 b[i] = 0;
1738         }
1739
1740         a[9] = 2;
1741         a[10] = 3;
1742         a[11] = 4;
1743         a[12] = 5;
1744         a[13] = 6;
1745         a[14] = 7;
1746         a[15] = 8;
1747         a[16] = 9;
1748         a[17] = 10;
1749         a[18] = 14;
1750         a[19] = 17;
1751         a[20] = 21;
1752         a[21] = 25;
1753         a[22] = 30;
1754         a[23] = 35;
1755         a[24] = 45;
1756         a[25] = 60;
1757         a[26] = 80;
1758         a[27] = 100;
1759         a[28] = 200;
1760         a[29] = 300;
1761         a[30] = 400;
1762         a[31] = 500;
1763
1764         b[9] = 1;
1765         b[10] = 1;
1766         b[11] = 2;
1767         b[12] = 2;
1768         b[13] = 3;
1769         b[14] = 3;
1770         b[15] = 3;
1771         b[16] = 3;
1772         b[17] = 4;
1773         b[18] = 4;
1774         b[19] = 4;
1775         b[20] = 4;
1776         b[21] = 4;
1777         b[22] = 5;
1778         b[23] = 5;
1779         b[24] = 5;
1780         b[25] = 5;
1781         b[26] = 5;
1782         b[27] = 5;
1783         b[28] = 6;
1784         b[29] = 6;
1785         b[30] = 7;
1786         b[31] = 7;
1787 }
1788
1789 #define INIT_CMD(var, cmd, rd_wr) do { \
1790         (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
1791                         F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
1792         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
1793 } while (0)
1794
1795 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
1796 {
1797         u32 cclk_param, cclk_val;
1798         int ret;
1799
1800         /*
1801          * Ask firmware for the Core Clock since it knows how to translate the
1802          * Reference Clock ('V2') VPD field into a Core Clock value ...
1803          */
1804         cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1805                       V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
1806         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
1807                               1, &cclk_param, &cclk_val);
1808         if (ret) {
1809                 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
1810                         __func__, ret);
1811                 return ret;
1812         }
1813
1814         p->cclk = cclk_val;
1815         dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
1816         return 0;
1817 }
1818
1819 /* serial flash and firmware constants and flash config file constants */
1820 enum {
1821         SF_ATTEMPTS = 10,             /* max retries for SF operations */
1822
1823         /* flash command opcodes */
1824         SF_PROG_PAGE    = 2,          /* program page */
1825         SF_WR_DISABLE   = 4,          /* disable writes */
1826         SF_RD_STATUS    = 5,          /* read status register */
1827         SF_WR_ENABLE    = 6,          /* enable writes */
1828         SF_RD_DATA_FAST = 0xb,        /* read flash */
1829         SF_RD_ID        = 0x9f,       /* read ID */
1830         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
1831 };
1832
1833 /**
1834  * sf1_read - read data from the serial flash
1835  * @adapter: the adapter
1836  * @byte_cnt: number of bytes to read
1837  * @cont: whether another operation will be chained
1838  * @lock: whether to lock SF for PL access only
1839  * @valp: where to store the read data
1840  *
1841  * Reads up to 4 bytes of data from the serial flash.  The location of
1842  * the read needs to be specified prior to calling this by issuing the
1843  * appropriate commands to the serial flash.
1844  */
1845 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
1846                     int lock, u32 *valp)
1847 {
1848         int ret;
1849
1850         if (!byte_cnt || byte_cnt > 4)
1851                 return -EINVAL;
1852         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
1853                 return -EBUSY;
1854         t4_write_reg(adapter, A_SF_OP,
1855                      V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
1856         ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
1857         if (!ret)
1858                 *valp = t4_read_reg(adapter, A_SF_DATA);
1859         return ret;
1860 }
1861
1862 /**
1863  * sf1_write - write data to the serial flash
1864  * @adapter: the adapter
1865  * @byte_cnt: number of bytes to write
1866  * @cont: whether another operation will be chained
1867  * @lock: whether to lock SF for PL access only
1868  * @val: value to write
1869  *
1870  * Writes up to 4 bytes of data to the serial flash.  The location of
1871  * the write needs to be specified prior to calling this by issuing the
1872  * appropriate commands to the serial flash.
1873  */
1874 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
1875                      int lock, u32 val)
1876 {
1877         if (!byte_cnt || byte_cnt > 4)
1878                 return -EINVAL;
1879         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
1880                 return -EBUSY;
1881         t4_write_reg(adapter, A_SF_DATA, val);
1882         t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
1883                      V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
1884         return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
1885 }
1886
1887 /**
1888  * t4_read_flash - read words from serial flash
1889  * @adapter: the adapter
1890  * @addr: the start address for the read
1891  * @nwords: how many 32-bit words to read
1892  * @data: where to store the read data
1893  * @byte_oriented: whether to store data as bytes or as words
1894  *
1895  * Read the specified number of 32-bit words from the serial flash.
1896  * If @byte_oriented is set the read data is stored as a byte array
1897  * (i.e., big-endian), otherwise as 32-bit words in the platform's
1898  * natural endianness.
1899  */
1900 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1901                   unsigned int nwords, u32 *data, int byte_oriented)
1902 {
1903         int ret;
1904
1905         if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
1906             (addr & 3))
1907                 return -EINVAL;
1908
1909         addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
1910
1911         ret = sf1_write(adapter, 4, 1, 0, addr);
1912         if (ret != 0)
1913                 return ret;
1914
1915         ret = sf1_read(adapter, 1, 1, 0, data);
1916         if (ret != 0)
1917                 return ret;
1918
1919         for ( ; nwords; nwords--, data++) {
1920                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
1921                 if (nwords == 1)
1922                         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
1923                 if (ret)
1924                         return ret;
1925                 if (byte_oriented)
1926                         *data = cpu_to_be32(*data);
1927         }
1928         return 0;
1929 }
1930
1931 /**
1932  * t4_get_fw_version - read the firmware version
1933  * @adapter: the adapter
1934  * @vers: where to place the version
1935  *
1936  * Reads the FW version from flash.
1937  */
1938 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
1939 {
1940         return t4_read_flash(adapter, FLASH_FW_START +
1941                              offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
1942 }
1943
1944 /**
1945  * t4_get_tp_version - read the TP microcode version
1946  * @adapter: the adapter
1947  * @vers: where to place the version
1948  *
1949  * Reads the TP microcode version from flash.
1950  */
1951 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
1952 {
1953         return t4_read_flash(adapter, FLASH_FW_START +
1954                              offsetof(struct fw_hdr, tp_microcode_ver),
1955                              1, vers, 0);
1956 }
1957
1958 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1959                 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
1960                 FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG)
1961
1962 /**
1963  * t4_link_l1cfg - apply link configuration to MAC/PHY
1964  * @phy: the PHY to setup
1965  * @mac: the MAC to setup
1966  * @lc: the requested link configuration
1967  *
1968  * Set up a port's MAC and PHY according to a desired link configuration.
1969  * - If the PHY can auto-negotiate first decide what to advertise, then
1970  *   enable/disable auto-negotiation as desired, and reset.
1971  * - If the PHY does not auto-negotiate just reset it.
1972  * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1973  *   otherwise do it later based on the outcome of auto-negotiation.
1974  */
1975 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1976                   struct link_config *lc)
1977 {
1978         struct fw_port_cmd c;
1979         unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
1980
1981         lc->link_ok = 0;
1982         if (lc->requested_fc & PAUSE_RX)
1983                 fc |= FW_PORT_CAP_FC_RX;
1984         if (lc->requested_fc & PAUSE_TX)
1985                 fc |= FW_PORT_CAP_FC_TX;
1986
1987         memset(&c, 0, sizeof(c));
1988         c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
1989                                      F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
1990                                      V_FW_PORT_CMD_PORTID(port));
1991         c.action_to_len16 =
1992                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1993                             FW_LEN16(c));
1994
1995         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1996                 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
1997                                              fc);
1998                 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1999         } else if (lc->autoneg == AUTONEG_DISABLE) {
2000                 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
2001                 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
2002         } else {
2003                 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
2004         }
2005
2006         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2007 }
2008
2009 /**
2010  * t4_flash_cfg_addr - return the address of the flash configuration file
2011  * @adapter: the adapter
2012  *
2013  * Return the address within the flash where the Firmware Configuration
2014  * File is stored, or an error if the device FLASH is too small to contain
2015  * a Firmware Configuration File.
2016  */
2017 int t4_flash_cfg_addr(struct adapter *adapter)
2018 {
2019         /*
2020          * If the device FLASH isn't large enough to hold a Firmware
2021          * Configuration File, return an error.
2022          */
2023         if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2024                 return -ENOSPC;
2025
2026         return FLASH_CFG_START;
2027 }
2028
2029 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2030
2031 /**
2032  * t4_intr_enable - enable interrupts
2033  * @adapter: the adapter whose interrupts should be enabled
2034  *
2035  * Enable PF-specific interrupts for the calling function and the top-level
2036  * interrupt concentrator for global interrupts.  Interrupts are already
2037  * enabled at each module, here we just enable the roots of the interrupt
2038  * hierarchies.
2039  *
2040  * Note: this function should be called only when the driver manages
2041  * non PF-specific interrupts from the various HW modules.  Only one PCI
2042  * function at a time should be doing this.
2043  */
2044 void t4_intr_enable(struct adapter *adapter)
2045 {
2046         u32 val = 0;
2047         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2048         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2049                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2050
2051         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2052                 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2053         t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2054                      F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2055                      F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2056                      F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2057                      F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2058                      F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2059                      F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2060         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2061         t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2062 }
2063
2064 /**
2065  * t4_intr_disable - disable interrupts
2066  * @adapter: the adapter whose interrupts should be disabled
2067  *
2068  * Disable interrupts.  We only disable the top-level interrupt
2069  * concentrators.  The caller must be a PCI function managing global
2070  * interrupts.
2071  */
2072 void t4_intr_disable(struct adapter *adapter)
2073 {
2074         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2075         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2076                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2077
2078         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2079         t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2080 }
2081
2082 /**
2083  * t4_get_port_type_description - return Port Type string description
2084  * @port_type: firmware Port Type enumeration
2085  */
2086 const char *t4_get_port_type_description(enum fw_port_type port_type)
2087 {
2088         static const char * const port_type_description[] = {
2089                 "Fiber_XFI",
2090                 "Fiber_XAUI",
2091                 "BT_SGMII",
2092                 "BT_XFI",
2093                 "BT_XAUI",
2094                 "KX4",
2095                 "CX4",
2096                 "KX",
2097                 "KR",
2098                 "SFP",
2099                 "BP_AP",
2100                 "BP4_AP",
2101                 "QSFP_10G",
2102                 "QSA",
2103                 "QSFP",
2104                 "BP40_BA",
2105         };
2106
2107         if (port_type < ARRAY_SIZE(port_type_description))
2108                 return port_type_description[port_type];
2109         return "UNKNOWN";
2110 }
2111
2112 /**
2113  * t4_get_mps_bg_map - return the buffer groups associated with a port
2114  * @adap: the adapter
2115  * @idx: the port index
2116  *
2117  * Returns a bitmap indicating which MPS buffer groups are associated
2118  * with the given port.  Bit i is set if buffer group i is used by the
2119  * port.
2120  */
2121 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
2122 {
2123         u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
2124
2125         if (n == 0)
2126                 return idx == 0 ? 0xf : 0;
2127         if (n == 1)
2128                 return idx < 2 ? (3 << (2 * idx)) : 0;
2129         return 1 << idx;
2130 }
2131
2132 /**
2133  * t4_get_port_stats - collect port statistics
2134  * @adap: the adapter
2135  * @idx: the port index
2136  * @p: the stats structure to fill
2137  *
2138  * Collect statistics related to the given port from HW.
2139  */
2140 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2141 {
2142         u32 bgmap = t4_get_mps_bg_map(adap, idx);
2143
2144 #define GET_STAT(name) \
2145         t4_read_reg64(adap, \
2146                       (is_t4(adap->params.chip) ? \
2147                        PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2148                        T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2149 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2150
2151         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
2152         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
2153         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
2154         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
2155         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
2156         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
2157         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
2158         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
2159         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
2160         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
2161         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
2162         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2163         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
2164         p->tx_drop             = GET_STAT(TX_PORT_DROP);
2165         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
2166         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
2167         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
2168         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
2169         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
2170         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
2171         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
2172         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
2173         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
2174
2175         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
2176         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
2177         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
2178         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
2179         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
2180         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
2181         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2182         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
2183         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
2184         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
2185         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
2186         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
2187         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
2188         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
2189         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
2190         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
2191         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2192         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
2193         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
2194         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
2195         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
2196         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
2197         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
2198         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
2199         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
2200         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
2201         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
2202         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2203         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2204         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2205         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2206         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2207         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2208         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2209         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2210
2211 #undef GET_STAT
2212 #undef GET_STAT_COM
2213 }
2214
2215 /**
2216  * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
2217  * @adap: The adapter
2218  * @idx: The port
2219  * @stats: Current stats to fill
2220  * @offset: Previous stats snapshot
2221  */
2222 void t4_get_port_stats_offset(struct adapter *adap, int idx,
2223                               struct port_stats *stats,
2224                               struct port_stats *offset)
2225 {
2226         u64 *s, *o;
2227         unsigned int i;
2228
2229         t4_get_port_stats(adap, idx, stats);
2230         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
2231              i < (sizeof(struct port_stats) / sizeof(u64));
2232              i++, s++, o++)
2233                 *s -= *o;
2234 }
2235
2236 /**
2237  * t4_clr_port_stats - clear port statistics
2238  * @adap: the adapter
2239  * @idx: the port index
2240  *
2241  * Clear HW statistics for the given port.
2242  */
2243 void t4_clr_port_stats(struct adapter *adap, int idx)
2244 {
2245         unsigned int i;
2246         u32 bgmap = t4_get_mps_bg_map(adap, idx);
2247         u32 port_base_addr;
2248
2249         if (is_t4(adap->params.chip))
2250                 port_base_addr = PORT_BASE(idx);
2251         else
2252                 port_base_addr = T5_PORT_BASE(idx);
2253
2254         for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
2255              i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
2256                 t4_write_reg(adap, port_base_addr + i, 0);
2257         for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
2258              i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
2259                 t4_write_reg(adap, port_base_addr + i, 0);
2260         for (i = 0; i < 4; i++)
2261                 if (bgmap & (1 << i)) {
2262                         t4_write_reg(adap,
2263                                      A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
2264                                      i * 8, 0);
2265                         t4_write_reg(adap,
2266                                      A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
2267                                      i * 8, 0);
2268                 }
2269 }
2270
2271 /**
2272  * t4_fw_hello - establish communication with FW
2273  * @adap: the adapter
2274  * @mbox: mailbox to use for the FW command
2275  * @evt_mbox: mailbox to receive async FW events
2276  * @master: specifies the caller's willingness to be the device master
2277  * @state: returns the current device state (if non-NULL)
2278  *
2279  * Issues a command to establish communication with FW.  Returns either
2280  * an error (negative integer) or the mailbox of the Master PF.
2281  */
2282 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2283                 enum dev_master master, enum dev_state *state)
2284 {
2285         int ret;
2286         struct fw_hello_cmd c;
2287         u32 v;
2288         unsigned int master_mbox;
2289         int retries = FW_CMD_HELLO_RETRIES;
2290
2291 retry:
2292         memset(&c, 0, sizeof(c));
2293         INIT_CMD(c, HELLO, WRITE);
2294         c.err_to_clearinit = cpu_to_be32(
2295                         V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2296                         V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2297                         V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2298                                                 M_FW_HELLO_CMD_MBMASTER) |
2299                         V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2300                         V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
2301                         F_FW_HELLO_CMD_CLEARINIT);
2302
2303         /*
2304          * Issue the HELLO command to the firmware.  If it's not successful
2305          * but indicates that we got a "busy" or "timeout" condition, retry
2306          * the HELLO until we exhaust our retry limit.  If we do exceed our
2307          * retry limit, check to see if the firmware left us any error
2308          * information and report that if so ...
2309          */
2310         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2311         if (ret != FW_SUCCESS) {
2312                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2313                         goto retry;
2314                 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
2315                         t4_report_fw_error(adap);
2316                 return ret;
2317         }
2318
2319         v = be32_to_cpu(c.err_to_clearinit);
2320         master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
2321         if (state) {
2322                 if (v & F_FW_HELLO_CMD_ERR)
2323                         *state = DEV_STATE_ERR;
2324                 else if (v & F_FW_HELLO_CMD_INIT)
2325                         *state = DEV_STATE_INIT;
2326                 else
2327                         *state = DEV_STATE_UNINIT;
2328         }
2329
2330         /*
2331          * If we're not the Master PF then we need to wait around for the
2332          * Master PF Driver to finish setting up the adapter.
2333          *
2334          * Note that we also do this wait if we're a non-Master-capable PF and
2335          * there is no current Master PF; a Master PF may show up momentarily
2336          * and we wouldn't want to fail pointlessly.  (This can happen when an
2337          * OS loads lots of different drivers rapidly at the same time).  In
2338          * this case, the Master PF returned by the firmware will be
2339          * M_PCIE_FW_MASTER so the test below will work ...
2340          */
2341         if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
2342             master_mbox != mbox) {
2343                 int waiting = FW_CMD_HELLO_TIMEOUT;
2344
2345                 /*
2346                  * Wait for the firmware to either indicate an error or
2347                  * initialized state.  If we see either of these we bail out
2348                  * and report the issue to the caller.  If we exhaust the
2349                  * "hello timeout" and we haven't exhausted our retries, try
2350                  * again.  Otherwise bail with a timeout error.
2351                  */
2352                 for (;;) {
2353                         u32 pcie_fw;
2354
2355                         msleep(50);
2356                         waiting -= 50;
2357
2358                         /*
2359                          * If neither Error nor Initialialized are indicated
2360                          * by the firmware keep waiting till we exaust our
2361                          * timeout ... and then retry if we haven't exhausted
2362                          * our retries ...
2363                          */
2364                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
2365                         if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
2366                                 if (waiting <= 0) {
2367                                         if (retries-- > 0)
2368                                                 goto retry;
2369
2370                                         return -ETIMEDOUT;
2371                                 }
2372                                 continue;
2373                         }
2374
2375                         /*
2376                          * We either have an Error or Initialized condition
2377                          * report errors preferentially.
2378                          */
2379                         if (state) {
2380                                 if (pcie_fw & F_PCIE_FW_ERR)
2381                                         *state = DEV_STATE_ERR;
2382                                 else if (pcie_fw & F_PCIE_FW_INIT)
2383                                         *state = DEV_STATE_INIT;
2384                         }
2385
2386                         /*
2387                          * If we arrived before a Master PF was selected and
2388                          * there's not a valid Master PF, grab its identity
2389                          * for our caller.
2390                          */
2391                         if (master_mbox == M_PCIE_FW_MASTER &&
2392                             (pcie_fw & F_PCIE_FW_MASTER_VLD))
2393                                 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
2394                         break;
2395                 }
2396         }
2397
2398         return master_mbox;
2399 }
2400
2401 /**
2402  * t4_fw_bye - end communication with FW
2403  * @adap: the adapter
2404  * @mbox: mailbox to use for the FW command
2405  *
2406  * Issues a command to terminate communication with FW.
2407  */
2408 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2409 {
2410         struct fw_bye_cmd c;
2411
2412         memset(&c, 0, sizeof(c));
2413         INIT_CMD(c, BYE, WRITE);
2414         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2415 }
2416
2417 /**
2418  * t4_fw_reset - issue a reset to FW
2419  * @adap: the adapter
2420  * @mbox: mailbox to use for the FW command
2421  * @reset: specifies the type of reset to perform
2422  *
2423  * Issues a reset command of the specified type to FW.
2424  */
2425 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2426 {
2427         struct fw_reset_cmd c;
2428
2429         memset(&c, 0, sizeof(c));
2430         INIT_CMD(c, RESET, WRITE);
2431         c.val = cpu_to_be32(reset);
2432         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2433 }
2434
2435 /**
2436  * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2437  * @adap: the adapter
2438  * @mbox: mailbox to use for the FW RESET command (if desired)
2439  * @force: force uP into RESET even if FW RESET command fails
2440  *
2441  * Issues a RESET command to firmware (if desired) with a HALT indication
2442  * and then puts the microprocessor into RESET state.  The RESET command
2443  * will only be issued if a legitimate mailbox is provided (mbox <=
2444  * M_PCIE_FW_MASTER).
2445  *
2446  * This is generally used in order for the host to safely manipulate the
2447  * adapter without fear of conflicting with whatever the firmware might
2448  * be doing.  The only way out of this state is to RESTART the firmware
2449  * ...
2450  */
2451 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2452 {
2453         int ret = 0;
2454
2455         /*
2456          * If a legitimate mailbox is provided, issue a RESET command
2457          * with a HALT indication.
2458          */
2459         if (mbox <= M_PCIE_FW_MASTER) {
2460                 struct fw_reset_cmd c;
2461
2462                 memset(&c, 0, sizeof(c));
2463                 INIT_CMD(c, RESET, WRITE);
2464                 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
2465                 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
2466                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2467         }
2468
2469         /*
2470          * Normally we won't complete the operation if the firmware RESET
2471          * command fails but if our caller insists we'll go ahead and put the
2472          * uP into RESET.  This can be useful if the firmware is hung or even
2473          * missing ...  We'll have to take the risk of putting the uP into
2474          * RESET without the cooperation of firmware in that case.
2475          *
2476          * We also force the firmware's HALT flag to be on in case we bypassed
2477          * the firmware RESET command above or we're dealing with old firmware
2478          * which doesn't have the HALT capability.  This will serve as a flag
2479          * for the incoming firmware to know that it's coming out of a HALT
2480          * rather than a RESET ... if it's new enough to understand that ...
2481          */
2482         if (ret == 0 || force) {
2483                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
2484                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
2485                                  F_PCIE_FW_HALT);
2486         }
2487
2488         /*
2489          * And we always return the result of the firmware RESET command
2490          * even when we force the uP into RESET ...
2491          */
2492         return ret;
2493 }
2494
2495 /**
2496  * t4_fw_restart - restart the firmware by taking the uP out of RESET
2497  * @adap: the adapter
2498  * @mbox: mailbox to use for the FW RESET command (if desired)
2499  * @reset: if we want to do a RESET to restart things
2500  *
2501  * Restart firmware previously halted by t4_fw_halt().  On successful
2502  * return the previous PF Master remains as the new PF Master and there
2503  * is no need to issue a new HELLO command, etc.
2504  *
2505  * We do this in two ways:
2506  *
2507  * 1. If we're dealing with newer firmware we'll simply want to take
2508  *    the chip's microprocessor out of RESET.  This will cause the
2509  *    firmware to start up from its start vector.  And then we'll loop
2510  *    until the firmware indicates it's started again (PCIE_FW.HALT
2511  *    reset to 0) or we timeout.
2512  *
2513  * 2. If we're dealing with older firmware then we'll need to RESET
2514  *    the chip since older firmware won't recognize the PCIE_FW.HALT
2515  *    flag and automatically RESET itself on startup.
2516  */
2517 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
2518 {
2519         if (reset) {
2520                 /*
2521                  * Since we're directing the RESET instead of the firmware
2522                  * doing it automatically, we need to clear the PCIE_FW.HALT
2523                  * bit.
2524                  */
2525                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
2526
2527                 /*
2528                  * If we've been given a valid mailbox, first try to get the
2529                  * firmware to do the RESET.  If that works, great and we can
2530                  * return success.  Otherwise, if we haven't been given a
2531                  * valid mailbox or the RESET command failed, fall back to
2532                  * hitting the chip with a hammer.
2533                  */
2534                 if (mbox <= M_PCIE_FW_MASTER) {
2535                         t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
2536                         msleep(100);
2537                         if (t4_fw_reset(adap, mbox,
2538                                         F_PIORST | F_PIORSTMODE) == 0)
2539                                 return 0;
2540                 }
2541
2542                 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
2543                 msleep(2000);
2544         } else {
2545                 int ms;
2546
2547                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
2548                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
2549                         if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
2550                                 return FW_SUCCESS;
2551                         msleep(100);
2552                         ms += 100;
2553                 }
2554                 return -ETIMEDOUT;
2555         }
2556         return 0;
2557 }
2558
2559 /**
2560  * t4_fixup_host_params_compat - fix up host-dependent parameters
2561  * @adap: the adapter
2562  * @page_size: the host's Base Page Size
2563  * @cache_line_size: the host's Cache Line Size
2564  * @chip_compat: maintain compatibility with designated chip
2565  *
2566  * Various registers in the chip contain values which are dependent on the
2567  * host's Base Page and Cache Line Sizes.  This function will fix all of
2568  * those registers with the appropriate values as passed in ...
2569  *
2570  * @chip_compat is used to limit the set of changes that are made
2571  * to be compatible with the indicated chip release.  This is used by
2572  * drivers to maintain compatibility with chip register settings when
2573  * the drivers haven't [yet] been updated with new chip support.
2574  */
2575 int t4_fixup_host_params_compat(struct adapter *adap,
2576                                 unsigned int page_size,
2577                                 unsigned int cache_line_size,
2578                                 enum chip_type chip_compat)
2579 {
2580         unsigned int page_shift = cxgbe_fls(page_size) - 1;
2581         unsigned int sge_hps = page_shift - 10;
2582         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
2583         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
2584         unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
2585
2586         t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
2587                      V_HOSTPAGESIZEPF0(sge_hps) |
2588                      V_HOSTPAGESIZEPF1(sge_hps) |
2589                      V_HOSTPAGESIZEPF2(sge_hps) |
2590                      V_HOSTPAGESIZEPF3(sge_hps) |
2591                      V_HOSTPAGESIZEPF4(sge_hps) |
2592                      V_HOSTPAGESIZEPF5(sge_hps) |
2593                      V_HOSTPAGESIZEPF6(sge_hps) |
2594                      V_HOSTPAGESIZEPF7(sge_hps));
2595
2596         if (is_t4(adap->params.chip) || is_t4(chip_compat))
2597                 t4_set_reg_field(adap, A_SGE_CONTROL,
2598                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
2599                                  F_EGRSTATUSPAGESIZE,
2600                                  V_INGPADBOUNDARY(fl_align_log -
2601                                                   X_INGPADBOUNDARY_SHIFT) |
2602                                 V_EGRSTATUSPAGESIZE(stat_len != 64));
2603         else {
2604                 /*
2605                  * T5 introduced the separation of the Free List Padding and
2606                  * Packing Boundaries.  Thus, we can select a smaller Padding
2607                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
2608                  * Bandwidth, and use a Packing Boundary which is large enough
2609                  * to avoid false sharing between CPUs, etc.
2610                  *
2611                  * For the PCI Link, the smaller the Padding Boundary the
2612                  * better.  For the Memory Controller, a smaller Padding
2613                  * Boundary is better until we cross under the Memory Line
2614                  * Size (the minimum unit of transfer to/from Memory).  If we
2615                  * have a Padding Boundary which is smaller than the Memory
2616                  * Line Size, that'll involve a Read-Modify-Write cycle on the
2617                  * Memory Controller which is never good.  For T5 the smallest
2618                  * Padding Boundary which we can select is 32 bytes which is
2619                  * larger than any known Memory Controller Line Size so we'll
2620                  * use that.
2621                  */
2622
2623                 /*
2624                  * N.B. T5 has a different interpretation of the "0" value for
2625                  * the Packing Boundary.  This corresponds to 16 bytes instead
2626                  * of the expected 32 bytes.  We never have a Packing Boundary
2627                  * less than 32 bytes so we can't use that special value but
2628                  * on the other hand, if we wanted 32 bytes, the best we can
2629                  * really do is 64 bytes ...
2630                  */
2631                 if (fl_align <= 32) {
2632                         fl_align = 64;
2633                         fl_align_log = 6;
2634                 }
2635                 t4_set_reg_field(adap, A_SGE_CONTROL,
2636                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
2637                                  F_EGRSTATUSPAGESIZE,
2638                                  V_INGPADBOUNDARY(X_INGPCIEBOUNDARY_32B) |
2639                                  V_EGRSTATUSPAGESIZE(stat_len != 64));
2640                 t4_set_reg_field(adap, A_SGE_CONTROL2,
2641                                  V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
2642                                  V_INGPACKBOUNDARY(fl_align_log -
2643                                                    X_INGPACKBOUNDARY_SHIFT));
2644         }
2645
2646         /*
2647          * Adjust various SGE Free List Host Buffer Sizes.
2648          *
2649          * The first four entries are:
2650          *
2651          *   0: Host Page Size
2652          *   1: 64KB
2653          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
2654          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
2655          *
2656          * For the single-MTU buffers in unpacked mode we need to include
2657          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
2658          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
2659          * Padding boundary.  All of these are accommodated in the Factory
2660          * Default Firmware Configuration File but we need to adjust it for
2661          * this host's cache line size.
2662          */
2663         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
2664         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
2665                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
2666                      & ~(fl_align - 1));
2667         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
2668                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
2669                      & ~(fl_align - 1));
2670
2671         t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
2672
2673         return 0;
2674 }
2675
2676 /**
2677  * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
2678  * @adap: the adapter
2679  * @page_size: the host's Base Page Size
2680  * @cache_line_size: the host's Cache Line Size
2681  *
2682  * Various registers in T4 contain values which are dependent on the
2683  * host's Base Page and Cache Line Sizes.  This function will fix all of
2684  * those registers with the appropriate values as passed in ...
2685  *
2686  * This routine makes changes which are compatible with T4 chips.
2687  */
2688 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
2689                          unsigned int cache_line_size)
2690 {
2691         return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
2692                                            T4_LAST_REV);
2693 }
2694
2695 /**
2696  * t4_fw_initialize - ask FW to initialize the device
2697  * @adap: the adapter
2698  * @mbox: mailbox to use for the FW command
2699  *
2700  * Issues a command to FW to partially initialize the device.  This
2701  * performs initialization that generally doesn't depend on user input.
2702  */
2703 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
2704 {
2705         struct fw_initialize_cmd c;
2706
2707         memset(&c, 0, sizeof(c));
2708         INIT_CMD(c, INITIALIZE, WRITE);
2709         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2710 }
2711
2712 /**
2713  * t4_query_params_rw - query FW or device parameters
2714  * @adap: the adapter
2715  * @mbox: mailbox to use for the FW command
2716  * @pf: the PF
2717  * @vf: the VF
2718  * @nparams: the number of parameters
2719  * @params: the parameter names
2720  * @val: the parameter values
2721  * @rw: Write and read flag
2722  *
2723  * Reads the value of FW or device parameters.  Up to 7 parameters can be
2724  * queried at once.
2725  */
2726 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
2727                               unsigned int pf, unsigned int vf,
2728                               unsigned int nparams, const u32 *params,
2729                               u32 *val, int rw)
2730 {
2731         unsigned int i;
2732         int ret;
2733         struct fw_params_cmd c;
2734         __be32 *p = &c.param[0].mnem;
2735
2736         if (nparams > 7)
2737                 return -EINVAL;
2738
2739         memset(&c, 0, sizeof(c));
2740         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
2741                                   F_FW_CMD_REQUEST | F_FW_CMD_READ |
2742                                   V_FW_PARAMS_CMD_PFN(pf) |
2743                                   V_FW_PARAMS_CMD_VFN(vf));
2744         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2745
2746         for (i = 0; i < nparams; i++) {
2747                 *p++ = cpu_to_be32(*params++);
2748                 if (rw)
2749                         *p = cpu_to_be32(*(val + i));
2750                 p++;
2751         }
2752
2753         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2754         if (ret == 0)
2755                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
2756                         *val++ = be32_to_cpu(*p);
2757         return ret;
2758 }
2759
2760 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2761                     unsigned int vf, unsigned int nparams, const u32 *params,
2762                     u32 *val)
2763 {
2764         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
2765 }
2766
2767 /**
2768  * t4_set_params_timeout - sets FW or device parameters
2769  * @adap: the adapter
2770  * @mbox: mailbox to use for the FW command
2771  * @pf: the PF
2772  * @vf: the VF
2773  * @nparams: the number of parameters
2774  * @params: the parameter names
2775  * @val: the parameter values
2776  * @timeout: the timeout time
2777  *
2778  * Sets the value of FW or device parameters.  Up to 7 parameters can be
2779  * specified at once.
2780  */
2781 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
2782                           unsigned int pf, unsigned int vf,
2783                           unsigned int nparams, const u32 *params,
2784                           const u32 *val, int timeout)
2785 {
2786         struct fw_params_cmd c;
2787         __be32 *p = &c.param[0].mnem;
2788
2789         if (nparams > 7)
2790                 return -EINVAL;
2791
2792         memset(&c, 0, sizeof(c));
2793         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
2794                                   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2795                                   V_FW_PARAMS_CMD_PFN(pf) |
2796                                   V_FW_PARAMS_CMD_VFN(vf));
2797         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2798
2799         while (nparams--) {
2800                 *p++ = cpu_to_be32(*params++);
2801                 *p++ = cpu_to_be32(*val++);
2802         }
2803
2804         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
2805 }
2806
2807 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2808                   unsigned int vf, unsigned int nparams, const u32 *params,
2809                   const u32 *val)
2810 {
2811         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
2812                                      FW_CMD_MAX_TIMEOUT);
2813 }
2814
2815 /**
2816  * t4_alloc_vi_func - allocate a virtual interface
2817  * @adap: the adapter
2818  * @mbox: mailbox to use for the FW command
2819  * @port: physical port associated with the VI
2820  * @pf: the PF owning the VI
2821  * @vf: the VF owning the VI
2822  * @nmac: number of MAC addresses needed (1 to 5)
2823  * @mac: the MAC addresses of the VI
2824  * @rss_size: size of RSS table slice associated with this VI
2825  * @portfunc: which Port Application Function MAC Address is desired
2826  * @idstype: Intrusion Detection Type
2827  *
2828  * Allocates a virtual interface for the given physical port.  If @mac is
2829  * not %NULL it contains the MAC addresses of the VI as assigned by FW.
2830  * @mac should be large enough to hold @nmac Ethernet addresses, they are
2831  * stored consecutively so the space needed is @nmac * 6 bytes.
2832  * Returns a negative error number or the non-negative VI id.
2833  */
2834 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
2835                      unsigned int port, unsigned int pf, unsigned int vf,
2836                      unsigned int nmac, u8 *mac, unsigned int *rss_size,
2837                      unsigned int portfunc, unsigned int idstype)
2838 {
2839         int ret;
2840         struct fw_vi_cmd c;
2841
2842         memset(&c, 0, sizeof(c));
2843         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
2844                                   F_FW_CMD_WRITE | F_FW_CMD_EXEC |
2845                                   V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
2846         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
2847         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
2848                                      V_FW_VI_CMD_FUNC(portfunc));
2849         c.portid_pkd = V_FW_VI_CMD_PORTID(port);
2850         c.nmac = nmac - 1;
2851
2852         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2853         if (ret)
2854                 return ret;
2855
2856         if (mac) {
2857                 memcpy(mac, c.mac, sizeof(c.mac));
2858                 switch (nmac) {
2859                 case 5:
2860                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
2861                         /* FALLTHROUGH */
2862                 case 4:
2863                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
2864                         /* FALLTHROUGH */
2865                 case 3:
2866                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
2867                         /* FALLTHROUGH */
2868                 case 2:
2869                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
2870                         /* FALLTHROUGH */
2871                 }
2872         }
2873         if (rss_size)
2874                 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
2875         return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
2876 }
2877
2878 /**
2879  * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
2880  * @adap: the adapter
2881  * @mbox: mailbox to use for the FW command
2882  * @port: physical port associated with the VI
2883  * @pf: the PF owning the VI
2884  * @vf: the VF owning the VI
2885  * @nmac: number of MAC addresses needed (1 to 5)
2886  * @mac: the MAC addresses of the VI
2887  * @rss_size: size of RSS table slice associated with this VI
2888  *
2889  * Backwards compatible and convieniance routine to allocate a Virtual
2890  * Interface with a Ethernet Port Application Function and Intrustion
2891  * Detection System disabled.
2892  */
2893 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
2894                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
2895                 unsigned int *rss_size)
2896 {
2897         return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
2898                                 FW_VI_FUNC_ETH, 0);
2899 }
2900
2901 /**
2902  * t4_free_vi - free a virtual interface
2903  * @adap: the adapter
2904  * @mbox: mailbox to use for the FW command
2905  * @pf: the PF owning the VI
2906  * @vf: the VF owning the VI
2907  * @viid: virtual interface identifiler
2908  *
2909  * Free a previously allocated virtual interface.
2910  */
2911 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
2912                unsigned int vf, unsigned int viid)
2913 {
2914         struct fw_vi_cmd c;
2915
2916         memset(&c, 0, sizeof(c));
2917         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
2918                                   F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
2919                                   V_FW_VI_CMD_VFN(vf));
2920         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
2921         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
2922
2923         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2924 }
2925
2926 /**
2927  * t4_set_rxmode - set Rx properties of a virtual interface
2928  * @adap: the adapter
2929  * @mbox: mailbox to use for the FW command
2930  * @viid: the VI id
2931  * @mtu: the new MTU or -1
2932  * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
2933  * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
2934  * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
2935  * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
2936  *          -1 no change
2937  * @sleep_ok: if true we may sleep while awaiting command completion
2938  *
2939  * Sets Rx properties of a virtual interface.
2940  */
2941 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
2942                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
2943                   bool sleep_ok)
2944 {
2945         struct fw_vi_rxmode_cmd c;
2946
2947         /* convert to FW values */
2948         if (mtu < 0)
2949                 mtu = M_FW_VI_RXMODE_CMD_MTU;
2950         if (promisc < 0)
2951                 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
2952         if (all_multi < 0)
2953                 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
2954         if (bcast < 0)
2955                 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
2956         if (vlanex < 0)
2957                 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
2958
2959         memset(&c, 0, sizeof(c));
2960         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
2961                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2962                                    V_FW_VI_RXMODE_CMD_VIID(viid));
2963         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2964         c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
2965                             V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
2966                             V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
2967                             V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
2968                             V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
2969         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
2970 }
2971
2972 /**
2973  * t4_change_mac - modifies the exact-match filter for a MAC address
2974  * @adap: the adapter
2975  * @mbox: mailbox to use for the FW command
2976  * @viid: the VI id
2977  * @idx: index of existing filter for old value of MAC address, or -1
2978  * @addr: the new MAC address value
2979  * @persist: whether a new MAC allocation should be persistent
2980  * @add_smt: if true also add the address to the HW SMT
2981  *
2982  * Modifies an exact-match filter and sets it to the new MAC address if
2983  * @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
2984  * latter case the address is added persistently if @persist is %true.
2985  *
2986  * Note that in general it is not possible to modify the value of a given
2987  * filter so the generic way to modify an address filter is to free the one
2988  * being used by the old address value and allocate a new filter for the
2989  * new address value.
2990  *
2991  * Returns a negative error number or the index of the filter with the new
2992  * MAC value.  Note that this index may differ from @idx.
2993  */
2994 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
2995                   int idx, const u8 *addr, bool persist, bool add_smt)
2996 {
2997         int ret, mode;
2998         struct fw_vi_mac_cmd c;
2999         struct fw_vi_mac_exact *p = c.u.exact;
3000         int max_mac_addr = adap->params.arch.mps_tcam_size;
3001
3002         if (idx < 0)                             /* new allocation */
3003                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3004         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3005
3006         memset(&c, 0, sizeof(c));
3007         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3008                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3009                                    V_FW_VI_MAC_CMD_VIID(viid));
3010         c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3011         p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3012                                       V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3013                                       V_FW_VI_MAC_CMD_IDX(idx));
3014         memcpy(p->macaddr, addr, sizeof(p->macaddr));
3015
3016         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3017         if (ret == 0) {
3018                 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3019                 if (ret >= max_mac_addr)
3020                         ret = -ENOMEM;
3021         }
3022         return ret;
3023 }
3024
3025 /**
3026  * t4_enable_vi_params - enable/disable a virtual interface
3027  * @adap: the adapter
3028  * @mbox: mailbox to use for the FW command
3029  * @viid: the VI id
3030  * @rx_en: 1=enable Rx, 0=disable Rx
3031  * @tx_en: 1=enable Tx, 0=disable Tx
3032  * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3033  *
3034  * Enables/disables a virtual interface.  Note that setting DCB Enable
3035  * only makes sense when enabling a Virtual Interface ...
3036  */
3037 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3038                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3039 {
3040         struct fw_vi_enable_cmd c;
3041
3042         memset(&c, 0, sizeof(c));
3043         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3044                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3045                                    V_FW_VI_ENABLE_CMD_VIID(viid));
3046         c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3047                                      V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3048                                      V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3049                                      FW_LEN16(c));
3050         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3051 }
3052
3053 /**
3054  * t4_enable_vi - enable/disable a virtual interface
3055  * @adap: the adapter
3056  * @mbox: mailbox to use for the FW command
3057  * @viid: the VI id
3058  * @rx_en: 1=enable Rx, 0=disable Rx
3059  * @tx_en: 1=enable Tx, 0=disable Tx
3060  *
3061  * Enables/disables a virtual interface.  Note that setting DCB Enable
3062  * only makes sense when enabling a Virtual Interface ...
3063  */
3064 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3065                  bool rx_en, bool tx_en)
3066 {
3067         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3068 }
3069
3070 /**
3071  * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3072  * @adap: the adapter
3073  * @mbox: mailbox to use for the FW command
3074  * @start: %true to enable the queues, %false to disable them
3075  * @pf: the PF owning the queues
3076  * @vf: the VF owning the queues
3077  * @iqid: ingress queue id
3078  * @fl0id: FL0 queue id or 0xffff if no attached FL0
3079  * @fl1id: FL1 queue id or 0xffff if no attached FL1
3080  *
3081  * Starts or stops an ingress queue and its associated FLs, if any.
3082  */
3083 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3084                      unsigned int pf, unsigned int vf, unsigned int iqid,
3085                      unsigned int fl0id, unsigned int fl1id)
3086 {
3087         struct fw_iq_cmd c;
3088
3089         memset(&c, 0, sizeof(c));
3090         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3091                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3092                                   V_FW_IQ_CMD_VFN(vf));
3093         c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
3094                                        V_FW_IQ_CMD_IQSTOP(!start) |
3095                                        FW_LEN16(c));
3096         c.iqid = cpu_to_be16(iqid);
3097         c.fl0id = cpu_to_be16(fl0id);
3098         c.fl1id = cpu_to_be16(fl1id);
3099         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3100 }
3101
3102 /**
3103  * t4_iq_free - free an ingress queue and its FLs
3104  * @adap: the adapter
3105  * @mbox: mailbox to use for the FW command
3106  * @pf: the PF owning the queues
3107  * @vf: the VF owning the queues
3108  * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
3109  * @iqid: ingress queue id
3110  * @fl0id: FL0 queue id or 0xffff if no attached FL0
3111  * @fl1id: FL1 queue id or 0xffff if no attached FL1
3112  *
3113  * Frees an ingress queue and its associated FLs, if any.
3114  */
3115 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3116                unsigned int vf, unsigned int iqtype, unsigned int iqid,
3117                unsigned int fl0id, unsigned int fl1id)
3118 {
3119         struct fw_iq_cmd c;
3120
3121         memset(&c, 0, sizeof(c));
3122         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3123                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3124                                   V_FW_IQ_CMD_VFN(vf));
3125         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
3126         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
3127         c.iqid = cpu_to_be16(iqid);
3128         c.fl0id = cpu_to_be16(fl0id);
3129         c.fl1id = cpu_to_be16(fl1id);
3130         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3131 }
3132
3133 /**
3134  * t4_eth_eq_free - free an Ethernet egress queue
3135  * @adap: the adapter
3136  * @mbox: mailbox to use for the FW command
3137  * @pf: the PF owning the queue
3138  * @vf: the VF owning the queue
3139  * @eqid: egress queue id
3140  *
3141  * Frees an Ethernet egress queue.
3142  */
3143 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3144                    unsigned int vf, unsigned int eqid)
3145 {
3146         struct fw_eq_eth_cmd c;
3147
3148         memset(&c, 0, sizeof(c));
3149         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
3150                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3151                                   V_FW_EQ_ETH_CMD_PFN(pf) |
3152                                   V_FW_EQ_ETH_CMD_VFN(vf));
3153         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3154         c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
3155         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3156 }
3157
3158 /**
3159  * t4_handle_fw_rpl - process a FW reply message
3160  * @adap: the adapter
3161  * @rpl: start of the FW message
3162  *
3163  * Processes a FW message, such as link state change messages.
3164  */
3165 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3166 {
3167         u8 opcode = *(const u8 *)rpl;
3168
3169         /*
3170          * This might be a port command ... this simplifies the following
3171          * conditionals ...  We can get away with pre-dereferencing
3172          * action_to_len16 because it's in the first 16 bytes and all messages
3173          * will be at least that long.
3174          */
3175         const struct fw_port_cmd *p = (const void *)rpl;
3176         unsigned int action =
3177                 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
3178
3179         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
3180                 /* link/module state change message */
3181                 int speed = 0, fc = 0, i;
3182                 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
3183                 struct port_info *pi = NULL;
3184                 struct link_config *lc;
3185                 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
3186                 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
3187                 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
3188
3189                 if (stat & F_FW_PORT_CMD_RXPAUSE)
3190                         fc |= PAUSE_RX;
3191                 if (stat & F_FW_PORT_CMD_TXPAUSE)
3192                         fc |= PAUSE_TX;
3193                 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3194                         speed = ETH_SPEED_NUM_100M;
3195                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3196                         speed = ETH_SPEED_NUM_1G;
3197                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3198                         speed = ETH_SPEED_NUM_10G;
3199                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
3200                         speed = ETH_SPEED_NUM_40G;
3201
3202                 for_each_port(adap, i) {
3203                         pi = adap2pinfo(adap, i);
3204                         if (pi->tx_chan == chan)
3205                                 break;
3206                 }
3207                 lc = &pi->link_cfg;
3208
3209                 if (mod != pi->mod_type) {
3210                         pi->mod_type = mod;
3211                         t4_os_portmod_changed(adap, i);
3212                 }
3213                 if (link_ok != lc->link_ok || speed != lc->speed ||
3214                     fc != lc->fc) {                    /* something changed */
3215                         if (!link_ok && lc->link_ok) {
3216                                 static const char * const reason[] = {
3217                                         "Link Down",
3218                                         "Remote Fault",
3219                                         "Auto-negotiation Failure",
3220                                         "Reserved",
3221                                         "Insufficient Airflow",
3222                                         "Unable To Determine Reason",
3223                                         "No RX Signal Detected",
3224                                         "Reserved",
3225                                 };
3226                                 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
3227
3228                                 dev_warn(adap, "Port %d link down, reason: %s\n",
3229                                          chan, reason[rc]);
3230                         }
3231                         lc->link_ok = link_ok;
3232                         lc->speed = speed;
3233                         lc->fc = fc;
3234                         lc->supported = be16_to_cpu(p->u.info.pcap);
3235                 }
3236         } else {
3237                 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
3238                 return -EINVAL;
3239         }
3240         return 0;
3241 }
3242
3243 void t4_reset_link_config(struct adapter *adap, int idx)
3244 {
3245         struct port_info *pi = adap2pinfo(adap, idx);
3246         struct link_config *lc = &pi->link_cfg;
3247
3248         lc->link_ok = 0;
3249         lc->requested_speed = 0;
3250         lc->requested_fc = 0;
3251         lc->speed = 0;
3252         lc->fc = 0;
3253 }
3254
3255 /**
3256  * init_link_config - initialize a link's SW state
3257  * @lc: structure holding the link state
3258  * @caps: link capabilities
3259  *
3260  * Initializes the SW state maintained for each link, including the link's
3261  * capabilities and default speed/flow-control/autonegotiation settings.
3262  */
3263 static void init_link_config(struct link_config *lc,
3264                              unsigned int caps)
3265 {
3266         lc->supported = caps;
3267         lc->requested_speed = 0;
3268         lc->speed = 0;
3269         lc->requested_fc = 0;
3270         lc->fc = 0;
3271         if (lc->supported & FW_PORT_CAP_ANEG) {
3272                 lc->advertising = lc->supported & ADVERT_MASK;
3273                 lc->autoneg = AUTONEG_ENABLE;
3274         } else {
3275                 lc->advertising = 0;
3276                 lc->autoneg = AUTONEG_DISABLE;
3277         }
3278 }
3279
3280 /**
3281  * t4_wait_dev_ready - wait till to reads of registers work
3282  *
3283  * Right after the device is RESET is can take a small amount of time
3284  * for it to respond to register reads.  Until then, all reads will
3285  * return either 0xff...ff or 0xee...ee.  Return an error if reads
3286  * don't work within a reasonable time frame.
3287  */
3288 static int t4_wait_dev_ready(struct adapter *adapter)
3289 {
3290         u32 whoami;
3291
3292         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3293
3294         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
3295                 return 0;
3296
3297         msleep(500);
3298         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3299         return (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS
3300                         ? 0 : -EIO);
3301 }
3302
3303 struct flash_desc {
3304         u32 vendor_and_model_id;
3305         u32 size_mb;
3306 };
3307
3308 int t4_get_flash_params(struct adapter *adapter)
3309 {
3310         /*
3311          * Table for non-Numonix supported flash parts.  Numonix parts are left
3312          * to the preexisting well-tested code.  All flash parts have 64KB
3313          * sectors.
3314          */
3315         static struct flash_desc supported_flash[] = {
3316                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
3317         };
3318
3319         int ret;
3320         unsigned int i;
3321         u32 info = 0;
3322
3323         ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
3324         if (!ret)
3325                 ret = sf1_read(adapter, 3, 0, 1, &info);
3326         t4_write_reg(adapter, A_SF_OP, 0);               /* unlock SF */
3327         if (ret < 0)
3328                 return ret;
3329
3330         for (i = 0; i < ARRAY_SIZE(supported_flash); ++i)
3331                 if (supported_flash[i].vendor_and_model_id == info) {
3332                         adapter->params.sf_size = supported_flash[i].size_mb;
3333                         adapter->params.sf_nsec =
3334                                 adapter->params.sf_size / SF_SEC_SIZE;
3335                         return 0;
3336                 }
3337
3338         if ((info & 0xff) != 0x20)             /* not a Numonix flash */
3339                 return -EINVAL;
3340         info >>= 16;                           /* log2 of size */
3341         if (info >= 0x14 && info < 0x18)
3342                 adapter->params.sf_nsec = 1 << (info - 16);
3343         else if (info == 0x18)
3344                 adapter->params.sf_nsec = 64;
3345         else
3346                 return -EINVAL;
3347         adapter->params.sf_size = 1 << info;
3348
3349         /*
3350          * We should reject adapters with FLASHes which are too small. So, emit
3351          * a warning.
3352          */
3353         if (adapter->params.sf_size < FLASH_MIN_SIZE) {
3354                 dev_warn(adapter, "WARNING!!! FLASH size %#x < %#x!!!\n",
3355                          adapter->params.sf_size, FLASH_MIN_SIZE);
3356         }
3357
3358         return 0;
3359 }
3360
3361 static void set_pcie_completion_timeout(struct adapter *adapter,
3362                                         u8 range)
3363 {
3364         u32 pcie_cap;
3365         u16 val;
3366
3367         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
3368         if (pcie_cap) {
3369                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
3370                 val &= 0xfff0;
3371                 val |= range;
3372                 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
3373         }
3374 }
3375
3376 /**
3377  * t4_get_chip_type - Determine chip type from device ID
3378  * @adap: the adapter
3379  * @ver: adapter version
3380  */
3381 int t4_get_chip_type(struct adapter *adap, int ver)
3382 {
3383         enum chip_type chip = 0;
3384         u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
3385
3386         /* Retrieve adapter's device ID */
3387         switch (ver) {
3388         case CHELSIO_T5:
3389                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3390                 break;
3391         case CHELSIO_T6:
3392                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
3393                 break;
3394         default:
3395                 dev_err(adap, "Device %d is not supported\n",
3396                         adap->params.pci.device_id);
3397                 return -EINVAL;
3398         }
3399
3400         return chip;
3401 }
3402
3403 /**
3404  * t4_prep_adapter - prepare SW and HW for operation
3405  * @adapter: the adapter
3406  *
3407  * Initialize adapter SW state for the various HW modules, set initial
3408  * values for some adapter tunables, take PHYs out of reset, and
3409  * initialize the MDIO interface.
3410  */
3411 int t4_prep_adapter(struct adapter *adapter)
3412 {
3413         int ret, ver;
3414         u32 pl_rev;
3415
3416         ret = t4_wait_dev_ready(adapter);
3417         if (ret < 0)
3418                 return ret;
3419
3420         pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
3421         adapter->params.pci.device_id = adapter->pdev->id.device_id;
3422         adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
3423
3424         /*
3425          * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
3426          * ADAPTER (VERSION << 4 | REVISION)
3427          */
3428         ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
3429         adapter->params.chip = 0;
3430         switch (ver) {
3431         case CHELSIO_T5:
3432                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3433                 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
3434                 adapter->params.arch.mps_tcam_size =
3435                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3436                 adapter->params.arch.mps_rplc_size = 128;
3437                 adapter->params.arch.nchan = NCHAN;
3438                 adapter->params.arch.vfcount = 128;
3439                 break;
3440         case CHELSIO_T6:
3441                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
3442                 adapter->params.arch.sge_fl_db = 0;
3443                 adapter->params.arch.mps_tcam_size =
3444                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3445                 adapter->params.arch.mps_rplc_size = 256;
3446                 adapter->params.arch.nchan = 2;
3447                 adapter->params.arch.vfcount = 256;
3448                 break;
3449         default:
3450                 dev_err(adapter, "%s: Device %d is not supported\n",
3451                         __func__, adapter->params.pci.device_id);
3452                 return -EINVAL;
3453         }
3454
3455         adapter->params.pci.vpd_cap_addr =
3456                 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
3457
3458         ret = t4_get_flash_params(adapter);
3459         if (ret < 0)
3460                 return ret;
3461
3462         adapter->params.cim_la_size = CIMLA_SIZE;
3463
3464         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3465
3466         /*
3467          * Default port and clock for debugging in case we can't reach FW.
3468          */
3469         adapter->params.nports = 1;
3470         adapter->params.portvec = 1;
3471         adapter->params.vpd.cclk = 50000;
3472
3473         /* Set pci completion timeout value to 4 seconds. */
3474         set_pcie_completion_timeout(adapter, 0xd);
3475         return 0;
3476 }
3477
3478 /**
3479  * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
3480  * @adapter: the adapter
3481  * @qid: the Queue ID
3482  * @qtype: the Ingress or Egress type for @qid
3483  * @pbar2_qoffset: BAR2 Queue Offset
3484  * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
3485  *
3486  * Returns the BAR2 SGE Queue Registers information associated with the
3487  * indicated Absolute Queue ID.  These are passed back in return value
3488  * pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
3489  * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
3490  *
3491  * This may return an error which indicates that BAR2 SGE Queue
3492  * registers aren't available.  If an error is not returned, then the
3493  * following values are returned:
3494  *
3495  *   *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
3496  *   *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
3497  *
3498  * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
3499  * require the "Inferred Queue ID" ability may be used.  E.g. the
3500  * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
3501  * then these "Inferred Queue ID" register may not be used.
3502  */
3503 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
3504                       enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
3505                       unsigned int *pbar2_qid)
3506 {
3507         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
3508         u64 bar2_page_offset, bar2_qoffset;
3509         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
3510
3511         /*
3512          * T4 doesn't support BAR2 SGE Queue registers.
3513          */
3514         if (is_t4(adapter->params.chip))
3515                 return -EINVAL;
3516
3517         /*
3518          * Get our SGE Page Size parameters.
3519          */
3520         page_shift = adapter->params.sge.hps + 10;
3521         page_size = 1 << page_shift;
3522
3523         /*
3524          * Get the right Queues per Page parameters for our Queue.
3525          */
3526         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
3527                               adapter->params.sge.eq_qpp :
3528                               adapter->params.sge.iq_qpp);
3529         qpp_mask = (1 << qpp_shift) - 1;
3530
3531         /*
3532          * Calculate the basics of the BAR2 SGE Queue register area:
3533          *  o The BAR2 page the Queue registers will be in.
3534          *  o The BAR2 Queue ID.
3535          *  o The BAR2 Queue ID Offset into the BAR2 page.
3536          */
3537         bar2_page_offset = ((qid >> qpp_shift) << page_shift);
3538         bar2_qid = qid & qpp_mask;
3539         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
3540
3541         /*
3542          * If the BAR2 Queue ID Offset is less than the Page Size, then the
3543          * hardware will infer the Absolute Queue ID simply from the writes to
3544          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
3545          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
3546          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
3547          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
3548          * from the BAR2 Page and BAR2 Queue ID.
3549          *
3550          * One important censequence of this is that some BAR2 SGE registers
3551          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
3552          * there.  But other registers synthesize the SGE Queue ID purely
3553          * from the writes to the registers -- the Write Combined Doorbell
3554          * Buffer is a good example.  These BAR2 SGE Registers are only
3555          * available for those BAR2 SGE Register areas where the SGE Absolute
3556          * Queue ID can be inferred from simple writes.
3557          */
3558         bar2_qoffset = bar2_page_offset;
3559         bar2_qinferred = (bar2_qid_offset < page_size);
3560         if (bar2_qinferred) {
3561                 bar2_qoffset += bar2_qid_offset;
3562                 bar2_qid = 0;
3563         }
3564
3565         *pbar2_qoffset = bar2_qoffset;
3566         *pbar2_qid = bar2_qid;
3567         return 0;
3568 }
3569
3570 /**
3571  * t4_init_sge_params - initialize adap->params.sge
3572  * @adapter: the adapter
3573  *
3574  * Initialize various fields of the adapter's SGE Parameters structure.
3575  */
3576 int t4_init_sge_params(struct adapter *adapter)
3577 {
3578         struct sge_params *sge_params = &adapter->params.sge;
3579         u32 hps, qpp;
3580         unsigned int s_hps, s_qpp;
3581
3582         /*
3583          * Extract the SGE Page Size for our PF.
3584          */
3585         hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
3586         s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
3587                  adapter->pf);
3588         sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
3589
3590         /*
3591          * Extract the SGE Egress and Ingess Queues Per Page for our PF.
3592          */
3593         s_qpp = (S_QUEUESPERPAGEPF0 +
3594                  (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
3595         qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
3596         sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
3597         qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
3598         sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
3599
3600         return 0;
3601 }
3602
3603 /**
3604  * t4_init_tp_params - initialize adap->params.tp
3605  * @adap: the adapter
3606  *
3607  * Initialize various fields of the adapter's TP Parameters structure.
3608  */
3609 int t4_init_tp_params(struct adapter *adap)
3610 {
3611         int chan;
3612         u32 v;
3613
3614         v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
3615         adap->params.tp.tre = G_TIMERRESOLUTION(v);
3616         adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
3617
3618         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
3619         for (chan = 0; chan < NCHAN; chan++)
3620                 adap->params.tp.tx_modq[chan] = chan;
3621
3622         /*
3623          * Cache the adapter's Compressed Filter Mode and global Incress
3624          * Configuration.
3625          */
3626         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
3627                          &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
3628         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
3629                          &adap->params.tp.ingress_config, 1,
3630                          A_TP_INGRESS_CONFIG);
3631
3632         /*
3633          * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
3634          * shift positions of several elements of the Compressed Filter Tuple
3635          * for this adapter which we need frequently ...
3636          */
3637         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
3638         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
3639         adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
3640         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
3641                                                                F_PROTOCOL);
3642
3643         /*
3644          * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
3645          * represents the presense of an Outer VLAN instead of a VNIC ID.
3646          */
3647         if ((adap->params.tp.ingress_config & F_VNIC) == 0)
3648                 adap->params.tp.vnic_shift = -1;
3649
3650         return 0;
3651 }
3652
3653 /**
3654  * t4_filter_field_shift - calculate filter field shift
3655  * @adap: the adapter
3656  * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
3657  *
3658  * Return the shift position of a filter field within the Compressed
3659  * Filter Tuple.  The filter field is specified via its selection bit
3660  * within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
3661  */
3662 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
3663 {
3664         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
3665         unsigned int sel;
3666         int field_shift;
3667
3668         if ((filter_mode & filter_sel) == 0)
3669                 return -1;
3670
3671         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
3672                 switch (filter_mode & sel) {
3673                 case F_FCOE:
3674                         field_shift += W_FT_FCOE;
3675                         break;
3676                 case F_PORT:
3677                         field_shift += W_FT_PORT;
3678                         break;
3679                 case F_VNIC_ID:
3680                         field_shift += W_FT_VNIC_ID;
3681                         break;
3682                 case F_VLAN:
3683                         field_shift += W_FT_VLAN;
3684                         break;
3685                 case F_TOS:
3686                         field_shift += W_FT_TOS;
3687                         break;
3688                 case F_PROTOCOL:
3689                         field_shift += W_FT_PROTOCOL;
3690                         break;
3691                 case F_ETHERTYPE:
3692                         field_shift += W_FT_ETHERTYPE;
3693                         break;
3694                 case F_MACMATCH:
3695                         field_shift += W_FT_MACMATCH;
3696                         break;
3697                 case F_MPSHITTYPE:
3698                         field_shift += W_FT_MPSHITTYPE;
3699                         break;
3700                 case F_FRAGMENTATION:
3701                         field_shift += W_FT_FRAGMENTATION;
3702                         break;
3703                 }
3704         }
3705         return field_shift;
3706 }
3707
3708 int t4_init_rss_mode(struct adapter *adap, int mbox)
3709 {
3710         int i, ret;
3711         struct fw_rss_vi_config_cmd rvc;
3712
3713         memset(&rvc, 0, sizeof(rvc));
3714
3715         for_each_port(adap, i) {
3716                 struct port_info *p = adap2pinfo(adap, i);
3717
3718                 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
3719                                        F_FW_CMD_REQUEST | F_FW_CMD_READ |
3720                                        V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
3721                 rvc.retval_len16 = htonl(FW_LEN16(rvc));
3722                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
3723                 if (ret)
3724                         return ret;
3725                 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
3726         }
3727         return 0;
3728 }
3729
3730 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
3731 {
3732         u8 addr[6];
3733         int ret, i, j = 0;
3734         struct fw_port_cmd c;
3735
3736         memset(&c, 0, sizeof(c));
3737
3738         for_each_port(adap, i) {
3739                 unsigned int rss_size = 0;
3740                 struct port_info *p = adap2pinfo(adap, i);
3741
3742                 while ((adap->params.portvec & (1 << j)) == 0)
3743                         j++;
3744
3745                 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3746                                              F_FW_CMD_REQUEST | F_FW_CMD_READ |
3747                                              V_FW_PORT_CMD_PORTID(j));
3748                 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
3749                                                 FW_PORT_ACTION_GET_PORT_INFO) |
3750                                                 FW_LEN16(c));
3751                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3752                 if (ret)
3753                         return ret;
3754
3755                 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
3756                 if (ret < 0)
3757                         return ret;
3758
3759                 p->viid = ret;
3760                 p->tx_chan = j;
3761                 p->rss_size = rss_size;
3762                 t4_os_set_hw_addr(adap, i, addr);
3763
3764                 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
3765                 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
3766                                 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
3767                 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
3768                 p->mod_type = FW_PORT_MOD_TYPE_NA;
3769
3770                 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
3771                 j++;
3772         }
3773         return 0;
3774 }