4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <netinet/in.h>
36 #include <rte_interrupts.h>
38 #include <rte_debug.h>
40 #include <rte_atomic.h>
41 #include <rte_branch_prediction.h>
42 #include <rte_memory.h>
43 #include <rte_memzone.h>
44 #include <rte_tailq.h>
46 #include <rte_alarm.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_atomic.h>
50 #include <rte_malloc.h>
51 #include <rte_random.h>
53 #include <rte_byteorder.h>
57 #include "t4_regs_values.h"
58 #include "t4fw_interface.h"
60 static void init_link_config(struct link_config *lc, unsigned int caps);
63 * t4_read_mtu_tbl - returns the values in the HW path MTU table
65 * @mtus: where to store the MTU values
66 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
68 * Reads the HW path MTU table.
70 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
75 for (i = 0; i < NMTUS; ++i) {
76 t4_write_reg(adap, A_TP_MTU_TABLE,
77 V_MTUINDEX(0xff) | V_MTUVALUE(i));
78 v = t4_read_reg(adap, A_TP_MTU_TABLE);
79 mtus[i] = G_MTUVALUE(v);
81 mtu_log[i] = G_MTUWIDTH(v);
86 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
88 * @addr: the indirect TP register address
89 * @mask: specifies the field within the register to modify
90 * @val: new value for the field
92 * Sets a field of an indirect TP register to the given value.
94 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
95 unsigned int mask, unsigned int val)
97 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
98 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
99 t4_write_reg(adap, A_TP_PIO_DATA, val);
102 /* The minimum additive increment value for the congestion control table */
103 #define CC_MIN_INCR 2U
106 * t4_load_mtus - write the MTU and congestion control HW tables
108 * @mtus: the values for the MTU table
109 * @alpha: the values for the congestion control alpha parameter
110 * @beta: the values for the congestion control beta parameter
112 * Write the HW MTU table with the supplied MTUs and the high-speed
113 * congestion control table with the supplied alpha, beta, and MTUs.
114 * We write the two tables together because the additive increments
115 * depend on the MTUs.
117 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
118 const unsigned short *alpha, const unsigned short *beta)
120 static const unsigned int avg_pkts[NCCTRL_WIN] = {
121 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
122 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
123 28672, 40960, 57344, 81920, 114688, 163840, 229376
128 for (i = 0; i < NMTUS; ++i) {
129 unsigned int mtu = mtus[i];
130 unsigned int log2 = cxgbe_fls(mtu);
132 if (!(mtu & ((1 << log2) >> 2))) /* round */
134 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
135 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
137 for (w = 0; w < NCCTRL_WIN; ++w) {
140 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
143 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
144 (w << 16) | (beta[w] << 13) | inc);
150 * t4_wait_op_done_val - wait until an operation is completed
151 * @adapter: the adapter performing the operation
152 * @reg: the register to check for completion
153 * @mask: a single-bit field within @reg that indicates completion
154 * @polarity: the value of the field when the operation is completed
155 * @attempts: number of check iterations
156 * @delay: delay in usecs between iterations
157 * @valp: where to store the value of the register at completion time
159 * Wait until an operation is completed by checking a bit in a register
160 * up to @attempts times. If @valp is not NULL the value of the register
161 * at the time it indicated completion is stored there. Returns 0 if the
162 * operation completes and -EAGAIN otherwise.
164 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
165 int polarity, int attempts, int delay, u32 *valp)
168 u32 val = t4_read_reg(adapter, reg);
170 if (!!(val & mask) == polarity) {
183 * t4_set_reg_field - set a register field to a value
184 * @adapter: the adapter to program
185 * @addr: the register address
186 * @mask: specifies the portion of the register to modify
187 * @val: the new value for the register field
189 * Sets a register field specified by the supplied mask to the
192 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
195 u32 v = t4_read_reg(adapter, addr) & ~mask;
197 t4_write_reg(adapter, addr, v | val);
198 (void)t4_read_reg(adapter, addr); /* flush */
202 * t4_read_indirect - read indirectly addressed registers
204 * @addr_reg: register holding the indirect address
205 * @data_reg: register holding the value of the indirect register
206 * @vals: where the read register values are stored
207 * @nregs: how many indirect registers to read
208 * @start_idx: index of first indirect register to read
210 * Reads registers that are accessed indirectly through an address/data
213 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
214 unsigned int data_reg, u32 *vals, unsigned int nregs,
215 unsigned int start_idx)
218 t4_write_reg(adap, addr_reg, start_idx);
219 *vals++ = t4_read_reg(adap, data_reg);
225 * t4_write_indirect - write indirectly addressed registers
227 * @addr_reg: register holding the indirect addresses
228 * @data_reg: register holding the value for the indirect registers
229 * @vals: values to write
230 * @nregs: how many indirect registers to write
231 * @start_idx: address of first indirect register to write
233 * Writes a sequential block of registers that are accessed indirectly
234 * through an address/data register pair.
236 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
237 unsigned int data_reg, const u32 *vals,
238 unsigned int nregs, unsigned int start_idx)
241 t4_write_reg(adap, addr_reg, start_idx++);
242 t4_write_reg(adap, data_reg, *vals++);
247 * t4_report_fw_error - report firmware error
250 * The adapter firmware can indicate error conditions to the host.
251 * If the firmware has indicated an error, print out the reason for
252 * the firmware error.
254 static void t4_report_fw_error(struct adapter *adap)
256 static const char * const reason[] = {
257 "Crash", /* PCIE_FW_EVAL_CRASH */
258 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
259 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
260 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
261 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
262 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
263 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
264 "Reserved", /* reserved */
268 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
269 if (pcie_fw & F_PCIE_FW_ERR)
270 pr_err("%s: Firmware reports adapter error: %s\n",
271 __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
275 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
277 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
280 for ( ; nflit; nflit--, mbox_addr += 8)
281 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
285 * Handle a FW assertion reported in a mailbox.
287 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
289 struct fw_debug_cmd asrt;
291 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
292 pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
293 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
294 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
297 #define X_CIM_PF_NOACCESS 0xeeeeeeee
300 * If the Host OS Driver needs locking arround accesses to the mailbox, this
301 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
303 /* makes single-statement usage a bit cleaner ... */
304 #ifdef T4_OS_NEEDS_MBOX_LOCKING
305 #define T4_OS_MBOX_LOCKING(x) x
307 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
311 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
313 * @mbox: index of the mailbox to use
314 * @cmd: the command to write
315 * @size: command length in bytes
316 * @rpl: where to optionally store the reply
317 * @sleep_ok: if true we may sleep while awaiting command completion
318 * @timeout: time to wait for command to finish before timing out
319 * (negative implies @sleep_ok=false)
321 * Sends the given command to FW through the selected mailbox and waits
322 * for the FW to execute the command. If @rpl is not %NULL it is used to
323 * store the FW's reply to the command. The command and its optional
324 * reply are of the same length. Some FW commands like RESET and
325 * INITIALIZE can take a considerable amount of time to execute.
326 * @sleep_ok determines whether we may sleep while awaiting the response.
327 * If sleeping is allowed we use progressive backoff otherwise we spin.
328 * Note that passing in a negative @timeout is an alternate mechanism
329 * for specifying @sleep_ok=false. This is useful when a higher level
330 * interface allows for specification of @timeout but not @sleep_ok ...
332 * Returns 0 on success or a negative errno on failure. A
333 * failure can happen either because we are not able to execute the
334 * command or FW executes it but signals an error. In the latter case
335 * the return value is the error code indicated by FW (negated).
337 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
338 const void __attribute__((__may_alias__)) *cmd,
339 int size, void *rpl, bool sleep_ok, int timeout)
342 * We delay in small increments at first in an effort to maintain
343 * responsiveness for simple, fast executing commands but then back
344 * off to larger delays to a maximum retry delay.
346 static const int delay[] = {
347 1, 1, 3, 5, 10, 10, 20, 50, 100
353 unsigned int delay_idx;
354 __be64 *temp = (__be64 *)malloc(size * sizeof(char));
356 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
357 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
359 struct mbox_entry entry;
365 if ((size & 15) || size > MBOX_LEN) {
371 memcpy(p, (const __be64 *)cmd, size);
374 * If we have a negative timeout, that implies that we can't sleep.
381 #ifdef T4_OS_NEEDS_MBOX_LOCKING
383 * Queue ourselves onto the mailbox access list. When our entry is at
384 * the front of the list, we have rights to access the mailbox. So we
385 * wait [for a while] till we're at the front [or bail out with an
388 t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
393 for (i = 0; ; i += ms) {
395 * If we've waited too long, return a busy indication. This
396 * really ought to be based on our initial position in the
397 * mailbox access list but this is a start. We very rarely
398 * contend on access to the mailbox ... Also check for a
399 * firmware error which we'll report as a device error.
401 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
402 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
403 t4_os_atomic_list_del(&entry, &adap->mbox_list,
405 t4_report_fw_error(adap);
406 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
410 * If we're at the head, break out and start the mailbox
413 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
417 * Delay for a bit before checking again ...
420 ms = delay[delay_idx]; /* last element may repeat */
421 if (delay_idx < ARRAY_SIZE(delay) - 1)
428 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
431 * Attempt to gain access to the mailbox.
433 for (i = 0; i < 4; i++) {
434 ctl = t4_read_reg(adap, ctl_reg);
436 if (v != X_MBOWNER_NONE)
441 * If we were unable to gain access, dequeue ourselves from the
442 * mailbox atomic access list and report the error to our caller.
444 if (v != X_MBOWNER_PL) {
445 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
448 t4_report_fw_error(adap);
449 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
453 * If we gain ownership of the mailbox and there's a "valid" message
454 * in it, this is likely an asynchronous error message from the
455 * firmware. So we'll report that and then proceed on with attempting
456 * to issue our own command ... which may well fail if the error
457 * presaged the firmware crashing ...
459 if (ctl & F_MBMSGVALID) {
460 dev_err(adap, "found VALID command in mbox %u: "
461 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
462 (unsigned long long)t4_read_reg64(adap, data_reg),
463 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
464 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
465 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
466 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
467 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
468 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
469 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
473 * Copy in the new mailbox command and send it on its way ...
475 for (i = 0; i < size; i += 8, p++)
476 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
478 CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
479 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
480 (unsigned long long)t4_read_reg64(adap, data_reg),
481 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
482 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
483 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
484 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
485 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
486 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
487 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
489 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
490 t4_read_reg(adap, ctl_reg); /* flush write */
496 * Loop waiting for the reply; bail out if we time out or the firmware
499 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
500 for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
502 ms = delay[delay_idx]; /* last element may repeat */
503 if (delay_idx < ARRAY_SIZE(delay) - 1)
510 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
511 v = t4_read_reg(adap, ctl_reg);
512 if (v == X_CIM_PF_NOACCESS)
514 if (G_MBOWNER(v) == X_MBOWNER_PL) {
515 if (!(v & F_MBMSGVALID)) {
516 t4_write_reg(adap, ctl_reg,
517 V_MBOWNER(X_MBOWNER_NONE));
521 CXGBE_DEBUG_MBOX(adap,
522 "%s: mbox %u: %016llx %016llx %016llx %016llx "
523 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
524 (unsigned long long)t4_read_reg64(adap, data_reg),
525 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
526 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
527 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
528 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
529 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
530 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
531 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
533 CXGBE_DEBUG_MBOX(adap,
534 "command %#x completed in %d ms (%ssleeping)\n",
536 i + ms, sleep_ok ? "" : "non-");
538 res = t4_read_reg64(adap, data_reg);
539 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
540 fw_asrt(adap, data_reg);
541 res = V_FW_CMD_RETVAL(EIO);
543 get_mbox_rpl(adap, rpl, size / 8, data_reg);
545 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
547 t4_os_atomic_list_del(&entry, &adap->mbox_list,
549 return -G_FW_CMD_RETVAL((int)res);
554 * We timed out waiting for a reply to our mailbox command. Report
555 * the error and also check to see if the firmware reported any
558 dev_err(adap, "command %#x in mailbox %d timed out\n",
559 *(const u8 *)cmd, mbox);
560 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
563 t4_report_fw_error(adap);
565 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
568 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
569 void *rpl, bool sleep_ok)
571 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
576 * t4_get_regs_len - return the size of the chips register set
577 * @adapter: the adapter
579 * Returns the size of the chip's BAR0 register space.
581 unsigned int t4_get_regs_len(struct adapter *adapter)
583 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
585 switch (chip_version) {
587 return T5_REGMAP_SIZE;
591 "Unsupported chip version %d\n", chip_version);
596 * t4_get_regs - read chip registers into provided buffer
598 * @buf: register buffer
599 * @buf_size: size (in bytes) of register buffer
601 * If the provided register buffer isn't large enough for the chip's
602 * full register range, the register dump will be truncated to the
603 * register buffer's size.
605 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
607 static const unsigned int t5_reg_ranges[] = {
1382 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1383 const unsigned int *reg_ranges;
1384 int reg_ranges_size, range;
1385 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1387 /* Select the right set of register ranges to dump depending on the
1388 * adapter chip type.
1390 switch (chip_version) {
1392 reg_ranges = t5_reg_ranges;
1393 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1398 "Unsupported chip version %d\n", chip_version);
1402 /* Clear the register buffer and insert the appropriate register
1403 * values selected by the above register ranges.
1405 memset(buf, 0, buf_size);
1406 for (range = 0; range < reg_ranges_size; range += 2) {
1407 unsigned int reg = reg_ranges[range];
1408 unsigned int last_reg = reg_ranges[range + 1];
1409 u32 *bufp = (u32 *)((char *)buf + reg);
1411 /* Iterate across the register range filling in the register
1412 * buffer but don't write past the end of the register buffer.
1414 while (reg <= last_reg && bufp < buf_end) {
1415 *bufp++ = t4_read_reg(adap, reg);
1421 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1422 #define EEPROM_DELAY 10 /* 10us per poll spin */
1423 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
1425 #define EEPROM_STAT_ADDR 0x7bfc
1428 * Small utility function to wait till any outstanding VPD Access is complete.
1429 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1430 * VPD Access in flight. This allows us to handle the problem of having a
1431 * previous VPD Access time out and prevent an attempt to inject a new VPD
1432 * Request before any in-flight VPD request has completed.
1434 static int t4_seeprom_wait(struct adapter *adapter)
1436 unsigned int base = adapter->params.pci.vpd_cap_addr;
1439 /* If no VPD Access is in flight, we can just return success right
1442 if (!adapter->vpd_busy)
1445 /* Poll the VPD Capability Address/Flag register waiting for it
1446 * to indicate that the operation is complete.
1448 max_poll = EEPROM_MAX_POLL;
1452 udelay(EEPROM_DELAY);
1453 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
1455 /* If the operation is complete, mark the VPD as no longer
1456 * busy and return success.
1458 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
1459 adapter->vpd_busy = 0;
1462 } while (--max_poll);
1464 /* Failure! Note that we leave the VPD Busy status set in order to
1465 * avoid pushing a new VPD Access request into the VPD Capability till
1466 * the current operation eventually succeeds. It's a bug to issue a
1467 * new request when an existing request is in flight and will result
1468 * in corrupt hardware state.
1474 * t4_seeprom_read - read a serial EEPROM location
1475 * @adapter: adapter to read
1476 * @addr: EEPROM virtual address
1477 * @data: where to store the read data
1479 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
1480 * VPD capability. Note that this function must be called with a virtual
1483 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
1485 unsigned int base = adapter->params.pci.vpd_cap_addr;
1488 /* VPD Accesses must alway be 4-byte aligned!
1490 if (addr >= EEPROMVSIZE || (addr & 3))
1493 /* Wait for any previous operation which may still be in flight to
1496 ret = t4_seeprom_wait(adapter);
1498 dev_err(adapter, "VPD still busy from previous operation\n");
1502 /* Issue our new VPD Read request, mark the VPD as being busy and wait
1503 * for our request to complete. If it doesn't complete, note the
1504 * error and return it to our caller. Note that we do not reset the
1507 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
1508 adapter->vpd_busy = 1;
1509 adapter->vpd_flag = PCI_VPD_ADDR_F;
1510 ret = t4_seeprom_wait(adapter);
1512 dev_err(adapter, "VPD read of address %#x failed\n", addr);
1516 /* Grab the returned data, swizzle it into our endianness and
1519 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
1520 *data = le32_to_cpu(*data);
1525 * t4_seeprom_write - write a serial EEPROM location
1526 * @adapter: adapter to write
1527 * @addr: virtual EEPROM address
1528 * @data: value to write
1530 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
1531 * VPD capability. Note that this function must be called with a virtual
1534 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
1536 unsigned int base = adapter->params.pci.vpd_cap_addr;
1541 /* VPD Accesses must alway be 4-byte aligned!
1543 if (addr >= EEPROMVSIZE || (addr & 3))
1546 /* Wait for any previous operation which may still be in flight to
1549 ret = t4_seeprom_wait(adapter);
1551 dev_err(adapter, "VPD still busy from previous operation\n");
1555 /* Issue our new VPD Read request, mark the VPD as being busy and wait
1556 * for our request to complete. If it doesn't complete, note the
1557 * error and return it to our caller. Note that we do not reset the
1560 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
1562 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
1563 (u16)addr | PCI_VPD_ADDR_F);
1564 adapter->vpd_busy = 1;
1565 adapter->vpd_flag = 0;
1566 ret = t4_seeprom_wait(adapter);
1568 dev_err(adapter, "VPD write of address %#x failed\n", addr);
1572 /* Reset PCI_VPD_DATA register after a transaction and wait for our
1573 * request to complete. If it doesn't complete, return error.
1575 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
1576 max_poll = EEPROM_MAX_POLL;
1578 udelay(EEPROM_DELAY);
1579 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
1580 } while ((stats_reg & 0x1) && --max_poll);
1584 /* Return success! */
1589 * t4_seeprom_wp - enable/disable EEPROM write protection
1590 * @adapter: the adapter
1591 * @enable: whether to enable or disable write protection
1593 * Enables or disables write protection on the serial EEPROM.
1595 int t4_seeprom_wp(struct adapter *adapter, int enable)
1597 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
1601 * t4_config_rss_range - configure a portion of the RSS mapping table
1602 * @adapter: the adapter
1603 * @mbox: mbox to use for the FW command
1604 * @viid: virtual interface whose RSS subtable is to be written
1605 * @start: start entry in the table to write
1606 * @n: how many table entries to write
1607 * @rspq: values for the "response queue" (Ingress Queue) lookup table
1608 * @nrspq: number of values in @rspq
1610 * Programs the selected part of the VI's RSS mapping table with the
1611 * provided values. If @nrspq < @n the supplied values are used repeatedly
1612 * until the full table range is populated.
1614 * The caller must ensure the values in @rspq are in the range allowed for
1617 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1618 int start, int n, const u16 *rspq, unsigned int nrspq)
1621 const u16 *rsp = rspq;
1622 const u16 *rsp_end = rspq + nrspq;
1623 struct fw_rss_ind_tbl_cmd cmd;
1625 memset(&cmd, 0, sizeof(cmd));
1626 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
1627 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
1628 V_FW_RSS_IND_TBL_CMD_VIID(viid));
1629 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1632 * Each firmware RSS command can accommodate up to 32 RSS Ingress
1633 * Queue Identifiers. These Ingress Queue IDs are packed three to
1634 * a 32-bit word as 10-bit values with the upper remaining 2 bits
1638 int nq = min(n, 32);
1640 __be32 *qp = &cmd.iq0_to_iq2;
1643 * Set up the firmware RSS command header to send the next
1644 * "nq" Ingress Queue IDs to the firmware.
1646 cmd.niqid = cpu_to_be16(nq);
1647 cmd.startidx = cpu_to_be16(start);
1650 * "nq" more done for the start of the next loop.
1656 * While there are still Ingress Queue IDs to stuff into the
1657 * current firmware RSS command, retrieve them from the
1658 * Ingress Queue ID array and insert them into the command.
1662 * Grab up to the next 3 Ingress Queue IDs (wrapping
1663 * around the Ingress Queue ID array if necessary) and
1664 * insert them into the firmware RSS command at the
1665 * current 3-tuple position within the commad.
1669 int nqbuf = min(3, nq);
1675 while (nqbuf && nq_packed < 32) {
1682 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
1683 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
1684 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
1688 * Send this portion of the RRS table update to the firmware;
1689 * bail out on any errors.
1691 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
1700 * t4_config_vi_rss - configure per VI RSS settings
1701 * @adapter: the adapter
1702 * @mbox: mbox to use for the FW command
1705 * @defq: id of the default RSS queue for the VI.
1707 * Configures VI-specific RSS properties.
1709 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1710 unsigned int flags, unsigned int defq)
1712 struct fw_rss_vi_config_cmd c;
1714 memset(&c, 0, sizeof(c));
1715 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
1716 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
1717 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
1718 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
1719 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
1720 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
1721 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
1725 * init_cong_ctrl - initialize congestion control parameters
1726 * @a: the alpha values for congestion control
1727 * @b: the beta values for congestion control
1729 * Initialize the congestion control parameters.
1731 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
1735 for (i = 0; i < 9; i++) {
1789 #define INIT_CMD(var, cmd, rd_wr) do { \
1790 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
1791 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
1792 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
1795 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
1797 u32 cclk_param, cclk_val;
1801 * Ask firmware for the Core Clock since it knows how to translate the
1802 * Reference Clock ('V2') VPD field into a Core Clock value ...
1804 cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1805 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
1806 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
1807 1, &cclk_param, &cclk_val);
1809 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
1815 dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
1819 /* serial flash and firmware constants and flash config file constants */
1821 SF_ATTEMPTS = 10, /* max retries for SF operations */
1823 /* flash command opcodes */
1824 SF_PROG_PAGE = 2, /* program page */
1825 SF_WR_DISABLE = 4, /* disable writes */
1826 SF_RD_STATUS = 5, /* read status register */
1827 SF_WR_ENABLE = 6, /* enable writes */
1828 SF_RD_DATA_FAST = 0xb, /* read flash */
1829 SF_RD_ID = 0x9f, /* read ID */
1830 SF_ERASE_SECTOR = 0xd8, /* erase sector */
1834 * sf1_read - read data from the serial flash
1835 * @adapter: the adapter
1836 * @byte_cnt: number of bytes to read
1837 * @cont: whether another operation will be chained
1838 * @lock: whether to lock SF for PL access only
1839 * @valp: where to store the read data
1841 * Reads up to 4 bytes of data from the serial flash. The location of
1842 * the read needs to be specified prior to calling this by issuing the
1843 * appropriate commands to the serial flash.
1845 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
1846 int lock, u32 *valp)
1850 if (!byte_cnt || byte_cnt > 4)
1852 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
1854 t4_write_reg(adapter, A_SF_OP,
1855 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
1856 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
1858 *valp = t4_read_reg(adapter, A_SF_DATA);
1863 * sf1_write - write data to the serial flash
1864 * @adapter: the adapter
1865 * @byte_cnt: number of bytes to write
1866 * @cont: whether another operation will be chained
1867 * @lock: whether to lock SF for PL access only
1868 * @val: value to write
1870 * Writes up to 4 bytes of data to the serial flash. The location of
1871 * the write needs to be specified prior to calling this by issuing the
1872 * appropriate commands to the serial flash.
1874 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
1877 if (!byte_cnt || byte_cnt > 4)
1879 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
1881 t4_write_reg(adapter, A_SF_DATA, val);
1882 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
1883 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
1884 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
1888 * t4_read_flash - read words from serial flash
1889 * @adapter: the adapter
1890 * @addr: the start address for the read
1891 * @nwords: how many 32-bit words to read
1892 * @data: where to store the read data
1893 * @byte_oriented: whether to store data as bytes or as words
1895 * Read the specified number of 32-bit words from the serial flash.
1896 * If @byte_oriented is set the read data is stored as a byte array
1897 * (i.e., big-endian), otherwise as 32-bit words in the platform's
1898 * natural endianness.
1900 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1901 unsigned int nwords, u32 *data, int byte_oriented)
1905 if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
1909 addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
1911 ret = sf1_write(adapter, 4, 1, 0, addr);
1915 ret = sf1_read(adapter, 1, 1, 0, data);
1919 for ( ; nwords; nwords--, data++) {
1920 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
1922 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
1926 *data = cpu_to_be32(*data);
1932 * t4_get_fw_version - read the firmware version
1933 * @adapter: the adapter
1934 * @vers: where to place the version
1936 * Reads the FW version from flash.
1938 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
1940 return t4_read_flash(adapter, FLASH_FW_START +
1941 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
1945 * t4_get_tp_version - read the TP microcode version
1946 * @adapter: the adapter
1947 * @vers: where to place the version
1949 * Reads the TP microcode version from flash.
1951 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
1953 return t4_read_flash(adapter, FLASH_FW_START +
1954 offsetof(struct fw_hdr, tp_microcode_ver),
1958 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1959 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
1960 FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG)
1963 * t4_link_l1cfg - apply link configuration to MAC/PHY
1964 * @phy: the PHY to setup
1965 * @mac: the MAC to setup
1966 * @lc: the requested link configuration
1968 * Set up a port's MAC and PHY according to a desired link configuration.
1969 * - If the PHY can auto-negotiate first decide what to advertise, then
1970 * enable/disable auto-negotiation as desired, and reset.
1971 * - If the PHY does not auto-negotiate just reset it.
1972 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1973 * otherwise do it later based on the outcome of auto-negotiation.
1975 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1976 struct link_config *lc)
1978 struct fw_port_cmd c;
1979 unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
1982 if (lc->requested_fc & PAUSE_RX)
1983 fc |= FW_PORT_CAP_FC_RX;
1984 if (lc->requested_fc & PAUSE_TX)
1985 fc |= FW_PORT_CAP_FC_TX;
1987 memset(&c, 0, sizeof(c));
1988 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
1989 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
1990 V_FW_PORT_CMD_PORTID(port));
1992 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1995 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1996 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
1998 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1999 } else if (lc->autoneg == AUTONEG_DISABLE) {
2000 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
2001 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
2003 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
2006 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2010 * t4_flash_cfg_addr - return the address of the flash configuration file
2011 * @adapter: the adapter
2013 * Return the address within the flash where the Firmware Configuration
2014 * File is stored, or an error if the device FLASH is too small to contain
2015 * a Firmware Configuration File.
2017 int t4_flash_cfg_addr(struct adapter *adapter)
2020 * If the device FLASH isn't large enough to hold a Firmware
2021 * Configuration File, return an error.
2023 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2026 return FLASH_CFG_START;
2029 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2032 * t4_intr_enable - enable interrupts
2033 * @adapter: the adapter whose interrupts should be enabled
2035 * Enable PF-specific interrupts for the calling function and the top-level
2036 * interrupt concentrator for global interrupts. Interrupts are already
2037 * enabled at each module, here we just enable the roots of the interrupt
2040 * Note: this function should be called only when the driver manages
2041 * non PF-specific interrupts from the various HW modules. Only one PCI
2042 * function at a time should be doing this.
2044 void t4_intr_enable(struct adapter *adapter)
2047 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2048 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2049 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2051 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2052 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2053 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2054 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2055 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2056 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2057 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2058 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2059 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2060 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2061 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2065 * t4_intr_disable - disable interrupts
2066 * @adapter: the adapter whose interrupts should be disabled
2068 * Disable interrupts. We only disable the top-level interrupt
2069 * concentrators. The caller must be a PCI function managing global
2072 void t4_intr_disable(struct adapter *adapter)
2074 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2075 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2076 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2078 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2079 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2083 * t4_get_port_type_description - return Port Type string description
2084 * @port_type: firmware Port Type enumeration
2086 const char *t4_get_port_type_description(enum fw_port_type port_type)
2088 static const char * const port_type_description[] = {
2107 if (port_type < ARRAY_SIZE(port_type_description))
2108 return port_type_description[port_type];
2113 * t4_get_mps_bg_map - return the buffer groups associated with a port
2114 * @adap: the adapter
2115 * @idx: the port index
2117 * Returns a bitmap indicating which MPS buffer groups are associated
2118 * with the given port. Bit i is set if buffer group i is used by the
2121 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
2123 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
2126 return idx == 0 ? 0xf : 0;
2128 return idx < 2 ? (3 << (2 * idx)) : 0;
2133 * t4_get_port_stats - collect port statistics
2134 * @adap: the adapter
2135 * @idx: the port index
2136 * @p: the stats structure to fill
2138 * Collect statistics related to the given port from HW.
2140 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2142 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2144 #define GET_STAT(name) \
2145 t4_read_reg64(adap, \
2146 (is_t4(adap->params.chip) ? \
2147 PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2148 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2149 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2151 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2152 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2153 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2154 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2155 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2156 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2157 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2158 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2159 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2160 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2161 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2162 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2163 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2164 p->tx_drop = GET_STAT(TX_PORT_DROP);
2165 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2166 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2167 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2168 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2169 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2170 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2171 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2172 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2173 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2175 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2176 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2177 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2178 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2179 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2180 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2181 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2182 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2183 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2184 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2185 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2186 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2187 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2188 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2189 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2190 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2191 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2192 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2193 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2194 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2195 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2196 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2197 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2198 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2199 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2200 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2201 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2202 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2203 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2204 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2205 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2206 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2207 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2208 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2209 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2216 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
2217 * @adap: The adapter
2219 * @stats: Current stats to fill
2220 * @offset: Previous stats snapshot
2222 void t4_get_port_stats_offset(struct adapter *adap, int idx,
2223 struct port_stats *stats,
2224 struct port_stats *offset)
2229 t4_get_port_stats(adap, idx, stats);
2230 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
2231 i < (sizeof(struct port_stats) / sizeof(u64));
2237 * t4_clr_port_stats - clear port statistics
2238 * @adap: the adapter
2239 * @idx: the port index
2241 * Clear HW statistics for the given port.
2243 void t4_clr_port_stats(struct adapter *adap, int idx)
2246 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2249 if (is_t4(adap->params.chip))
2250 port_base_addr = PORT_BASE(idx);
2252 port_base_addr = T5_PORT_BASE(idx);
2254 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
2255 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
2256 t4_write_reg(adap, port_base_addr + i, 0);
2257 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
2258 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
2259 t4_write_reg(adap, port_base_addr + i, 0);
2260 for (i = 0; i < 4; i++)
2261 if (bgmap & (1 << i)) {
2263 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
2266 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
2272 * t4_fw_hello - establish communication with FW
2273 * @adap: the adapter
2274 * @mbox: mailbox to use for the FW command
2275 * @evt_mbox: mailbox to receive async FW events
2276 * @master: specifies the caller's willingness to be the device master
2277 * @state: returns the current device state (if non-NULL)
2279 * Issues a command to establish communication with FW. Returns either
2280 * an error (negative integer) or the mailbox of the Master PF.
2282 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2283 enum dev_master master, enum dev_state *state)
2286 struct fw_hello_cmd c;
2288 unsigned int master_mbox;
2289 int retries = FW_CMD_HELLO_RETRIES;
2292 memset(&c, 0, sizeof(c));
2293 INIT_CMD(c, HELLO, WRITE);
2294 c.err_to_clearinit = cpu_to_be32(
2295 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2296 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2297 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2298 M_FW_HELLO_CMD_MBMASTER) |
2299 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2300 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
2301 F_FW_HELLO_CMD_CLEARINIT);
2304 * Issue the HELLO command to the firmware. If it's not successful
2305 * but indicates that we got a "busy" or "timeout" condition, retry
2306 * the HELLO until we exhaust our retry limit. If we do exceed our
2307 * retry limit, check to see if the firmware left us any error
2308 * information and report that if so ...
2310 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2311 if (ret != FW_SUCCESS) {
2312 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2314 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
2315 t4_report_fw_error(adap);
2319 v = be32_to_cpu(c.err_to_clearinit);
2320 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
2322 if (v & F_FW_HELLO_CMD_ERR)
2323 *state = DEV_STATE_ERR;
2324 else if (v & F_FW_HELLO_CMD_INIT)
2325 *state = DEV_STATE_INIT;
2327 *state = DEV_STATE_UNINIT;
2331 * If we're not the Master PF then we need to wait around for the
2332 * Master PF Driver to finish setting up the adapter.
2334 * Note that we also do this wait if we're a non-Master-capable PF and
2335 * there is no current Master PF; a Master PF may show up momentarily
2336 * and we wouldn't want to fail pointlessly. (This can happen when an
2337 * OS loads lots of different drivers rapidly at the same time). In
2338 * this case, the Master PF returned by the firmware will be
2339 * M_PCIE_FW_MASTER so the test below will work ...
2341 if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
2342 master_mbox != mbox) {
2343 int waiting = FW_CMD_HELLO_TIMEOUT;
2346 * Wait for the firmware to either indicate an error or
2347 * initialized state. If we see either of these we bail out
2348 * and report the issue to the caller. If we exhaust the
2349 * "hello timeout" and we haven't exhausted our retries, try
2350 * again. Otherwise bail with a timeout error.
2359 * If neither Error nor Initialialized are indicated
2360 * by the firmware keep waiting till we exaust our
2361 * timeout ... and then retry if we haven't exhausted
2364 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
2365 if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
2376 * We either have an Error or Initialized condition
2377 * report errors preferentially.
2380 if (pcie_fw & F_PCIE_FW_ERR)
2381 *state = DEV_STATE_ERR;
2382 else if (pcie_fw & F_PCIE_FW_INIT)
2383 *state = DEV_STATE_INIT;
2387 * If we arrived before a Master PF was selected and
2388 * there's not a valid Master PF, grab its identity
2391 if (master_mbox == M_PCIE_FW_MASTER &&
2392 (pcie_fw & F_PCIE_FW_MASTER_VLD))
2393 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
2402 * t4_fw_bye - end communication with FW
2403 * @adap: the adapter
2404 * @mbox: mailbox to use for the FW command
2406 * Issues a command to terminate communication with FW.
2408 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2410 struct fw_bye_cmd c;
2412 memset(&c, 0, sizeof(c));
2413 INIT_CMD(c, BYE, WRITE);
2414 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2418 * t4_fw_reset - issue a reset to FW
2419 * @adap: the adapter
2420 * @mbox: mailbox to use for the FW command
2421 * @reset: specifies the type of reset to perform
2423 * Issues a reset command of the specified type to FW.
2425 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2427 struct fw_reset_cmd c;
2429 memset(&c, 0, sizeof(c));
2430 INIT_CMD(c, RESET, WRITE);
2431 c.val = cpu_to_be32(reset);
2432 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2436 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2437 * @adap: the adapter
2438 * @mbox: mailbox to use for the FW RESET command (if desired)
2439 * @force: force uP into RESET even if FW RESET command fails
2441 * Issues a RESET command to firmware (if desired) with a HALT indication
2442 * and then puts the microprocessor into RESET state. The RESET command
2443 * will only be issued if a legitimate mailbox is provided (mbox <=
2444 * M_PCIE_FW_MASTER).
2446 * This is generally used in order for the host to safely manipulate the
2447 * adapter without fear of conflicting with whatever the firmware might
2448 * be doing. The only way out of this state is to RESTART the firmware
2451 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2456 * If a legitimate mailbox is provided, issue a RESET command
2457 * with a HALT indication.
2459 if (mbox <= M_PCIE_FW_MASTER) {
2460 struct fw_reset_cmd c;
2462 memset(&c, 0, sizeof(c));
2463 INIT_CMD(c, RESET, WRITE);
2464 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
2465 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
2466 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2470 * Normally we won't complete the operation if the firmware RESET
2471 * command fails but if our caller insists we'll go ahead and put the
2472 * uP into RESET. This can be useful if the firmware is hung or even
2473 * missing ... We'll have to take the risk of putting the uP into
2474 * RESET without the cooperation of firmware in that case.
2476 * We also force the firmware's HALT flag to be on in case we bypassed
2477 * the firmware RESET command above or we're dealing with old firmware
2478 * which doesn't have the HALT capability. This will serve as a flag
2479 * for the incoming firmware to know that it's coming out of a HALT
2480 * rather than a RESET ... if it's new enough to understand that ...
2482 if (ret == 0 || force) {
2483 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
2484 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
2489 * And we always return the result of the firmware RESET command
2490 * even when we force the uP into RESET ...
2496 * t4_fw_restart - restart the firmware by taking the uP out of RESET
2497 * @adap: the adapter
2498 * @mbox: mailbox to use for the FW RESET command (if desired)
2499 * @reset: if we want to do a RESET to restart things
2501 * Restart firmware previously halted by t4_fw_halt(). On successful
2502 * return the previous PF Master remains as the new PF Master and there
2503 * is no need to issue a new HELLO command, etc.
2505 * We do this in two ways:
2507 * 1. If we're dealing with newer firmware we'll simply want to take
2508 * the chip's microprocessor out of RESET. This will cause the
2509 * firmware to start up from its start vector. And then we'll loop
2510 * until the firmware indicates it's started again (PCIE_FW.HALT
2511 * reset to 0) or we timeout.
2513 * 2. If we're dealing with older firmware then we'll need to RESET
2514 * the chip since older firmware won't recognize the PCIE_FW.HALT
2515 * flag and automatically RESET itself on startup.
2517 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
2521 * Since we're directing the RESET instead of the firmware
2522 * doing it automatically, we need to clear the PCIE_FW.HALT
2525 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
2528 * If we've been given a valid mailbox, first try to get the
2529 * firmware to do the RESET. If that works, great and we can
2530 * return success. Otherwise, if we haven't been given a
2531 * valid mailbox or the RESET command failed, fall back to
2532 * hitting the chip with a hammer.
2534 if (mbox <= M_PCIE_FW_MASTER) {
2535 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
2537 if (t4_fw_reset(adap, mbox,
2538 F_PIORST | F_PIORSTMODE) == 0)
2542 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
2547 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
2548 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
2549 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
2560 * t4_fixup_host_params_compat - fix up host-dependent parameters
2561 * @adap: the adapter
2562 * @page_size: the host's Base Page Size
2563 * @cache_line_size: the host's Cache Line Size
2564 * @chip_compat: maintain compatibility with designated chip
2566 * Various registers in the chip contain values which are dependent on the
2567 * host's Base Page and Cache Line Sizes. This function will fix all of
2568 * those registers with the appropriate values as passed in ...
2570 * @chip_compat is used to limit the set of changes that are made
2571 * to be compatible with the indicated chip release. This is used by
2572 * drivers to maintain compatibility with chip register settings when
2573 * the drivers haven't [yet] been updated with new chip support.
2575 int t4_fixup_host_params_compat(struct adapter *adap,
2576 unsigned int page_size,
2577 unsigned int cache_line_size,
2578 enum chip_type chip_compat)
2580 unsigned int page_shift = cxgbe_fls(page_size) - 1;
2581 unsigned int sge_hps = page_shift - 10;
2582 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
2583 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
2584 unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
2586 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
2587 V_HOSTPAGESIZEPF0(sge_hps) |
2588 V_HOSTPAGESIZEPF1(sge_hps) |
2589 V_HOSTPAGESIZEPF2(sge_hps) |
2590 V_HOSTPAGESIZEPF3(sge_hps) |
2591 V_HOSTPAGESIZEPF4(sge_hps) |
2592 V_HOSTPAGESIZEPF5(sge_hps) |
2593 V_HOSTPAGESIZEPF6(sge_hps) |
2594 V_HOSTPAGESIZEPF7(sge_hps));
2596 if (is_t4(adap->params.chip) || is_t4(chip_compat))
2597 t4_set_reg_field(adap, A_SGE_CONTROL,
2598 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
2599 F_EGRSTATUSPAGESIZE,
2600 V_INGPADBOUNDARY(fl_align_log -
2601 X_INGPADBOUNDARY_SHIFT) |
2602 V_EGRSTATUSPAGESIZE(stat_len != 64));
2605 * T5 introduced the separation of the Free List Padding and
2606 * Packing Boundaries. Thus, we can select a smaller Padding
2607 * Boundary to avoid uselessly chewing up PCIe Link and Memory
2608 * Bandwidth, and use a Packing Boundary which is large enough
2609 * to avoid false sharing between CPUs, etc.
2611 * For the PCI Link, the smaller the Padding Boundary the
2612 * better. For the Memory Controller, a smaller Padding
2613 * Boundary is better until we cross under the Memory Line
2614 * Size (the minimum unit of transfer to/from Memory). If we
2615 * have a Padding Boundary which is smaller than the Memory
2616 * Line Size, that'll involve a Read-Modify-Write cycle on the
2617 * Memory Controller which is never good. For T5 the smallest
2618 * Padding Boundary which we can select is 32 bytes which is
2619 * larger than any known Memory Controller Line Size so we'll
2624 * N.B. T5 has a different interpretation of the "0" value for
2625 * the Packing Boundary. This corresponds to 16 bytes instead
2626 * of the expected 32 bytes. We never have a Packing Boundary
2627 * less than 32 bytes so we can't use that special value but
2628 * on the other hand, if we wanted 32 bytes, the best we can
2629 * really do is 64 bytes ...
2631 if (fl_align <= 32) {
2635 t4_set_reg_field(adap, A_SGE_CONTROL,
2636 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
2637 F_EGRSTATUSPAGESIZE,
2638 V_INGPADBOUNDARY(X_INGPCIEBOUNDARY_32B) |
2639 V_EGRSTATUSPAGESIZE(stat_len != 64));
2640 t4_set_reg_field(adap, A_SGE_CONTROL2,
2641 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
2642 V_INGPACKBOUNDARY(fl_align_log -
2643 X_INGPACKBOUNDARY_SHIFT));
2647 * Adjust various SGE Free List Host Buffer Sizes.
2649 * The first four entries are:
2653 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
2654 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
2656 * For the single-MTU buffers in unpacked mode we need to include
2657 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
2658 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
2659 * Padding boundary. All of these are accommodated in the Factory
2660 * Default Firmware Configuration File but we need to adjust it for
2661 * this host's cache line size.
2663 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
2664 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
2665 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
2667 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
2668 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
2671 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
2677 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
2678 * @adap: the adapter
2679 * @page_size: the host's Base Page Size
2680 * @cache_line_size: the host's Cache Line Size
2682 * Various registers in T4 contain values which are dependent on the
2683 * host's Base Page and Cache Line Sizes. This function will fix all of
2684 * those registers with the appropriate values as passed in ...
2686 * This routine makes changes which are compatible with T4 chips.
2688 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
2689 unsigned int cache_line_size)
2691 return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
2696 * t4_fw_initialize - ask FW to initialize the device
2697 * @adap: the adapter
2698 * @mbox: mailbox to use for the FW command
2700 * Issues a command to FW to partially initialize the device. This
2701 * performs initialization that generally doesn't depend on user input.
2703 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
2705 struct fw_initialize_cmd c;
2707 memset(&c, 0, sizeof(c));
2708 INIT_CMD(c, INITIALIZE, WRITE);
2709 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2713 * t4_query_params_rw - query FW or device parameters
2714 * @adap: the adapter
2715 * @mbox: mailbox to use for the FW command
2718 * @nparams: the number of parameters
2719 * @params: the parameter names
2720 * @val: the parameter values
2721 * @rw: Write and read flag
2723 * Reads the value of FW or device parameters. Up to 7 parameters can be
2726 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
2727 unsigned int pf, unsigned int vf,
2728 unsigned int nparams, const u32 *params,
2733 struct fw_params_cmd c;
2734 __be32 *p = &c.param[0].mnem;
2739 memset(&c, 0, sizeof(c));
2740 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
2741 F_FW_CMD_REQUEST | F_FW_CMD_READ |
2742 V_FW_PARAMS_CMD_PFN(pf) |
2743 V_FW_PARAMS_CMD_VFN(vf));
2744 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2746 for (i = 0; i < nparams; i++) {
2747 *p++ = cpu_to_be32(*params++);
2749 *p = cpu_to_be32(*(val + i));
2753 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2755 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
2756 *val++ = be32_to_cpu(*p);
2760 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2761 unsigned int vf, unsigned int nparams, const u32 *params,
2764 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
2768 * t4_set_params_timeout - sets FW or device parameters
2769 * @adap: the adapter
2770 * @mbox: mailbox to use for the FW command
2773 * @nparams: the number of parameters
2774 * @params: the parameter names
2775 * @val: the parameter values
2776 * @timeout: the timeout time
2778 * Sets the value of FW or device parameters. Up to 7 parameters can be
2779 * specified at once.
2781 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
2782 unsigned int pf, unsigned int vf,
2783 unsigned int nparams, const u32 *params,
2784 const u32 *val, int timeout)
2786 struct fw_params_cmd c;
2787 __be32 *p = &c.param[0].mnem;
2792 memset(&c, 0, sizeof(c));
2793 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
2794 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2795 V_FW_PARAMS_CMD_PFN(pf) |
2796 V_FW_PARAMS_CMD_VFN(vf));
2797 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2800 *p++ = cpu_to_be32(*params++);
2801 *p++ = cpu_to_be32(*val++);
2804 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
2807 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2808 unsigned int vf, unsigned int nparams, const u32 *params,
2811 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
2812 FW_CMD_MAX_TIMEOUT);
2816 * t4_alloc_vi_func - allocate a virtual interface
2817 * @adap: the adapter
2818 * @mbox: mailbox to use for the FW command
2819 * @port: physical port associated with the VI
2820 * @pf: the PF owning the VI
2821 * @vf: the VF owning the VI
2822 * @nmac: number of MAC addresses needed (1 to 5)
2823 * @mac: the MAC addresses of the VI
2824 * @rss_size: size of RSS table slice associated with this VI
2825 * @portfunc: which Port Application Function MAC Address is desired
2826 * @idstype: Intrusion Detection Type
2828 * Allocates a virtual interface for the given physical port. If @mac is
2829 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
2830 * @mac should be large enough to hold @nmac Ethernet addresses, they are
2831 * stored consecutively so the space needed is @nmac * 6 bytes.
2832 * Returns a negative error number or the non-negative VI id.
2834 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
2835 unsigned int port, unsigned int pf, unsigned int vf,
2836 unsigned int nmac, u8 *mac, unsigned int *rss_size,
2837 unsigned int portfunc, unsigned int idstype)
2842 memset(&c, 0, sizeof(c));
2843 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
2844 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
2845 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
2846 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
2847 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
2848 V_FW_VI_CMD_FUNC(portfunc));
2849 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
2852 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2857 memcpy(mac, c.mac, sizeof(c.mac));
2860 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
2863 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
2866 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
2869 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
2874 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
2875 return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
2879 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
2880 * @adap: the adapter
2881 * @mbox: mailbox to use for the FW command
2882 * @port: physical port associated with the VI
2883 * @pf: the PF owning the VI
2884 * @vf: the VF owning the VI
2885 * @nmac: number of MAC addresses needed (1 to 5)
2886 * @mac: the MAC addresses of the VI
2887 * @rss_size: size of RSS table slice associated with this VI
2889 * Backwards compatible and convieniance routine to allocate a Virtual
2890 * Interface with a Ethernet Port Application Function and Intrustion
2891 * Detection System disabled.
2893 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
2894 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
2895 unsigned int *rss_size)
2897 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
2902 * t4_free_vi - free a virtual interface
2903 * @adap: the adapter
2904 * @mbox: mailbox to use for the FW command
2905 * @pf: the PF owning the VI
2906 * @vf: the VF owning the VI
2907 * @viid: virtual interface identifiler
2909 * Free a previously allocated virtual interface.
2911 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
2912 unsigned int vf, unsigned int viid)
2916 memset(&c, 0, sizeof(c));
2917 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
2918 F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
2919 V_FW_VI_CMD_VFN(vf));
2920 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
2921 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
2923 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2927 * t4_set_rxmode - set Rx properties of a virtual interface
2928 * @adap: the adapter
2929 * @mbox: mailbox to use for the FW command
2931 * @mtu: the new MTU or -1
2932 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
2933 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
2934 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
2935 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
2937 * @sleep_ok: if true we may sleep while awaiting command completion
2939 * Sets Rx properties of a virtual interface.
2941 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
2942 int mtu, int promisc, int all_multi, int bcast, int vlanex,
2945 struct fw_vi_rxmode_cmd c;
2947 /* convert to FW values */
2949 mtu = M_FW_VI_RXMODE_CMD_MTU;
2951 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
2953 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
2955 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
2957 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
2959 memset(&c, 0, sizeof(c));
2960 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
2961 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2962 V_FW_VI_RXMODE_CMD_VIID(viid));
2963 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2964 c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
2965 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
2966 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
2967 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
2968 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
2969 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
2973 * t4_change_mac - modifies the exact-match filter for a MAC address
2974 * @adap: the adapter
2975 * @mbox: mailbox to use for the FW command
2977 * @idx: index of existing filter for old value of MAC address, or -1
2978 * @addr: the new MAC address value
2979 * @persist: whether a new MAC allocation should be persistent
2980 * @add_smt: if true also add the address to the HW SMT
2982 * Modifies an exact-match filter and sets it to the new MAC address if
2983 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
2984 * latter case the address is added persistently if @persist is %true.
2986 * Note that in general it is not possible to modify the value of a given
2987 * filter so the generic way to modify an address filter is to free the one
2988 * being used by the old address value and allocate a new filter for the
2989 * new address value.
2991 * Returns a negative error number or the index of the filter with the new
2992 * MAC value. Note that this index may differ from @idx.
2994 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
2995 int idx, const u8 *addr, bool persist, bool add_smt)
2998 struct fw_vi_mac_cmd c;
2999 struct fw_vi_mac_exact *p = c.u.exact;
3000 int max_mac_addr = adap->params.arch.mps_tcam_size;
3002 if (idx < 0) /* new allocation */
3003 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3004 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3006 memset(&c, 0, sizeof(c));
3007 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3008 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3009 V_FW_VI_MAC_CMD_VIID(viid));
3010 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3011 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3012 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3013 V_FW_VI_MAC_CMD_IDX(idx));
3014 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3016 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3018 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3019 if (ret >= max_mac_addr)
3026 * t4_enable_vi_params - enable/disable a virtual interface
3027 * @adap: the adapter
3028 * @mbox: mailbox to use for the FW command
3030 * @rx_en: 1=enable Rx, 0=disable Rx
3031 * @tx_en: 1=enable Tx, 0=disable Tx
3032 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3034 * Enables/disables a virtual interface. Note that setting DCB Enable
3035 * only makes sense when enabling a Virtual Interface ...
3037 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3038 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3040 struct fw_vi_enable_cmd c;
3042 memset(&c, 0, sizeof(c));
3043 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3044 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3045 V_FW_VI_ENABLE_CMD_VIID(viid));
3046 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3047 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3048 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3050 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3054 * t4_enable_vi - enable/disable a virtual interface
3055 * @adap: the adapter
3056 * @mbox: mailbox to use for the FW command
3058 * @rx_en: 1=enable Rx, 0=disable Rx
3059 * @tx_en: 1=enable Tx, 0=disable Tx
3061 * Enables/disables a virtual interface. Note that setting DCB Enable
3062 * only makes sense when enabling a Virtual Interface ...
3064 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3065 bool rx_en, bool tx_en)
3067 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3071 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3072 * @adap: the adapter
3073 * @mbox: mailbox to use for the FW command
3074 * @start: %true to enable the queues, %false to disable them
3075 * @pf: the PF owning the queues
3076 * @vf: the VF owning the queues
3077 * @iqid: ingress queue id
3078 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3079 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3081 * Starts or stops an ingress queue and its associated FLs, if any.
3083 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3084 unsigned int pf, unsigned int vf, unsigned int iqid,
3085 unsigned int fl0id, unsigned int fl1id)
3089 memset(&c, 0, sizeof(c));
3090 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3091 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3092 V_FW_IQ_CMD_VFN(vf));
3093 c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
3094 V_FW_IQ_CMD_IQSTOP(!start) |
3096 c.iqid = cpu_to_be16(iqid);
3097 c.fl0id = cpu_to_be16(fl0id);
3098 c.fl1id = cpu_to_be16(fl1id);
3099 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3103 * t4_iq_free - free an ingress queue and its FLs
3104 * @adap: the adapter
3105 * @mbox: mailbox to use for the FW command
3106 * @pf: the PF owning the queues
3107 * @vf: the VF owning the queues
3108 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
3109 * @iqid: ingress queue id
3110 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3111 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3113 * Frees an ingress queue and its associated FLs, if any.
3115 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3116 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3117 unsigned int fl0id, unsigned int fl1id)
3121 memset(&c, 0, sizeof(c));
3122 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3123 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3124 V_FW_IQ_CMD_VFN(vf));
3125 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
3126 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
3127 c.iqid = cpu_to_be16(iqid);
3128 c.fl0id = cpu_to_be16(fl0id);
3129 c.fl1id = cpu_to_be16(fl1id);
3130 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3134 * t4_eth_eq_free - free an Ethernet egress queue
3135 * @adap: the adapter
3136 * @mbox: mailbox to use for the FW command
3137 * @pf: the PF owning the queue
3138 * @vf: the VF owning the queue
3139 * @eqid: egress queue id
3141 * Frees an Ethernet egress queue.
3143 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3144 unsigned int vf, unsigned int eqid)
3146 struct fw_eq_eth_cmd c;
3148 memset(&c, 0, sizeof(c));
3149 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
3150 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3151 V_FW_EQ_ETH_CMD_PFN(pf) |
3152 V_FW_EQ_ETH_CMD_VFN(vf));
3153 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3154 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
3155 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3159 * t4_handle_fw_rpl - process a FW reply message
3160 * @adap: the adapter
3161 * @rpl: start of the FW message
3163 * Processes a FW message, such as link state change messages.
3165 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3167 u8 opcode = *(const u8 *)rpl;
3170 * This might be a port command ... this simplifies the following
3171 * conditionals ... We can get away with pre-dereferencing
3172 * action_to_len16 because it's in the first 16 bytes and all messages
3173 * will be at least that long.
3175 const struct fw_port_cmd *p = (const void *)rpl;
3176 unsigned int action =
3177 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
3179 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
3180 /* link/module state change message */
3181 int speed = 0, fc = 0, i;
3182 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
3183 struct port_info *pi = NULL;
3184 struct link_config *lc;
3185 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
3186 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
3187 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
3189 if (stat & F_FW_PORT_CMD_RXPAUSE)
3191 if (stat & F_FW_PORT_CMD_TXPAUSE)
3193 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3194 speed = ETH_SPEED_NUM_100M;
3195 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3196 speed = ETH_SPEED_NUM_1G;
3197 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3198 speed = ETH_SPEED_NUM_10G;
3199 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
3200 speed = ETH_SPEED_NUM_40G;
3202 for_each_port(adap, i) {
3203 pi = adap2pinfo(adap, i);
3204 if (pi->tx_chan == chan)
3209 if (mod != pi->mod_type) {
3211 t4_os_portmod_changed(adap, i);
3213 if (link_ok != lc->link_ok || speed != lc->speed ||
3214 fc != lc->fc) { /* something changed */
3215 if (!link_ok && lc->link_ok) {
3216 static const char * const reason[] = {
3219 "Auto-negotiation Failure",
3221 "Insufficient Airflow",
3222 "Unable To Determine Reason",
3223 "No RX Signal Detected",
3226 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
3228 dev_warn(adap, "Port %d link down, reason: %s\n",
3231 lc->link_ok = link_ok;
3234 lc->supported = be16_to_cpu(p->u.info.pcap);
3237 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
3243 void t4_reset_link_config(struct adapter *adap, int idx)
3245 struct port_info *pi = adap2pinfo(adap, idx);
3246 struct link_config *lc = &pi->link_cfg;
3249 lc->requested_speed = 0;
3250 lc->requested_fc = 0;
3256 * init_link_config - initialize a link's SW state
3257 * @lc: structure holding the link state
3258 * @caps: link capabilities
3260 * Initializes the SW state maintained for each link, including the link's
3261 * capabilities and default speed/flow-control/autonegotiation settings.
3263 static void init_link_config(struct link_config *lc,
3266 lc->supported = caps;
3267 lc->requested_speed = 0;
3269 lc->requested_fc = 0;
3271 if (lc->supported & FW_PORT_CAP_ANEG) {
3272 lc->advertising = lc->supported & ADVERT_MASK;
3273 lc->autoneg = AUTONEG_ENABLE;
3275 lc->advertising = 0;
3276 lc->autoneg = AUTONEG_DISABLE;
3281 * t4_wait_dev_ready - wait till to reads of registers work
3283 * Right after the device is RESET is can take a small amount of time
3284 * for it to respond to register reads. Until then, all reads will
3285 * return either 0xff...ff or 0xee...ee. Return an error if reads
3286 * don't work within a reasonable time frame.
3288 static int t4_wait_dev_ready(struct adapter *adapter)
3292 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3294 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
3298 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3299 return (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS
3304 u32 vendor_and_model_id;
3308 int t4_get_flash_params(struct adapter *adapter)
3311 * Table for non-Numonix supported flash parts. Numonix parts are left
3312 * to the preexisting well-tested code. All flash parts have 64KB
3315 static struct flash_desc supported_flash[] = {
3316 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
3323 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
3325 ret = sf1_read(adapter, 3, 0, 1, &info);
3326 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3330 for (i = 0; i < ARRAY_SIZE(supported_flash); ++i)
3331 if (supported_flash[i].vendor_and_model_id == info) {
3332 adapter->params.sf_size = supported_flash[i].size_mb;
3333 adapter->params.sf_nsec =
3334 adapter->params.sf_size / SF_SEC_SIZE;
3338 if ((info & 0xff) != 0x20) /* not a Numonix flash */
3340 info >>= 16; /* log2 of size */
3341 if (info >= 0x14 && info < 0x18)
3342 adapter->params.sf_nsec = 1 << (info - 16);
3343 else if (info == 0x18)
3344 adapter->params.sf_nsec = 64;
3347 adapter->params.sf_size = 1 << info;
3350 * We should reject adapters with FLASHes which are too small. So, emit
3353 if (adapter->params.sf_size < FLASH_MIN_SIZE) {
3354 dev_warn(adapter, "WARNING!!! FLASH size %#x < %#x!!!\n",
3355 adapter->params.sf_size, FLASH_MIN_SIZE);
3361 static void set_pcie_completion_timeout(struct adapter *adapter,
3367 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
3369 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
3372 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
3377 * t4_get_chip_type - Determine chip type from device ID
3378 * @adap: the adapter
3379 * @ver: adapter version
3381 int t4_get_chip_type(struct adapter *adap, int ver)
3383 enum chip_type chip = 0;
3384 u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
3386 /* Retrieve adapter's device ID */
3389 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3392 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
3395 dev_err(adap, "Device %d is not supported\n",
3396 adap->params.pci.device_id);
3404 * t4_prep_adapter - prepare SW and HW for operation
3405 * @adapter: the adapter
3407 * Initialize adapter SW state for the various HW modules, set initial
3408 * values for some adapter tunables, take PHYs out of reset, and
3409 * initialize the MDIO interface.
3411 int t4_prep_adapter(struct adapter *adapter)
3416 ret = t4_wait_dev_ready(adapter);
3420 pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
3421 adapter->params.pci.device_id = adapter->pdev->id.device_id;
3422 adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
3425 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
3426 * ADAPTER (VERSION << 4 | REVISION)
3428 ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
3429 adapter->params.chip = 0;
3432 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3433 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
3434 adapter->params.arch.mps_tcam_size =
3435 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3436 adapter->params.arch.mps_rplc_size = 128;
3437 adapter->params.arch.nchan = NCHAN;
3438 adapter->params.arch.vfcount = 128;
3441 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
3442 adapter->params.arch.sge_fl_db = 0;
3443 adapter->params.arch.mps_tcam_size =
3444 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3445 adapter->params.arch.mps_rplc_size = 256;
3446 adapter->params.arch.nchan = 2;
3447 adapter->params.arch.vfcount = 256;
3450 dev_err(adapter, "%s: Device %d is not supported\n",
3451 __func__, adapter->params.pci.device_id);
3455 adapter->params.pci.vpd_cap_addr =
3456 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
3458 ret = t4_get_flash_params(adapter);
3462 adapter->params.cim_la_size = CIMLA_SIZE;
3464 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3467 * Default port and clock for debugging in case we can't reach FW.
3469 adapter->params.nports = 1;
3470 adapter->params.portvec = 1;
3471 adapter->params.vpd.cclk = 50000;
3473 /* Set pci completion timeout value to 4 seconds. */
3474 set_pcie_completion_timeout(adapter, 0xd);
3479 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
3480 * @adapter: the adapter
3481 * @qid: the Queue ID
3482 * @qtype: the Ingress or Egress type for @qid
3483 * @pbar2_qoffset: BAR2 Queue Offset
3484 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
3486 * Returns the BAR2 SGE Queue Registers information associated with the
3487 * indicated Absolute Queue ID. These are passed back in return value
3488 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
3489 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
3491 * This may return an error which indicates that BAR2 SGE Queue
3492 * registers aren't available. If an error is not returned, then the
3493 * following values are returned:
3495 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
3496 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
3498 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
3499 * require the "Inferred Queue ID" ability may be used. E.g. the
3500 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
3501 * then these "Inferred Queue ID" register may not be used.
3503 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
3504 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
3505 unsigned int *pbar2_qid)
3507 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
3508 u64 bar2_page_offset, bar2_qoffset;
3509 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
3512 * T4 doesn't support BAR2 SGE Queue registers.
3514 if (is_t4(adapter->params.chip))
3518 * Get our SGE Page Size parameters.
3520 page_shift = adapter->params.sge.hps + 10;
3521 page_size = 1 << page_shift;
3524 * Get the right Queues per Page parameters for our Queue.
3526 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
3527 adapter->params.sge.eq_qpp :
3528 adapter->params.sge.iq_qpp);
3529 qpp_mask = (1 << qpp_shift) - 1;
3532 * Calculate the basics of the BAR2 SGE Queue register area:
3533 * o The BAR2 page the Queue registers will be in.
3534 * o The BAR2 Queue ID.
3535 * o The BAR2 Queue ID Offset into the BAR2 page.
3537 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
3538 bar2_qid = qid & qpp_mask;
3539 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
3542 * If the BAR2 Queue ID Offset is less than the Page Size, then the
3543 * hardware will infer the Absolute Queue ID simply from the writes to
3544 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
3545 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
3546 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
3547 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
3548 * from the BAR2 Page and BAR2 Queue ID.
3550 * One important censequence of this is that some BAR2 SGE registers
3551 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
3552 * there. But other registers synthesize the SGE Queue ID purely
3553 * from the writes to the registers -- the Write Combined Doorbell
3554 * Buffer is a good example. These BAR2 SGE Registers are only
3555 * available for those BAR2 SGE Register areas where the SGE Absolute
3556 * Queue ID can be inferred from simple writes.
3558 bar2_qoffset = bar2_page_offset;
3559 bar2_qinferred = (bar2_qid_offset < page_size);
3560 if (bar2_qinferred) {
3561 bar2_qoffset += bar2_qid_offset;
3565 *pbar2_qoffset = bar2_qoffset;
3566 *pbar2_qid = bar2_qid;
3571 * t4_init_sge_params - initialize adap->params.sge
3572 * @adapter: the adapter
3574 * Initialize various fields of the adapter's SGE Parameters structure.
3576 int t4_init_sge_params(struct adapter *adapter)
3578 struct sge_params *sge_params = &adapter->params.sge;
3580 unsigned int s_hps, s_qpp;
3583 * Extract the SGE Page Size for our PF.
3585 hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
3586 s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
3588 sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
3591 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
3593 s_qpp = (S_QUEUESPERPAGEPF0 +
3594 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
3595 qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
3596 sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
3597 qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
3598 sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
3604 * t4_init_tp_params - initialize adap->params.tp
3605 * @adap: the adapter
3607 * Initialize various fields of the adapter's TP Parameters structure.
3609 int t4_init_tp_params(struct adapter *adap)
3614 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
3615 adap->params.tp.tre = G_TIMERRESOLUTION(v);
3616 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
3618 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
3619 for (chan = 0; chan < NCHAN; chan++)
3620 adap->params.tp.tx_modq[chan] = chan;
3623 * Cache the adapter's Compressed Filter Mode and global Incress
3626 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
3627 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
3628 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
3629 &adap->params.tp.ingress_config, 1,
3630 A_TP_INGRESS_CONFIG);
3633 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
3634 * shift positions of several elements of the Compressed Filter Tuple
3635 * for this adapter which we need frequently ...
3637 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
3638 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
3639 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
3640 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
3644 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
3645 * represents the presense of an Outer VLAN instead of a VNIC ID.
3647 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
3648 adap->params.tp.vnic_shift = -1;
3654 * t4_filter_field_shift - calculate filter field shift
3655 * @adap: the adapter
3656 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
3658 * Return the shift position of a filter field within the Compressed
3659 * Filter Tuple. The filter field is specified via its selection bit
3660 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
3662 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
3664 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
3668 if ((filter_mode & filter_sel) == 0)
3671 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
3672 switch (filter_mode & sel) {
3674 field_shift += W_FT_FCOE;
3677 field_shift += W_FT_PORT;
3680 field_shift += W_FT_VNIC_ID;
3683 field_shift += W_FT_VLAN;
3686 field_shift += W_FT_TOS;
3689 field_shift += W_FT_PROTOCOL;
3692 field_shift += W_FT_ETHERTYPE;
3695 field_shift += W_FT_MACMATCH;
3698 field_shift += W_FT_MPSHITTYPE;
3700 case F_FRAGMENTATION:
3701 field_shift += W_FT_FRAGMENTATION;
3708 int t4_init_rss_mode(struct adapter *adap, int mbox)
3711 struct fw_rss_vi_config_cmd rvc;
3713 memset(&rvc, 0, sizeof(rvc));
3715 for_each_port(adap, i) {
3716 struct port_info *p = adap2pinfo(adap, i);
3718 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
3719 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3720 V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
3721 rvc.retval_len16 = htonl(FW_LEN16(rvc));
3722 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
3725 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
3730 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
3734 struct fw_port_cmd c;
3736 memset(&c, 0, sizeof(c));
3738 for_each_port(adap, i) {
3739 unsigned int rss_size = 0;
3740 struct port_info *p = adap2pinfo(adap, i);
3742 while ((adap->params.portvec & (1 << j)) == 0)
3745 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3746 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3747 V_FW_PORT_CMD_PORTID(j));
3748 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
3749 FW_PORT_ACTION_GET_PORT_INFO) |
3751 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3755 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
3761 p->rss_size = rss_size;
3762 t4_os_set_hw_addr(adap, i, addr);
3764 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
3765 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
3766 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
3767 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
3768 p->mod_type = FW_PORT_MOD_TYPE_NA;
3770 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));