4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <netinet/in.h>
36 #include <rte_interrupts.h>
38 #include <rte_debug.h>
40 #include <rte_atomic.h>
41 #include <rte_branch_prediction.h>
42 #include <rte_memory.h>
43 #include <rte_tailq.h>
45 #include <rte_alarm.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev_driver.h>
48 #include <rte_malloc.h>
49 #include <rte_random.h>
51 #include <rte_byteorder.h>
55 #include "t4_regs_values.h"
56 #include "t4fw_interface.h"
58 static void init_link_config(struct link_config *lc, unsigned int pcaps,
62 * t4_read_mtu_tbl - returns the values in the HW path MTU table
64 * @mtus: where to store the MTU values
65 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
67 * Reads the HW path MTU table.
69 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
74 for (i = 0; i < NMTUS; ++i) {
75 t4_write_reg(adap, A_TP_MTU_TABLE,
76 V_MTUINDEX(0xff) | V_MTUVALUE(i));
77 v = t4_read_reg(adap, A_TP_MTU_TABLE);
78 mtus[i] = G_MTUVALUE(v);
80 mtu_log[i] = G_MTUWIDTH(v);
85 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
87 * @addr: the indirect TP register address
88 * @mask: specifies the field within the register to modify
89 * @val: new value for the field
91 * Sets a field of an indirect TP register to the given value.
93 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
94 unsigned int mask, unsigned int val)
96 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
97 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
98 t4_write_reg(adap, A_TP_PIO_DATA, val);
101 /* The minimum additive increment value for the congestion control table */
102 #define CC_MIN_INCR 2U
105 * t4_load_mtus - write the MTU and congestion control HW tables
107 * @mtus: the values for the MTU table
108 * @alpha: the values for the congestion control alpha parameter
109 * @beta: the values for the congestion control beta parameter
111 * Write the HW MTU table with the supplied MTUs and the high-speed
112 * congestion control table with the supplied alpha, beta, and MTUs.
113 * We write the two tables together because the additive increments
114 * depend on the MTUs.
116 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
117 const unsigned short *alpha, const unsigned short *beta)
119 static const unsigned int avg_pkts[NCCTRL_WIN] = {
120 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
121 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
122 28672, 40960, 57344, 81920, 114688, 163840, 229376
127 for (i = 0; i < NMTUS; ++i) {
128 unsigned int mtu = mtus[i];
129 unsigned int log2 = cxgbe_fls(mtu);
131 if (!(mtu & ((1 << log2) >> 2))) /* round */
133 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
134 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
136 for (w = 0; w < NCCTRL_WIN; ++w) {
139 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
142 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
143 (w << 16) | (beta[w] << 13) | inc);
149 * t4_wait_op_done_val - wait until an operation is completed
150 * @adapter: the adapter performing the operation
151 * @reg: the register to check for completion
152 * @mask: a single-bit field within @reg that indicates completion
153 * @polarity: the value of the field when the operation is completed
154 * @attempts: number of check iterations
155 * @delay: delay in usecs between iterations
156 * @valp: where to store the value of the register at completion time
158 * Wait until an operation is completed by checking a bit in a register
159 * up to @attempts times. If @valp is not NULL the value of the register
160 * at the time it indicated completion is stored there. Returns 0 if the
161 * operation completes and -EAGAIN otherwise.
163 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
164 int polarity, int attempts, int delay, u32 *valp)
167 u32 val = t4_read_reg(adapter, reg);
169 if (!!(val & mask) == polarity) {
182 * t4_set_reg_field - set a register field to a value
183 * @adapter: the adapter to program
184 * @addr: the register address
185 * @mask: specifies the portion of the register to modify
186 * @val: the new value for the register field
188 * Sets a register field specified by the supplied mask to the
191 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
194 u32 v = t4_read_reg(adapter, addr) & ~mask;
196 t4_write_reg(adapter, addr, v | val);
197 (void)t4_read_reg(adapter, addr); /* flush */
201 * t4_read_indirect - read indirectly addressed registers
203 * @addr_reg: register holding the indirect address
204 * @data_reg: register holding the value of the indirect register
205 * @vals: where the read register values are stored
206 * @nregs: how many indirect registers to read
207 * @start_idx: index of first indirect register to read
209 * Reads registers that are accessed indirectly through an address/data
212 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
213 unsigned int data_reg, u32 *vals, unsigned int nregs,
214 unsigned int start_idx)
217 t4_write_reg(adap, addr_reg, start_idx);
218 *vals++ = t4_read_reg(adap, data_reg);
224 * t4_write_indirect - write indirectly addressed registers
226 * @addr_reg: register holding the indirect addresses
227 * @data_reg: register holding the value for the indirect registers
228 * @vals: values to write
229 * @nregs: how many indirect registers to write
230 * @start_idx: address of first indirect register to write
232 * Writes a sequential block of registers that are accessed indirectly
233 * through an address/data register pair.
235 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
236 unsigned int data_reg, const u32 *vals,
237 unsigned int nregs, unsigned int start_idx)
240 t4_write_reg(adap, addr_reg, start_idx++);
241 t4_write_reg(adap, data_reg, *vals++);
246 * t4_report_fw_error - report firmware error
249 * The adapter firmware can indicate error conditions to the host.
250 * If the firmware has indicated an error, print out the reason for
251 * the firmware error.
253 static void t4_report_fw_error(struct adapter *adap)
255 static const char * const reason[] = {
256 "Crash", /* PCIE_FW_EVAL_CRASH */
257 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
258 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
259 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
260 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
261 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
262 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
263 "Reserved", /* reserved */
267 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
268 if (pcie_fw & F_PCIE_FW_ERR)
269 pr_err("%s: Firmware reports adapter error: %s\n",
270 __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
274 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
276 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
279 for ( ; nflit; nflit--, mbox_addr += 8)
280 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
284 * Handle a FW assertion reported in a mailbox.
286 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
288 struct fw_debug_cmd asrt;
290 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
291 pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
292 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
293 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
296 #define X_CIM_PF_NOACCESS 0xeeeeeeee
299 * If the Host OS Driver needs locking arround accesses to the mailbox, this
300 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
302 /* makes single-statement usage a bit cleaner ... */
303 #ifdef T4_OS_NEEDS_MBOX_LOCKING
304 #define T4_OS_MBOX_LOCKING(x) x
306 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
310 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
312 * @mbox: index of the mailbox to use
313 * @cmd: the command to write
314 * @size: command length in bytes
315 * @rpl: where to optionally store the reply
316 * @sleep_ok: if true we may sleep while awaiting command completion
317 * @timeout: time to wait for command to finish before timing out
318 * (negative implies @sleep_ok=false)
320 * Sends the given command to FW through the selected mailbox and waits
321 * for the FW to execute the command. If @rpl is not %NULL it is used to
322 * store the FW's reply to the command. The command and its optional
323 * reply are of the same length. Some FW commands like RESET and
324 * INITIALIZE can take a considerable amount of time to execute.
325 * @sleep_ok determines whether we may sleep while awaiting the response.
326 * If sleeping is allowed we use progressive backoff otherwise we spin.
327 * Note that passing in a negative @timeout is an alternate mechanism
328 * for specifying @sleep_ok=false. This is useful when a higher level
329 * interface allows for specification of @timeout but not @sleep_ok ...
331 * Returns 0 on success or a negative errno on failure. A
332 * failure can happen either because we are not able to execute the
333 * command or FW executes it but signals an error. In the latter case
334 * the return value is the error code indicated by FW (negated).
336 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
337 const void __attribute__((__may_alias__)) *cmd,
338 int size, void *rpl, bool sleep_ok, int timeout)
341 * We delay in small increments at first in an effort to maintain
342 * responsiveness for simple, fast executing commands but then back
343 * off to larger delays to a maximum retry delay.
345 static const int delay[] = {
346 1, 1, 3, 5, 10, 10, 20, 50, 100
352 unsigned int delay_idx;
353 __be64 *temp = (__be64 *)malloc(size * sizeof(char));
355 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
356 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
358 struct mbox_entry entry;
364 if ((size & 15) || size > MBOX_LEN) {
370 memcpy(p, (const __be64 *)cmd, size);
373 * If we have a negative timeout, that implies that we can't sleep.
380 #ifdef T4_OS_NEEDS_MBOX_LOCKING
382 * Queue ourselves onto the mailbox access list. When our entry is at
383 * the front of the list, we have rights to access the mailbox. So we
384 * wait [for a while] till we're at the front [or bail out with an
387 t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
392 for (i = 0; ; i += ms) {
394 * If we've waited too long, return a busy indication. This
395 * really ought to be based on our initial position in the
396 * mailbox access list but this is a start. We very rarely
397 * contend on access to the mailbox ... Also check for a
398 * firmware error which we'll report as a device error.
400 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
401 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
402 t4_os_atomic_list_del(&entry, &adap->mbox_list,
404 t4_report_fw_error(adap);
406 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
410 * If we're at the head, break out and start the mailbox
413 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
417 * Delay for a bit before checking again ...
420 ms = delay[delay_idx]; /* last element may repeat */
421 if (delay_idx < ARRAY_SIZE(delay) - 1)
428 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
431 * Attempt to gain access to the mailbox.
433 for (i = 0; i < 4; i++) {
434 ctl = t4_read_reg(adap, ctl_reg);
436 if (v != X_MBOWNER_NONE)
441 * If we were unable to gain access, dequeue ourselves from the
442 * mailbox atomic access list and report the error to our caller.
444 if (v != X_MBOWNER_PL) {
445 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
448 t4_report_fw_error(adap);
450 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
454 * If we gain ownership of the mailbox and there's a "valid" message
455 * in it, this is likely an asynchronous error message from the
456 * firmware. So we'll report that and then proceed on with attempting
457 * to issue our own command ... which may well fail if the error
458 * presaged the firmware crashing ...
460 if (ctl & F_MBMSGVALID) {
461 dev_err(adap, "found VALID command in mbox %u: "
462 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
463 (unsigned long long)t4_read_reg64(adap, data_reg),
464 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
465 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
466 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
467 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
468 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
469 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
470 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
474 * Copy in the new mailbox command and send it on its way ...
476 for (i = 0; i < size; i += 8, p++)
477 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
479 CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
480 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
481 (unsigned long long)t4_read_reg64(adap, data_reg),
482 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
483 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
484 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
485 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
486 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
487 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
488 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
490 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
491 t4_read_reg(adap, ctl_reg); /* flush write */
497 * Loop waiting for the reply; bail out if we time out or the firmware
500 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
501 for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
503 ms = delay[delay_idx]; /* last element may repeat */
504 if (delay_idx < ARRAY_SIZE(delay) - 1)
511 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
512 v = t4_read_reg(adap, ctl_reg);
513 if (v == X_CIM_PF_NOACCESS)
515 if (G_MBOWNER(v) == X_MBOWNER_PL) {
516 if (!(v & F_MBMSGVALID)) {
517 t4_write_reg(adap, ctl_reg,
518 V_MBOWNER(X_MBOWNER_NONE));
522 CXGBE_DEBUG_MBOX(adap,
523 "%s: mbox %u: %016llx %016llx %016llx %016llx "
524 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
525 (unsigned long long)t4_read_reg64(adap, data_reg),
526 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
527 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
528 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
529 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
530 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
531 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
532 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
534 CXGBE_DEBUG_MBOX(adap,
535 "command %#x completed in %d ms (%ssleeping)\n",
537 i + ms, sleep_ok ? "" : "non-");
539 res = t4_read_reg64(adap, data_reg);
540 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
541 fw_asrt(adap, data_reg);
542 res = V_FW_CMD_RETVAL(EIO);
544 get_mbox_rpl(adap, rpl, size / 8, data_reg);
546 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
548 t4_os_atomic_list_del(&entry, &adap->mbox_list,
551 return -G_FW_CMD_RETVAL((int)res);
556 * We timed out waiting for a reply to our mailbox command. Report
557 * the error and also check to see if the firmware reported any
560 dev_err(adap, "command %#x in mailbox %d timed out\n",
561 *(const u8 *)cmd, mbox);
562 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
565 t4_report_fw_error(adap);
567 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
570 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
571 void *rpl, bool sleep_ok)
573 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
578 * t4_get_regs_len - return the size of the chips register set
579 * @adapter: the adapter
581 * Returns the size of the chip's BAR0 register space.
583 unsigned int t4_get_regs_len(struct adapter *adapter)
585 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
587 switch (chip_version) {
590 return T5_REGMAP_SIZE;
594 "Unsupported chip version %d\n", chip_version);
599 * t4_get_regs - read chip registers into provided buffer
601 * @buf: register buffer
602 * @buf_size: size (in bytes) of register buffer
604 * If the provided register buffer isn't large enough for the chip's
605 * full register range, the register dump will be truncated to the
606 * register buffer's size.
608 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
610 static const unsigned int t5_reg_ranges[] = {
1385 static const unsigned int t6_reg_ranges[] = {
1946 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1947 const unsigned int *reg_ranges;
1948 int reg_ranges_size, range;
1949 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1951 /* Select the right set of register ranges to dump depending on the
1952 * adapter chip type.
1954 switch (chip_version) {
1956 reg_ranges = t5_reg_ranges;
1957 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1961 reg_ranges = t6_reg_ranges;
1962 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1967 "Unsupported chip version %d\n", chip_version);
1971 /* Clear the register buffer and insert the appropriate register
1972 * values selected by the above register ranges.
1974 memset(buf, 0, buf_size);
1975 for (range = 0; range < reg_ranges_size; range += 2) {
1976 unsigned int reg = reg_ranges[range];
1977 unsigned int last_reg = reg_ranges[range + 1];
1978 u32 *bufp = (u32 *)((char *)buf + reg);
1980 /* Iterate across the register range filling in the register
1981 * buffer but don't write past the end of the register buffer.
1983 while (reg <= last_reg && bufp < buf_end) {
1984 *bufp++ = t4_read_reg(adap, reg);
1990 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1991 #define EEPROM_DELAY 10 /* 10us per poll spin */
1992 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
1994 #define EEPROM_STAT_ADDR 0x7bfc
1997 * Small utility function to wait till any outstanding VPD Access is complete.
1998 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1999 * VPD Access in flight. This allows us to handle the problem of having a
2000 * previous VPD Access time out and prevent an attempt to inject a new VPD
2001 * Request before any in-flight VPD request has completed.
2003 static int t4_seeprom_wait(struct adapter *adapter)
2005 unsigned int base = adapter->params.pci.vpd_cap_addr;
2008 /* If no VPD Access is in flight, we can just return success right
2011 if (!adapter->vpd_busy)
2014 /* Poll the VPD Capability Address/Flag register waiting for it
2015 * to indicate that the operation is complete.
2017 max_poll = EEPROM_MAX_POLL;
2021 udelay(EEPROM_DELAY);
2022 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2024 /* If the operation is complete, mark the VPD as no longer
2025 * busy and return success.
2027 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2028 adapter->vpd_busy = 0;
2031 } while (--max_poll);
2033 /* Failure! Note that we leave the VPD Busy status set in order to
2034 * avoid pushing a new VPD Access request into the VPD Capability till
2035 * the current operation eventually succeeds. It's a bug to issue a
2036 * new request when an existing request is in flight and will result
2037 * in corrupt hardware state.
2043 * t4_seeprom_read - read a serial EEPROM location
2044 * @adapter: adapter to read
2045 * @addr: EEPROM virtual address
2046 * @data: where to store the read data
2048 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2049 * VPD capability. Note that this function must be called with a virtual
2052 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2054 unsigned int base = adapter->params.pci.vpd_cap_addr;
2057 /* VPD Accesses must alway be 4-byte aligned!
2059 if (addr >= EEPROMVSIZE || (addr & 3))
2062 /* Wait for any previous operation which may still be in flight to
2065 ret = t4_seeprom_wait(adapter);
2067 dev_err(adapter, "VPD still busy from previous operation\n");
2071 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2072 * for our request to complete. If it doesn't complete, note the
2073 * error and return it to our caller. Note that we do not reset the
2076 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2077 adapter->vpd_busy = 1;
2078 adapter->vpd_flag = PCI_VPD_ADDR_F;
2079 ret = t4_seeprom_wait(adapter);
2081 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2085 /* Grab the returned data, swizzle it into our endianness and
2088 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2089 *data = le32_to_cpu(*data);
2094 * t4_seeprom_write - write a serial EEPROM location
2095 * @adapter: adapter to write
2096 * @addr: virtual EEPROM address
2097 * @data: value to write
2099 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2100 * VPD capability. Note that this function must be called with a virtual
2103 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2105 unsigned int base = adapter->params.pci.vpd_cap_addr;
2110 /* VPD Accesses must alway be 4-byte aligned!
2112 if (addr >= EEPROMVSIZE || (addr & 3))
2115 /* Wait for any previous operation which may still be in flight to
2118 ret = t4_seeprom_wait(adapter);
2120 dev_err(adapter, "VPD still busy from previous operation\n");
2124 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2125 * for our request to complete. If it doesn't complete, note the
2126 * error and return it to our caller. Note that we do not reset the
2129 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2131 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2132 (u16)addr | PCI_VPD_ADDR_F);
2133 adapter->vpd_busy = 1;
2134 adapter->vpd_flag = 0;
2135 ret = t4_seeprom_wait(adapter);
2137 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2141 /* Reset PCI_VPD_DATA register after a transaction and wait for our
2142 * request to complete. If it doesn't complete, return error.
2144 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2145 max_poll = EEPROM_MAX_POLL;
2147 udelay(EEPROM_DELAY);
2148 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2149 } while ((stats_reg & 0x1) && --max_poll);
2153 /* Return success! */
2158 * t4_seeprom_wp - enable/disable EEPROM write protection
2159 * @adapter: the adapter
2160 * @enable: whether to enable or disable write protection
2162 * Enables or disables write protection on the serial EEPROM.
2164 int t4_seeprom_wp(struct adapter *adapter, int enable)
2166 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2170 * t4_fw_tp_pio_rw - Access TP PIO through LDST
2171 * @adap: the adapter
2172 * @vals: where the indirect register values are stored/written
2173 * @nregs: how many indirect registers to read/write
2174 * @start_idx: index of first indirect register to read/write
2175 * @rw: Read (1) or Write (0)
2177 * Access TP PIO registers through LDST
2179 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
2180 unsigned int start_index, unsigned int rw)
2182 int cmd = FW_LDST_ADDRSPC_TP_PIO;
2183 struct fw_ldst_cmd c;
2187 for (i = 0 ; i < nregs; i++) {
2188 memset(&c, 0, sizeof(c));
2189 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
2191 (rw ? F_FW_CMD_READ :
2193 V_FW_LDST_CMD_ADDRSPACE(cmd));
2194 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
2196 c.u.addrval.addr = cpu_to_be32(start_index + i);
2197 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
2198 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2201 vals[i] = be32_to_cpu(c.u.addrval.val);
2207 * t4_read_rss_key - read the global RSS key
2208 * @adap: the adapter
2209 * @key: 10-entry array holding the 320-bit RSS key
2211 * Reads the global 320-bit RSS key.
2213 void t4_read_rss_key(struct adapter *adap, u32 *key)
2215 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 1);
2219 * t4_write_rss_key - program one of the RSS keys
2220 * @adap: the adapter
2221 * @key: 10-entry array holding the 320-bit RSS key
2222 * @idx: which RSS key to write
2224 * Writes one of the RSS keys with the given 320-bit value. If @idx is
2225 * 0..15 the corresponding entry in the RSS key table is written,
2226 * otherwise the global RSS key is written.
2228 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
2230 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
2231 u8 rss_key_addr_cnt = 16;
2233 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
2234 * allows access to key addresses 16-63 by using KeyWrAddrX
2235 * as index[5:4](upper 2) into key table
2237 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
2238 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
2239 rss_key_addr_cnt = 32;
2241 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
2243 if (idx >= 0 && idx < rss_key_addr_cnt) {
2244 if (rss_key_addr_cnt > 16)
2245 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2246 V_KEYWRADDRX(idx >> 4) |
2247 V_T6_VFWRADDR(idx) | F_KEYWREN);
2249 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2250 V_KEYWRADDR(idx) | F_KEYWREN);
2255 * t4_config_rss_range - configure a portion of the RSS mapping table
2256 * @adapter: the adapter
2257 * @mbox: mbox to use for the FW command
2258 * @viid: virtual interface whose RSS subtable is to be written
2259 * @start: start entry in the table to write
2260 * @n: how many table entries to write
2261 * @rspq: values for the "response queue" (Ingress Queue) lookup table
2262 * @nrspq: number of values in @rspq
2264 * Programs the selected part of the VI's RSS mapping table with the
2265 * provided values. If @nrspq < @n the supplied values are used repeatedly
2266 * until the full table range is populated.
2268 * The caller must ensure the values in @rspq are in the range allowed for
2271 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2272 int start, int n, const u16 *rspq, unsigned int nrspq)
2275 const u16 *rsp = rspq;
2276 const u16 *rsp_end = rspq + nrspq;
2277 struct fw_rss_ind_tbl_cmd cmd;
2279 memset(&cmd, 0, sizeof(cmd));
2280 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2281 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2282 V_FW_RSS_IND_TBL_CMD_VIID(viid));
2283 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2286 * Each firmware RSS command can accommodate up to 32 RSS Ingress
2287 * Queue Identifiers. These Ingress Queue IDs are packed three to
2288 * a 32-bit word as 10-bit values with the upper remaining 2 bits
2292 int nq = min(n, 32);
2294 __be32 *qp = &cmd.iq0_to_iq2;
2297 * Set up the firmware RSS command header to send the next
2298 * "nq" Ingress Queue IDs to the firmware.
2300 cmd.niqid = cpu_to_be16(nq);
2301 cmd.startidx = cpu_to_be16(start);
2304 * "nq" more done for the start of the next loop.
2310 * While there are still Ingress Queue IDs to stuff into the
2311 * current firmware RSS command, retrieve them from the
2312 * Ingress Queue ID array and insert them into the command.
2316 * Grab up to the next 3 Ingress Queue IDs (wrapping
2317 * around the Ingress Queue ID array if necessary) and
2318 * insert them into the firmware RSS command at the
2319 * current 3-tuple position within the commad.
2323 int nqbuf = min(3, nq);
2329 while (nqbuf && nq_packed < 32) {
2336 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2337 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2338 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2342 * Send this portion of the RRS table update to the firmware;
2343 * bail out on any errors.
2345 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2354 * t4_config_vi_rss - configure per VI RSS settings
2355 * @adapter: the adapter
2356 * @mbox: mbox to use for the FW command
2359 * @defq: id of the default RSS queue for the VI.
2361 * Configures VI-specific RSS properties.
2363 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2364 unsigned int flags, unsigned int defq)
2366 struct fw_rss_vi_config_cmd c;
2368 memset(&c, 0, sizeof(c));
2369 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2370 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2371 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2372 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2373 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2374 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2375 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2379 * t4_read_config_vi_rss - read the configured per VI RSS settings
2380 * @adapter: the adapter
2381 * @mbox: mbox to use for the FW command
2383 * @flags: where to place the configured flags
2384 * @defq: where to place the id of the default RSS queue for the VI.
2386 * Read configured VI-specific RSS properties.
2388 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2389 u64 *flags, unsigned int *defq)
2391 struct fw_rss_vi_config_cmd c;
2392 unsigned int result;
2395 memset(&c, 0, sizeof(c));
2396 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2397 F_FW_CMD_REQUEST | F_FW_CMD_READ |
2398 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2399 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2400 ret = t4_wr_mbox(adapter, mbox, &c, sizeof(c), &c);
2402 result = be32_to_cpu(c.u.basicvirtual.defaultq_to_udpen);
2404 *defq = G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(result);
2406 *flags = result & M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ;
2413 * init_cong_ctrl - initialize congestion control parameters
2414 * @a: the alpha values for congestion control
2415 * @b: the beta values for congestion control
2417 * Initialize the congestion control parameters.
2419 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2423 for (i = 0; i < 9; i++) {
2477 #define INIT_CMD(var, cmd, rd_wr) do { \
2478 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2479 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2480 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2483 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2485 u32 cclk_param, cclk_val;
2489 * Ask firmware for the Core Clock since it knows how to translate the
2490 * Reference Clock ('V2') VPD field into a Core Clock value ...
2492 cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2493 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2494 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2495 1, &cclk_param, &cclk_val);
2497 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2503 dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2507 /* serial flash and firmware constants and flash config file constants */
2509 SF_ATTEMPTS = 10, /* max retries for SF operations */
2511 /* flash command opcodes */
2512 SF_PROG_PAGE = 2, /* program page */
2513 SF_WR_DISABLE = 4, /* disable writes */
2514 SF_RD_STATUS = 5, /* read status register */
2515 SF_WR_ENABLE = 6, /* enable writes */
2516 SF_RD_DATA_FAST = 0xb, /* read flash */
2517 SF_RD_ID = 0x9f, /* read ID */
2518 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2522 * sf1_read - read data from the serial flash
2523 * @adapter: the adapter
2524 * @byte_cnt: number of bytes to read
2525 * @cont: whether another operation will be chained
2526 * @lock: whether to lock SF for PL access only
2527 * @valp: where to store the read data
2529 * Reads up to 4 bytes of data from the serial flash. The location of
2530 * the read needs to be specified prior to calling this by issuing the
2531 * appropriate commands to the serial flash.
2533 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2534 int lock, u32 *valp)
2538 if (!byte_cnt || byte_cnt > 4)
2540 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2542 t4_write_reg(adapter, A_SF_OP,
2543 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2544 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2546 *valp = t4_read_reg(adapter, A_SF_DATA);
2551 * sf1_write - write data to the serial flash
2552 * @adapter: the adapter
2553 * @byte_cnt: number of bytes to write
2554 * @cont: whether another operation will be chained
2555 * @lock: whether to lock SF for PL access only
2556 * @val: value to write
2558 * Writes up to 4 bytes of data to the serial flash. The location of
2559 * the write needs to be specified prior to calling this by issuing the
2560 * appropriate commands to the serial flash.
2562 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2565 if (!byte_cnt || byte_cnt > 4)
2567 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2569 t4_write_reg(adapter, A_SF_DATA, val);
2570 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2571 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2572 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2576 * t4_read_flash - read words from serial flash
2577 * @adapter: the adapter
2578 * @addr: the start address for the read
2579 * @nwords: how many 32-bit words to read
2580 * @data: where to store the read data
2581 * @byte_oriented: whether to store data as bytes or as words
2583 * Read the specified number of 32-bit words from the serial flash.
2584 * If @byte_oriented is set the read data is stored as a byte array
2585 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2586 * natural endianness.
2588 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2589 unsigned int nwords, u32 *data, int byte_oriented)
2593 if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2597 addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2599 ret = sf1_write(adapter, 4, 1, 0, addr);
2603 ret = sf1_read(adapter, 1, 1, 0, data);
2607 for ( ; nwords; nwords--, data++) {
2608 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2610 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
2614 *data = cpu_to_be32(*data);
2620 * t4_get_exprom_version - return the Expansion ROM version (if any)
2621 * @adapter: the adapter
2622 * @vers: where to place the version
2624 * Reads the Expansion ROM header from FLASH and returns the version
2625 * number (if present) through the @vers return value pointer. We return
2626 * this in the Firmware Version Format since it's convenient. Return
2627 * 0 on success, -ENOENT if no Expansion ROM is present.
2629 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2631 struct exprom_header {
2632 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2633 unsigned char hdr_ver[4]; /* Expansion ROM version */
2635 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2639 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2640 ARRAY_SIZE(exprom_header_buf),
2641 exprom_header_buf, 0);
2645 hdr = (struct exprom_header *)exprom_header_buf;
2646 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2649 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2650 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2651 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2652 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2657 * t4_get_fw_version - read the firmware version
2658 * @adapter: the adapter
2659 * @vers: where to place the version
2661 * Reads the FW version from flash.
2663 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2665 return t4_read_flash(adapter, FLASH_FW_START +
2666 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2670 * t4_get_bs_version - read the firmware bootstrap version
2671 * @adapter: the adapter
2672 * @vers: where to place the version
2674 * Reads the FW Bootstrap version from flash.
2676 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2678 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2679 offsetof(struct fw_hdr, fw_ver), 1,
2684 * t4_get_tp_version - read the TP microcode version
2685 * @adapter: the adapter
2686 * @vers: where to place the version
2688 * Reads the TP microcode version from flash.
2690 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2692 return t4_read_flash(adapter, FLASH_FW_START +
2693 offsetof(struct fw_hdr, tp_microcode_ver),
2698 * t4_get_version_info - extract various chip/firmware version information
2699 * @adapter: the adapter
2701 * Reads various chip/firmware version numbers and stores them into the
2702 * adapter Adapter Parameters structure. If any of the efforts fails
2703 * the first failure will be returned, but all of the version numbers
2706 int t4_get_version_info(struct adapter *adapter)
2710 #define FIRST_RET(__getvinfo) \
2712 int __ret = __getvinfo; \
2713 if (__ret && !ret) \
2717 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2718 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2719 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2720 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2728 * t4_dump_version_info - dump all of the adapter configuration IDs
2729 * @adapter: the adapter
2731 * Dumps all of the various bits of adapter configuration version/revision
2732 * IDs information. This is typically called at some point after
2733 * t4_get_version_info() has been called.
2735 void t4_dump_version_info(struct adapter *adapter)
2738 * Device information.
2740 dev_info(adapter, "Chelsio rev %d\n",
2741 CHELSIO_CHIP_RELEASE(adapter->params.chip));
2746 if (!adapter->params.fw_vers)
2747 dev_warn(adapter, "No firmware loaded\n");
2749 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2750 G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2751 G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2752 G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2753 G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2756 * Bootstrap Firmware Version.
2758 if (!adapter->params.bs_vers)
2759 dev_warn(adapter, "No bootstrap loaded\n");
2761 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2762 G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2763 G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2764 G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2765 G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2768 * TP Microcode Version.
2770 if (!adapter->params.tp_vers)
2771 dev_warn(adapter, "No TP Microcode loaded\n");
2773 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2774 G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2775 G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2776 G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2777 G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2780 * Expansion ROM version.
2782 if (!adapter->params.er_vers)
2783 dev_info(adapter, "No Expansion ROM loaded\n");
2785 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2786 G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2787 G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2788 G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2789 G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2792 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
2795 /* Translate Firmware Pause specification to Common Code */
2796 static inline unsigned int fwcap_to_cc_pause(unsigned int fw_pause)
2798 unsigned int cc_pause = 0;
2800 if (fw_pause & F_FW_PORT_CMD_RXPAUSE)
2801 cc_pause |= PAUSE_RX;
2802 if (fw_pause & F_FW_PORT_CMD_TXPAUSE)
2803 cc_pause |= PAUSE_TX;
2808 /* Translate Common Code Pause Frame specification into Firmware */
2809 static inline unsigned int cc_to_fwcap_pause(unsigned int cc_pause)
2811 unsigned int fw_pause = 0;
2813 if (cc_pause & PAUSE_RX)
2814 fw_pause |= F_FW_PORT_CMD_RXPAUSE;
2815 if (cc_pause & PAUSE_TX)
2816 fw_pause |= F_FW_PORT_CMD_TXPAUSE;
2821 /* Translate Firmware Forward Error Correction specification to Common Code */
2822 static inline unsigned int fwcap_to_cc_fec(unsigned int fw_fec)
2824 unsigned int cc_fec = 0;
2826 if (fw_fec & FW_PORT_CAP_FEC_RS)
2828 if (fw_fec & FW_PORT_CAP_FEC_BASER_RS)
2829 cc_fec |= FEC_BASER_RS;
2834 /* Translate Common Code Forward Error Correction specification to Firmware */
2835 static inline unsigned int cc_to_fwcap_fec(unsigned int cc_fec)
2837 unsigned int fw_fec = 0;
2839 if (cc_fec & FEC_RS)
2840 fw_fec |= FW_PORT_CAP_FEC_RS;
2841 if (cc_fec & FEC_BASER_RS)
2842 fw_fec |= FW_PORT_CAP_FEC_BASER_RS;
2848 * t4_link_l1cfg - apply link configuration to MAC/PHY
2849 * @phy: the PHY to setup
2850 * @mac: the MAC to setup
2851 * @lc: the requested link configuration
2853 * Set up a port's MAC and PHY according to a desired link configuration.
2854 * - If the PHY can auto-negotiate first decide what to advertise, then
2855 * enable/disable auto-negotiation as desired, and reset.
2856 * - If the PHY does not auto-negotiate just reset it.
2857 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2858 * otherwise do it later based on the outcome of auto-negotiation.
2860 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2861 struct link_config *lc)
2863 struct fw_port_cmd c;
2864 unsigned int fw_mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
2865 unsigned int fw_fc, cc_fec, fw_fec;
2869 fw_fc = cc_to_fwcap_pause(lc->requested_fc);
2871 /* Convert Common Code Forward Error Control settings into the
2872 * Firmware's API. If the current Requested FEC has "Automatic"
2873 * (IEEE 802.3) specified, then we use whatever the Firmware
2874 * sent us as part of it's IEEE 802.3-based interpratation of
2875 * the Transceiver Module EPROM FEC parameters. Otherwise we
2876 * use whatever is in the current Requested FEC settings.
2878 if (lc->requested_fec & FEC_AUTO)
2879 cc_fec = lc->auto_fec;
2881 cc_fec = lc->requested_fec;
2882 fw_fec = cc_to_fwcap_fec(cc_fec);
2884 memset(&c, 0, sizeof(c));
2885 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2886 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2887 V_FW_PORT_CMD_PORTID(port));
2889 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2892 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2893 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2895 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2897 } else if (lc->autoneg == AUTONEG_DISABLE) {
2898 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fw_fc |
2900 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2903 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fw_fc | fw_fec |
2907 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2911 * t4_flash_cfg_addr - return the address of the flash configuration file
2912 * @adapter: the adapter
2914 * Return the address within the flash where the Firmware Configuration
2915 * File is stored, or an error if the device FLASH is too small to contain
2916 * a Firmware Configuration File.
2918 int t4_flash_cfg_addr(struct adapter *adapter)
2921 * If the device FLASH isn't large enough to hold a Firmware
2922 * Configuration File, return an error.
2924 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2927 return FLASH_CFG_START;
2930 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2933 * t4_intr_enable - enable interrupts
2934 * @adapter: the adapter whose interrupts should be enabled
2936 * Enable PF-specific interrupts for the calling function and the top-level
2937 * interrupt concentrator for global interrupts. Interrupts are already
2938 * enabled at each module, here we just enable the roots of the interrupt
2941 * Note: this function should be called only when the driver manages
2942 * non PF-specific interrupts from the various HW modules. Only one PCI
2943 * function at a time should be doing this.
2945 void t4_intr_enable(struct adapter *adapter)
2948 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2949 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2950 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2952 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2953 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2954 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2955 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2956 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2957 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2958 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2959 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2960 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2961 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2962 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2966 * t4_intr_disable - disable interrupts
2967 * @adapter: the adapter whose interrupts should be disabled
2969 * Disable interrupts. We only disable the top-level interrupt
2970 * concentrators. The caller must be a PCI function managing global
2973 void t4_intr_disable(struct adapter *adapter)
2975 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2976 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2977 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2979 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2980 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2984 * t4_get_port_type_description - return Port Type string description
2985 * @port_type: firmware Port Type enumeration
2987 const char *t4_get_port_type_description(enum fw_port_type port_type)
2989 static const char * const port_type_description[] = {
3014 if (port_type < ARRAY_SIZE(port_type_description))
3015 return port_type_description[port_type];
3020 * t4_get_mps_bg_map - return the buffer groups associated with a port
3021 * @adap: the adapter
3022 * @pidx: the port index
3024 * Returns a bitmap indicating which MPS buffer groups are associated
3025 * with the given port. Bit i is set if buffer group i is used by the
3028 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
3030 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3031 unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
3034 if (pidx >= nports) {
3035 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
3040 switch (chip_version) {
3045 case 2: return 3 << (2 * pidx);
3046 case 4: return 1 << pidx;
3052 case 2: return 1 << (2 * pidx);
3057 dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
3058 chip_version, nports);
3063 * t4_get_tp_ch_map - return TP ingress channels associated with a port
3064 * @adapter: the adapter
3065 * @pidx: the port index
3067 * Returns a bitmap indicating which TP Ingress Channels are associated with
3068 * a given Port. Bit i is set if TP Ingress Channel i is used by the Port.
3070 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
3072 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
3073 unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
3076 if (pidx >= nports) {
3077 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
3082 switch (chip_version) {
3085 /* Note that this happens to be the same values as the MPS
3086 * Buffer Group Map for these Chips. But we replicate the code
3087 * here because they're really separate concepts.
3091 case 2: return 3 << (2 * pidx);
3092 case 4: return 1 << pidx;
3098 case 2: return 1 << pidx;
3103 dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
3104 chip_version, nports);
3109 * t4_get_port_stats - collect port statistics
3110 * @adap: the adapter
3111 * @idx: the port index
3112 * @p: the stats structure to fill
3114 * Collect statistics related to the given port from HW.
3116 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
3118 u32 bgmap = t4_get_mps_bg_map(adap, idx);
3119 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
3121 #define GET_STAT(name) \
3122 t4_read_reg64(adap, \
3123 (is_t4(adap->params.chip) ? \
3124 PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
3125 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
3126 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
3128 p->tx_octets = GET_STAT(TX_PORT_BYTES);
3129 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
3130 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
3131 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
3132 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
3133 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
3134 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
3135 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
3136 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
3137 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
3138 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
3139 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
3140 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
3141 p->tx_drop = GET_STAT(TX_PORT_DROP);
3142 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
3143 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
3144 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
3145 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
3146 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
3147 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
3148 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
3149 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
3150 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
3152 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3153 if (stat_ctl & F_COUNTPAUSESTATTX) {
3154 p->tx_frames -= p->tx_pause;
3155 p->tx_octets -= p->tx_pause * 64;
3157 if (stat_ctl & F_COUNTPAUSEMCTX)
3158 p->tx_mcast_frames -= p->tx_pause;
3161 p->rx_octets = GET_STAT(RX_PORT_BYTES);
3162 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
3163 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
3164 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
3165 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
3166 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
3167 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
3168 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
3169 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
3170 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
3171 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
3172 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
3173 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
3174 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
3175 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
3176 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
3177 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3178 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
3179 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
3180 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
3181 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
3182 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
3183 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
3184 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
3185 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
3186 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
3187 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
3189 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3190 if (stat_ctl & F_COUNTPAUSESTATRX) {
3191 p->rx_frames -= p->rx_pause;
3192 p->rx_octets -= p->rx_pause * 64;
3194 if (stat_ctl & F_COUNTPAUSEMCRX)
3195 p->rx_mcast_frames -= p->rx_pause;
3198 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3199 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3200 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3201 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3202 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3203 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3204 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3205 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3212 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3213 * @adap: The adapter
3215 * @stats: Current stats to fill
3216 * @offset: Previous stats snapshot
3218 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3219 struct port_stats *stats,
3220 struct port_stats *offset)
3225 t4_get_port_stats(adap, idx, stats);
3226 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3227 i < (sizeof(struct port_stats) / sizeof(u64));
3233 * t4_clr_port_stats - clear port statistics
3234 * @adap: the adapter
3235 * @idx: the port index
3237 * Clear HW statistics for the given port.
3239 void t4_clr_port_stats(struct adapter *adap, int idx)
3242 u32 bgmap = t4_get_mps_bg_map(adap, idx);
3245 if (is_t4(adap->params.chip))
3246 port_base_addr = PORT_BASE(idx);
3248 port_base_addr = T5_PORT_BASE(idx);
3250 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3251 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3252 t4_write_reg(adap, port_base_addr + i, 0);
3253 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3254 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3255 t4_write_reg(adap, port_base_addr + i, 0);
3256 for (i = 0; i < 4; i++)
3257 if (bgmap & (1 << i)) {
3259 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3262 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3268 * t4_fw_hello - establish communication with FW
3269 * @adap: the adapter
3270 * @mbox: mailbox to use for the FW command
3271 * @evt_mbox: mailbox to receive async FW events
3272 * @master: specifies the caller's willingness to be the device master
3273 * @state: returns the current device state (if non-NULL)
3275 * Issues a command to establish communication with FW. Returns either
3276 * an error (negative integer) or the mailbox of the Master PF.
3278 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3279 enum dev_master master, enum dev_state *state)
3282 struct fw_hello_cmd c;
3284 unsigned int master_mbox;
3285 int retries = FW_CMD_HELLO_RETRIES;
3288 memset(&c, 0, sizeof(c));
3289 INIT_CMD(c, HELLO, WRITE);
3290 c.err_to_clearinit = cpu_to_be32(
3291 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3292 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3293 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3294 M_FW_HELLO_CMD_MBMASTER) |
3295 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3296 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3297 F_FW_HELLO_CMD_CLEARINIT);
3300 * Issue the HELLO command to the firmware. If it's not successful
3301 * but indicates that we got a "busy" or "timeout" condition, retry
3302 * the HELLO until we exhaust our retry limit. If we do exceed our
3303 * retry limit, check to see if the firmware left us any error
3304 * information and report that if so ...
3306 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3307 if (ret != FW_SUCCESS) {
3308 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3310 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3311 t4_report_fw_error(adap);
3315 v = be32_to_cpu(c.err_to_clearinit);
3316 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3318 if (v & F_FW_HELLO_CMD_ERR)
3319 *state = DEV_STATE_ERR;
3320 else if (v & F_FW_HELLO_CMD_INIT)
3321 *state = DEV_STATE_INIT;
3323 *state = DEV_STATE_UNINIT;
3327 * If we're not the Master PF then we need to wait around for the
3328 * Master PF Driver to finish setting up the adapter.
3330 * Note that we also do this wait if we're a non-Master-capable PF and
3331 * there is no current Master PF; a Master PF may show up momentarily
3332 * and we wouldn't want to fail pointlessly. (This can happen when an
3333 * OS loads lots of different drivers rapidly at the same time). In
3334 * this case, the Master PF returned by the firmware will be
3335 * M_PCIE_FW_MASTER so the test below will work ...
3337 if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3338 master_mbox != mbox) {
3339 int waiting = FW_CMD_HELLO_TIMEOUT;
3342 * Wait for the firmware to either indicate an error or
3343 * initialized state. If we see either of these we bail out
3344 * and report the issue to the caller. If we exhaust the
3345 * "hello timeout" and we haven't exhausted our retries, try
3346 * again. Otherwise bail with a timeout error.
3355 * If neither Error nor Initialialized are indicated
3356 * by the firmware keep waiting till we exaust our
3357 * timeout ... and then retry if we haven't exhausted
3360 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3361 if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3372 * We either have an Error or Initialized condition
3373 * report errors preferentially.
3376 if (pcie_fw & F_PCIE_FW_ERR)
3377 *state = DEV_STATE_ERR;
3378 else if (pcie_fw & F_PCIE_FW_INIT)
3379 *state = DEV_STATE_INIT;
3383 * If we arrived before a Master PF was selected and
3384 * there's not a valid Master PF, grab its identity
3387 if (master_mbox == M_PCIE_FW_MASTER &&
3388 (pcie_fw & F_PCIE_FW_MASTER_VLD))
3389 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3398 * t4_fw_bye - end communication with FW
3399 * @adap: the adapter
3400 * @mbox: mailbox to use for the FW command
3402 * Issues a command to terminate communication with FW.
3404 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3406 struct fw_bye_cmd c;
3408 memset(&c, 0, sizeof(c));
3409 INIT_CMD(c, BYE, WRITE);
3410 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3414 * t4_fw_reset - issue a reset to FW
3415 * @adap: the adapter
3416 * @mbox: mailbox to use for the FW command
3417 * @reset: specifies the type of reset to perform
3419 * Issues a reset command of the specified type to FW.
3421 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3423 struct fw_reset_cmd c;
3425 memset(&c, 0, sizeof(c));
3426 INIT_CMD(c, RESET, WRITE);
3427 c.val = cpu_to_be32(reset);
3428 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3432 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3433 * @adap: the adapter
3434 * @mbox: mailbox to use for the FW RESET command (if desired)
3435 * @force: force uP into RESET even if FW RESET command fails
3437 * Issues a RESET command to firmware (if desired) with a HALT indication
3438 * and then puts the microprocessor into RESET state. The RESET command
3439 * will only be issued if a legitimate mailbox is provided (mbox <=
3440 * M_PCIE_FW_MASTER).
3442 * This is generally used in order for the host to safely manipulate the
3443 * adapter without fear of conflicting with whatever the firmware might
3444 * be doing. The only way out of this state is to RESTART the firmware
3447 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3452 * If a legitimate mailbox is provided, issue a RESET command
3453 * with a HALT indication.
3455 if (mbox <= M_PCIE_FW_MASTER) {
3456 struct fw_reset_cmd c;
3458 memset(&c, 0, sizeof(c));
3459 INIT_CMD(c, RESET, WRITE);
3460 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3461 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3462 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3466 * Normally we won't complete the operation if the firmware RESET
3467 * command fails but if our caller insists we'll go ahead and put the
3468 * uP into RESET. This can be useful if the firmware is hung or even
3469 * missing ... We'll have to take the risk of putting the uP into
3470 * RESET without the cooperation of firmware in that case.
3472 * We also force the firmware's HALT flag to be on in case we bypassed
3473 * the firmware RESET command above or we're dealing with old firmware
3474 * which doesn't have the HALT capability. This will serve as a flag
3475 * for the incoming firmware to know that it's coming out of a HALT
3476 * rather than a RESET ... if it's new enough to understand that ...
3478 if (ret == 0 || force) {
3479 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3480 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3485 * And we always return the result of the firmware RESET command
3486 * even when we force the uP into RESET ...
3492 * t4_fw_restart - restart the firmware by taking the uP out of RESET
3493 * @adap: the adapter
3494 * @mbox: mailbox to use for the FW RESET command (if desired)
3495 * @reset: if we want to do a RESET to restart things
3497 * Restart firmware previously halted by t4_fw_halt(). On successful
3498 * return the previous PF Master remains as the new PF Master and there
3499 * is no need to issue a new HELLO command, etc.
3501 * We do this in two ways:
3503 * 1. If we're dealing with newer firmware we'll simply want to take
3504 * the chip's microprocessor out of RESET. This will cause the
3505 * firmware to start up from its start vector. And then we'll loop
3506 * until the firmware indicates it's started again (PCIE_FW.HALT
3507 * reset to 0) or we timeout.
3509 * 2. If we're dealing with older firmware then we'll need to RESET
3510 * the chip since older firmware won't recognize the PCIE_FW.HALT
3511 * flag and automatically RESET itself on startup.
3513 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3517 * Since we're directing the RESET instead of the firmware
3518 * doing it automatically, we need to clear the PCIE_FW.HALT
3521 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3524 * If we've been given a valid mailbox, first try to get the
3525 * firmware to do the RESET. If that works, great and we can
3526 * return success. Otherwise, if we haven't been given a
3527 * valid mailbox or the RESET command failed, fall back to
3528 * hitting the chip with a hammer.
3530 if (mbox <= M_PCIE_FW_MASTER) {
3531 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3533 if (t4_fw_reset(adap, mbox,
3534 F_PIORST | F_PIORSTMODE) == 0)
3538 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3543 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3544 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3545 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3556 * t4_fl_pkt_align - return the fl packet alignment
3557 * @adap: the adapter
3559 * T4 has a single field to specify the packing and padding boundary.
3560 * T5 onwards has separate fields for this and hence the alignment for
3561 * next packet offset is maximum of these two.
3563 int t4_fl_pkt_align(struct adapter *adap)
3565 u32 sge_control, sge_control2;
3566 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3568 sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3570 /* T4 uses a single control field to specify both the PCIe Padding and
3571 * Packing Boundary. T5 introduced the ability to specify these
3572 * separately. The actual Ingress Packet Data alignment boundary
3573 * within Packed Buffer Mode is the maximum of these two
3576 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3577 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3579 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3581 ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3583 fl_align = ingpadboundary;
3584 if (!is_t4(adap->params.chip)) {
3585 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3586 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3587 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3588 ingpackboundary = 16;
3590 ingpackboundary = 1 << (ingpackboundary +
3591 X_INGPACKBOUNDARY_SHIFT);
3593 fl_align = max(ingpadboundary, ingpackboundary);
3599 * t4_fixup_host_params_compat - fix up host-dependent parameters
3600 * @adap: the adapter
3601 * @page_size: the host's Base Page Size
3602 * @cache_line_size: the host's Cache Line Size
3603 * @chip_compat: maintain compatibility with designated chip
3605 * Various registers in the chip contain values which are dependent on the
3606 * host's Base Page and Cache Line Sizes. This function will fix all of
3607 * those registers with the appropriate values as passed in ...
3609 * @chip_compat is used to limit the set of changes that are made
3610 * to be compatible with the indicated chip release. This is used by
3611 * drivers to maintain compatibility with chip register settings when
3612 * the drivers haven't [yet] been updated with new chip support.
3614 int t4_fixup_host_params_compat(struct adapter *adap,
3615 unsigned int page_size,
3616 unsigned int cache_line_size,
3617 enum chip_type chip_compat)
3619 unsigned int page_shift = cxgbe_fls(page_size) - 1;
3620 unsigned int sge_hps = page_shift - 10;
3621 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3622 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3623 unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3625 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3626 V_HOSTPAGESIZEPF0(sge_hps) |
3627 V_HOSTPAGESIZEPF1(sge_hps) |
3628 V_HOSTPAGESIZEPF2(sge_hps) |
3629 V_HOSTPAGESIZEPF3(sge_hps) |
3630 V_HOSTPAGESIZEPF4(sge_hps) |
3631 V_HOSTPAGESIZEPF5(sge_hps) |
3632 V_HOSTPAGESIZEPF6(sge_hps) |
3633 V_HOSTPAGESIZEPF7(sge_hps));
3635 if (is_t4(adap->params.chip) || is_t4(chip_compat))
3636 t4_set_reg_field(adap, A_SGE_CONTROL,
3637 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3638 F_EGRSTATUSPAGESIZE,
3639 V_INGPADBOUNDARY(fl_align_log -
3640 X_INGPADBOUNDARY_SHIFT) |
3641 V_EGRSTATUSPAGESIZE(stat_len != 64));
3643 unsigned int pack_align;
3644 unsigned int ingpad, ingpack;
3645 unsigned int pcie_cap;
3648 * T5 introduced the separation of the Free List Padding and
3649 * Packing Boundaries. Thus, we can select a smaller Padding
3650 * Boundary to avoid uselessly chewing up PCIe Link and Memory
3651 * Bandwidth, and use a Packing Boundary which is large enough
3652 * to avoid false sharing between CPUs, etc.
3654 * For the PCI Link, the smaller the Padding Boundary the
3655 * better. For the Memory Controller, a smaller Padding
3656 * Boundary is better until we cross under the Memory Line
3657 * Size (the minimum unit of transfer to/from Memory). If we
3658 * have a Padding Boundary which is smaller than the Memory
3659 * Line Size, that'll involve a Read-Modify-Write cycle on the
3660 * Memory Controller which is never good.
3663 /* We want the Packing Boundary to be based on the Cache Line
3664 * Size in order to help avoid False Sharing performance
3665 * issues between CPUs, etc. We also want the Packing
3666 * Boundary to incorporate the PCI-E Maximum Payload Size. We
3667 * get best performance when the Packing Boundary is a
3668 * multiple of the Maximum Payload Size.
3670 pack_align = fl_align;
3671 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3673 unsigned int mps, mps_log;
3676 /* The PCIe Device Control Maximum Payload Size field
3677 * [bits 7:5] encodes sizes as powers of 2 starting at
3680 t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3682 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3684 if (mps > pack_align)
3689 * N.B. T5 has a different interpretation of the "0" value for
3690 * the Packing Boundary. This corresponds to 16 bytes instead
3691 * of the expected 32 bytes. We never have a Packing Boundary
3692 * less than 32 bytes so we can't use that special value but
3693 * on the other hand, if we wanted 32 bytes, the best we can
3694 * really do is 64 bytes ...
3696 if (pack_align <= 16) {
3697 ingpack = X_INGPACKBOUNDARY_16B;
3699 } else if (pack_align == 32) {
3700 ingpack = X_INGPACKBOUNDARY_64B;
3703 unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3705 ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3706 fl_align = pack_align;
3709 /* Use the smallest Ingress Padding which isn't smaller than
3710 * the Memory Controller Read/Write Size. We'll take that as
3711 * being 8 bytes since we don't know of any system with a
3712 * wider Memory Controller Bus Width.
3714 if (is_t5(adap->params.chip))
3715 ingpad = X_INGPADBOUNDARY_32B;
3717 ingpad = X_T6_INGPADBOUNDARY_8B;
3718 t4_set_reg_field(adap, A_SGE_CONTROL,
3719 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3720 F_EGRSTATUSPAGESIZE,
3721 V_INGPADBOUNDARY(ingpad) |
3722 V_EGRSTATUSPAGESIZE(stat_len != 64));
3723 t4_set_reg_field(adap, A_SGE_CONTROL2,
3724 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3725 V_INGPACKBOUNDARY(ingpack));
3729 * Adjust various SGE Free List Host Buffer Sizes.
3731 * The first four entries are:
3735 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3736 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3738 * For the single-MTU buffers in unpacked mode we need to include
3739 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3740 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3741 * Padding boundary. All of these are accommodated in the Factory
3742 * Default Firmware Configuration File but we need to adjust it for
3743 * this host's cache line size.
3745 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3746 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3747 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3749 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3750 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3753 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3759 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3760 * @adap: the adapter
3761 * @page_size: the host's Base Page Size
3762 * @cache_line_size: the host's Cache Line Size
3764 * Various registers in T4 contain values which are dependent on the
3765 * host's Base Page and Cache Line Sizes. This function will fix all of
3766 * those registers with the appropriate values as passed in ...
3768 * This routine makes changes which are compatible with T4 chips.
3770 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3771 unsigned int cache_line_size)
3773 return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3778 * t4_fw_initialize - ask FW to initialize the device
3779 * @adap: the adapter
3780 * @mbox: mailbox to use for the FW command
3782 * Issues a command to FW to partially initialize the device. This
3783 * performs initialization that generally doesn't depend on user input.
3785 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3787 struct fw_initialize_cmd c;
3789 memset(&c, 0, sizeof(c));
3790 INIT_CMD(c, INITIALIZE, WRITE);
3791 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3795 * t4_query_params_rw - query FW or device parameters
3796 * @adap: the adapter
3797 * @mbox: mailbox to use for the FW command
3800 * @nparams: the number of parameters
3801 * @params: the parameter names
3802 * @val: the parameter values
3803 * @rw: Write and read flag
3805 * Reads the value of FW or device parameters. Up to 7 parameters can be
3808 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3809 unsigned int pf, unsigned int vf,
3810 unsigned int nparams, const u32 *params,
3815 struct fw_params_cmd c;
3816 __be32 *p = &c.param[0].mnem;
3821 memset(&c, 0, sizeof(c));
3822 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3823 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3824 V_FW_PARAMS_CMD_PFN(pf) |
3825 V_FW_PARAMS_CMD_VFN(vf));
3826 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3828 for (i = 0; i < nparams; i++) {
3829 *p++ = cpu_to_be32(*params++);
3831 *p = cpu_to_be32(*(val + i));
3835 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3837 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3838 *val++ = be32_to_cpu(*p);
3842 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3843 unsigned int vf, unsigned int nparams, const u32 *params,
3846 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3850 * t4_set_params_timeout - sets FW or device parameters
3851 * @adap: the adapter
3852 * @mbox: mailbox to use for the FW command
3855 * @nparams: the number of parameters
3856 * @params: the parameter names
3857 * @val: the parameter values
3858 * @timeout: the timeout time
3860 * Sets the value of FW or device parameters. Up to 7 parameters can be
3861 * specified at once.
3863 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3864 unsigned int pf, unsigned int vf,
3865 unsigned int nparams, const u32 *params,
3866 const u32 *val, int timeout)
3868 struct fw_params_cmd c;
3869 __be32 *p = &c.param[0].mnem;
3874 memset(&c, 0, sizeof(c));
3875 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3876 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3877 V_FW_PARAMS_CMD_PFN(pf) |
3878 V_FW_PARAMS_CMD_VFN(vf));
3879 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3882 *p++ = cpu_to_be32(*params++);
3883 *p++ = cpu_to_be32(*val++);
3886 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3889 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3890 unsigned int vf, unsigned int nparams, const u32 *params,
3893 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3894 FW_CMD_MAX_TIMEOUT);
3898 * t4_alloc_vi_func - allocate a virtual interface
3899 * @adap: the adapter
3900 * @mbox: mailbox to use for the FW command
3901 * @port: physical port associated with the VI
3902 * @pf: the PF owning the VI
3903 * @vf: the VF owning the VI
3904 * @nmac: number of MAC addresses needed (1 to 5)
3905 * @mac: the MAC addresses of the VI
3906 * @rss_size: size of RSS table slice associated with this VI
3907 * @portfunc: which Port Application Function MAC Address is desired
3908 * @idstype: Intrusion Detection Type
3910 * Allocates a virtual interface for the given physical port. If @mac is
3911 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3912 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3913 * stored consecutively so the space needed is @nmac * 6 bytes.
3914 * Returns a negative error number or the non-negative VI id.
3916 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3917 unsigned int port, unsigned int pf, unsigned int vf,
3918 unsigned int nmac, u8 *mac, unsigned int *rss_size,
3919 unsigned int portfunc, unsigned int idstype)
3924 memset(&c, 0, sizeof(c));
3925 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3926 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3927 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3928 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3929 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3930 V_FW_VI_CMD_FUNC(portfunc));
3931 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3934 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3939 memcpy(mac, c.mac, sizeof(c.mac));
3942 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3945 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3948 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3951 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3956 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3957 return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3961 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3962 * @adap: the adapter
3963 * @mbox: mailbox to use for the FW command
3964 * @port: physical port associated with the VI
3965 * @pf: the PF owning the VI
3966 * @vf: the VF owning the VI
3967 * @nmac: number of MAC addresses needed (1 to 5)
3968 * @mac: the MAC addresses of the VI
3969 * @rss_size: size of RSS table slice associated with this VI
3971 * Backwards compatible and convieniance routine to allocate a Virtual
3972 * Interface with a Ethernet Port Application Function and Intrustion
3973 * Detection System disabled.
3975 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3976 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3977 unsigned int *rss_size)
3979 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3984 * t4_free_vi - free a virtual interface
3985 * @adap: the adapter
3986 * @mbox: mailbox to use for the FW command
3987 * @pf: the PF owning the VI
3988 * @vf: the VF owning the VI
3989 * @viid: virtual interface identifiler
3991 * Free a previously allocated virtual interface.
3993 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3994 unsigned int vf, unsigned int viid)
3998 memset(&c, 0, sizeof(c));
3999 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
4000 F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
4001 V_FW_VI_CMD_VFN(vf));
4002 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
4003 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
4005 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4009 * t4_set_rxmode - set Rx properties of a virtual interface
4010 * @adap: the adapter
4011 * @mbox: mailbox to use for the FW command
4013 * @mtu: the new MTU or -1
4014 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
4015 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
4016 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
4017 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
4019 * @sleep_ok: if true we may sleep while awaiting command completion
4021 * Sets Rx properties of a virtual interface.
4023 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
4024 int mtu, int promisc, int all_multi, int bcast, int vlanex,
4027 struct fw_vi_rxmode_cmd c;
4029 /* convert to FW values */
4031 mtu = M_FW_VI_RXMODE_CMD_MTU;
4033 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
4035 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
4037 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
4039 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
4041 memset(&c, 0, sizeof(c));
4042 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
4043 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4044 V_FW_VI_RXMODE_CMD_VIID(viid));
4045 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4046 c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
4047 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
4048 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
4049 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
4050 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
4051 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
4055 * t4_change_mac - modifies the exact-match filter for a MAC address
4056 * @adap: the adapter
4057 * @mbox: mailbox to use for the FW command
4059 * @idx: index of existing filter for old value of MAC address, or -1
4060 * @addr: the new MAC address value
4061 * @persist: whether a new MAC allocation should be persistent
4062 * @add_smt: if true also add the address to the HW SMT
4064 * Modifies an exact-match filter and sets it to the new MAC address if
4065 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
4066 * latter case the address is added persistently if @persist is %true.
4068 * Note that in general it is not possible to modify the value of a given
4069 * filter so the generic way to modify an address filter is to free the one
4070 * being used by the old address value and allocate a new filter for the
4071 * new address value.
4073 * Returns a negative error number or the index of the filter with the new
4074 * MAC value. Note that this index may differ from @idx.
4076 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
4077 int idx, const u8 *addr, bool persist, bool add_smt)
4080 struct fw_vi_mac_cmd c;
4081 struct fw_vi_mac_exact *p = c.u.exact;
4082 int max_mac_addr = adap->params.arch.mps_tcam_size;
4084 if (idx < 0) /* new allocation */
4085 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
4086 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
4088 memset(&c, 0, sizeof(c));
4089 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
4090 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4091 V_FW_VI_MAC_CMD_VIID(viid));
4092 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
4093 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
4094 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
4095 V_FW_VI_MAC_CMD_IDX(idx));
4096 memcpy(p->macaddr, addr, sizeof(p->macaddr));
4098 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4100 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
4101 if (ret >= max_mac_addr)
4108 * t4_enable_vi_params - enable/disable a virtual interface
4109 * @adap: the adapter
4110 * @mbox: mailbox to use for the FW command
4112 * @rx_en: 1=enable Rx, 0=disable Rx
4113 * @tx_en: 1=enable Tx, 0=disable Tx
4114 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
4116 * Enables/disables a virtual interface. Note that setting DCB Enable
4117 * only makes sense when enabling a Virtual Interface ...
4119 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
4120 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
4122 struct fw_vi_enable_cmd c;
4124 memset(&c, 0, sizeof(c));
4125 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
4126 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4127 V_FW_VI_ENABLE_CMD_VIID(viid));
4128 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
4129 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
4130 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
4132 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
4136 * t4_enable_vi - enable/disable a virtual interface
4137 * @adap: the adapter
4138 * @mbox: mailbox to use for the FW command
4140 * @rx_en: 1=enable Rx, 0=disable Rx
4141 * @tx_en: 1=enable Tx, 0=disable Tx
4143 * Enables/disables a virtual interface. Note that setting DCB Enable
4144 * only makes sense when enabling a Virtual Interface ...
4146 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
4147 bool rx_en, bool tx_en)
4149 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
4153 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
4154 * @adap: the adapter
4155 * @mbox: mailbox to use for the FW command
4156 * @start: %true to enable the queues, %false to disable them
4157 * @pf: the PF owning the queues
4158 * @vf: the VF owning the queues
4159 * @iqid: ingress queue id
4160 * @fl0id: FL0 queue id or 0xffff if no attached FL0
4161 * @fl1id: FL1 queue id or 0xffff if no attached FL1
4163 * Starts or stops an ingress queue and its associated FLs, if any.
4165 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
4166 unsigned int pf, unsigned int vf, unsigned int iqid,
4167 unsigned int fl0id, unsigned int fl1id)
4171 memset(&c, 0, sizeof(c));
4172 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4173 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4174 V_FW_IQ_CMD_VFN(vf));
4175 c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4176 V_FW_IQ_CMD_IQSTOP(!start) |
4178 c.iqid = cpu_to_be16(iqid);
4179 c.fl0id = cpu_to_be16(fl0id);
4180 c.fl1id = cpu_to_be16(fl1id);
4181 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4185 * t4_iq_free - free an ingress queue and its FLs
4186 * @adap: the adapter
4187 * @mbox: mailbox to use for the FW command
4188 * @pf: the PF owning the queues
4189 * @vf: the VF owning the queues
4190 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4191 * @iqid: ingress queue id
4192 * @fl0id: FL0 queue id or 0xffff if no attached FL0
4193 * @fl1id: FL1 queue id or 0xffff if no attached FL1
4195 * Frees an ingress queue and its associated FLs, if any.
4197 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4198 unsigned int vf, unsigned int iqtype, unsigned int iqid,
4199 unsigned int fl0id, unsigned int fl1id)
4203 memset(&c, 0, sizeof(c));
4204 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4205 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4206 V_FW_IQ_CMD_VFN(vf));
4207 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4208 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4209 c.iqid = cpu_to_be16(iqid);
4210 c.fl0id = cpu_to_be16(fl0id);
4211 c.fl1id = cpu_to_be16(fl1id);
4212 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4216 * t4_eth_eq_free - free an Ethernet egress queue
4217 * @adap: the adapter
4218 * @mbox: mailbox to use for the FW command
4219 * @pf: the PF owning the queue
4220 * @vf: the VF owning the queue
4221 * @eqid: egress queue id
4223 * Frees an Ethernet egress queue.
4225 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4226 unsigned int vf, unsigned int eqid)
4228 struct fw_eq_eth_cmd c;
4230 memset(&c, 0, sizeof(c));
4231 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4232 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4233 V_FW_EQ_ETH_CMD_PFN(pf) |
4234 V_FW_EQ_ETH_CMD_VFN(vf));
4235 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4236 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4237 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4241 * t4_handle_fw_rpl - process a FW reply message
4242 * @adap: the adapter
4243 * @rpl: start of the FW message
4245 * Processes a FW message, such as link state change messages.
4247 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4249 u8 opcode = *(const u8 *)rpl;
4252 * This might be a port command ... this simplifies the following
4253 * conditionals ... We can get away with pre-dereferencing
4254 * action_to_len16 because it's in the first 16 bytes and all messages
4255 * will be at least that long.
4257 const struct fw_port_cmd *p = (const void *)rpl;
4258 unsigned int action =
4259 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4261 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
4262 /* link/module state change message */
4263 unsigned int speed = 0, fc = 0, i;
4264 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4265 struct port_info *pi = NULL;
4266 struct link_config *lc;
4267 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
4268 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
4269 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
4272 fc = fwcap_to_cc_pause(stat);
4273 fec = fwcap_to_cc_fec(stat);
4275 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4276 speed = ETH_SPEED_NUM_100M;
4277 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4278 speed = ETH_SPEED_NUM_1G;
4279 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4280 speed = ETH_SPEED_NUM_10G;
4281 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4282 speed = ETH_SPEED_NUM_25G;
4283 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4284 speed = ETH_SPEED_NUM_40G;
4285 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4286 speed = ETH_SPEED_NUM_100G;
4288 for_each_port(adap, i) {
4289 pi = adap2pinfo(adap, i);
4290 if (pi->tx_chan == chan)
4295 if (mod != pi->mod_type) {
4298 t4_os_portmod_changed(adap, i);
4300 if (link_ok != lc->link_ok || speed != lc->speed ||
4301 fc != lc->fc || fec != lc->fec) { /* something changed */
4302 if (!link_ok && lc->link_ok) {
4303 static const char * const reason[] = {
4306 "Auto-negotiation Failure",
4308 "Insufficient Airflow",
4309 "Unable To Determine Reason",
4310 "No RX Signal Detected",
4313 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
4315 dev_warn(adap, "Port %d link down, reason: %s\n",
4318 lc->link_ok = link_ok;
4322 lc->supported = be16_to_cpu(p->u.info.pcap);
4325 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4331 void t4_reset_link_config(struct adapter *adap, int idx)
4333 struct port_info *pi = adap2pinfo(adap, idx);
4334 struct link_config *lc = &pi->link_cfg;
4337 lc->requested_speed = 0;
4338 lc->requested_fc = 0;
4344 * init_link_config - initialize a link's SW state
4345 * @lc: structure holding the link state
4346 * @pcaps: link Port Capabilities
4347 * @acaps: link current Advertised Port Capabilities
4349 * Initializes the SW state maintained for each link, including the link's
4350 * capabilities and default speed/flow-control/autonegotiation settings.
4352 static void init_link_config(struct link_config *lc, unsigned int pcaps,
4355 lc->supported = pcaps;
4356 lc->requested_speed = 0;
4358 lc->requested_fc = 0;
4362 * For Forward Error Control, we default to whatever the Firmware
4363 * tells us the Link is currently advertising.
4365 lc->auto_fec = fwcap_to_cc_fec(acaps);
4366 lc->requested_fec = FEC_AUTO;
4367 lc->fec = lc->auto_fec;
4369 if (lc->supported & FW_PORT_CAP_ANEG) {
4370 lc->advertising = lc->supported & ADVERT_MASK;
4371 lc->autoneg = AUTONEG_ENABLE;
4373 lc->advertising = 0;
4374 lc->autoneg = AUTONEG_DISABLE;
4379 * t4_wait_dev_ready - wait till to reads of registers work
4381 * Right after the device is RESET is can take a small amount of time
4382 * for it to respond to register reads. Until then, all reads will
4383 * return either 0xff...ff or 0xee...ee. Return an error if reads
4384 * don't work within a reasonable time frame.
4386 static int t4_wait_dev_ready(struct adapter *adapter)
4390 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4392 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4396 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4397 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4400 dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4406 u32 vendor_and_model_id;
4410 int t4_get_flash_params(struct adapter *adapter)
4413 * Table for non-Numonix supported flash parts. Numonix parts are left
4414 * to the preexisting well-tested code. All flash parts have 64KB
4417 static struct flash_desc supported_flash[] = {
4418 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
4423 unsigned int part, manufacturer;
4424 unsigned int density, size;
4427 * Issue a Read ID Command to the Flash part. We decode supported
4428 * Flash parts and their sizes from this. There's a newer Query
4429 * Command which can retrieve detailed geometry information but
4430 * many Flash parts don't support it.
4432 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4434 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4435 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
4439 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4440 if (supported_flash[part].vendor_and_model_id == flashid) {
4441 adapter->params.sf_size =
4442 supported_flash[part].size_mb;
4443 adapter->params.sf_nsec =
4444 adapter->params.sf_size / SF_SEC_SIZE;
4449 manufacturer = flashid & 0xff;
4450 switch (manufacturer) {
4451 case 0x20: { /* Micron/Numonix */
4453 * This Density -> Size decoding table is taken from Micron
4456 density = (flashid >> 16) & 0xff;
4459 size = 1 << 20; /* 1MB */
4462 size = 1 << 21; /* 2MB */
4465 size = 1 << 22; /* 4MB */
4468 size = 1 << 23; /* 8MB */
4471 size = 1 << 24; /* 16MB */
4474 size = 1 << 25; /* 32MB */
4477 size = 1 << 26; /* 64MB */
4480 size = 1 << 27; /* 128MB */
4483 size = 1 << 28; /* 256MB */
4486 dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4491 adapter->params.sf_size = size;
4492 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4496 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4502 * We should reject adapters with FLASHes which are too small. So, emit
4505 if (adapter->params.sf_size < FLASH_MIN_SIZE)
4506 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4507 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4512 static void set_pcie_completion_timeout(struct adapter *adapter,
4518 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4520 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4523 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4528 * t4_get_chip_type - Determine chip type from device ID
4529 * @adap: the adapter
4530 * @ver: adapter version
4532 int t4_get_chip_type(struct adapter *adap, int ver)
4534 enum chip_type chip = 0;
4535 u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4537 /* Retrieve adapter's device ID */
4540 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4543 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4546 dev_err(adap, "Device %d is not supported\n",
4547 adap->params.pci.device_id);
4555 * t4_prep_adapter - prepare SW and HW for operation
4556 * @adapter: the adapter
4558 * Initialize adapter SW state for the various HW modules, set initial
4559 * values for some adapter tunables, take PHYs out of reset, and
4560 * initialize the MDIO interface.
4562 int t4_prep_adapter(struct adapter *adapter)
4567 ret = t4_wait_dev_ready(adapter);
4571 pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4572 adapter->params.pci.device_id = adapter->pdev->id.device_id;
4573 adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4576 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4577 * ADAPTER (VERSION << 4 | REVISION)
4579 ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4580 adapter->params.chip = 0;
4583 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4584 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4585 adapter->params.arch.mps_tcam_size =
4586 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4587 adapter->params.arch.mps_rplc_size = 128;
4588 adapter->params.arch.nchan = NCHAN;
4589 adapter->params.arch.vfcount = 128;
4592 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4593 adapter->params.arch.sge_fl_db = 0;
4594 adapter->params.arch.mps_tcam_size =
4595 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4596 adapter->params.arch.mps_rplc_size = 256;
4597 adapter->params.arch.nchan = 2;
4598 adapter->params.arch.vfcount = 256;
4601 dev_err(adapter, "%s: Device %d is not supported\n",
4602 __func__, adapter->params.pci.device_id);
4606 adapter->params.pci.vpd_cap_addr =
4607 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4609 ret = t4_get_flash_params(adapter);
4611 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4616 adapter->params.cim_la_size = CIMLA_SIZE;
4618 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4621 * Default port and clock for debugging in case we can't reach FW.
4623 adapter->params.nports = 1;
4624 adapter->params.portvec = 1;
4625 adapter->params.vpd.cclk = 50000;
4627 /* Set pci completion timeout value to 4 seconds. */
4628 set_pcie_completion_timeout(adapter, 0xd);
4633 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4634 * @adapter: the adapter
4635 * @qid: the Queue ID
4636 * @qtype: the Ingress or Egress type for @qid
4637 * @pbar2_qoffset: BAR2 Queue Offset
4638 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4640 * Returns the BAR2 SGE Queue Registers information associated with the
4641 * indicated Absolute Queue ID. These are passed back in return value
4642 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4643 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4645 * This may return an error which indicates that BAR2 SGE Queue
4646 * registers aren't available. If an error is not returned, then the
4647 * following values are returned:
4649 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4650 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4652 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4653 * require the "Inferred Queue ID" ability may be used. E.g. the
4654 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4655 * then these "Inferred Queue ID" register may not be used.
4657 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4658 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4659 unsigned int *pbar2_qid)
4661 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4662 u64 bar2_page_offset, bar2_qoffset;
4663 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4666 * T4 doesn't support BAR2 SGE Queue registers.
4668 if (is_t4(adapter->params.chip))
4672 * Get our SGE Page Size parameters.
4674 page_shift = adapter->params.sge.hps + 10;
4675 page_size = 1 << page_shift;
4678 * Get the right Queues per Page parameters for our Queue.
4680 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4681 adapter->params.sge.eq_qpp :
4682 adapter->params.sge.iq_qpp);
4683 qpp_mask = (1 << qpp_shift) - 1;
4686 * Calculate the basics of the BAR2 SGE Queue register area:
4687 * o The BAR2 page the Queue registers will be in.
4688 * o The BAR2 Queue ID.
4689 * o The BAR2 Queue ID Offset into the BAR2 page.
4691 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4692 bar2_qid = qid & qpp_mask;
4693 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4696 * If the BAR2 Queue ID Offset is less than the Page Size, then the
4697 * hardware will infer the Absolute Queue ID simply from the writes to
4698 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4699 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
4700 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4701 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4702 * from the BAR2 Page and BAR2 Queue ID.
4704 * One important censequence of this is that some BAR2 SGE registers
4705 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4706 * there. But other registers synthesize the SGE Queue ID purely
4707 * from the writes to the registers -- the Write Combined Doorbell
4708 * Buffer is a good example. These BAR2 SGE Registers are only
4709 * available for those BAR2 SGE Register areas where the SGE Absolute
4710 * Queue ID can be inferred from simple writes.
4712 bar2_qoffset = bar2_page_offset;
4713 bar2_qinferred = (bar2_qid_offset < page_size);
4714 if (bar2_qinferred) {
4715 bar2_qoffset += bar2_qid_offset;
4719 *pbar2_qoffset = bar2_qoffset;
4720 *pbar2_qid = bar2_qid;
4725 * t4_init_sge_params - initialize adap->params.sge
4726 * @adapter: the adapter
4728 * Initialize various fields of the adapter's SGE Parameters structure.
4730 int t4_init_sge_params(struct adapter *adapter)
4732 struct sge_params *sge_params = &adapter->params.sge;
4734 unsigned int s_hps, s_qpp;
4737 * Extract the SGE Page Size for our PF.
4739 hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4740 s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4742 sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4745 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4747 s_qpp = (S_QUEUESPERPAGEPF0 +
4748 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4749 qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4750 sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4751 qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4752 sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4758 * t4_init_tp_params - initialize adap->params.tp
4759 * @adap: the adapter
4761 * Initialize various fields of the adapter's TP Parameters structure.
4763 int t4_init_tp_params(struct adapter *adap)
4768 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4769 adap->params.tp.tre = G_TIMERRESOLUTION(v);
4770 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4772 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4773 for (chan = 0; chan < NCHAN; chan++)
4774 adap->params.tp.tx_modq[chan] = chan;
4777 * Cache the adapter's Compressed Filter Mode and global Incress
4780 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4781 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4782 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4783 &adap->params.tp.ingress_config, 1,
4784 A_TP_INGRESS_CONFIG);
4786 /* For T6, cache the adapter's compressed error vector
4787 * and passing outer header info for encapsulated packets.
4789 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4790 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
4791 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
4795 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4796 * shift positions of several elements of the Compressed Filter Tuple
4797 * for this adapter which we need frequently ...
4799 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4800 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4801 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4802 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4806 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4807 * represents the presense of an Outer VLAN instead of a VNIC ID.
4809 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4810 adap->params.tp.vnic_shift = -1;
4816 * t4_filter_field_shift - calculate filter field shift
4817 * @adap: the adapter
4818 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4820 * Return the shift position of a filter field within the Compressed
4821 * Filter Tuple. The filter field is specified via its selection bit
4822 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
4824 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4826 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4830 if ((filter_mode & filter_sel) == 0)
4833 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4834 switch (filter_mode & sel) {
4836 field_shift += W_FT_FCOE;
4839 field_shift += W_FT_PORT;
4842 field_shift += W_FT_VNIC_ID;
4845 field_shift += W_FT_VLAN;
4848 field_shift += W_FT_TOS;
4851 field_shift += W_FT_PROTOCOL;
4854 field_shift += W_FT_ETHERTYPE;
4857 field_shift += W_FT_MACMATCH;
4860 field_shift += W_FT_MPSHITTYPE;
4862 case F_FRAGMENTATION:
4863 field_shift += W_FT_FRAGMENTATION;
4870 int t4_init_rss_mode(struct adapter *adap, int mbox)
4873 struct fw_rss_vi_config_cmd rvc;
4875 memset(&rvc, 0, sizeof(rvc));
4877 for_each_port(adap, i) {
4878 struct port_info *p = adap2pinfo(adap, i);
4880 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4881 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4882 V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4883 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4884 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4887 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4892 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4896 struct fw_port_cmd c;
4898 memset(&c, 0, sizeof(c));
4900 for_each_port(adap, i) {
4901 unsigned int rss_size = 0;
4902 struct port_info *p = adap2pinfo(adap, i);
4904 while ((adap->params.portvec & (1 << j)) == 0)
4907 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4908 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4909 V_FW_PORT_CMD_PORTID(j));
4910 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4911 FW_PORT_ACTION_GET_PORT_INFO) |
4913 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4917 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4923 p->rss_size = rss_size;
4924 t4_os_set_hw_addr(adap, i, addr);
4926 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
4927 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
4928 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
4929 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
4930 p->mod_type = FW_PORT_MOD_TYPE_NA;
4932 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
4933 be16_to_cpu(c.u.info.acap));