4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <netinet/in.h>
36 #include <rte_interrupts.h>
38 #include <rte_debug.h>
40 #include <rte_atomic.h>
41 #include <rte_branch_prediction.h>
42 #include <rte_memory.h>
43 #include <rte_tailq.h>
45 #include <rte_alarm.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev_driver.h>
48 #include <rte_malloc.h>
49 #include <rte_random.h>
51 #include <rte_byteorder.h>
55 #include "t4_regs_values.h"
56 #include "t4fw_interface.h"
58 static void init_link_config(struct link_config *lc, unsigned int pcaps,
62 * t4_read_mtu_tbl - returns the values in the HW path MTU table
64 * @mtus: where to store the MTU values
65 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
67 * Reads the HW path MTU table.
69 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
74 for (i = 0; i < NMTUS; ++i) {
75 t4_write_reg(adap, A_TP_MTU_TABLE,
76 V_MTUINDEX(0xff) | V_MTUVALUE(i));
77 v = t4_read_reg(adap, A_TP_MTU_TABLE);
78 mtus[i] = G_MTUVALUE(v);
80 mtu_log[i] = G_MTUWIDTH(v);
85 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
87 * @addr: the indirect TP register address
88 * @mask: specifies the field within the register to modify
89 * @val: new value for the field
91 * Sets a field of an indirect TP register to the given value.
93 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
94 unsigned int mask, unsigned int val)
96 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
97 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
98 t4_write_reg(adap, A_TP_PIO_DATA, val);
101 /* The minimum additive increment value for the congestion control table */
102 #define CC_MIN_INCR 2U
105 * t4_load_mtus - write the MTU and congestion control HW tables
107 * @mtus: the values for the MTU table
108 * @alpha: the values for the congestion control alpha parameter
109 * @beta: the values for the congestion control beta parameter
111 * Write the HW MTU table with the supplied MTUs and the high-speed
112 * congestion control table with the supplied alpha, beta, and MTUs.
113 * We write the two tables together because the additive increments
114 * depend on the MTUs.
116 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
117 const unsigned short *alpha, const unsigned short *beta)
119 static const unsigned int avg_pkts[NCCTRL_WIN] = {
120 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
121 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
122 28672, 40960, 57344, 81920, 114688, 163840, 229376
127 for (i = 0; i < NMTUS; ++i) {
128 unsigned int mtu = mtus[i];
129 unsigned int log2 = cxgbe_fls(mtu);
131 if (!(mtu & ((1 << log2) >> 2))) /* round */
133 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
134 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
136 for (w = 0; w < NCCTRL_WIN; ++w) {
139 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
142 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
143 (w << 16) | (beta[w] << 13) | inc);
149 * t4_wait_op_done_val - wait until an operation is completed
150 * @adapter: the adapter performing the operation
151 * @reg: the register to check for completion
152 * @mask: a single-bit field within @reg that indicates completion
153 * @polarity: the value of the field when the operation is completed
154 * @attempts: number of check iterations
155 * @delay: delay in usecs between iterations
156 * @valp: where to store the value of the register at completion time
158 * Wait until an operation is completed by checking a bit in a register
159 * up to @attempts times. If @valp is not NULL the value of the register
160 * at the time it indicated completion is stored there. Returns 0 if the
161 * operation completes and -EAGAIN otherwise.
163 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
164 int polarity, int attempts, int delay, u32 *valp)
167 u32 val = t4_read_reg(adapter, reg);
169 if (!!(val & mask) == polarity) {
182 * t4_set_reg_field - set a register field to a value
183 * @adapter: the adapter to program
184 * @addr: the register address
185 * @mask: specifies the portion of the register to modify
186 * @val: the new value for the register field
188 * Sets a register field specified by the supplied mask to the
191 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
194 u32 v = t4_read_reg(adapter, addr) & ~mask;
196 t4_write_reg(adapter, addr, v | val);
197 (void)t4_read_reg(adapter, addr); /* flush */
201 * t4_read_indirect - read indirectly addressed registers
203 * @addr_reg: register holding the indirect address
204 * @data_reg: register holding the value of the indirect register
205 * @vals: where the read register values are stored
206 * @nregs: how many indirect registers to read
207 * @start_idx: index of first indirect register to read
209 * Reads registers that are accessed indirectly through an address/data
212 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
213 unsigned int data_reg, u32 *vals, unsigned int nregs,
214 unsigned int start_idx)
217 t4_write_reg(adap, addr_reg, start_idx);
218 *vals++ = t4_read_reg(adap, data_reg);
224 * t4_write_indirect - write indirectly addressed registers
226 * @addr_reg: register holding the indirect addresses
227 * @data_reg: register holding the value for the indirect registers
228 * @vals: values to write
229 * @nregs: how many indirect registers to write
230 * @start_idx: address of first indirect register to write
232 * Writes a sequential block of registers that are accessed indirectly
233 * through an address/data register pair.
235 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
236 unsigned int data_reg, const u32 *vals,
237 unsigned int nregs, unsigned int start_idx)
240 t4_write_reg(adap, addr_reg, start_idx++);
241 t4_write_reg(adap, data_reg, *vals++);
246 * t4_report_fw_error - report firmware error
249 * The adapter firmware can indicate error conditions to the host.
250 * If the firmware has indicated an error, print out the reason for
251 * the firmware error.
253 static void t4_report_fw_error(struct adapter *adap)
255 static const char * const reason[] = {
256 "Crash", /* PCIE_FW_EVAL_CRASH */
257 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
258 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
259 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
260 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
261 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
262 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
263 "Reserved", /* reserved */
267 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
268 if (pcie_fw & F_PCIE_FW_ERR)
269 pr_err("%s: Firmware reports adapter error: %s\n",
270 __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
274 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
276 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
279 for ( ; nflit; nflit--, mbox_addr += 8)
280 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
284 * Handle a FW assertion reported in a mailbox.
286 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
288 struct fw_debug_cmd asrt;
290 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
291 pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
292 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
293 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
296 #define X_CIM_PF_NOACCESS 0xeeeeeeee
299 * If the Host OS Driver needs locking arround accesses to the mailbox, this
300 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
302 /* makes single-statement usage a bit cleaner ... */
303 #ifdef T4_OS_NEEDS_MBOX_LOCKING
304 #define T4_OS_MBOX_LOCKING(x) x
306 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
310 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
312 * @mbox: index of the mailbox to use
313 * @cmd: the command to write
314 * @size: command length in bytes
315 * @rpl: where to optionally store the reply
316 * @sleep_ok: if true we may sleep while awaiting command completion
317 * @timeout: time to wait for command to finish before timing out
318 * (negative implies @sleep_ok=false)
320 * Sends the given command to FW through the selected mailbox and waits
321 * for the FW to execute the command. If @rpl is not %NULL it is used to
322 * store the FW's reply to the command. The command and its optional
323 * reply are of the same length. Some FW commands like RESET and
324 * INITIALIZE can take a considerable amount of time to execute.
325 * @sleep_ok determines whether we may sleep while awaiting the response.
326 * If sleeping is allowed we use progressive backoff otherwise we spin.
327 * Note that passing in a negative @timeout is an alternate mechanism
328 * for specifying @sleep_ok=false. This is useful when a higher level
329 * interface allows for specification of @timeout but not @sleep_ok ...
331 * Returns 0 on success or a negative errno on failure. A
332 * failure can happen either because we are not able to execute the
333 * command or FW executes it but signals an error. In the latter case
334 * the return value is the error code indicated by FW (negated).
336 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
337 const void __attribute__((__may_alias__)) *cmd,
338 int size, void *rpl, bool sleep_ok, int timeout)
341 * We delay in small increments at first in an effort to maintain
342 * responsiveness for simple, fast executing commands but then back
343 * off to larger delays to a maximum retry delay.
345 static const int delay[] = {
346 1, 1, 3, 5, 10, 10, 20, 50, 100
352 unsigned int delay_idx;
353 __be64 *temp = (__be64 *)malloc(size * sizeof(char));
355 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
356 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
358 struct mbox_entry entry;
364 if ((size & 15) || size > MBOX_LEN) {
370 memcpy(p, (const __be64 *)cmd, size);
373 * If we have a negative timeout, that implies that we can't sleep.
380 #ifdef T4_OS_NEEDS_MBOX_LOCKING
382 * Queue ourselves onto the mailbox access list. When our entry is at
383 * the front of the list, we have rights to access the mailbox. So we
384 * wait [for a while] till we're at the front [or bail out with an
387 t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
392 for (i = 0; ; i += ms) {
394 * If we've waited too long, return a busy indication. This
395 * really ought to be based on our initial position in the
396 * mailbox access list but this is a start. We very rarely
397 * contend on access to the mailbox ... Also check for a
398 * firmware error which we'll report as a device error.
400 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
401 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
402 t4_os_atomic_list_del(&entry, &adap->mbox_list,
404 t4_report_fw_error(adap);
406 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
410 * If we're at the head, break out and start the mailbox
413 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
417 * Delay for a bit before checking again ...
420 ms = delay[delay_idx]; /* last element may repeat */
421 if (delay_idx < ARRAY_SIZE(delay) - 1)
428 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
431 * Attempt to gain access to the mailbox.
433 for (i = 0; i < 4; i++) {
434 ctl = t4_read_reg(adap, ctl_reg);
436 if (v != X_MBOWNER_NONE)
441 * If we were unable to gain access, dequeue ourselves from the
442 * mailbox atomic access list and report the error to our caller.
444 if (v != X_MBOWNER_PL) {
445 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
448 t4_report_fw_error(adap);
450 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
454 * If we gain ownership of the mailbox and there's a "valid" message
455 * in it, this is likely an asynchronous error message from the
456 * firmware. So we'll report that and then proceed on with attempting
457 * to issue our own command ... which may well fail if the error
458 * presaged the firmware crashing ...
460 if (ctl & F_MBMSGVALID) {
461 dev_err(adap, "found VALID command in mbox %u: "
462 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
463 (unsigned long long)t4_read_reg64(adap, data_reg),
464 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
465 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
466 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
467 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
468 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
469 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
470 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
474 * Copy in the new mailbox command and send it on its way ...
476 for (i = 0; i < size; i += 8, p++)
477 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
479 CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
480 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
481 (unsigned long long)t4_read_reg64(adap, data_reg),
482 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
483 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
484 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
485 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
486 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
487 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
488 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
490 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
491 t4_read_reg(adap, ctl_reg); /* flush write */
497 * Loop waiting for the reply; bail out if we time out or the firmware
500 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
501 for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
503 ms = delay[delay_idx]; /* last element may repeat */
504 if (delay_idx < ARRAY_SIZE(delay) - 1)
511 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
512 v = t4_read_reg(adap, ctl_reg);
513 if (v == X_CIM_PF_NOACCESS)
515 if (G_MBOWNER(v) == X_MBOWNER_PL) {
516 if (!(v & F_MBMSGVALID)) {
517 t4_write_reg(adap, ctl_reg,
518 V_MBOWNER(X_MBOWNER_NONE));
522 CXGBE_DEBUG_MBOX(adap,
523 "%s: mbox %u: %016llx %016llx %016llx %016llx "
524 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
525 (unsigned long long)t4_read_reg64(adap, data_reg),
526 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
527 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
528 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
529 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
530 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
531 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
532 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
534 CXGBE_DEBUG_MBOX(adap,
535 "command %#x completed in %d ms (%ssleeping)\n",
537 i + ms, sleep_ok ? "" : "non-");
539 res = t4_read_reg64(adap, data_reg);
540 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
541 fw_asrt(adap, data_reg);
542 res = V_FW_CMD_RETVAL(EIO);
544 get_mbox_rpl(adap, rpl, size / 8, data_reg);
546 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
548 t4_os_atomic_list_del(&entry, &adap->mbox_list,
551 return -G_FW_CMD_RETVAL((int)res);
556 * We timed out waiting for a reply to our mailbox command. Report
557 * the error and also check to see if the firmware reported any
560 dev_err(adap, "command %#x in mailbox %d timed out\n",
561 *(const u8 *)cmd, mbox);
562 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
565 t4_report_fw_error(adap);
567 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
570 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
571 void *rpl, bool sleep_ok)
573 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
578 * t4_get_regs_len - return the size of the chips register set
579 * @adapter: the adapter
581 * Returns the size of the chip's BAR0 register space.
583 unsigned int t4_get_regs_len(struct adapter *adapter)
585 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
587 switch (chip_version) {
590 return T5_REGMAP_SIZE;
594 "Unsupported chip version %d\n", chip_version);
599 * t4_get_regs - read chip registers into provided buffer
601 * @buf: register buffer
602 * @buf_size: size (in bytes) of register buffer
604 * If the provided register buffer isn't large enough for the chip's
605 * full register range, the register dump will be truncated to the
606 * register buffer's size.
608 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
610 static const unsigned int t5_reg_ranges[] = {
1385 static const unsigned int t6_reg_ranges[] = {
1946 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1947 const unsigned int *reg_ranges;
1948 int reg_ranges_size, range;
1949 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1951 /* Select the right set of register ranges to dump depending on the
1952 * adapter chip type.
1954 switch (chip_version) {
1956 reg_ranges = t5_reg_ranges;
1957 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1961 reg_ranges = t6_reg_ranges;
1962 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1967 "Unsupported chip version %d\n", chip_version);
1971 /* Clear the register buffer and insert the appropriate register
1972 * values selected by the above register ranges.
1974 memset(buf, 0, buf_size);
1975 for (range = 0; range < reg_ranges_size; range += 2) {
1976 unsigned int reg = reg_ranges[range];
1977 unsigned int last_reg = reg_ranges[range + 1];
1978 u32 *bufp = (u32 *)((char *)buf + reg);
1980 /* Iterate across the register range filling in the register
1981 * buffer but don't write past the end of the register buffer.
1983 while (reg <= last_reg && bufp < buf_end) {
1984 *bufp++ = t4_read_reg(adap, reg);
1990 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1991 #define EEPROM_DELAY 10 /* 10us per poll spin */
1992 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
1994 #define EEPROM_STAT_ADDR 0x7bfc
1997 * Small utility function to wait till any outstanding VPD Access is complete.
1998 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1999 * VPD Access in flight. This allows us to handle the problem of having a
2000 * previous VPD Access time out and prevent an attempt to inject a new VPD
2001 * Request before any in-flight VPD request has completed.
2003 static int t4_seeprom_wait(struct adapter *adapter)
2005 unsigned int base = adapter->params.pci.vpd_cap_addr;
2008 /* If no VPD Access is in flight, we can just return success right
2011 if (!adapter->vpd_busy)
2014 /* Poll the VPD Capability Address/Flag register waiting for it
2015 * to indicate that the operation is complete.
2017 max_poll = EEPROM_MAX_POLL;
2021 udelay(EEPROM_DELAY);
2022 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2024 /* If the operation is complete, mark the VPD as no longer
2025 * busy and return success.
2027 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2028 adapter->vpd_busy = 0;
2031 } while (--max_poll);
2033 /* Failure! Note that we leave the VPD Busy status set in order to
2034 * avoid pushing a new VPD Access request into the VPD Capability till
2035 * the current operation eventually succeeds. It's a bug to issue a
2036 * new request when an existing request is in flight and will result
2037 * in corrupt hardware state.
2043 * t4_seeprom_read - read a serial EEPROM location
2044 * @adapter: adapter to read
2045 * @addr: EEPROM virtual address
2046 * @data: where to store the read data
2048 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2049 * VPD capability. Note that this function must be called with a virtual
2052 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2054 unsigned int base = adapter->params.pci.vpd_cap_addr;
2057 /* VPD Accesses must alway be 4-byte aligned!
2059 if (addr >= EEPROMVSIZE || (addr & 3))
2062 /* Wait for any previous operation which may still be in flight to
2065 ret = t4_seeprom_wait(adapter);
2067 dev_err(adapter, "VPD still busy from previous operation\n");
2071 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2072 * for our request to complete. If it doesn't complete, note the
2073 * error and return it to our caller. Note that we do not reset the
2076 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2077 adapter->vpd_busy = 1;
2078 adapter->vpd_flag = PCI_VPD_ADDR_F;
2079 ret = t4_seeprom_wait(adapter);
2081 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2085 /* Grab the returned data, swizzle it into our endianness and
2088 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2089 *data = le32_to_cpu(*data);
2094 * t4_seeprom_write - write a serial EEPROM location
2095 * @adapter: adapter to write
2096 * @addr: virtual EEPROM address
2097 * @data: value to write
2099 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2100 * VPD capability. Note that this function must be called with a virtual
2103 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2105 unsigned int base = adapter->params.pci.vpd_cap_addr;
2110 /* VPD Accesses must alway be 4-byte aligned!
2112 if (addr >= EEPROMVSIZE || (addr & 3))
2115 /* Wait for any previous operation which may still be in flight to
2118 ret = t4_seeprom_wait(adapter);
2120 dev_err(adapter, "VPD still busy from previous operation\n");
2124 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2125 * for our request to complete. If it doesn't complete, note the
2126 * error and return it to our caller. Note that we do not reset the
2129 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2131 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2132 (u16)addr | PCI_VPD_ADDR_F);
2133 adapter->vpd_busy = 1;
2134 adapter->vpd_flag = 0;
2135 ret = t4_seeprom_wait(adapter);
2137 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2141 /* Reset PCI_VPD_DATA register after a transaction and wait for our
2142 * request to complete. If it doesn't complete, return error.
2144 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2145 max_poll = EEPROM_MAX_POLL;
2147 udelay(EEPROM_DELAY);
2148 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2149 } while ((stats_reg & 0x1) && --max_poll);
2153 /* Return success! */
2158 * t4_seeprom_wp - enable/disable EEPROM write protection
2159 * @adapter: the adapter
2160 * @enable: whether to enable or disable write protection
2162 * Enables or disables write protection on the serial EEPROM.
2164 int t4_seeprom_wp(struct adapter *adapter, int enable)
2166 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2170 * t4_fw_tp_pio_rw - Access TP PIO through LDST
2171 * @adap: the adapter
2172 * @vals: where the indirect register values are stored/written
2173 * @nregs: how many indirect registers to read/write
2174 * @start_idx: index of first indirect register to read/write
2175 * @rw: Read (1) or Write (0)
2177 * Access TP PIO registers through LDST
2179 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
2180 unsigned int start_index, unsigned int rw)
2182 int cmd = FW_LDST_ADDRSPC_TP_PIO;
2183 struct fw_ldst_cmd c;
2187 for (i = 0 ; i < nregs; i++) {
2188 memset(&c, 0, sizeof(c));
2189 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
2191 (rw ? F_FW_CMD_READ :
2193 V_FW_LDST_CMD_ADDRSPACE(cmd));
2194 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
2196 c.u.addrval.addr = cpu_to_be32(start_index + i);
2197 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
2198 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2201 vals[i] = be32_to_cpu(c.u.addrval.val);
2207 * t4_read_rss_key - read the global RSS key
2208 * @adap: the adapter
2209 * @key: 10-entry array holding the 320-bit RSS key
2211 * Reads the global 320-bit RSS key.
2213 void t4_read_rss_key(struct adapter *adap, u32 *key)
2215 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 1);
2219 * t4_write_rss_key - program one of the RSS keys
2220 * @adap: the adapter
2221 * @key: 10-entry array holding the 320-bit RSS key
2222 * @idx: which RSS key to write
2224 * Writes one of the RSS keys with the given 320-bit value. If @idx is
2225 * 0..15 the corresponding entry in the RSS key table is written,
2226 * otherwise the global RSS key is written.
2228 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
2230 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
2231 u8 rss_key_addr_cnt = 16;
2233 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
2234 * allows access to key addresses 16-63 by using KeyWrAddrX
2235 * as index[5:4](upper 2) into key table
2237 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
2238 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
2239 rss_key_addr_cnt = 32;
2241 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
2243 if (idx >= 0 && idx < rss_key_addr_cnt) {
2244 if (rss_key_addr_cnt > 16)
2245 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2246 V_KEYWRADDRX(idx >> 4) |
2247 V_T6_VFWRADDR(idx) | F_KEYWREN);
2249 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2250 V_KEYWRADDR(idx) | F_KEYWREN);
2255 * t4_config_rss_range - configure a portion of the RSS mapping table
2256 * @adapter: the adapter
2257 * @mbox: mbox to use for the FW command
2258 * @viid: virtual interface whose RSS subtable is to be written
2259 * @start: start entry in the table to write
2260 * @n: how many table entries to write
2261 * @rspq: values for the "response queue" (Ingress Queue) lookup table
2262 * @nrspq: number of values in @rspq
2264 * Programs the selected part of the VI's RSS mapping table with the
2265 * provided values. If @nrspq < @n the supplied values are used repeatedly
2266 * until the full table range is populated.
2268 * The caller must ensure the values in @rspq are in the range allowed for
2271 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2272 int start, int n, const u16 *rspq, unsigned int nrspq)
2275 const u16 *rsp = rspq;
2276 const u16 *rsp_end = rspq + nrspq;
2277 struct fw_rss_ind_tbl_cmd cmd;
2279 memset(&cmd, 0, sizeof(cmd));
2280 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2281 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2282 V_FW_RSS_IND_TBL_CMD_VIID(viid));
2283 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2286 * Each firmware RSS command can accommodate up to 32 RSS Ingress
2287 * Queue Identifiers. These Ingress Queue IDs are packed three to
2288 * a 32-bit word as 10-bit values with the upper remaining 2 bits
2292 int nq = min(n, 32);
2294 __be32 *qp = &cmd.iq0_to_iq2;
2297 * Set up the firmware RSS command header to send the next
2298 * "nq" Ingress Queue IDs to the firmware.
2300 cmd.niqid = cpu_to_be16(nq);
2301 cmd.startidx = cpu_to_be16(start);
2304 * "nq" more done for the start of the next loop.
2310 * While there are still Ingress Queue IDs to stuff into the
2311 * current firmware RSS command, retrieve them from the
2312 * Ingress Queue ID array and insert them into the command.
2316 * Grab up to the next 3 Ingress Queue IDs (wrapping
2317 * around the Ingress Queue ID array if necessary) and
2318 * insert them into the firmware RSS command at the
2319 * current 3-tuple position within the commad.
2323 int nqbuf = min(3, nq);
2329 while (nqbuf && nq_packed < 32) {
2336 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2337 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2338 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2342 * Send this portion of the RRS table update to the firmware;
2343 * bail out on any errors.
2345 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2354 * t4_config_vi_rss - configure per VI RSS settings
2355 * @adapter: the adapter
2356 * @mbox: mbox to use for the FW command
2359 * @defq: id of the default RSS queue for the VI.
2361 * Configures VI-specific RSS properties.
2363 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2364 unsigned int flags, unsigned int defq)
2366 struct fw_rss_vi_config_cmd c;
2368 memset(&c, 0, sizeof(c));
2369 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2370 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2371 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2372 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2373 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2374 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2375 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2379 * t4_read_config_vi_rss - read the configured per VI RSS settings
2380 * @adapter: the adapter
2381 * @mbox: mbox to use for the FW command
2383 * @flags: where to place the configured flags
2384 * @defq: where to place the id of the default RSS queue for the VI.
2386 * Read configured VI-specific RSS properties.
2388 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2389 u64 *flags, unsigned int *defq)
2391 struct fw_rss_vi_config_cmd c;
2392 unsigned int result;
2395 memset(&c, 0, sizeof(c));
2396 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2397 F_FW_CMD_REQUEST | F_FW_CMD_READ |
2398 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2399 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2400 ret = t4_wr_mbox(adapter, mbox, &c, sizeof(c), &c);
2402 result = be32_to_cpu(c.u.basicvirtual.defaultq_to_udpen);
2404 *defq = G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(result);
2406 *flags = result & M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ;
2413 * init_cong_ctrl - initialize congestion control parameters
2414 * @a: the alpha values for congestion control
2415 * @b: the beta values for congestion control
2417 * Initialize the congestion control parameters.
2419 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2423 for (i = 0; i < 9; i++) {
2477 #define INIT_CMD(var, cmd, rd_wr) do { \
2478 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2479 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2480 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2483 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2485 u32 cclk_param, cclk_val;
2489 * Ask firmware for the Core Clock since it knows how to translate the
2490 * Reference Clock ('V2') VPD field into a Core Clock value ...
2492 cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2493 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2494 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2495 1, &cclk_param, &cclk_val);
2497 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2503 dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2507 /* serial flash and firmware constants and flash config file constants */
2509 SF_ATTEMPTS = 10, /* max retries for SF operations */
2511 /* flash command opcodes */
2512 SF_PROG_PAGE = 2, /* program page */
2513 SF_WR_DISABLE = 4, /* disable writes */
2514 SF_RD_STATUS = 5, /* read status register */
2515 SF_WR_ENABLE = 6, /* enable writes */
2516 SF_RD_DATA_FAST = 0xb, /* read flash */
2517 SF_RD_ID = 0x9f, /* read ID */
2518 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2522 * sf1_read - read data from the serial flash
2523 * @adapter: the adapter
2524 * @byte_cnt: number of bytes to read
2525 * @cont: whether another operation will be chained
2526 * @lock: whether to lock SF for PL access only
2527 * @valp: where to store the read data
2529 * Reads up to 4 bytes of data from the serial flash. The location of
2530 * the read needs to be specified prior to calling this by issuing the
2531 * appropriate commands to the serial flash.
2533 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2534 int lock, u32 *valp)
2538 if (!byte_cnt || byte_cnt > 4)
2540 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2542 t4_write_reg(adapter, A_SF_OP,
2543 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2544 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2546 *valp = t4_read_reg(adapter, A_SF_DATA);
2551 * sf1_write - write data to the serial flash
2552 * @adapter: the adapter
2553 * @byte_cnt: number of bytes to write
2554 * @cont: whether another operation will be chained
2555 * @lock: whether to lock SF for PL access only
2556 * @val: value to write
2558 * Writes up to 4 bytes of data to the serial flash. The location of
2559 * the write needs to be specified prior to calling this by issuing the
2560 * appropriate commands to the serial flash.
2562 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2565 if (!byte_cnt || byte_cnt > 4)
2567 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2569 t4_write_reg(adapter, A_SF_DATA, val);
2570 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2571 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2572 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2576 * t4_read_flash - read words from serial flash
2577 * @adapter: the adapter
2578 * @addr: the start address for the read
2579 * @nwords: how many 32-bit words to read
2580 * @data: where to store the read data
2581 * @byte_oriented: whether to store data as bytes or as words
2583 * Read the specified number of 32-bit words from the serial flash.
2584 * If @byte_oriented is set the read data is stored as a byte array
2585 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2586 * natural endianness.
2588 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2589 unsigned int nwords, u32 *data, int byte_oriented)
2593 if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2597 addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2599 ret = sf1_write(adapter, 4, 1, 0, addr);
2603 ret = sf1_read(adapter, 1, 1, 0, data);
2607 for ( ; nwords; nwords--, data++) {
2608 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2610 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
2614 *data = cpu_to_be32(*data);
2620 * t4_get_exprom_version - return the Expansion ROM version (if any)
2621 * @adapter: the adapter
2622 * @vers: where to place the version
2624 * Reads the Expansion ROM header from FLASH and returns the version
2625 * number (if present) through the @vers return value pointer. We return
2626 * this in the Firmware Version Format since it's convenient. Return
2627 * 0 on success, -ENOENT if no Expansion ROM is present.
2629 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2631 struct exprom_header {
2632 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2633 unsigned char hdr_ver[4]; /* Expansion ROM version */
2635 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2639 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2640 ARRAY_SIZE(exprom_header_buf),
2641 exprom_header_buf, 0);
2645 hdr = (struct exprom_header *)exprom_header_buf;
2646 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2649 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2650 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2651 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2652 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2657 * t4_get_fw_version - read the firmware version
2658 * @adapter: the adapter
2659 * @vers: where to place the version
2661 * Reads the FW version from flash.
2663 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2665 return t4_read_flash(adapter, FLASH_FW_START +
2666 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2670 * t4_get_bs_version - read the firmware bootstrap version
2671 * @adapter: the adapter
2672 * @vers: where to place the version
2674 * Reads the FW Bootstrap version from flash.
2676 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2678 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2679 offsetof(struct fw_hdr, fw_ver), 1,
2684 * t4_get_tp_version - read the TP microcode version
2685 * @adapter: the adapter
2686 * @vers: where to place the version
2688 * Reads the TP microcode version from flash.
2690 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2692 return t4_read_flash(adapter, FLASH_FW_START +
2693 offsetof(struct fw_hdr, tp_microcode_ver),
2698 * t4_get_version_info - extract various chip/firmware version information
2699 * @adapter: the adapter
2701 * Reads various chip/firmware version numbers and stores them into the
2702 * adapter Adapter Parameters structure. If any of the efforts fails
2703 * the first failure will be returned, but all of the version numbers
2706 int t4_get_version_info(struct adapter *adapter)
2710 #define FIRST_RET(__getvinfo) \
2712 int __ret = __getvinfo; \
2713 if (__ret && !ret) \
2717 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2718 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2719 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2720 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2728 * t4_dump_version_info - dump all of the adapter configuration IDs
2729 * @adapter: the adapter
2731 * Dumps all of the various bits of adapter configuration version/revision
2732 * IDs information. This is typically called at some point after
2733 * t4_get_version_info() has been called.
2735 void t4_dump_version_info(struct adapter *adapter)
2738 * Device information.
2740 dev_info(adapter, "Chelsio rev %d\n",
2741 CHELSIO_CHIP_RELEASE(adapter->params.chip));
2746 if (!adapter->params.fw_vers)
2747 dev_warn(adapter, "No firmware loaded\n");
2749 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2750 G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2751 G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2752 G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2753 G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2756 * Bootstrap Firmware Version.
2758 if (!adapter->params.bs_vers)
2759 dev_warn(adapter, "No bootstrap loaded\n");
2761 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2762 G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2763 G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2764 G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2765 G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2768 * TP Microcode Version.
2770 if (!adapter->params.tp_vers)
2771 dev_warn(adapter, "No TP Microcode loaded\n");
2773 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2774 G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2775 G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2776 G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2777 G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2780 * Expansion ROM version.
2782 if (!adapter->params.er_vers)
2783 dev_info(adapter, "No Expansion ROM loaded\n");
2785 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2786 G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2787 G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2788 G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2789 G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2792 #define ADVERT_MASK (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) | \
2795 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
2796 * @caps16: a 16-bit Port Capabilities value
2798 * Returns the equivalent 32-bit Port Capabilities value.
2800 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
2802 fw_port_cap32_t caps32 = 0;
2804 #define CAP16_TO_CAP32(__cap) \
2806 if (caps16 & FW_PORT_CAP_##__cap) \
2807 caps32 |= FW_PORT_CAP32_##__cap; \
2810 CAP16_TO_CAP32(SPEED_100M);
2811 CAP16_TO_CAP32(SPEED_1G);
2812 CAP16_TO_CAP32(SPEED_25G);
2813 CAP16_TO_CAP32(SPEED_10G);
2814 CAP16_TO_CAP32(SPEED_40G);
2815 CAP16_TO_CAP32(SPEED_100G);
2816 CAP16_TO_CAP32(FC_RX);
2817 CAP16_TO_CAP32(FC_TX);
2818 CAP16_TO_CAP32(ANEG);
2819 CAP16_TO_CAP32(MDIX);
2820 CAP16_TO_CAP32(MDIAUTO);
2821 CAP16_TO_CAP32(FEC_RS);
2822 CAP16_TO_CAP32(FEC_BASER_RS);
2823 CAP16_TO_CAP32(802_3_PAUSE);
2824 CAP16_TO_CAP32(802_3_ASM_DIR);
2826 #undef CAP16_TO_CAP32
2832 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
2833 * @caps32: a 32-bit Port Capabilities value
2835 * Returns the equivalent 16-bit Port Capabilities value. Note that
2836 * not all 32-bit Port Capabilities can be represented in the 16-bit
2837 * Port Capabilities and some fields/values may not make it.
2839 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
2841 fw_port_cap16_t caps16 = 0;
2843 #define CAP32_TO_CAP16(__cap) \
2845 if (caps32 & FW_PORT_CAP32_##__cap) \
2846 caps16 |= FW_PORT_CAP_##__cap; \
2849 CAP32_TO_CAP16(SPEED_100M);
2850 CAP32_TO_CAP16(SPEED_1G);
2851 CAP32_TO_CAP16(SPEED_10G);
2852 CAP32_TO_CAP16(SPEED_25G);
2853 CAP32_TO_CAP16(SPEED_40G);
2854 CAP32_TO_CAP16(SPEED_100G);
2855 CAP32_TO_CAP16(FC_RX);
2856 CAP32_TO_CAP16(FC_TX);
2857 CAP32_TO_CAP16(802_3_PAUSE);
2858 CAP32_TO_CAP16(802_3_ASM_DIR);
2859 CAP32_TO_CAP16(ANEG);
2860 CAP32_TO_CAP16(MDIX);
2861 CAP32_TO_CAP16(MDIAUTO);
2862 CAP32_TO_CAP16(FEC_RS);
2863 CAP32_TO_CAP16(FEC_BASER_RS);
2865 #undef CAP32_TO_CAP16
2870 /* Translate Firmware Pause specification to Common Code */
2871 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
2873 enum cc_pause cc_pause = 0;
2875 if (fw_pause & FW_PORT_CAP32_FC_RX)
2876 cc_pause |= PAUSE_RX;
2877 if (fw_pause & FW_PORT_CAP32_FC_TX)
2878 cc_pause |= PAUSE_TX;
2883 /* Translate Common Code Pause Frame specification into Firmware */
2884 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
2886 fw_port_cap32_t fw_pause = 0;
2888 if (cc_pause & PAUSE_RX)
2889 fw_pause |= FW_PORT_CAP32_FC_RX;
2890 if (cc_pause & PAUSE_TX)
2891 fw_pause |= FW_PORT_CAP32_FC_TX;
2896 /* Translate Firmware Forward Error Correction specification to Common Code */
2897 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
2899 enum cc_fec cc_fec = 0;
2901 if (fw_fec & FW_PORT_CAP32_FEC_RS)
2903 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
2904 cc_fec |= FEC_BASER_RS;
2909 /* Translate Common Code Forward Error Correction specification to Firmware */
2910 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
2912 fw_port_cap32_t fw_fec = 0;
2914 if (cc_fec & FEC_RS)
2915 fw_fec |= FW_PORT_CAP32_FEC_RS;
2916 if (cc_fec & FEC_BASER_RS)
2917 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
2923 * t4_link_l1cfg - apply link configuration to MAC/PHY
2924 * @adapter: the adapter
2925 * @mbox: the Firmware Mailbox to use
2926 * @port: the Port ID
2927 * @lc: the Port's Link Configuration
2929 * Set up a port's MAC and PHY according to a desired link configuration.
2930 * - If the PHY can auto-negotiate first decide what to advertise, then
2931 * enable/disable auto-negotiation as desired, and reset.
2932 * - If the PHY does not auto-negotiate just reset it.
2933 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2934 * otherwise do it later based on the outcome of auto-negotiation.
2936 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2937 struct link_config *lc)
2939 unsigned int fw_mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
2940 unsigned int fw_caps = adap->params.fw_caps_support;
2941 fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
2942 struct fw_port_cmd cmd;
2946 fw_fc = cc_to_fwcap_pause(lc->requested_fc);
2948 /* Convert Common Code Forward Error Control settings into the
2949 * Firmware's API. If the current Requested FEC has "Automatic"
2950 * (IEEE 802.3) specified, then we use whatever the Firmware
2951 * sent us as part of it's IEEE 802.3-based interpratation of
2952 * the Transceiver Module EPROM FEC parameters. Otherwise we
2953 * use whatever is in the current Requested FEC settings.
2955 if (lc->requested_fec & FEC_AUTO)
2956 cc_fec = lc->auto_fec;
2958 cc_fec = lc->requested_fec;
2959 fw_fec = cc_to_fwcap_fec(cc_fec);
2961 /* Figure out what our Requested Port Capabilities are going to be.
2963 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
2964 rcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
2965 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2967 } else if (lc->autoneg == AUTONEG_DISABLE) {
2968 rcap = lc->requested_speed | fw_fc | fw_fec | fw_mdi;
2969 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2972 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
2975 /* And send that on to the Firmware ...
2977 memset(&cmd, 0, sizeof(cmd));
2978 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2979 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2980 V_FW_PORT_CMD_PORTID(port));
2981 cmd.action_to_len16 =
2982 cpu_to_be32(V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16 ?
2983 FW_PORT_ACTION_L1_CFG :
2984 FW_PORT_ACTION_L1_CFG32) |
2987 if (fw_caps == FW_CAPS16)
2988 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
2990 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
2992 return t4_wr_mbox(adap, mbox, &cmd, sizeof(cmd), NULL);
2996 * t4_flash_cfg_addr - return the address of the flash configuration file
2997 * @adapter: the adapter
2999 * Return the address within the flash where the Firmware Configuration
3000 * File is stored, or an error if the device FLASH is too small to contain
3001 * a Firmware Configuration File.
3003 int t4_flash_cfg_addr(struct adapter *adapter)
3006 * If the device FLASH isn't large enough to hold a Firmware
3007 * Configuration File, return an error.
3009 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3012 return FLASH_CFG_START;
3015 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
3018 * t4_intr_enable - enable interrupts
3019 * @adapter: the adapter whose interrupts should be enabled
3021 * Enable PF-specific interrupts for the calling function and the top-level
3022 * interrupt concentrator for global interrupts. Interrupts are already
3023 * enabled at each module, here we just enable the roots of the interrupt
3026 * Note: this function should be called only when the driver manages
3027 * non PF-specific interrupts from the various HW modules. Only one PCI
3028 * function at a time should be doing this.
3030 void t4_intr_enable(struct adapter *adapter)
3033 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3034 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
3035 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
3037 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3038 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
3039 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
3040 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
3041 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
3042 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
3043 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
3044 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
3045 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
3046 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
3047 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
3051 * t4_intr_disable - disable interrupts
3052 * @adapter: the adapter whose interrupts should be disabled
3054 * Disable interrupts. We only disable the top-level interrupt
3055 * concentrators. The caller must be a PCI function managing global
3058 void t4_intr_disable(struct adapter *adapter)
3060 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3061 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
3062 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
3064 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
3065 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
3069 * t4_get_port_type_description - return Port Type string description
3070 * @port_type: firmware Port Type enumeration
3072 const char *t4_get_port_type_description(enum fw_port_type port_type)
3074 static const char * const port_type_description[] = {
3099 if (port_type < ARRAY_SIZE(port_type_description))
3100 return port_type_description[port_type];
3105 * t4_get_mps_bg_map - return the buffer groups associated with a port
3106 * @adap: the adapter
3107 * @pidx: the port index
3109 * Returns a bitmap indicating which MPS buffer groups are associated
3110 * with the given port. Bit i is set if buffer group i is used by the
3113 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
3115 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3116 unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
3119 if (pidx >= nports) {
3120 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
3125 switch (chip_version) {
3130 case 2: return 3 << (2 * pidx);
3131 case 4: return 1 << pidx;
3137 case 2: return 1 << (2 * pidx);
3142 dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
3143 chip_version, nports);
3148 * t4_get_tp_ch_map - return TP ingress channels associated with a port
3149 * @adapter: the adapter
3150 * @pidx: the port index
3152 * Returns a bitmap indicating which TP Ingress Channels are associated with
3153 * a given Port. Bit i is set if TP Ingress Channel i is used by the Port.
3155 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
3157 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
3158 unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
3161 if (pidx >= nports) {
3162 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
3167 switch (chip_version) {
3170 /* Note that this happens to be the same values as the MPS
3171 * Buffer Group Map for these Chips. But we replicate the code
3172 * here because they're really separate concepts.
3176 case 2: return 3 << (2 * pidx);
3177 case 4: return 1 << pidx;
3183 case 2: return 1 << pidx;
3188 dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
3189 chip_version, nports);
3194 * t4_get_port_stats - collect port statistics
3195 * @adap: the adapter
3196 * @idx: the port index
3197 * @p: the stats structure to fill
3199 * Collect statistics related to the given port from HW.
3201 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
3203 u32 bgmap = t4_get_mps_bg_map(adap, idx);
3204 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
3206 #define GET_STAT(name) \
3207 t4_read_reg64(adap, \
3208 (is_t4(adap->params.chip) ? \
3209 PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
3210 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
3211 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
3213 p->tx_octets = GET_STAT(TX_PORT_BYTES);
3214 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
3215 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
3216 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
3217 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
3218 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
3219 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
3220 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
3221 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
3222 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
3223 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
3224 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
3225 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
3226 p->tx_drop = GET_STAT(TX_PORT_DROP);
3227 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
3228 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
3229 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
3230 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
3231 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
3232 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
3233 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
3234 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
3235 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
3237 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3238 if (stat_ctl & F_COUNTPAUSESTATTX) {
3239 p->tx_frames -= p->tx_pause;
3240 p->tx_octets -= p->tx_pause * 64;
3242 if (stat_ctl & F_COUNTPAUSEMCTX)
3243 p->tx_mcast_frames -= p->tx_pause;
3246 p->rx_octets = GET_STAT(RX_PORT_BYTES);
3247 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
3248 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
3249 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
3250 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
3251 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
3252 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
3253 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
3254 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
3255 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
3256 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
3257 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
3258 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
3259 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
3260 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
3261 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
3262 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3263 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
3264 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
3265 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
3266 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
3267 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
3268 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
3269 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
3270 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
3271 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
3272 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
3274 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3275 if (stat_ctl & F_COUNTPAUSESTATRX) {
3276 p->rx_frames -= p->rx_pause;
3277 p->rx_octets -= p->rx_pause * 64;
3279 if (stat_ctl & F_COUNTPAUSEMCRX)
3280 p->rx_mcast_frames -= p->rx_pause;
3283 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3284 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3285 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3286 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3287 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3288 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3289 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3290 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3297 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3298 * @adap: The adapter
3300 * @stats: Current stats to fill
3301 * @offset: Previous stats snapshot
3303 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3304 struct port_stats *stats,
3305 struct port_stats *offset)
3310 t4_get_port_stats(adap, idx, stats);
3311 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3312 i < (sizeof(struct port_stats) / sizeof(u64));
3318 * t4_clr_port_stats - clear port statistics
3319 * @adap: the adapter
3320 * @idx: the port index
3322 * Clear HW statistics for the given port.
3324 void t4_clr_port_stats(struct adapter *adap, int idx)
3327 u32 bgmap = t4_get_mps_bg_map(adap, idx);
3330 if (is_t4(adap->params.chip))
3331 port_base_addr = PORT_BASE(idx);
3333 port_base_addr = T5_PORT_BASE(idx);
3335 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3336 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3337 t4_write_reg(adap, port_base_addr + i, 0);
3338 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3339 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3340 t4_write_reg(adap, port_base_addr + i, 0);
3341 for (i = 0; i < 4; i++)
3342 if (bgmap & (1 << i)) {
3344 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3347 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3353 * t4_fw_hello - establish communication with FW
3354 * @adap: the adapter
3355 * @mbox: mailbox to use for the FW command
3356 * @evt_mbox: mailbox to receive async FW events
3357 * @master: specifies the caller's willingness to be the device master
3358 * @state: returns the current device state (if non-NULL)
3360 * Issues a command to establish communication with FW. Returns either
3361 * an error (negative integer) or the mailbox of the Master PF.
3363 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3364 enum dev_master master, enum dev_state *state)
3367 struct fw_hello_cmd c;
3369 unsigned int master_mbox;
3370 int retries = FW_CMD_HELLO_RETRIES;
3373 memset(&c, 0, sizeof(c));
3374 INIT_CMD(c, HELLO, WRITE);
3375 c.err_to_clearinit = cpu_to_be32(
3376 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3377 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3378 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3379 M_FW_HELLO_CMD_MBMASTER) |
3380 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3381 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3382 F_FW_HELLO_CMD_CLEARINIT);
3385 * Issue the HELLO command to the firmware. If it's not successful
3386 * but indicates that we got a "busy" or "timeout" condition, retry
3387 * the HELLO until we exhaust our retry limit. If we do exceed our
3388 * retry limit, check to see if the firmware left us any error
3389 * information and report that if so ...
3391 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3392 if (ret != FW_SUCCESS) {
3393 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3395 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3396 t4_report_fw_error(adap);
3400 v = be32_to_cpu(c.err_to_clearinit);
3401 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3403 if (v & F_FW_HELLO_CMD_ERR)
3404 *state = DEV_STATE_ERR;
3405 else if (v & F_FW_HELLO_CMD_INIT)
3406 *state = DEV_STATE_INIT;
3408 *state = DEV_STATE_UNINIT;
3412 * If we're not the Master PF then we need to wait around for the
3413 * Master PF Driver to finish setting up the adapter.
3415 * Note that we also do this wait if we're a non-Master-capable PF and
3416 * there is no current Master PF; a Master PF may show up momentarily
3417 * and we wouldn't want to fail pointlessly. (This can happen when an
3418 * OS loads lots of different drivers rapidly at the same time). In
3419 * this case, the Master PF returned by the firmware will be
3420 * M_PCIE_FW_MASTER so the test below will work ...
3422 if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3423 master_mbox != mbox) {
3424 int waiting = FW_CMD_HELLO_TIMEOUT;
3427 * Wait for the firmware to either indicate an error or
3428 * initialized state. If we see either of these we bail out
3429 * and report the issue to the caller. If we exhaust the
3430 * "hello timeout" and we haven't exhausted our retries, try
3431 * again. Otherwise bail with a timeout error.
3440 * If neither Error nor Initialialized are indicated
3441 * by the firmware keep waiting till we exaust our
3442 * timeout ... and then retry if we haven't exhausted
3445 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3446 if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3457 * We either have an Error or Initialized condition
3458 * report errors preferentially.
3461 if (pcie_fw & F_PCIE_FW_ERR)
3462 *state = DEV_STATE_ERR;
3463 else if (pcie_fw & F_PCIE_FW_INIT)
3464 *state = DEV_STATE_INIT;
3468 * If we arrived before a Master PF was selected and
3469 * there's not a valid Master PF, grab its identity
3472 if (master_mbox == M_PCIE_FW_MASTER &&
3473 (pcie_fw & F_PCIE_FW_MASTER_VLD))
3474 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3483 * t4_fw_bye - end communication with FW
3484 * @adap: the adapter
3485 * @mbox: mailbox to use for the FW command
3487 * Issues a command to terminate communication with FW.
3489 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3491 struct fw_bye_cmd c;
3493 memset(&c, 0, sizeof(c));
3494 INIT_CMD(c, BYE, WRITE);
3495 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3499 * t4_fw_reset - issue a reset to FW
3500 * @adap: the adapter
3501 * @mbox: mailbox to use for the FW command
3502 * @reset: specifies the type of reset to perform
3504 * Issues a reset command of the specified type to FW.
3506 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3508 struct fw_reset_cmd c;
3510 memset(&c, 0, sizeof(c));
3511 INIT_CMD(c, RESET, WRITE);
3512 c.val = cpu_to_be32(reset);
3513 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3517 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3518 * @adap: the adapter
3519 * @mbox: mailbox to use for the FW RESET command (if desired)
3520 * @force: force uP into RESET even if FW RESET command fails
3522 * Issues a RESET command to firmware (if desired) with a HALT indication
3523 * and then puts the microprocessor into RESET state. The RESET command
3524 * will only be issued if a legitimate mailbox is provided (mbox <=
3525 * M_PCIE_FW_MASTER).
3527 * This is generally used in order for the host to safely manipulate the
3528 * adapter without fear of conflicting with whatever the firmware might
3529 * be doing. The only way out of this state is to RESTART the firmware
3532 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3537 * If a legitimate mailbox is provided, issue a RESET command
3538 * with a HALT indication.
3540 if (mbox <= M_PCIE_FW_MASTER) {
3541 struct fw_reset_cmd c;
3543 memset(&c, 0, sizeof(c));
3544 INIT_CMD(c, RESET, WRITE);
3545 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3546 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3547 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3551 * Normally we won't complete the operation if the firmware RESET
3552 * command fails but if our caller insists we'll go ahead and put the
3553 * uP into RESET. This can be useful if the firmware is hung or even
3554 * missing ... We'll have to take the risk of putting the uP into
3555 * RESET without the cooperation of firmware in that case.
3557 * We also force the firmware's HALT flag to be on in case we bypassed
3558 * the firmware RESET command above or we're dealing with old firmware
3559 * which doesn't have the HALT capability. This will serve as a flag
3560 * for the incoming firmware to know that it's coming out of a HALT
3561 * rather than a RESET ... if it's new enough to understand that ...
3563 if (ret == 0 || force) {
3564 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3565 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3570 * And we always return the result of the firmware RESET command
3571 * even when we force the uP into RESET ...
3577 * t4_fw_restart - restart the firmware by taking the uP out of RESET
3578 * @adap: the adapter
3579 * @mbox: mailbox to use for the FW RESET command (if desired)
3580 * @reset: if we want to do a RESET to restart things
3582 * Restart firmware previously halted by t4_fw_halt(). On successful
3583 * return the previous PF Master remains as the new PF Master and there
3584 * is no need to issue a new HELLO command, etc.
3586 * We do this in two ways:
3588 * 1. If we're dealing with newer firmware we'll simply want to take
3589 * the chip's microprocessor out of RESET. This will cause the
3590 * firmware to start up from its start vector. And then we'll loop
3591 * until the firmware indicates it's started again (PCIE_FW.HALT
3592 * reset to 0) or we timeout.
3594 * 2. If we're dealing with older firmware then we'll need to RESET
3595 * the chip since older firmware won't recognize the PCIE_FW.HALT
3596 * flag and automatically RESET itself on startup.
3598 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3602 * Since we're directing the RESET instead of the firmware
3603 * doing it automatically, we need to clear the PCIE_FW.HALT
3606 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3609 * If we've been given a valid mailbox, first try to get the
3610 * firmware to do the RESET. If that works, great and we can
3611 * return success. Otherwise, if we haven't been given a
3612 * valid mailbox or the RESET command failed, fall back to
3613 * hitting the chip with a hammer.
3615 if (mbox <= M_PCIE_FW_MASTER) {
3616 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3618 if (t4_fw_reset(adap, mbox,
3619 F_PIORST | F_PIORSTMODE) == 0)
3623 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3628 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3629 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3630 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3641 * t4_fl_pkt_align - return the fl packet alignment
3642 * @adap: the adapter
3644 * T4 has a single field to specify the packing and padding boundary.
3645 * T5 onwards has separate fields for this and hence the alignment for
3646 * next packet offset is maximum of these two.
3648 int t4_fl_pkt_align(struct adapter *adap)
3650 u32 sge_control, sge_control2;
3651 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3653 sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3655 /* T4 uses a single control field to specify both the PCIe Padding and
3656 * Packing Boundary. T5 introduced the ability to specify these
3657 * separately. The actual Ingress Packet Data alignment boundary
3658 * within Packed Buffer Mode is the maximum of these two
3661 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3662 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3664 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3666 ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3668 fl_align = ingpadboundary;
3669 if (!is_t4(adap->params.chip)) {
3670 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3671 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3672 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3673 ingpackboundary = 16;
3675 ingpackboundary = 1 << (ingpackboundary +
3676 X_INGPACKBOUNDARY_SHIFT);
3678 fl_align = max(ingpadboundary, ingpackboundary);
3684 * t4_fixup_host_params_compat - fix up host-dependent parameters
3685 * @adap: the adapter
3686 * @page_size: the host's Base Page Size
3687 * @cache_line_size: the host's Cache Line Size
3688 * @chip_compat: maintain compatibility with designated chip
3690 * Various registers in the chip contain values which are dependent on the
3691 * host's Base Page and Cache Line Sizes. This function will fix all of
3692 * those registers with the appropriate values as passed in ...
3694 * @chip_compat is used to limit the set of changes that are made
3695 * to be compatible with the indicated chip release. This is used by
3696 * drivers to maintain compatibility with chip register settings when
3697 * the drivers haven't [yet] been updated with new chip support.
3699 int t4_fixup_host_params_compat(struct adapter *adap,
3700 unsigned int page_size,
3701 unsigned int cache_line_size,
3702 enum chip_type chip_compat)
3704 unsigned int page_shift = cxgbe_fls(page_size) - 1;
3705 unsigned int sge_hps = page_shift - 10;
3706 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3707 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3708 unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3710 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3711 V_HOSTPAGESIZEPF0(sge_hps) |
3712 V_HOSTPAGESIZEPF1(sge_hps) |
3713 V_HOSTPAGESIZEPF2(sge_hps) |
3714 V_HOSTPAGESIZEPF3(sge_hps) |
3715 V_HOSTPAGESIZEPF4(sge_hps) |
3716 V_HOSTPAGESIZEPF5(sge_hps) |
3717 V_HOSTPAGESIZEPF6(sge_hps) |
3718 V_HOSTPAGESIZEPF7(sge_hps));
3720 if (is_t4(adap->params.chip) || is_t4(chip_compat))
3721 t4_set_reg_field(adap, A_SGE_CONTROL,
3722 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3723 F_EGRSTATUSPAGESIZE,
3724 V_INGPADBOUNDARY(fl_align_log -
3725 X_INGPADBOUNDARY_SHIFT) |
3726 V_EGRSTATUSPAGESIZE(stat_len != 64));
3728 unsigned int pack_align;
3729 unsigned int ingpad, ingpack;
3730 unsigned int pcie_cap;
3733 * T5 introduced the separation of the Free List Padding and
3734 * Packing Boundaries. Thus, we can select a smaller Padding
3735 * Boundary to avoid uselessly chewing up PCIe Link and Memory
3736 * Bandwidth, and use a Packing Boundary which is large enough
3737 * to avoid false sharing between CPUs, etc.
3739 * For the PCI Link, the smaller the Padding Boundary the
3740 * better. For the Memory Controller, a smaller Padding
3741 * Boundary is better until we cross under the Memory Line
3742 * Size (the minimum unit of transfer to/from Memory). If we
3743 * have a Padding Boundary which is smaller than the Memory
3744 * Line Size, that'll involve a Read-Modify-Write cycle on the
3745 * Memory Controller which is never good.
3748 /* We want the Packing Boundary to be based on the Cache Line
3749 * Size in order to help avoid False Sharing performance
3750 * issues between CPUs, etc. We also want the Packing
3751 * Boundary to incorporate the PCI-E Maximum Payload Size. We
3752 * get best performance when the Packing Boundary is a
3753 * multiple of the Maximum Payload Size.
3755 pack_align = fl_align;
3756 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3758 unsigned int mps, mps_log;
3761 /* The PCIe Device Control Maximum Payload Size field
3762 * [bits 7:5] encodes sizes as powers of 2 starting at
3765 t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3767 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3769 if (mps > pack_align)
3774 * N.B. T5 has a different interpretation of the "0" value for
3775 * the Packing Boundary. This corresponds to 16 bytes instead
3776 * of the expected 32 bytes. We never have a Packing Boundary
3777 * less than 32 bytes so we can't use that special value but
3778 * on the other hand, if we wanted 32 bytes, the best we can
3779 * really do is 64 bytes ...
3781 if (pack_align <= 16) {
3782 ingpack = X_INGPACKBOUNDARY_16B;
3784 } else if (pack_align == 32) {
3785 ingpack = X_INGPACKBOUNDARY_64B;
3788 unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3790 ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3791 fl_align = pack_align;
3794 /* Use the smallest Ingress Padding which isn't smaller than
3795 * the Memory Controller Read/Write Size. We'll take that as
3796 * being 8 bytes since we don't know of any system with a
3797 * wider Memory Controller Bus Width.
3799 if (is_t5(adap->params.chip))
3800 ingpad = X_INGPADBOUNDARY_32B;
3802 ingpad = X_T6_INGPADBOUNDARY_8B;
3803 t4_set_reg_field(adap, A_SGE_CONTROL,
3804 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3805 F_EGRSTATUSPAGESIZE,
3806 V_INGPADBOUNDARY(ingpad) |
3807 V_EGRSTATUSPAGESIZE(stat_len != 64));
3808 t4_set_reg_field(adap, A_SGE_CONTROL2,
3809 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3810 V_INGPACKBOUNDARY(ingpack));
3814 * Adjust various SGE Free List Host Buffer Sizes.
3816 * The first four entries are:
3820 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3821 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3823 * For the single-MTU buffers in unpacked mode we need to include
3824 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3825 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3826 * Padding boundary. All of these are accommodated in the Factory
3827 * Default Firmware Configuration File but we need to adjust it for
3828 * this host's cache line size.
3830 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3831 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3832 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3834 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3835 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3838 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3844 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3845 * @adap: the adapter
3846 * @page_size: the host's Base Page Size
3847 * @cache_line_size: the host's Cache Line Size
3849 * Various registers in T4 contain values which are dependent on the
3850 * host's Base Page and Cache Line Sizes. This function will fix all of
3851 * those registers with the appropriate values as passed in ...
3853 * This routine makes changes which are compatible with T4 chips.
3855 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3856 unsigned int cache_line_size)
3858 return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3863 * t4_fw_initialize - ask FW to initialize the device
3864 * @adap: the adapter
3865 * @mbox: mailbox to use for the FW command
3867 * Issues a command to FW to partially initialize the device. This
3868 * performs initialization that generally doesn't depend on user input.
3870 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3872 struct fw_initialize_cmd c;
3874 memset(&c, 0, sizeof(c));
3875 INIT_CMD(c, INITIALIZE, WRITE);
3876 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3880 * t4_query_params_rw - query FW or device parameters
3881 * @adap: the adapter
3882 * @mbox: mailbox to use for the FW command
3885 * @nparams: the number of parameters
3886 * @params: the parameter names
3887 * @val: the parameter values
3888 * @rw: Write and read flag
3890 * Reads the value of FW or device parameters. Up to 7 parameters can be
3893 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3894 unsigned int pf, unsigned int vf,
3895 unsigned int nparams, const u32 *params,
3900 struct fw_params_cmd c;
3901 __be32 *p = &c.param[0].mnem;
3906 memset(&c, 0, sizeof(c));
3907 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3908 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3909 V_FW_PARAMS_CMD_PFN(pf) |
3910 V_FW_PARAMS_CMD_VFN(vf));
3911 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3913 for (i = 0; i < nparams; i++) {
3914 *p++ = cpu_to_be32(*params++);
3916 *p = cpu_to_be32(*(val + i));
3920 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3922 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3923 *val++ = be32_to_cpu(*p);
3927 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3928 unsigned int vf, unsigned int nparams, const u32 *params,
3931 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3935 * t4_set_params_timeout - sets FW or device parameters
3936 * @adap: the adapter
3937 * @mbox: mailbox to use for the FW command
3940 * @nparams: the number of parameters
3941 * @params: the parameter names
3942 * @val: the parameter values
3943 * @timeout: the timeout time
3945 * Sets the value of FW or device parameters. Up to 7 parameters can be
3946 * specified at once.
3948 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3949 unsigned int pf, unsigned int vf,
3950 unsigned int nparams, const u32 *params,
3951 const u32 *val, int timeout)
3953 struct fw_params_cmd c;
3954 __be32 *p = &c.param[0].mnem;
3959 memset(&c, 0, sizeof(c));
3960 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3961 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3962 V_FW_PARAMS_CMD_PFN(pf) |
3963 V_FW_PARAMS_CMD_VFN(vf));
3964 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3967 *p++ = cpu_to_be32(*params++);
3968 *p++ = cpu_to_be32(*val++);
3971 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3974 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3975 unsigned int vf, unsigned int nparams, const u32 *params,
3978 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3979 FW_CMD_MAX_TIMEOUT);
3983 * t4_alloc_vi_func - allocate a virtual interface
3984 * @adap: the adapter
3985 * @mbox: mailbox to use for the FW command
3986 * @port: physical port associated with the VI
3987 * @pf: the PF owning the VI
3988 * @vf: the VF owning the VI
3989 * @nmac: number of MAC addresses needed (1 to 5)
3990 * @mac: the MAC addresses of the VI
3991 * @rss_size: size of RSS table slice associated with this VI
3992 * @portfunc: which Port Application Function MAC Address is desired
3993 * @idstype: Intrusion Detection Type
3995 * Allocates a virtual interface for the given physical port. If @mac is
3996 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3997 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3998 * stored consecutively so the space needed is @nmac * 6 bytes.
3999 * Returns a negative error number or the non-negative VI id.
4001 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
4002 unsigned int port, unsigned int pf, unsigned int vf,
4003 unsigned int nmac, u8 *mac, unsigned int *rss_size,
4004 unsigned int portfunc, unsigned int idstype)
4009 memset(&c, 0, sizeof(c));
4010 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
4011 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
4012 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
4013 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
4014 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
4015 V_FW_VI_CMD_FUNC(portfunc));
4016 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
4019 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4024 memcpy(mac, c.mac, sizeof(c.mac));
4027 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
4030 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
4033 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
4036 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
4041 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
4042 return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
4046 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
4047 * @adap: the adapter
4048 * @mbox: mailbox to use for the FW command
4049 * @port: physical port associated with the VI
4050 * @pf: the PF owning the VI
4051 * @vf: the VF owning the VI
4052 * @nmac: number of MAC addresses needed (1 to 5)
4053 * @mac: the MAC addresses of the VI
4054 * @rss_size: size of RSS table slice associated with this VI
4056 * Backwards compatible and convieniance routine to allocate a Virtual
4057 * Interface with a Ethernet Port Application Function and Intrustion
4058 * Detection System disabled.
4060 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
4061 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
4062 unsigned int *rss_size)
4064 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
4069 * t4_free_vi - free a virtual interface
4070 * @adap: the adapter
4071 * @mbox: mailbox to use for the FW command
4072 * @pf: the PF owning the VI
4073 * @vf: the VF owning the VI
4074 * @viid: virtual interface identifiler
4076 * Free a previously allocated virtual interface.
4078 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
4079 unsigned int vf, unsigned int viid)
4083 memset(&c, 0, sizeof(c));
4084 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
4085 F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
4086 V_FW_VI_CMD_VFN(vf));
4087 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
4088 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
4090 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4094 * t4_set_rxmode - set Rx properties of a virtual interface
4095 * @adap: the adapter
4096 * @mbox: mailbox to use for the FW command
4098 * @mtu: the new MTU or -1
4099 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
4100 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
4101 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
4102 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
4104 * @sleep_ok: if true we may sleep while awaiting command completion
4106 * Sets Rx properties of a virtual interface.
4108 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
4109 int mtu, int promisc, int all_multi, int bcast, int vlanex,
4112 struct fw_vi_rxmode_cmd c;
4114 /* convert to FW values */
4116 mtu = M_FW_VI_RXMODE_CMD_MTU;
4118 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
4120 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
4122 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
4124 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
4126 memset(&c, 0, sizeof(c));
4127 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
4128 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4129 V_FW_VI_RXMODE_CMD_VIID(viid));
4130 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4131 c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
4132 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
4133 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
4134 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
4135 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
4136 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
4140 * t4_change_mac - modifies the exact-match filter for a MAC address
4141 * @adap: the adapter
4142 * @mbox: mailbox to use for the FW command
4144 * @idx: index of existing filter for old value of MAC address, or -1
4145 * @addr: the new MAC address value
4146 * @persist: whether a new MAC allocation should be persistent
4147 * @add_smt: if true also add the address to the HW SMT
4149 * Modifies an exact-match filter and sets it to the new MAC address if
4150 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
4151 * latter case the address is added persistently if @persist is %true.
4153 * Note that in general it is not possible to modify the value of a given
4154 * filter so the generic way to modify an address filter is to free the one
4155 * being used by the old address value and allocate a new filter for the
4156 * new address value.
4158 * Returns a negative error number or the index of the filter with the new
4159 * MAC value. Note that this index may differ from @idx.
4161 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
4162 int idx, const u8 *addr, bool persist, bool add_smt)
4165 struct fw_vi_mac_cmd c;
4166 struct fw_vi_mac_exact *p = c.u.exact;
4167 int max_mac_addr = adap->params.arch.mps_tcam_size;
4169 if (idx < 0) /* new allocation */
4170 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
4171 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
4173 memset(&c, 0, sizeof(c));
4174 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
4175 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4176 V_FW_VI_MAC_CMD_VIID(viid));
4177 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
4178 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
4179 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
4180 V_FW_VI_MAC_CMD_IDX(idx));
4181 memcpy(p->macaddr, addr, sizeof(p->macaddr));
4183 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4185 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
4186 if (ret >= max_mac_addr)
4193 * t4_enable_vi_params - enable/disable a virtual interface
4194 * @adap: the adapter
4195 * @mbox: mailbox to use for the FW command
4197 * @rx_en: 1=enable Rx, 0=disable Rx
4198 * @tx_en: 1=enable Tx, 0=disable Tx
4199 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
4201 * Enables/disables a virtual interface. Note that setting DCB Enable
4202 * only makes sense when enabling a Virtual Interface ...
4204 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
4205 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
4207 struct fw_vi_enable_cmd c;
4209 memset(&c, 0, sizeof(c));
4210 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
4211 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4212 V_FW_VI_ENABLE_CMD_VIID(viid));
4213 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
4214 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
4215 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
4217 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
4221 * t4_enable_vi - enable/disable a virtual interface
4222 * @adap: the adapter
4223 * @mbox: mailbox to use for the FW command
4225 * @rx_en: 1=enable Rx, 0=disable Rx
4226 * @tx_en: 1=enable Tx, 0=disable Tx
4228 * Enables/disables a virtual interface. Note that setting DCB Enable
4229 * only makes sense when enabling a Virtual Interface ...
4231 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
4232 bool rx_en, bool tx_en)
4234 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
4238 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
4239 * @adap: the adapter
4240 * @mbox: mailbox to use for the FW command
4241 * @start: %true to enable the queues, %false to disable them
4242 * @pf: the PF owning the queues
4243 * @vf: the VF owning the queues
4244 * @iqid: ingress queue id
4245 * @fl0id: FL0 queue id or 0xffff if no attached FL0
4246 * @fl1id: FL1 queue id or 0xffff if no attached FL1
4248 * Starts or stops an ingress queue and its associated FLs, if any.
4250 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
4251 unsigned int pf, unsigned int vf, unsigned int iqid,
4252 unsigned int fl0id, unsigned int fl1id)
4256 memset(&c, 0, sizeof(c));
4257 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4258 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4259 V_FW_IQ_CMD_VFN(vf));
4260 c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4261 V_FW_IQ_CMD_IQSTOP(!start) |
4263 c.iqid = cpu_to_be16(iqid);
4264 c.fl0id = cpu_to_be16(fl0id);
4265 c.fl1id = cpu_to_be16(fl1id);
4266 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4270 * t4_iq_free - free an ingress queue and its FLs
4271 * @adap: the adapter
4272 * @mbox: mailbox to use for the FW command
4273 * @pf: the PF owning the queues
4274 * @vf: the VF owning the queues
4275 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4276 * @iqid: ingress queue id
4277 * @fl0id: FL0 queue id or 0xffff if no attached FL0
4278 * @fl1id: FL1 queue id or 0xffff if no attached FL1
4280 * Frees an ingress queue and its associated FLs, if any.
4282 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4283 unsigned int vf, unsigned int iqtype, unsigned int iqid,
4284 unsigned int fl0id, unsigned int fl1id)
4288 memset(&c, 0, sizeof(c));
4289 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4290 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4291 V_FW_IQ_CMD_VFN(vf));
4292 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4293 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4294 c.iqid = cpu_to_be16(iqid);
4295 c.fl0id = cpu_to_be16(fl0id);
4296 c.fl1id = cpu_to_be16(fl1id);
4297 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4301 * t4_eth_eq_free - free an Ethernet egress queue
4302 * @adap: the adapter
4303 * @mbox: mailbox to use for the FW command
4304 * @pf: the PF owning the queue
4305 * @vf: the VF owning the queue
4306 * @eqid: egress queue id
4308 * Frees an Ethernet egress queue.
4310 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4311 unsigned int vf, unsigned int eqid)
4313 struct fw_eq_eth_cmd c;
4315 memset(&c, 0, sizeof(c));
4316 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4317 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4318 V_FW_EQ_ETH_CMD_PFN(pf) |
4319 V_FW_EQ_ETH_CMD_VFN(vf));
4320 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4321 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4322 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4326 * t4_link_down_rc_str - return a string for a Link Down Reason Code
4327 * @link_down_rc: Link Down Reason Code
4329 * Returns a string representation of the Link Down Reason Code.
4331 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
4333 static const char * const reason[] = {
4336 "Auto-negotiation Failure",
4338 "Insufficient Airflow",
4339 "Unable To Determine Reason",
4340 "No RX Signal Detected",
4344 if (link_down_rc >= ARRAY_SIZE(reason))
4345 return "Bad Reason Code";
4347 return reason[link_down_rc];
4350 /* Return the highest speed set in the port capabilities, in Mb/s. */
4351 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
4353 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
4355 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
4359 TEST_SPEED_RETURN(100G, 100000);
4360 TEST_SPEED_RETURN(50G, 50000);
4361 TEST_SPEED_RETURN(40G, 40000);
4362 TEST_SPEED_RETURN(25G, 25000);
4363 TEST_SPEED_RETURN(10G, 10000);
4364 TEST_SPEED_RETURN(1G, 1000);
4365 TEST_SPEED_RETURN(100M, 100);
4367 #undef TEST_SPEED_RETURN
4373 * t4_handle_get_port_info - process a FW reply message
4374 * @pi: the port info
4375 * @rpl: start of the FW message
4377 * Processes a GET_PORT_INFO FW reply message.
4379 static void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
4381 const struct fw_port_cmd *cmd = (const void *)rpl;
4382 int action = G_FW_PORT_CMD_ACTION(be32_to_cpu(cmd->action_to_len16));
4383 fw_port_cap32_t pcaps, acaps, linkattr;
4384 struct link_config *lc = &pi->link_cfg;
4385 struct adapter *adapter = pi->adapter;
4386 enum fw_port_module_type mod_type;
4387 enum fw_port_type port_type;
4388 unsigned int speed, fc, fec;
4389 int link_ok, linkdnrc;
4391 /* Extract the various fields from the Port Information message.
4394 case FW_PORT_ACTION_GET_PORT_INFO: {
4395 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
4397 link_ok = (lstatus & F_FW_PORT_CMD_LSTATUS) != 0;
4398 linkdnrc = G_FW_PORT_CMD_LINKDNRC(lstatus);
4399 port_type = G_FW_PORT_CMD_PTYPE(lstatus);
4400 mod_type = G_FW_PORT_CMD_MODTYPE(lstatus);
4401 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
4402 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
4404 /* Unfortunately the format of the Link Status in the old
4405 * 16-bit Port Information message isn't the same as the
4406 * 16-bit Port Capabilities bitfield used everywhere else ...
4409 if (lstatus & F_FW_PORT_CMD_RXPAUSE)
4410 linkattr |= FW_PORT_CAP32_FC_RX;
4411 if (lstatus & F_FW_PORT_CMD_TXPAUSE)
4412 linkattr |= FW_PORT_CAP32_FC_TX;
4413 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4414 linkattr |= FW_PORT_CAP32_SPEED_100M;
4415 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4416 linkattr |= FW_PORT_CAP32_SPEED_1G;
4417 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4418 linkattr |= FW_PORT_CAP32_SPEED_10G;
4419 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4420 linkattr |= FW_PORT_CAP32_SPEED_25G;
4421 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4422 linkattr |= FW_PORT_CAP32_SPEED_40G;
4423 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4424 linkattr |= FW_PORT_CAP32_SPEED_100G;
4429 case FW_PORT_ACTION_GET_PORT_INFO32: {
4431 be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
4433 link_ok = (lstatus32 & F_FW_PORT_CMD_LSTATUS32) != 0;
4434 linkdnrc = G_FW_PORT_CMD_LINKDNRC32(lstatus32);
4435 port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);
4436 mod_type = G_FW_PORT_CMD_MODTYPE32(lstatus32);
4437 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
4438 acaps = be32_to_cpu(cmd->u.info32.acaps32);
4439 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
4444 dev_warn(adapter, "Handle Port Information: Bad Command/Action %#x\n",
4445 be32_to_cpu(cmd->action_to_len16));
4449 fec = fwcap_to_cc_fec(acaps);
4451 fc = fwcap_to_cc_pause(linkattr);
4452 speed = fwcap_to_speed(linkattr);
4454 if (mod_type != pi->mod_type) {
4456 pi->port_type = port_type;
4457 pi->mod_type = mod_type;
4458 t4_os_portmod_changed(adapter, pi->port_id);
4460 if (link_ok != lc->link_ok || speed != lc->speed ||
4461 fc != lc->fc || fec != lc->fec) { /* something changed */
4462 if (!link_ok && lc->link_ok) {
4463 lc->link_down_rc = linkdnrc;
4464 dev_warn(adap, "Port %d link down, reason: %s\n",
4465 pi->tx_chan, t4_link_down_rc_str(linkdnrc));
4467 lc->link_ok = link_ok;
4472 lc->acaps = acaps & ADVERT_MASK;
4474 if (lc->acaps & FW_PORT_CAP32_ANEG) {
4475 lc->autoneg = AUTONEG_ENABLE;
4477 /* When Autoneg is disabled, user needs to set
4479 * Similar to cxgb4_ethtool.c: set_link_ksettings
4482 lc->requested_speed = fwcap_to_speed(acaps);
4483 lc->autoneg = AUTONEG_DISABLE;
4489 * t4_handle_fw_rpl - process a FW reply message
4490 * @adap: the adapter
4491 * @rpl: start of the FW message
4493 * Processes a FW message, such as link state change messages.
4495 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4497 u8 opcode = *(const u8 *)rpl;
4500 * This might be a port command ... this simplifies the following
4501 * conditionals ... We can get away with pre-dereferencing
4502 * action_to_len16 because it's in the first 16 bytes and all messages
4503 * will be at least that long.
4505 const struct fw_port_cmd *p = (const void *)rpl;
4506 unsigned int action =
4507 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4509 if (opcode == FW_PORT_CMD &&
4510 (action == FW_PORT_ACTION_GET_PORT_INFO ||
4511 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
4512 /* link/module state change message */
4513 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4514 struct port_info *pi = NULL;
4517 for_each_port(adap, i) {
4518 pi = adap2pinfo(adap, i);
4519 if (pi->tx_chan == chan)
4523 t4_handle_get_port_info(pi, rpl);
4525 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4531 void t4_reset_link_config(struct adapter *adap, int idx)
4533 struct port_info *pi = adap2pinfo(adap, idx);
4534 struct link_config *lc = &pi->link_cfg;
4537 lc->requested_speed = 0;
4538 lc->requested_fc = 0;
4544 * init_link_config - initialize a link's SW state
4545 * @lc: structure holding the link state
4546 * @pcaps: link Port Capabilities
4547 * @acaps: link current Advertised Port Capabilities
4549 * Initializes the SW state maintained for each link, including the link's
4550 * capabilities and default speed/flow-control/autonegotiation settings.
4552 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
4553 fw_port_cap32_t acaps)
4556 lc->requested_speed = 0;
4558 lc->requested_fc = 0;
4562 * For Forward Error Control, we default to whatever the Firmware
4563 * tells us the Link is currently advertising.
4565 lc->auto_fec = fwcap_to_cc_fec(acaps);
4566 lc->requested_fec = FEC_AUTO;
4567 lc->fec = lc->auto_fec;
4569 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
4570 lc->acaps = lc->pcaps & ADVERT_MASK;
4571 lc->autoneg = AUTONEG_ENABLE;
4572 lc->requested_fc |= PAUSE_AUTONEG;
4575 lc->autoneg = AUTONEG_DISABLE;
4580 * t4_wait_dev_ready - wait till to reads of registers work
4582 * Right after the device is RESET is can take a small amount of time
4583 * for it to respond to register reads. Until then, all reads will
4584 * return either 0xff...ff or 0xee...ee. Return an error if reads
4585 * don't work within a reasonable time frame.
4587 static int t4_wait_dev_ready(struct adapter *adapter)
4591 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4593 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4597 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4598 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4601 dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4607 u32 vendor_and_model_id;
4611 int t4_get_flash_params(struct adapter *adapter)
4614 * Table for non-Numonix supported flash parts. Numonix parts are left
4615 * to the preexisting well-tested code. All flash parts have 64KB
4618 static struct flash_desc supported_flash[] = {
4619 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
4624 unsigned int part, manufacturer;
4625 unsigned int density, size;
4628 * Issue a Read ID Command to the Flash part. We decode supported
4629 * Flash parts and their sizes from this. There's a newer Query
4630 * Command which can retrieve detailed geometry information but
4631 * many Flash parts don't support it.
4633 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4635 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4636 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
4640 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4641 if (supported_flash[part].vendor_and_model_id == flashid) {
4642 adapter->params.sf_size =
4643 supported_flash[part].size_mb;
4644 adapter->params.sf_nsec =
4645 adapter->params.sf_size / SF_SEC_SIZE;
4650 manufacturer = flashid & 0xff;
4651 switch (manufacturer) {
4652 case 0x20: { /* Micron/Numonix */
4654 * This Density -> Size decoding table is taken from Micron
4657 density = (flashid >> 16) & 0xff;
4660 size = 1 << 20; /* 1MB */
4663 size = 1 << 21; /* 2MB */
4666 size = 1 << 22; /* 4MB */
4669 size = 1 << 23; /* 8MB */
4672 size = 1 << 24; /* 16MB */
4675 size = 1 << 25; /* 32MB */
4678 size = 1 << 26; /* 64MB */
4681 size = 1 << 27; /* 128MB */
4684 size = 1 << 28; /* 256MB */
4687 dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4692 adapter->params.sf_size = size;
4693 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4697 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4703 * We should reject adapters with FLASHes which are too small. So, emit
4706 if (adapter->params.sf_size < FLASH_MIN_SIZE)
4707 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4708 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4713 static void set_pcie_completion_timeout(struct adapter *adapter,
4719 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4721 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4724 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4729 * t4_get_chip_type - Determine chip type from device ID
4730 * @adap: the adapter
4731 * @ver: adapter version
4733 int t4_get_chip_type(struct adapter *adap, int ver)
4735 enum chip_type chip = 0;
4736 u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4738 /* Retrieve adapter's device ID */
4741 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4744 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4747 dev_err(adap, "Device %d is not supported\n",
4748 adap->params.pci.device_id);
4756 * t4_prep_adapter - prepare SW and HW for operation
4757 * @adapter: the adapter
4759 * Initialize adapter SW state for the various HW modules, set initial
4760 * values for some adapter tunables, take PHYs out of reset, and
4761 * initialize the MDIO interface.
4763 int t4_prep_adapter(struct adapter *adapter)
4768 ret = t4_wait_dev_ready(adapter);
4772 pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4773 adapter->params.pci.device_id = adapter->pdev->id.device_id;
4774 adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4777 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4778 * ADAPTER (VERSION << 4 | REVISION)
4780 ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4781 adapter->params.chip = 0;
4784 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4785 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4786 adapter->params.arch.mps_tcam_size =
4787 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4788 adapter->params.arch.mps_rplc_size = 128;
4789 adapter->params.arch.nchan = NCHAN;
4790 adapter->params.arch.vfcount = 128;
4793 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4794 adapter->params.arch.sge_fl_db = 0;
4795 adapter->params.arch.mps_tcam_size =
4796 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4797 adapter->params.arch.mps_rplc_size = 256;
4798 adapter->params.arch.nchan = 2;
4799 adapter->params.arch.vfcount = 256;
4802 dev_err(adapter, "%s: Device %d is not supported\n",
4803 __func__, adapter->params.pci.device_id);
4807 adapter->params.pci.vpd_cap_addr =
4808 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4810 ret = t4_get_flash_params(adapter);
4812 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4817 adapter->params.cim_la_size = CIMLA_SIZE;
4819 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4822 * Default port and clock for debugging in case we can't reach FW.
4824 adapter->params.nports = 1;
4825 adapter->params.portvec = 1;
4826 adapter->params.vpd.cclk = 50000;
4828 /* Set pci completion timeout value to 4 seconds. */
4829 set_pcie_completion_timeout(adapter, 0xd);
4834 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4835 * @adapter: the adapter
4836 * @qid: the Queue ID
4837 * @qtype: the Ingress or Egress type for @qid
4838 * @pbar2_qoffset: BAR2 Queue Offset
4839 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4841 * Returns the BAR2 SGE Queue Registers information associated with the
4842 * indicated Absolute Queue ID. These are passed back in return value
4843 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4844 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4846 * This may return an error which indicates that BAR2 SGE Queue
4847 * registers aren't available. If an error is not returned, then the
4848 * following values are returned:
4850 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4851 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4853 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4854 * require the "Inferred Queue ID" ability may be used. E.g. the
4855 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4856 * then these "Inferred Queue ID" register may not be used.
4858 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4859 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4860 unsigned int *pbar2_qid)
4862 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4863 u64 bar2_page_offset, bar2_qoffset;
4864 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4867 * T4 doesn't support BAR2 SGE Queue registers.
4869 if (is_t4(adapter->params.chip))
4873 * Get our SGE Page Size parameters.
4875 page_shift = adapter->params.sge.hps + 10;
4876 page_size = 1 << page_shift;
4879 * Get the right Queues per Page parameters for our Queue.
4881 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4882 adapter->params.sge.eq_qpp :
4883 adapter->params.sge.iq_qpp);
4884 qpp_mask = (1 << qpp_shift) - 1;
4887 * Calculate the basics of the BAR2 SGE Queue register area:
4888 * o The BAR2 page the Queue registers will be in.
4889 * o The BAR2 Queue ID.
4890 * o The BAR2 Queue ID Offset into the BAR2 page.
4892 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4893 bar2_qid = qid & qpp_mask;
4894 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4897 * If the BAR2 Queue ID Offset is less than the Page Size, then the
4898 * hardware will infer the Absolute Queue ID simply from the writes to
4899 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4900 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
4901 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4902 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4903 * from the BAR2 Page and BAR2 Queue ID.
4905 * One important censequence of this is that some BAR2 SGE registers
4906 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4907 * there. But other registers synthesize the SGE Queue ID purely
4908 * from the writes to the registers -- the Write Combined Doorbell
4909 * Buffer is a good example. These BAR2 SGE Registers are only
4910 * available for those BAR2 SGE Register areas where the SGE Absolute
4911 * Queue ID can be inferred from simple writes.
4913 bar2_qoffset = bar2_page_offset;
4914 bar2_qinferred = (bar2_qid_offset < page_size);
4915 if (bar2_qinferred) {
4916 bar2_qoffset += bar2_qid_offset;
4920 *pbar2_qoffset = bar2_qoffset;
4921 *pbar2_qid = bar2_qid;
4926 * t4_init_sge_params - initialize adap->params.sge
4927 * @adapter: the adapter
4929 * Initialize various fields of the adapter's SGE Parameters structure.
4931 int t4_init_sge_params(struct adapter *adapter)
4933 struct sge_params *sge_params = &adapter->params.sge;
4935 unsigned int s_hps, s_qpp;
4938 * Extract the SGE Page Size for our PF.
4940 hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4941 s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4943 sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4946 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4948 s_qpp = (S_QUEUESPERPAGEPF0 +
4949 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4950 qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4951 sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4952 qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4953 sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4959 * t4_init_tp_params - initialize adap->params.tp
4960 * @adap: the adapter
4962 * Initialize various fields of the adapter's TP Parameters structure.
4964 int t4_init_tp_params(struct adapter *adap)
4969 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4970 adap->params.tp.tre = G_TIMERRESOLUTION(v);
4971 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4973 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4974 for (chan = 0; chan < NCHAN; chan++)
4975 adap->params.tp.tx_modq[chan] = chan;
4978 * Cache the adapter's Compressed Filter Mode and global Incress
4981 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4982 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4983 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4984 &adap->params.tp.ingress_config, 1,
4985 A_TP_INGRESS_CONFIG);
4987 /* For T6, cache the adapter's compressed error vector
4988 * and passing outer header info for encapsulated packets.
4990 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4991 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
4992 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
4996 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4997 * shift positions of several elements of the Compressed Filter Tuple
4998 * for this adapter which we need frequently ...
5000 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
5001 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
5002 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
5003 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
5007 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
5008 * represents the presense of an Outer VLAN instead of a VNIC ID.
5010 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
5011 adap->params.tp.vnic_shift = -1;
5017 * t4_filter_field_shift - calculate filter field shift
5018 * @adap: the adapter
5019 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
5021 * Return the shift position of a filter field within the Compressed
5022 * Filter Tuple. The filter field is specified via its selection bit
5023 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
5025 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
5027 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
5031 if ((filter_mode & filter_sel) == 0)
5034 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
5035 switch (filter_mode & sel) {
5037 field_shift += W_FT_FCOE;
5040 field_shift += W_FT_PORT;
5043 field_shift += W_FT_VNIC_ID;
5046 field_shift += W_FT_VLAN;
5049 field_shift += W_FT_TOS;
5052 field_shift += W_FT_PROTOCOL;
5055 field_shift += W_FT_ETHERTYPE;
5058 field_shift += W_FT_MACMATCH;
5061 field_shift += W_FT_MPSHITTYPE;
5063 case F_FRAGMENTATION:
5064 field_shift += W_FT_FRAGMENTATION;
5071 int t4_init_rss_mode(struct adapter *adap, int mbox)
5074 struct fw_rss_vi_config_cmd rvc;
5076 memset(&rvc, 0, sizeof(rvc));
5078 for_each_port(adap, i) {
5079 struct port_info *p = adap2pinfo(adap, i);
5081 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
5082 F_FW_CMD_REQUEST | F_FW_CMD_READ |
5083 V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
5084 rvc.retval_len16 = htonl(FW_LEN16(rvc));
5085 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
5088 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
5093 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
5095 unsigned int fw_caps = adap->params.fw_caps_support;
5096 fw_port_cap32_t pcaps, acaps;
5097 enum fw_port_type port_type;
5098 struct fw_port_cmd cmd;
5104 memset(&cmd, 0, sizeof(cmd));
5106 for_each_port(adap, i) {
5107 struct port_info *pi = adap2pinfo(adap, i);
5108 unsigned int rss_size = 0;
5110 while ((adap->params.portvec & (1 << j)) == 0)
5113 /* If we haven't yet determined whether we're talking to
5114 * Firmware which knows the new 32-bit Port Capabilities, it's
5115 * time to find out now. This will also tell new Firmware to
5116 * send us Port Status Updates using the new 32-bit Port
5117 * Capabilities version of the Port Information message.
5119 if (fw_caps == FW_CAPS_UNKNOWN) {
5120 u32 param, val, caps;
5122 caps = FW_PARAMS_PARAM_PFVF_PORT_CAPS32;
5123 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) |
5124 V_FW_PARAMS_PARAM_X(caps));
5126 ret = t4_set_params(adap, mbox, pf, vf, 1, ¶m,
5128 fw_caps = ret == 0 ? FW_CAPS32 : FW_CAPS16;
5129 adap->params.fw_caps_support = fw_caps;
5132 memset(&cmd, 0, sizeof(cmd));
5133 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
5136 V_FW_PORT_CMD_PORTID(j));
5137 action = fw_caps == FW_CAPS16 ? FW_PORT_ACTION_GET_PORT_INFO :
5138 FW_PORT_ACTION_GET_PORT_INFO32;
5139 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
5141 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
5145 /* Extract the various fields from the Port Information message.
5147 if (fw_caps == FW_CAPS16) {
5149 be32_to_cpu(cmd.u.info.lstatus_to_modtype);
5151 port_type = G_FW_PORT_CMD_PTYPE(lstatus);
5152 mdio_addr = (lstatus & F_FW_PORT_CMD_MDIOCAP) ?
5153 (int)G_FW_PORT_CMD_MDIOADDR(lstatus) : -1;
5154 pcaps = be16_to_cpu(cmd.u.info.pcap);
5155 acaps = be16_to_cpu(cmd.u.info.acap);
5156 pcaps = fwcaps16_to_caps32(pcaps);
5157 acaps = fwcaps16_to_caps32(acaps);
5160 be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
5162 port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);
5163 mdio_addr = (lstatus32 & F_FW_PORT_CMD_MDIOCAP32) ?
5164 (int)G_FW_PORT_CMD_MDIOADDR32(lstatus32) :
5166 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
5167 acaps = be32_to_cpu(cmd.u.info32.acaps32);
5170 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
5176 pi->rss_size = rss_size;
5177 t4_os_set_hw_addr(adap, i, addr);
5179 pi->port_type = port_type;
5180 pi->mdio_addr = mdio_addr;
5181 pi->mod_type = FW_PORT_MOD_TYPE_NA;
5183 init_link_config(&pi->link_cfg, pcaps, acaps);