drivers/net/cxgbe/base/t4_hw.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <netinet/in.h>
  35
  36 #include <rte_interrupts.h>
  37 #include <rte_log.h>
  38 #include <rte_debug.h>
  39 #include <rte_pci.h>
  40 #include <rte_atomic.h>
  41 #include <rte_branch_prediction.h>
  42 #include <rte_memory.h>
  43 #include <rte_tailq.h>
  44 #include <rte_eal.h>
  45 #include <rte_alarm.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev_driver.h>
  48 #include <rte_malloc.h>
  49 #include <rte_random.h>
  50 #include <rte_dev.h>
  51 #include <rte_byteorder.h>
  52
  53 #include "common.h"
  54 #include "t4_regs.h"
  55 #include "t4_regs_values.h"
  56 #include "t4fw_interface.h"
  57
  58 static void init_link_config(struct link_config *lc, unsigned int pcaps,
  59                              unsigned int acaps);
  60
  61 /**
  62  * t4_read_mtu_tbl - returns the values in the HW path MTU table
  63  * @adap: the adapter
  64  * @mtus: where to store the MTU values
  65  * @mtu_log: where to store the MTU base-2 log (may be %NULL)
  66  *
  67  * Reads the HW path MTU table.
  68  */
  69 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
  70 {
  71         u32 v;
  72         int i;
  73
  74         for (i = 0; i < NMTUS; ++i) {
  75                 t4_write_reg(adap, A_TP_MTU_TABLE,
  76                              V_MTUINDEX(0xff) | V_MTUVALUE(i));
  77                 v = t4_read_reg(adap, A_TP_MTU_TABLE);
  78                 mtus[i] = G_MTUVALUE(v);
  79                 if (mtu_log)
  80                         mtu_log[i] = G_MTUWIDTH(v);
  81         }
  82 }
  83
  84 /**
  85  * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
  86  * @adap: the adapter
  87  * @addr: the indirect TP register address
  88  * @mask: specifies the field within the register to modify
  89  * @val: new value for the field
  90  *
  91  * Sets a field of an indirect TP register to the given value.
  92  */
  93 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
  94                             unsigned int mask, unsigned int val)
  95 {
  96         t4_write_reg(adap, A_TP_PIO_ADDR, addr);
  97         val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
  98         t4_write_reg(adap, A_TP_PIO_DATA, val);
  99 }
 100
 101 /* The minimum additive increment value for the congestion control table */
 102 #define CC_MIN_INCR 2U
 103
 104 /**
 105  * t4_load_mtus - write the MTU and congestion control HW tables
 106  * @adap: the adapter
 107  * @mtus: the values for the MTU table
 108  * @alpha: the values for the congestion control alpha parameter
 109  * @beta: the values for the congestion control beta parameter
 110  *
 111  * Write the HW MTU table with the supplied MTUs and the high-speed
 112  * congestion control table with the supplied alpha, beta, and MTUs.
 113  * We write the two tables together because the additive increments
 114  * depend on the MTUs.
 115  */
 116 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
 117                   const unsigned short *alpha, const unsigned short *beta)
 118 {
 119         static const unsigned int avg_pkts[NCCTRL_WIN] = {
 120                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
 121                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
 122                 28672, 40960, 57344, 81920, 114688, 163840, 229376
 123         };
 124
 125         unsigned int i, w;
 126
 127         for (i = 0; i < NMTUS; ++i) {
 128                 unsigned int mtu = mtus[i];
 129                 unsigned int log2 = cxgbe_fls(mtu);
 130
 131                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
 132                         log2--;
 133                 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
 134                              V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
 135
 136                 for (w = 0; w < NCCTRL_WIN; ++w) {
 137                         unsigned int inc;
 138
 139                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
 140                                   CC_MIN_INCR);
 141
 142                         t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
 143                                      (w << 16) | (beta[w] << 13) | inc);
 144                 }
 145         }
 146 }
 147
 148 /**
 149  * t4_wait_op_done_val - wait until an operation is completed
 150  * @adapter: the adapter performing the operation
 151  * @reg: the register to check for completion
 152  * @mask: a single-bit field within @reg that indicates completion
 153  * @polarity: the value of the field when the operation is completed
 154  * @attempts: number of check iterations
 155  * @delay: delay in usecs between iterations
 156  * @valp: where to store the value of the register at completion time
 157  *
 158  * Wait until an operation is completed by checking a bit in a register
 159  * up to @attempts times.  If @valp is not NULL the value of the register
 160  * at the time it indicated completion is stored there.  Returns 0 if the
 161  * operation completes and -EAGAIN otherwise.
 162  */
 163 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 164                         int polarity, int attempts, int delay, u32 *valp)
 165 {
 166         while (1) {
 167                 u32 val = t4_read_reg(adapter, reg);
 168
 169                 if (!!(val & mask) == polarity) {
 170                         if (valp)
 171                                 *valp = val;
 172                         return 0;
 173                 }
 174                 if (--attempts == 0)
 175                         return -EAGAIN;
 176                 if (delay)
 177                         udelay(delay);
 178         }
 179 }
 180
 181 /**
 182  * t4_set_reg_field - set a register field to a value
 183  * @adapter: the adapter to program
 184  * @addr: the register address
 185  * @mask: specifies the portion of the register to modify
 186  * @val: the new value for the register field
 187  *
 188  * Sets a register field specified by the supplied mask to the
 189  * given value.
 190  */
 191 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
 192                       u32 val)
 193 {
 194         u32 v = t4_read_reg(adapter, addr) & ~mask;
 195
 196         t4_write_reg(adapter, addr, v | val);
 197         (void)t4_read_reg(adapter, addr);      /* flush */
 198 }
 199
 200 /**
 201  * t4_read_indirect - read indirectly addressed registers
 202  * @adap: the adapter
 203  * @addr_reg: register holding the indirect address
 204  * @data_reg: register holding the value of the indirect register
 205  * @vals: where the read register values are stored
 206  * @nregs: how many indirect registers to read
 207  * @start_idx: index of first indirect register to read
 208  *
 209  * Reads registers that are accessed indirectly through an address/data
 210  * register pair.
 211  */
 212 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 213                       unsigned int data_reg, u32 *vals, unsigned int nregs,
 214                       unsigned int start_idx)
 215 {
 216         while (nregs--) {
 217                 t4_write_reg(adap, addr_reg, start_idx);
 218                 *vals++ = t4_read_reg(adap, data_reg);
 219                 start_idx++;
 220         }
 221 }
 222
 223 /**
 224  * t4_write_indirect - write indirectly addressed registers
 225  * @adap: the adapter
 226  * @addr_reg: register holding the indirect addresses
 227  * @data_reg: register holding the value for the indirect registers
 228  * @vals: values to write
 229  * @nregs: how many indirect registers to write
 230  * @start_idx: address of first indirect register to write
 231  *
 232  * Writes a sequential block of registers that are accessed indirectly
 233  * through an address/data register pair.
 234  */
 235 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 236                        unsigned int data_reg, const u32 *vals,
 237                        unsigned int nregs, unsigned int start_idx)
 238 {
 239         while (nregs--) {
 240                 t4_write_reg(adap, addr_reg, start_idx++);
 241                 t4_write_reg(adap, data_reg, *vals++);
 242         }
 243 }
 244
 245 /**
 246  * t4_report_fw_error - report firmware error
 247  * @adap: the adapter
 248  *
 249  * The adapter firmware can indicate error conditions to the host.
 250  * If the firmware has indicated an error, print out the reason for
 251  * the firmware error.
 252  */
 253 static void t4_report_fw_error(struct adapter *adap)
 254 {
 255         static const char * const reason[] = {
 256                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 257                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 258                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 259                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 260                 "Unexpected Event",     /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 261                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 262                 "Device Shutdown",      /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 263                 "Reserved",                     /* reserved */
 264         };
 265         u32 pcie_fw;
 266
 267         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 268         if (pcie_fw & F_PCIE_FW_ERR)
 269                 pr_err("%s: Firmware reports adapter error: %s\n",
 270                        __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
 271 }
 272
 273 /*
 274  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 275  */
 276 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 277                          u32 mbox_addr)
 278 {
 279         for ( ; nflit; nflit--, mbox_addr += 8)
 280                 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
 281 }
 282
 283 /*
 284  * Handle a FW assertion reported in a mailbox.
 285  */
 286 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 287 {
 288         struct fw_debug_cmd asrt;
 289
 290         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 291         pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 292                 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 293                 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 294 }
 295
 296 #define X_CIM_PF_NOACCESS 0xeeeeeeee
 297
 298 /*
 299  * If the Host OS Driver needs locking arround accesses to the mailbox, this
 300  * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
 301  */
 302 /* makes single-statement usage a bit cleaner ... */
 303 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 304 #define T4_OS_MBOX_LOCKING(x) x
 305 #else
 306 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
 307 #endif
 308
 309 /**
 310  * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 311  * @adap: the adapter
 312  * @mbox: index of the mailbox to use
 313  * @cmd: the command to write
 314  * @size: command length in bytes
 315  * @rpl: where to optionally store the reply
 316  * @sleep_ok: if true we may sleep while awaiting command completion
 317  * @timeout: time to wait for command to finish before timing out
 318  *           (negative implies @sleep_ok=false)
 319  *
 320  * Sends the given command to FW through the selected mailbox and waits
 321  * for the FW to execute the command.  If @rpl is not %NULL it is used to
 322  * store the FW's reply to the command.  The command and its optional
 323  * reply are of the same length.  Some FW commands like RESET and
 324  * INITIALIZE can take a considerable amount of time to execute.
 325  * @sleep_ok determines whether we may sleep while awaiting the response.
 326  * If sleeping is allowed we use progressive backoff otherwise we spin.
 327  * Note that passing in a negative @timeout is an alternate mechanism
 328  * for specifying @sleep_ok=false.  This is useful when a higher level
 329  * interface allows for specification of @timeout but not @sleep_ok ...
 330  *
 331  * Returns 0 on success or a negative errno on failure.  A
 332  * failure can happen either because we are not able to execute the
 333  * command or FW executes it but signals an error.  In the latter case
 334  * the return value is the error code indicated by FW (negated).
 335  */
 336 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
 337                             const void __attribute__((__may_alias__)) *cmd,
 338                             int size, void *rpl, bool sleep_ok, int timeout)
 339 {
 340         /*
 341          * We delay in small increments at first in an effort to maintain
 342          * responsiveness for simple, fast executing commands but then back
 343          * off to larger delays to a maximum retry delay.
 344          */
 345         static const int delay[] = {
 346                 1, 1, 3, 5, 10, 10, 20, 50, 100
 347         };
 348
 349         u32 v;
 350         u64 res;
 351         int i, ms;
 352         unsigned int delay_idx;
 353         __be64 *temp = (__be64 *)malloc(size * sizeof(char));
 354         __be64 *p = temp;
 355         u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
 356         u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
 357         u32 ctl;
 358         struct mbox_entry entry;
 359         u32 pcie_fw = 0;
 360
 361         if (!temp)
 362                 return -ENOMEM;
 363
 364         if ((size & 15) || size > MBOX_LEN) {
 365                 free(temp);
 366                 return -EINVAL;
 367         }
 368
 369         bzero(p, size);
 370         memcpy(p, (const __be64 *)cmd, size);
 371
 372         /*
 373          * If we have a negative timeout, that implies that we can't sleep.
 374          */
 375         if (timeout < 0) {
 376                 sleep_ok = false;
 377                 timeout = -timeout;
 378         }
 379
 380 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 381         /*
 382          * Queue ourselves onto the mailbox access list.  When our entry is at
 383          * the front of the list, we have rights to access the mailbox.  So we
 384          * wait [for a while] till we're at the front [or bail out with an
 385          * EBUSY] ...
 386          */
 387         t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
 388
 389         delay_idx = 0;
 390         ms = delay[0];
 391
 392         for (i = 0; ; i += ms) {
 393                 /*
 394                  * If we've waited too long, return a busy indication.  This
 395                  * really ought to be based on our initial position in the
 396                  * mailbox access list but this is a start.  We very rarely
 397                  * contend on access to the mailbox ...  Also check for a
 398                  * firmware error which we'll report as a device error.
 399                  */
 400                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 401                 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
 402                         t4_os_atomic_list_del(&entry, &adap->mbox_list,
 403                                               &adap->mbox_lock);
 404                         t4_report_fw_error(adap);
 405                         free(temp);
 406                         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
 407                 }
 408
 409                 /*
 410                  * If we're at the head, break out and start the mailbox
 411                  * protocol.
 412                  */
 413                 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
 414                         break;
 415
 416                 /*
 417                  * Delay for a bit before checking again ...
 418                  */
 419                 if (sleep_ok) {
 420                         ms = delay[delay_idx];  /* last element may repeat */
 421                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 422                                 delay_idx++;
 423                         msleep(ms);
 424                 } else {
 425                         rte_delay_ms(ms);
 426                 }
 427         }
 428 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
 429
 430         /*
 431          * Attempt to gain access to the mailbox.
 432          */
 433         for (i = 0; i < 4; i++) {
 434                 ctl = t4_read_reg(adap, ctl_reg);
 435                 v = G_MBOWNER(ctl);
 436                 if (v != X_MBOWNER_NONE)
 437                         break;
 438         }
 439
 440         /*
 441          * If we were unable to gain access, dequeue ourselves from the
 442          * mailbox atomic access list and report the error to our caller.
 443          */
 444         if (v != X_MBOWNER_PL) {
 445                 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 446                                                          &adap->mbox_list,
 447                                                          &adap->mbox_lock));
 448                 t4_report_fw_error(adap);
 449                 free(temp);
 450                 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
 451         }
 452
 453         /*
 454          * If we gain ownership of the mailbox and there's a "valid" message
 455          * in it, this is likely an asynchronous error message from the
 456          * firmware.  So we'll report that and then proceed on with attempting
 457          * to issue our own command ... which may well fail if the error
 458          * presaged the firmware crashing ...
 459          */
 460         if (ctl & F_MBMSGVALID) {
 461                 dev_err(adap, "found VALID command in mbox %u: "
 462                         "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 463                         (unsigned long long)t4_read_reg64(adap, data_reg),
 464                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 465                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 466                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 467                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 468                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 469                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 470                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 471         }
 472
 473         /*
 474          * Copy in the new mailbox command and send it on its way ...
 475          */
 476         for (i = 0; i < size; i += 8, p++)
 477                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
 478
 479         CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
 480                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 481                         (unsigned long long)t4_read_reg64(adap, data_reg),
 482                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 483                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 484                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 485                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 486                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 487                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 488                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 489
 490         t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
 491         t4_read_reg(adap, ctl_reg);          /* flush write */
 492
 493         delay_idx = 0;
 494         ms = delay[0];
 495
 496         /*
 497          * Loop waiting for the reply; bail out if we time out or the firmware
 498          * reports an error.
 499          */
 500         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 501         for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
 502                 if (sleep_ok) {
 503                         ms = delay[delay_idx];  /* last element may repeat */
 504                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 505                                 delay_idx++;
 506                         msleep(ms);
 507                 } else {
 508                         msleep(ms);
 509                 }
 510
 511                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 512                 v = t4_read_reg(adap, ctl_reg);
 513                 if (v == X_CIM_PF_NOACCESS)
 514                         continue;
 515                 if (G_MBOWNER(v) == X_MBOWNER_PL) {
 516                         if (!(v & F_MBMSGVALID)) {
 517                                 t4_write_reg(adap, ctl_reg,
 518                                              V_MBOWNER(X_MBOWNER_NONE));
 519                                 continue;
 520                         }
 521
 522                         CXGBE_DEBUG_MBOX(adap,
 523                         "%s: mbox %u: %016llx %016llx %016llx %016llx "
 524                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 525                         (unsigned long long)t4_read_reg64(adap, data_reg),
 526                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 527                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 528                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 529                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 530                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 531                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 532                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 533
 534                         CXGBE_DEBUG_MBOX(adap,
 535                                 "command %#x completed in %d ms (%ssleeping)\n",
 536                                 *(const u8 *)cmd,
 537                                 i + ms, sleep_ok ? "" : "non-");
 538
 539                         res = t4_read_reg64(adap, data_reg);
 540                         if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
 541                                 fw_asrt(adap, data_reg);
 542                                 res = V_FW_CMD_RETVAL(EIO);
 543                         } else if (rpl) {
 544                                 get_mbox_rpl(adap, rpl, size / 8, data_reg);
 545                         }
 546                         t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
 547                         T4_OS_MBOX_LOCKING(
 548                                 t4_os_atomic_list_del(&entry, &adap->mbox_list,
 549                                                       &adap->mbox_lock));
 550                         free(temp);
 551                         return -G_FW_CMD_RETVAL((int)res);
 552                 }
 553         }
 554
 555         /*
 556          * We timed out waiting for a reply to our mailbox command.  Report
 557          * the error and also check to see if the firmware reported any
 558          * errors ...
 559          */
 560         dev_err(adap, "command %#x in mailbox %d timed out\n",
 561                 *(const u8 *)cmd, mbox);
 562         T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 563                                                  &adap->mbox_list,
 564                                                  &adap->mbox_lock));
 565         t4_report_fw_error(adap);
 566         free(temp);
 567         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
 568 }
 569
 570 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 571                     void *rpl, bool sleep_ok)
 572 {
 573         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 574                                        FW_CMD_MAX_TIMEOUT);
 575 }
 576
 577 /**
 578  * t4_get_regs_len - return the size of the chips register set
 579  * @adapter: the adapter
 580  *
 581  * Returns the size of the chip's BAR0 register space.
 582  */
 583 unsigned int t4_get_regs_len(struct adapter *adapter)
 584 {
 585         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 586
 587         switch (chip_version) {
 588         case CHELSIO_T5:
 589         case CHELSIO_T6:
 590                 return T5_REGMAP_SIZE;
 591         }
 592
 593         dev_err(adapter,
 594                 "Unsupported chip version %d\n", chip_version);
 595         return 0;
 596 }
 597
 598 /**
 599  * t4_get_regs - read chip registers into provided buffer
 600  * @adap: the adapter
 601  * @buf: register buffer
 602  * @buf_size: size (in bytes) of register buffer
 603  *
 604  * If the provided register buffer isn't large enough for the chip's
 605  * full register range, the register dump will be truncated to the
 606  * register buffer's size.
 607  */
 608 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 609 {
 610         static const unsigned int t5_reg_ranges[] = {
 611                 0x1008, 0x10c0,
 612                 0x10cc, 0x10f8,
 613                 0x1100, 0x1100,
 614                 0x110c, 0x1148,
 615                 0x1180, 0x1184,
 616                 0x1190, 0x1194,
 617                 0x11a0, 0x11a4,
 618                 0x11b0, 0x11b4,
 619                 0x11fc, 0x123c,
 620                 0x1280, 0x173c,
 621                 0x1800, 0x18fc,
 622                 0x3000, 0x3028,
 623                 0x3060, 0x30b0,
 624                 0x30b8, 0x30d8,
 625                 0x30e0, 0x30fc,
 626                 0x3140, 0x357c,
 627                 0x35a8, 0x35cc,
 628                 0x35ec, 0x35ec,
 629                 0x3600, 0x5624,
 630                 0x56cc, 0x56ec,
 631                 0x56f4, 0x5720,
 632                 0x5728, 0x575c,
 633                 0x580c, 0x5814,
 634                 0x5890, 0x589c,
 635                 0x58a4, 0x58ac,
 636                 0x58b8, 0x58bc,
 637                 0x5940, 0x59c8,
 638                 0x59d0, 0x59dc,
 639                 0x59fc, 0x5a18,
 640                 0x5a60, 0x5a70,
 641                 0x5a80, 0x5a9c,
 642                 0x5b94, 0x5bfc,
 643                 0x6000, 0x6020,
 644                 0x6028, 0x6040,
 645                 0x6058, 0x609c,
 646                 0x60a8, 0x614c,
 647                 0x7700, 0x7798,
 648                 0x77c0, 0x78fc,
 649                 0x7b00, 0x7b58,
 650                 0x7b60, 0x7b84,
 651                 0x7b8c, 0x7c54,
 652                 0x7d00, 0x7d38,
 653                 0x7d40, 0x7d80,
 654                 0x7d8c, 0x7ddc,
 655                 0x7de4, 0x7e04,
 656                 0x7e10, 0x7e1c,
 657                 0x7e24, 0x7e38,
 658                 0x7e40, 0x7e44,
 659                 0x7e4c, 0x7e78,
 660                 0x7e80, 0x7edc,
 661                 0x7ee8, 0x7efc,
 662                 0x8dc0, 0x8de0,
 663                 0x8df8, 0x8e04,
 664                 0x8e10, 0x8e84,
 665                 0x8ea0, 0x8f84,
 666                 0x8fc0, 0x9058,
 667                 0x9060, 0x9060,
 668                 0x9068, 0x90f8,
 669                 0x9400, 0x9408,
 670                 0x9410, 0x9470,
 671                 0x9600, 0x9600,
 672                 0x9608, 0x9638,
 673                 0x9640, 0x96f4,
 674                 0x9800, 0x9808,
 675                 0x9820, 0x983c,
 676                 0x9850, 0x9864,
 677                 0x9c00, 0x9c6c,
 678                 0x9c80, 0x9cec,
 679                 0x9d00, 0x9d6c,
 680                 0x9d80, 0x9dec,
 681                 0x9e00, 0x9e6c,
 682                 0x9e80, 0x9eec,
 683                 0x9f00, 0x9f6c,
 684                 0x9f80, 0xa020,
 685                 0xd004, 0xd004,
 686                 0xd010, 0xd03c,
 687                 0xdfc0, 0xdfe0,
 688                 0xe000, 0x1106c,
 689                 0x11074, 0x11088,
 690                 0x1109c, 0x1117c,
 691                 0x11190, 0x11204,
 692                 0x19040, 0x1906c,
 693                 0x19078, 0x19080,
 694                 0x1908c, 0x190e8,
 695                 0x190f0, 0x190f8,
 696                 0x19100, 0x19110,
 697                 0x19120, 0x19124,
 698                 0x19150, 0x19194,
 699                 0x1919c, 0x191b0,
 700                 0x191d0, 0x191e8,
 701                 0x19238, 0x19290,
 702                 0x193f8, 0x19428,
 703                 0x19430, 0x19444,
 704                 0x1944c, 0x1946c,
 705                 0x19474, 0x19474,
 706                 0x19490, 0x194cc,
 707                 0x194f0, 0x194f8,
 708                 0x19c00, 0x19c08,
 709                 0x19c10, 0x19c60,
 710                 0x19c94, 0x19ce4,
 711                 0x19cf0, 0x19d40,
 712                 0x19d50, 0x19d94,
 713                 0x19da0, 0x19de8,
 714                 0x19df0, 0x19e10,
 715                 0x19e50, 0x19e90,
 716                 0x19ea0, 0x19f24,
 717                 0x19f34, 0x19f34,
 718                 0x19f40, 0x19f50,
 719                 0x19f90, 0x19fb4,
 720                 0x19fc4, 0x19fe4,
 721                 0x1a000, 0x1a004,
 722                 0x1a010, 0x1a06c,
 723                 0x1a0b0, 0x1a0e4,
 724                 0x1a0ec, 0x1a0f8,
 725                 0x1a100, 0x1a108,
 726                 0x1a114, 0x1a120,
 727                 0x1a128, 0x1a130,
 728                 0x1a138, 0x1a138,
 729                 0x1a190, 0x1a1c4,
 730                 0x1a1fc, 0x1a1fc,
 731                 0x1e008, 0x1e00c,
 732                 0x1e040, 0x1e044,
 733                 0x1e04c, 0x1e04c,
 734                 0x1e284, 0x1e290,
 735                 0x1e2c0, 0x1e2c0,
 736                 0x1e2e0, 0x1e2e0,
 737                 0x1e300, 0x1e384,
 738                 0x1e3c0, 0x1e3c8,
 739                 0x1e408, 0x1e40c,
 740                 0x1e440, 0x1e444,
 741                 0x1e44c, 0x1e44c,
 742                 0x1e684, 0x1e690,
 743                 0x1e6c0, 0x1e6c0,
 744                 0x1e6e0, 0x1e6e0,
 745                 0x1e700, 0x1e784,
 746                 0x1e7c0, 0x1e7c8,
 747                 0x1e808, 0x1e80c,
 748                 0x1e840, 0x1e844,
 749                 0x1e84c, 0x1e84c,
 750                 0x1ea84, 0x1ea90,
 751                 0x1eac0, 0x1eac0,
 752                 0x1eae0, 0x1eae0,
 753                 0x1eb00, 0x1eb84,
 754                 0x1ebc0, 0x1ebc8,
 755                 0x1ec08, 0x1ec0c,
 756                 0x1ec40, 0x1ec44,
 757                 0x1ec4c, 0x1ec4c,
 758                 0x1ee84, 0x1ee90,
 759                 0x1eec0, 0x1eec0,
 760                 0x1eee0, 0x1eee0,
 761                 0x1ef00, 0x1ef84,
 762                 0x1efc0, 0x1efc8,
 763                 0x1f008, 0x1f00c,
 764                 0x1f040, 0x1f044,
 765                 0x1f04c, 0x1f04c,
 766                 0x1f284, 0x1f290,
 767                 0x1f2c0, 0x1f2c0,
 768                 0x1f2e0, 0x1f2e0,
 769                 0x1f300, 0x1f384,
 770                 0x1f3c0, 0x1f3c8,
 771                 0x1f408, 0x1f40c,
 772                 0x1f440, 0x1f444,
 773                 0x1f44c, 0x1f44c,
 774                 0x1f684, 0x1f690,
 775                 0x1f6c0, 0x1f6c0,
 776                 0x1f6e0, 0x1f6e0,
 777                 0x1f700, 0x1f784,
 778                 0x1f7c0, 0x1f7c8,
 779                 0x1f808, 0x1f80c,
 780                 0x1f840, 0x1f844,
 781                 0x1f84c, 0x1f84c,
 782                 0x1fa84, 0x1fa90,
 783                 0x1fac0, 0x1fac0,
 784                 0x1fae0, 0x1fae0,
 785                 0x1fb00, 0x1fb84,
 786                 0x1fbc0, 0x1fbc8,
 787                 0x1fc08, 0x1fc0c,
 788                 0x1fc40, 0x1fc44,
 789                 0x1fc4c, 0x1fc4c,
 790                 0x1fe84, 0x1fe90,
 791                 0x1fec0, 0x1fec0,
 792                 0x1fee0, 0x1fee0,
 793                 0x1ff00, 0x1ff84,
 794                 0x1ffc0, 0x1ffc8,
 795                 0x30000, 0x30030,
 796                 0x30038, 0x30038,
 797                 0x30040, 0x30040,
 798                 0x30100, 0x30144,
 799                 0x30190, 0x301a0,
 800                 0x301a8, 0x301b8,
 801                 0x301c4, 0x301c8,
 802                 0x301d0, 0x301d0,
 803                 0x30200, 0x30318,
 804                 0x30400, 0x304b4,
 805                 0x304c0, 0x3052c,
 806                 0x30540, 0x3061c,
 807                 0x30800, 0x30828,
 808                 0x30834, 0x30834,
 809                 0x308c0, 0x30908,
 810                 0x30910, 0x309ac,
 811                 0x30a00, 0x30a14,
 812                 0x30a1c, 0x30a2c,
 813                 0x30a44, 0x30a50,
 814                 0x30a74, 0x30a74,
 815                 0x30a7c, 0x30afc,
 816                 0x30b08, 0x30c24,
 817                 0x30d00, 0x30d00,
 818                 0x30d08, 0x30d14,
 819                 0x30d1c, 0x30d20,
 820                 0x30d3c, 0x30d3c,
 821                 0x30d48, 0x30d50,
 822                 0x31200, 0x3120c,
 823                 0x31220, 0x31220,
 824                 0x31240, 0x31240,
 825                 0x31600, 0x3160c,
 826                 0x31a00, 0x31a1c,
 827                 0x31e00, 0x31e20,
 828                 0x31e38, 0x31e3c,
 829                 0x31e80, 0x31e80,
 830                 0x31e88, 0x31ea8,
 831                 0x31eb0, 0x31eb4,
 832                 0x31ec8, 0x31ed4,
 833                 0x31fb8, 0x32004,
 834                 0x32200, 0x32200,
 835                 0x32208, 0x32240,
 836                 0x32248, 0x32280,
 837                 0x32288, 0x322c0,
 838                 0x322c8, 0x322fc,
 839                 0x32600, 0x32630,
 840                 0x32a00, 0x32abc,
 841                 0x32b00, 0x32b10,
 842                 0x32b20, 0x32b30,
 843                 0x32b40, 0x32b50,
 844                 0x32b60, 0x32b70,
 845                 0x33000, 0x33028,
 846                 0x33030, 0x33048,
 847                 0x33060, 0x33068,
 848                 0x33070, 0x3309c,
 849                 0x330f0, 0x33128,
 850                 0x33130, 0x33148,
 851                 0x33160, 0x33168,
 852                 0x33170, 0x3319c,
 853                 0x331f0, 0x33238,
 854                 0x33240, 0x33240,
 855                 0x33248, 0x33250,
 856                 0x3325c, 0x33264,
 857                 0x33270, 0x332b8,
 858                 0x332c0, 0x332e4,
 859                 0x332f8, 0x33338,
 860                 0x33340, 0x33340,
 861                 0x33348, 0x33350,
 862                 0x3335c, 0x33364,
 863                 0x33370, 0x333b8,
 864                 0x333c0, 0x333e4,
 865                 0x333f8, 0x33428,
 866                 0x33430, 0x33448,
 867                 0x33460, 0x33468,
 868                 0x33470, 0x3349c,
 869                 0x334f0, 0x33528,
 870                 0x33530, 0x33548,
 871                 0x33560, 0x33568,
 872                 0x33570, 0x3359c,
 873                 0x335f0, 0x33638,
 874                 0x33640, 0x33640,
 875                 0x33648, 0x33650,
 876                 0x3365c, 0x33664,
 877                 0x33670, 0x336b8,
 878                 0x336c0, 0x336e4,
 879                 0x336f8, 0x33738,
 880                 0x33740, 0x33740,
 881                 0x33748, 0x33750,
 882                 0x3375c, 0x33764,
 883                 0x33770, 0x337b8,
 884                 0x337c0, 0x337e4,
 885                 0x337f8, 0x337fc,
 886                 0x33814, 0x33814,
 887                 0x3382c, 0x3382c,
 888                 0x33880, 0x3388c,
 889                 0x338e8, 0x338ec,
 890                 0x33900, 0x33928,
 891                 0x33930, 0x33948,
 892                 0x33960, 0x33968,
 893                 0x33970, 0x3399c,
 894                 0x339f0, 0x33a38,
 895                 0x33a40, 0x33a40,
 896                 0x33a48, 0x33a50,
 897                 0x33a5c, 0x33a64,
 898                 0x33a70, 0x33ab8,
 899                 0x33ac0, 0x33ae4,
 900                 0x33af8, 0x33b10,
 901                 0x33b28, 0x33b28,
 902                 0x33b3c, 0x33b50,
 903                 0x33bf0, 0x33c10,
 904                 0x33c28, 0x33c28,
 905                 0x33c3c, 0x33c50,
 906                 0x33cf0, 0x33cfc,
 907                 0x34000, 0x34030,
 908                 0x34038, 0x34038,
 909                 0x34040, 0x34040,
 910                 0x34100, 0x34144,
 911                 0x34190, 0x341a0,
 912                 0x341a8, 0x341b8,
 913                 0x341c4, 0x341c8,
 914                 0x341d0, 0x341d0,
 915                 0x34200, 0x34318,
 916                 0x34400, 0x344b4,
 917                 0x344c0, 0x3452c,
 918                 0x34540, 0x3461c,
 919                 0x34800, 0x34828,
 920                 0x34834, 0x34834,
 921                 0x348c0, 0x34908,
 922                 0x34910, 0x349ac,
 923                 0x34a00, 0x34a14,
 924                 0x34a1c, 0x34a2c,
 925                 0x34a44, 0x34a50,
 926                 0x34a74, 0x34a74,
 927                 0x34a7c, 0x34afc,
 928                 0x34b08, 0x34c24,
 929                 0x34d00, 0x34d00,
 930                 0x34d08, 0x34d14,
 931                 0x34d1c, 0x34d20,
 932                 0x34d3c, 0x34d3c,
 933                 0x34d48, 0x34d50,
 934                 0x35200, 0x3520c,
 935                 0x35220, 0x35220,
 936                 0x35240, 0x35240,
 937                 0x35600, 0x3560c,
 938                 0x35a00, 0x35a1c,
 939                 0x35e00, 0x35e20,
 940                 0x35e38, 0x35e3c,
 941                 0x35e80, 0x35e80,
 942                 0x35e88, 0x35ea8,
 943                 0x35eb0, 0x35eb4,
 944                 0x35ec8, 0x35ed4,
 945                 0x35fb8, 0x36004,
 946                 0x36200, 0x36200,
 947                 0x36208, 0x36240,
 948                 0x36248, 0x36280,
 949                 0x36288, 0x362c0,
 950                 0x362c8, 0x362fc,
 951                 0x36600, 0x36630,
 952                 0x36a00, 0x36abc,
 953                 0x36b00, 0x36b10,
 954                 0x36b20, 0x36b30,
 955                 0x36b40, 0x36b50,
 956                 0x36b60, 0x36b70,
 957                 0x37000, 0x37028,
 958                 0x37030, 0x37048,
 959                 0x37060, 0x37068,
 960                 0x37070, 0x3709c,
 961                 0x370f0, 0x37128,
 962                 0x37130, 0x37148,
 963                 0x37160, 0x37168,
 964                 0x37170, 0x3719c,
 965                 0x371f0, 0x37238,
 966                 0x37240, 0x37240,
 967                 0x37248, 0x37250,
 968                 0x3725c, 0x37264,
 969                 0x37270, 0x372b8,
 970                 0x372c0, 0x372e4,
 971                 0x372f8, 0x37338,
 972                 0x37340, 0x37340,
 973                 0x37348, 0x37350,
 974                 0x3735c, 0x37364,
 975                 0x37370, 0x373b8,
 976                 0x373c0, 0x373e4,
 977                 0x373f8, 0x37428,
 978                 0x37430, 0x37448,
 979                 0x37460, 0x37468,
 980                 0x37470, 0x3749c,
 981                 0x374f0, 0x37528,
 982                 0x37530, 0x37548,
 983                 0x37560, 0x37568,
 984                 0x37570, 0x3759c,
 985                 0x375f0, 0x37638,
 986                 0x37640, 0x37640,
 987                 0x37648, 0x37650,
 988                 0x3765c, 0x37664,
 989                 0x37670, 0x376b8,
 990                 0x376c0, 0x376e4,
 991                 0x376f8, 0x37738,
 992                 0x37740, 0x37740,
 993                 0x37748, 0x37750,
 994                 0x3775c, 0x37764,
 995                 0x37770, 0x377b8,
 996                 0x377c0, 0x377e4,
 997                 0x377f8, 0x377fc,
 998                 0x37814, 0x37814,
 999                 0x3782c, 0x3782c,
1000                 0x37880, 0x3788c,
1001                 0x378e8, 0x378ec,
1002                 0x37900, 0x37928,
1003                 0x37930, 0x37948,
1004                 0x37960, 0x37968,
1005                 0x37970, 0x3799c,
1006                 0x379f0, 0x37a38,
1007                 0x37a40, 0x37a40,
1008                 0x37a48, 0x37a50,
1009                 0x37a5c, 0x37a64,
1010                 0x37a70, 0x37ab8,
1011                 0x37ac0, 0x37ae4,
1012                 0x37af8, 0x37b10,
1013                 0x37b28, 0x37b28,
1014                 0x37b3c, 0x37b50,
1015                 0x37bf0, 0x37c10,
1016                 0x37c28, 0x37c28,
1017                 0x37c3c, 0x37c50,
1018                 0x37cf0, 0x37cfc,
1019                 0x38000, 0x38030,
1020                 0x38038, 0x38038,
1021                 0x38040, 0x38040,
1022                 0x38100, 0x38144,
1023                 0x38190, 0x381a0,
1024                 0x381a8, 0x381b8,
1025                 0x381c4, 0x381c8,
1026                 0x381d0, 0x381d0,
1027                 0x38200, 0x38318,
1028                 0x38400, 0x384b4,
1029                 0x384c0, 0x3852c,
1030                 0x38540, 0x3861c,
1031                 0x38800, 0x38828,
1032                 0x38834, 0x38834,
1033                 0x388c0, 0x38908,
1034                 0x38910, 0x389ac,
1035                 0x38a00, 0x38a14,
1036                 0x38a1c, 0x38a2c,
1037                 0x38a44, 0x38a50,
1038                 0x38a74, 0x38a74,
1039                 0x38a7c, 0x38afc,
1040                 0x38b08, 0x38c24,
1041                 0x38d00, 0x38d00,
1042                 0x38d08, 0x38d14,
1043                 0x38d1c, 0x38d20,
1044                 0x38d3c, 0x38d3c,
1045                 0x38d48, 0x38d50,
1046                 0x39200, 0x3920c,
1047                 0x39220, 0x39220,
1048                 0x39240, 0x39240,
1049                 0x39600, 0x3960c,
1050                 0x39a00, 0x39a1c,
1051                 0x39e00, 0x39e20,
1052                 0x39e38, 0x39e3c,
1053                 0x39e80, 0x39e80,
1054                 0x39e88, 0x39ea8,
1055                 0x39eb0, 0x39eb4,
1056                 0x39ec8, 0x39ed4,
1057                 0x39fb8, 0x3a004,
1058                 0x3a200, 0x3a200,
1059                 0x3a208, 0x3a240,
1060                 0x3a248, 0x3a280,
1061                 0x3a288, 0x3a2c0,
1062                 0x3a2c8, 0x3a2fc,
1063                 0x3a600, 0x3a630,
1064                 0x3aa00, 0x3aabc,
1065                 0x3ab00, 0x3ab10,
1066                 0x3ab20, 0x3ab30,
1067                 0x3ab40, 0x3ab50,
1068                 0x3ab60, 0x3ab70,
1069                 0x3b000, 0x3b028,
1070                 0x3b030, 0x3b048,
1071                 0x3b060, 0x3b068,
1072                 0x3b070, 0x3b09c,
1073                 0x3b0f0, 0x3b128,
1074                 0x3b130, 0x3b148,
1075                 0x3b160, 0x3b168,
1076                 0x3b170, 0x3b19c,
1077                 0x3b1f0, 0x3b238,
1078                 0x3b240, 0x3b240,
1079                 0x3b248, 0x3b250,
1080                 0x3b25c, 0x3b264,
1081                 0x3b270, 0x3b2b8,
1082                 0x3b2c0, 0x3b2e4,
1083                 0x3b2f8, 0x3b338,
1084                 0x3b340, 0x3b340,
1085                 0x3b348, 0x3b350,
1086                 0x3b35c, 0x3b364,
1087                 0x3b370, 0x3b3b8,
1088                 0x3b3c0, 0x3b3e4,
1089                 0x3b3f8, 0x3b428,
1090                 0x3b430, 0x3b448,
1091                 0x3b460, 0x3b468,
1092                 0x3b470, 0x3b49c,
1093                 0x3b4f0, 0x3b528,
1094                 0x3b530, 0x3b548,
1095                 0x3b560, 0x3b568,
1096                 0x3b570, 0x3b59c,
1097                 0x3b5f0, 0x3b638,
1098                 0x3b640, 0x3b640,
1099                 0x3b648, 0x3b650,
1100                 0x3b65c, 0x3b664,
1101                 0x3b670, 0x3b6b8,
1102                 0x3b6c0, 0x3b6e4,
1103                 0x3b6f8, 0x3b738,
1104                 0x3b740, 0x3b740,
1105                 0x3b748, 0x3b750,
1106                 0x3b75c, 0x3b764,
1107                 0x3b770, 0x3b7b8,
1108                 0x3b7c0, 0x3b7e4,
1109                 0x3b7f8, 0x3b7fc,
1110                 0x3b814, 0x3b814,
1111                 0x3b82c, 0x3b82c,
1112                 0x3b880, 0x3b88c,
1113                 0x3b8e8, 0x3b8ec,
1114                 0x3b900, 0x3b928,
1115                 0x3b930, 0x3b948,
1116                 0x3b960, 0x3b968,
1117                 0x3b970, 0x3b99c,
1118                 0x3b9f0, 0x3ba38,
1119                 0x3ba40, 0x3ba40,
1120                 0x3ba48, 0x3ba50,
1121                 0x3ba5c, 0x3ba64,
1122                 0x3ba70, 0x3bab8,
1123                 0x3bac0, 0x3bae4,
1124                 0x3baf8, 0x3bb10,
1125                 0x3bb28, 0x3bb28,
1126                 0x3bb3c, 0x3bb50,
1127                 0x3bbf0, 0x3bc10,
1128                 0x3bc28, 0x3bc28,
1129                 0x3bc3c, 0x3bc50,
1130                 0x3bcf0, 0x3bcfc,
1131                 0x3c000, 0x3c030,
1132                 0x3c038, 0x3c038,
1133                 0x3c040, 0x3c040,
1134                 0x3c100, 0x3c144,
1135                 0x3c190, 0x3c1a0,
1136                 0x3c1a8, 0x3c1b8,
1137                 0x3c1c4, 0x3c1c8,
1138                 0x3c1d0, 0x3c1d0,
1139                 0x3c200, 0x3c318,
1140                 0x3c400, 0x3c4b4,
1141                 0x3c4c0, 0x3c52c,
1142                 0x3c540, 0x3c61c,
1143                 0x3c800, 0x3c828,
1144                 0x3c834, 0x3c834,
1145                 0x3c8c0, 0x3c908,
1146                 0x3c910, 0x3c9ac,
1147                 0x3ca00, 0x3ca14,
1148                 0x3ca1c, 0x3ca2c,
1149                 0x3ca44, 0x3ca50,
1150                 0x3ca74, 0x3ca74,
1151                 0x3ca7c, 0x3cafc,
1152                 0x3cb08, 0x3cc24,
1153                 0x3cd00, 0x3cd00,
1154                 0x3cd08, 0x3cd14,
1155                 0x3cd1c, 0x3cd20,
1156                 0x3cd3c, 0x3cd3c,
1157                 0x3cd48, 0x3cd50,
1158                 0x3d200, 0x3d20c,
1159                 0x3d220, 0x3d220,
1160                 0x3d240, 0x3d240,
1161                 0x3d600, 0x3d60c,
1162                 0x3da00, 0x3da1c,
1163                 0x3de00, 0x3de20,
1164                 0x3de38, 0x3de3c,
1165                 0x3de80, 0x3de80,
1166                 0x3de88, 0x3dea8,
1167                 0x3deb0, 0x3deb4,
1168                 0x3dec8, 0x3ded4,
1169                 0x3dfb8, 0x3e004,
1170                 0x3e200, 0x3e200,
1171                 0x3e208, 0x3e240,
1172                 0x3e248, 0x3e280,
1173                 0x3e288, 0x3e2c0,
1174                 0x3e2c8, 0x3e2fc,
1175                 0x3e600, 0x3e630,
1176                 0x3ea00, 0x3eabc,
1177                 0x3eb00, 0x3eb10,
1178                 0x3eb20, 0x3eb30,
1179                 0x3eb40, 0x3eb50,
1180                 0x3eb60, 0x3eb70,
1181                 0x3f000, 0x3f028,
1182                 0x3f030, 0x3f048,
1183                 0x3f060, 0x3f068,
1184                 0x3f070, 0x3f09c,
1185                 0x3f0f0, 0x3f128,
1186                 0x3f130, 0x3f148,
1187                 0x3f160, 0x3f168,
1188                 0x3f170, 0x3f19c,
1189                 0x3f1f0, 0x3f238,
1190                 0x3f240, 0x3f240,
1191                 0x3f248, 0x3f250,
1192                 0x3f25c, 0x3f264,
1193                 0x3f270, 0x3f2b8,
1194                 0x3f2c0, 0x3f2e4,
1195                 0x3f2f8, 0x3f338,
1196                 0x3f340, 0x3f340,
1197                 0x3f348, 0x3f350,
1198                 0x3f35c, 0x3f364,
1199                 0x3f370, 0x3f3b8,
1200                 0x3f3c0, 0x3f3e4,
1201                 0x3f3f8, 0x3f428,
1202                 0x3f430, 0x3f448,
1203                 0x3f460, 0x3f468,
1204                 0x3f470, 0x3f49c,
1205                 0x3f4f0, 0x3f528,
1206                 0x3f530, 0x3f548,
1207                 0x3f560, 0x3f568,
1208                 0x3f570, 0x3f59c,
1209                 0x3f5f0, 0x3f638,
1210                 0x3f640, 0x3f640,
1211                 0x3f648, 0x3f650,
1212                 0x3f65c, 0x3f664,
1213                 0x3f670, 0x3f6b8,
1214                 0x3f6c0, 0x3f6e4,
1215                 0x3f6f8, 0x3f738,
1216                 0x3f740, 0x3f740,
1217                 0x3f748, 0x3f750,
1218                 0x3f75c, 0x3f764,
1219                 0x3f770, 0x3f7b8,
1220                 0x3f7c0, 0x3f7e4,
1221                 0x3f7f8, 0x3f7fc,
1222                 0x3f814, 0x3f814,
1223                 0x3f82c, 0x3f82c,
1224                 0x3f880, 0x3f88c,
1225                 0x3f8e8, 0x3f8ec,
1226                 0x3f900, 0x3f928,
1227                 0x3f930, 0x3f948,
1228                 0x3f960, 0x3f968,
1229                 0x3f970, 0x3f99c,
1230                 0x3f9f0, 0x3fa38,
1231                 0x3fa40, 0x3fa40,
1232                 0x3fa48, 0x3fa50,
1233                 0x3fa5c, 0x3fa64,
1234                 0x3fa70, 0x3fab8,
1235                 0x3fac0, 0x3fae4,
1236                 0x3faf8, 0x3fb10,
1237                 0x3fb28, 0x3fb28,
1238                 0x3fb3c, 0x3fb50,
1239                 0x3fbf0, 0x3fc10,
1240                 0x3fc28, 0x3fc28,
1241                 0x3fc3c, 0x3fc50,
1242                 0x3fcf0, 0x3fcfc,
1243                 0x40000, 0x4000c,
1244                 0x40040, 0x40050,
1245                 0x40060, 0x40068,
1246                 0x4007c, 0x4008c,
1247                 0x40094, 0x400b0,
1248                 0x400c0, 0x40144,
1249                 0x40180, 0x4018c,
1250                 0x40200, 0x40254,
1251                 0x40260, 0x40264,
1252                 0x40270, 0x40288,
1253                 0x40290, 0x40298,
1254                 0x402ac, 0x402c8,
1255                 0x402d0, 0x402e0,
1256                 0x402f0, 0x402f0,
1257                 0x40300, 0x4033c,
1258                 0x403f8, 0x403fc,
1259                 0x41304, 0x413c4,
1260                 0x41400, 0x4140c,
1261                 0x41414, 0x4141c,
1262                 0x41480, 0x414d0,
1263                 0x44000, 0x44054,
1264                 0x4405c, 0x44078,
1265                 0x440c0, 0x44174,
1266                 0x44180, 0x441ac,
1267                 0x441b4, 0x441b8,
1268                 0x441c0, 0x44254,
1269                 0x4425c, 0x44278,
1270                 0x442c0, 0x44374,
1271                 0x44380, 0x443ac,
1272                 0x443b4, 0x443b8,
1273                 0x443c0, 0x44454,
1274                 0x4445c, 0x44478,
1275                 0x444c0, 0x44574,
1276                 0x44580, 0x445ac,
1277                 0x445b4, 0x445b8,
1278                 0x445c0, 0x44654,
1279                 0x4465c, 0x44678,
1280                 0x446c0, 0x44774,
1281                 0x44780, 0x447ac,
1282                 0x447b4, 0x447b8,
1283                 0x447c0, 0x44854,
1284                 0x4485c, 0x44878,
1285                 0x448c0, 0x44974,
1286                 0x44980, 0x449ac,
1287                 0x449b4, 0x449b8,
1288                 0x449c0, 0x449fc,
1289                 0x45000, 0x45004,
1290                 0x45010, 0x45030,
1291                 0x45040, 0x45060,
1292                 0x45068, 0x45068,
1293                 0x45080, 0x45084,
1294                 0x450a0, 0x450b0,
1295                 0x45200, 0x45204,
1296                 0x45210, 0x45230,
1297                 0x45240, 0x45260,
1298                 0x45268, 0x45268,
1299                 0x45280, 0x45284,
1300                 0x452a0, 0x452b0,
1301                 0x460c0, 0x460e4,
1302                 0x47000, 0x4703c,
1303                 0x47044, 0x4708c,
1304                 0x47200, 0x47250,
1305                 0x47400, 0x47408,
1306                 0x47414, 0x47420,
1307                 0x47600, 0x47618,
1308                 0x47800, 0x47814,
1309                 0x48000, 0x4800c,
1310                 0x48040, 0x48050,
1311                 0x48060, 0x48068,
1312                 0x4807c, 0x4808c,
1313                 0x48094, 0x480b0,
1314                 0x480c0, 0x48144,
1315                 0x48180, 0x4818c,
1316                 0x48200, 0x48254,
1317                 0x48260, 0x48264,
1318                 0x48270, 0x48288,
1319                 0x48290, 0x48298,
1320                 0x482ac, 0x482c8,
1321                 0x482d0, 0x482e0,
1322                 0x482f0, 0x482f0,
1323                 0x48300, 0x4833c,
1324                 0x483f8, 0x483fc,
1325                 0x49304, 0x493c4,
1326                 0x49400, 0x4940c,
1327                 0x49414, 0x4941c,
1328                 0x49480, 0x494d0,
1329                 0x4c000, 0x4c054,
1330                 0x4c05c, 0x4c078,
1331                 0x4c0c0, 0x4c174,
1332                 0x4c180, 0x4c1ac,
1333                 0x4c1b4, 0x4c1b8,
1334                 0x4c1c0, 0x4c254,
1335                 0x4c25c, 0x4c278,
1336                 0x4c2c0, 0x4c374,
1337                 0x4c380, 0x4c3ac,
1338                 0x4c3b4, 0x4c3b8,
1339                 0x4c3c0, 0x4c454,
1340                 0x4c45c, 0x4c478,
1341                 0x4c4c0, 0x4c574,
1342                 0x4c580, 0x4c5ac,
1343                 0x4c5b4, 0x4c5b8,
1344                 0x4c5c0, 0x4c654,
1345                 0x4c65c, 0x4c678,
1346                 0x4c6c0, 0x4c774,
1347                 0x4c780, 0x4c7ac,
1348                 0x4c7b4, 0x4c7b8,
1349                 0x4c7c0, 0x4c854,
1350                 0x4c85c, 0x4c878,
1351                 0x4c8c0, 0x4c974,
1352                 0x4c980, 0x4c9ac,
1353                 0x4c9b4, 0x4c9b8,
1354                 0x4c9c0, 0x4c9fc,
1355                 0x4d000, 0x4d004,
1356                 0x4d010, 0x4d030,
1357                 0x4d040, 0x4d060,
1358                 0x4d068, 0x4d068,
1359                 0x4d080, 0x4d084,
1360                 0x4d0a0, 0x4d0b0,
1361                 0x4d200, 0x4d204,
1362                 0x4d210, 0x4d230,
1363                 0x4d240, 0x4d260,
1364                 0x4d268, 0x4d268,
1365                 0x4d280, 0x4d284,
1366                 0x4d2a0, 0x4d2b0,
1367                 0x4e0c0, 0x4e0e4,
1368                 0x4f000, 0x4f03c,
1369                 0x4f044, 0x4f08c,
1370                 0x4f200, 0x4f250,
1371                 0x4f400, 0x4f408,
1372                 0x4f414, 0x4f420,
1373                 0x4f600, 0x4f618,
1374                 0x4f800, 0x4f814,
1375                 0x50000, 0x50084,
1376                 0x50090, 0x500cc,
1377                 0x50400, 0x50400,
1378                 0x50800, 0x50884,
1379                 0x50890, 0x508cc,
1380                 0x50c00, 0x50c00,
1381                 0x51000, 0x5101c,
1382                 0x51300, 0x51308,
1383         };
1384
1385         static const unsigned int t6_reg_ranges[] = {
1386                 0x1008, 0x101c,
1387                 0x1024, 0x10a8,
1388                 0x10b4, 0x10f8,
1389                 0x1100, 0x1114,
1390                 0x111c, 0x112c,
1391                 0x1138, 0x113c,
1392                 0x1144, 0x114c,
1393                 0x1180, 0x1184,
1394                 0x1190, 0x1194,
1395                 0x11a0, 0x11a4,
1396                 0x11b0, 0x11b4,
1397                 0x11fc, 0x1274,
1398                 0x1280, 0x133c,
1399                 0x1800, 0x18fc,
1400                 0x3000, 0x302c,
1401                 0x3060, 0x30b0,
1402                 0x30b8, 0x30d8,
1403                 0x30e0, 0x30fc,
1404                 0x3140, 0x357c,
1405                 0x35a8, 0x35cc,
1406                 0x35ec, 0x35ec,
1407                 0x3600, 0x5624,
1408                 0x56cc, 0x56ec,
1409                 0x56f4, 0x5720,
1410                 0x5728, 0x575c,
1411                 0x580c, 0x5814,
1412                 0x5890, 0x589c,
1413                 0x58a4, 0x58ac,
1414                 0x58b8, 0x58bc,
1415                 0x5940, 0x595c,
1416                 0x5980, 0x598c,
1417                 0x59b0, 0x59c8,
1418                 0x59d0, 0x59dc,
1419                 0x59fc, 0x5a18,
1420                 0x5a60, 0x5a6c,
1421                 0x5a80, 0x5a8c,
1422                 0x5a94, 0x5a9c,
1423                 0x5b94, 0x5bfc,
1424                 0x5c10, 0x5e48,
1425                 0x5e50, 0x5e94,
1426                 0x5ea0, 0x5eb0,
1427                 0x5ec0, 0x5ec0,
1428                 0x5ec8, 0x5ed0,
1429                 0x5ee0, 0x5ee0,
1430                 0x5ef0, 0x5ef0,
1431                 0x5f00, 0x5f00,
1432                 0x6000, 0x6020,
1433                 0x6028, 0x6040,
1434                 0x6058, 0x609c,
1435                 0x60a8, 0x619c,
1436                 0x7700, 0x7798,
1437                 0x77c0, 0x7880,
1438                 0x78cc, 0x78fc,
1439                 0x7b00, 0x7b58,
1440                 0x7b60, 0x7b84,
1441                 0x7b8c, 0x7c54,
1442                 0x7d00, 0x7d38,
1443                 0x7d40, 0x7d84,
1444                 0x7d8c, 0x7ddc,
1445                 0x7de4, 0x7e04,
1446                 0x7e10, 0x7e1c,
1447                 0x7e24, 0x7e38,
1448                 0x7e40, 0x7e44,
1449                 0x7e4c, 0x7e78,
1450                 0x7e80, 0x7edc,
1451                 0x7ee8, 0x7efc,
1452                 0x8dc0, 0x8de4,
1453                 0x8df8, 0x8e04,
1454                 0x8e10, 0x8e84,
1455                 0x8ea0, 0x8f88,
1456                 0x8fb8, 0x9058,
1457                 0x9060, 0x9060,
1458                 0x9068, 0x90f8,
1459                 0x9100, 0x9124,
1460                 0x9400, 0x9470,
1461                 0x9600, 0x9600,
1462                 0x9608, 0x9638,
1463                 0x9640, 0x9704,
1464                 0x9710, 0x971c,
1465                 0x9800, 0x9808,
1466                 0x9820, 0x983c,
1467                 0x9850, 0x9864,
1468                 0x9c00, 0x9c6c,
1469                 0x9c80, 0x9cec,
1470                 0x9d00, 0x9d6c,
1471                 0x9d80, 0x9dec,
1472                 0x9e00, 0x9e6c,
1473                 0x9e80, 0x9eec,
1474                 0x9f00, 0x9f6c,
1475                 0x9f80, 0xa020,
1476                 0xd004, 0xd03c,
1477                 0xd100, 0xd118,
1478                 0xd200, 0xd214,
1479                 0xd220, 0xd234,
1480                 0xd240, 0xd254,
1481                 0xd260, 0xd274,
1482                 0xd280, 0xd294,
1483                 0xd2a0, 0xd2b4,
1484                 0xd2c0, 0xd2d4,
1485                 0xd2e0, 0xd2f4,
1486                 0xd300, 0xd31c,
1487                 0xdfc0, 0xdfe0,
1488                 0xe000, 0xf008,
1489                 0xf010, 0xf018,
1490                 0xf020, 0xf028,
1491                 0x11000, 0x11014,
1492                 0x11048, 0x1106c,
1493                 0x11074, 0x11088,
1494                 0x11098, 0x11120,
1495                 0x1112c, 0x1117c,
1496                 0x11190, 0x112e0,
1497                 0x11300, 0x1130c,
1498                 0x12000, 0x1206c,
1499                 0x19040, 0x1906c,
1500                 0x19078, 0x19080,
1501                 0x1908c, 0x190e8,
1502                 0x190f0, 0x190f8,
1503                 0x19100, 0x19110,
1504                 0x19120, 0x19124,
1505                 0x19150, 0x19194,
1506                 0x1919c, 0x191b0,
1507                 0x191d0, 0x191e8,
1508                 0x19238, 0x19290,
1509                 0x192a4, 0x192b0,
1510                 0x192bc, 0x192bc,
1511                 0x19348, 0x1934c,
1512                 0x193f8, 0x19418,
1513                 0x19420, 0x19428,
1514                 0x19430, 0x19444,
1515                 0x1944c, 0x1946c,
1516                 0x19474, 0x19474,
1517                 0x19490, 0x194cc,
1518                 0x194f0, 0x194f8,
1519                 0x19c00, 0x19c48,
1520                 0x19c50, 0x19c80,
1521                 0x19c94, 0x19c98,
1522                 0x19ca0, 0x19cbc,
1523                 0x19ce4, 0x19ce4,
1524                 0x19cf0, 0x19cf8,
1525                 0x19d00, 0x19d28,
1526                 0x19d50, 0x19d78,
1527                 0x19d94, 0x19d98,
1528                 0x19da0, 0x19dc8,
1529                 0x19df0, 0x19e10,
1530                 0x19e50, 0x19e6c,
1531                 0x19ea0, 0x19ebc,
1532                 0x19ec4, 0x19ef4,
1533                 0x19f04, 0x19f2c,
1534                 0x19f34, 0x19f34,
1535                 0x19f40, 0x19f50,
1536                 0x19f90, 0x19fac,
1537                 0x19fc4, 0x19fc8,
1538                 0x19fd0, 0x19fe4,
1539                 0x1a000, 0x1a004,
1540                 0x1a010, 0x1a06c,
1541                 0x1a0b0, 0x1a0e4,
1542                 0x1a0ec, 0x1a0f8,
1543                 0x1a100, 0x1a108,
1544                 0x1a114, 0x1a120,
1545                 0x1a128, 0x1a130,
1546                 0x1a138, 0x1a138,
1547                 0x1a190, 0x1a1c4,
1548                 0x1a1fc, 0x1a1fc,
1549                 0x1e008, 0x1e00c,
1550                 0x1e040, 0x1e044,
1551                 0x1e04c, 0x1e04c,
1552                 0x1e284, 0x1e290,
1553                 0x1e2c0, 0x1e2c0,
1554                 0x1e2e0, 0x1e2e0,
1555                 0x1e300, 0x1e384,
1556                 0x1e3c0, 0x1e3c8,
1557                 0x1e408, 0x1e40c,
1558                 0x1e440, 0x1e444,
1559                 0x1e44c, 0x1e44c,
1560                 0x1e684, 0x1e690,
1561                 0x1e6c0, 0x1e6c0,
1562                 0x1e6e0, 0x1e6e0,
1563                 0x1e700, 0x1e784,
1564                 0x1e7c0, 0x1e7c8,
1565                 0x1e808, 0x1e80c,
1566                 0x1e840, 0x1e844,
1567                 0x1e84c, 0x1e84c,
1568                 0x1ea84, 0x1ea90,
1569                 0x1eac0, 0x1eac0,
1570                 0x1eae0, 0x1eae0,
1571                 0x1eb00, 0x1eb84,
1572                 0x1ebc0, 0x1ebc8,
1573                 0x1ec08, 0x1ec0c,
1574                 0x1ec40, 0x1ec44,
1575                 0x1ec4c, 0x1ec4c,
1576                 0x1ee84, 0x1ee90,
1577                 0x1eec0, 0x1eec0,
1578                 0x1eee0, 0x1eee0,
1579                 0x1ef00, 0x1ef84,
1580                 0x1efc0, 0x1efc8,
1581                 0x1f008, 0x1f00c,
1582                 0x1f040, 0x1f044,
1583                 0x1f04c, 0x1f04c,
1584                 0x1f284, 0x1f290,
1585                 0x1f2c0, 0x1f2c0,
1586                 0x1f2e0, 0x1f2e0,
1587                 0x1f300, 0x1f384,
1588                 0x1f3c0, 0x1f3c8,
1589                 0x1f408, 0x1f40c,
1590                 0x1f440, 0x1f444,
1591                 0x1f44c, 0x1f44c,
1592                 0x1f684, 0x1f690,
1593                 0x1f6c0, 0x1f6c0,
1594                 0x1f6e0, 0x1f6e0,
1595                 0x1f700, 0x1f784,
1596                 0x1f7c0, 0x1f7c8,
1597                 0x1f808, 0x1f80c,
1598                 0x1f840, 0x1f844,
1599                 0x1f84c, 0x1f84c,
1600                 0x1fa84, 0x1fa90,
1601                 0x1fac0, 0x1fac0,
1602                 0x1fae0, 0x1fae0,
1603                 0x1fb00, 0x1fb84,
1604                 0x1fbc0, 0x1fbc8,
1605                 0x1fc08, 0x1fc0c,
1606                 0x1fc40, 0x1fc44,
1607                 0x1fc4c, 0x1fc4c,
1608                 0x1fe84, 0x1fe90,
1609                 0x1fec0, 0x1fec0,
1610                 0x1fee0, 0x1fee0,
1611                 0x1ff00, 0x1ff84,
1612                 0x1ffc0, 0x1ffc8,
1613                 0x30000, 0x30030,
1614                 0x30100, 0x30168,
1615                 0x30190, 0x301a0,
1616                 0x301a8, 0x301b8,
1617                 0x301c4, 0x301c8,
1618                 0x301d0, 0x301d0,
1619                 0x30200, 0x30320,
1620                 0x30400, 0x304b4,
1621                 0x304c0, 0x3052c,
1622                 0x30540, 0x3061c,
1623                 0x30800, 0x308a0,
1624                 0x308c0, 0x30908,
1625                 0x30910, 0x309b8,
1626                 0x30a00, 0x30a04,
1627                 0x30a0c, 0x30a14,
1628                 0x30a1c, 0x30a2c,
1629                 0x30a44, 0x30a50,
1630                 0x30a74, 0x30a74,
1631                 0x30a7c, 0x30afc,
1632                 0x30b08, 0x30c24,
1633                 0x30d00, 0x30d14,
1634                 0x30d1c, 0x30d3c,
1635                 0x30d44, 0x30d4c,
1636                 0x30d54, 0x30d74,
1637                 0x30d7c, 0x30d7c,
1638                 0x30de0, 0x30de0,
1639                 0x30e00, 0x30ed4,
1640                 0x30f00, 0x30fa4,
1641                 0x30fc0, 0x30fc4,
1642                 0x31000, 0x31004,
1643                 0x31080, 0x310fc,
1644                 0x31208, 0x31220,
1645                 0x3123c, 0x31254,
1646                 0x31300, 0x31300,
1647                 0x31308, 0x3131c,
1648                 0x31338, 0x3133c,
1649                 0x31380, 0x31380,
1650                 0x31388, 0x313a8,
1651                 0x313b4, 0x313b4,
1652                 0x31400, 0x31420,
1653                 0x31438, 0x3143c,
1654                 0x31480, 0x31480,
1655                 0x314a8, 0x314a8,
1656                 0x314b0, 0x314b4,
1657                 0x314c8, 0x314d4,
1658                 0x31a40, 0x31a4c,
1659                 0x31af0, 0x31b20,
1660                 0x31b38, 0x31b3c,
1661                 0x31b80, 0x31b80,
1662                 0x31ba8, 0x31ba8,
1663                 0x31bb0, 0x31bb4,
1664                 0x31bc8, 0x31bd4,
1665                 0x32140, 0x3218c,
1666                 0x321f0, 0x321f4,
1667                 0x32200, 0x32200,
1668                 0x32218, 0x32218,
1669                 0x32400, 0x32400,
1670                 0x32408, 0x3241c,
1671                 0x32618, 0x32620,
1672                 0x32664, 0x32664,
1673                 0x326a8, 0x326a8,
1674                 0x326ec, 0x326ec,
1675                 0x32a00, 0x32abc,
1676                 0x32b00, 0x32b38,
1677                 0x32b20, 0x32b38,
1678                 0x32b40, 0x32b58,
1679                 0x32b60, 0x32b78,
1680                 0x32c00, 0x32c00,
1681                 0x32c08, 0x32c3c,
1682                 0x33000, 0x3302c,
1683                 0x33034, 0x33050,
1684                 0x33058, 0x33058,
1685                 0x33060, 0x3308c,
1686                 0x3309c, 0x330ac,
1687                 0x330c0, 0x330c0,
1688                 0x330c8, 0x330d0,
1689                 0x330d8, 0x330e0,
1690                 0x330ec, 0x3312c,
1691                 0x33134, 0x33150,
1692                 0x33158, 0x33158,
1693                 0x33160, 0x3318c,
1694                 0x3319c, 0x331ac,
1695                 0x331c0, 0x331c0,
1696                 0x331c8, 0x331d0,
1697                 0x331d8, 0x331e0,
1698                 0x331ec, 0x33290,
1699                 0x33298, 0x332c4,
1700                 0x332e4, 0x33390,
1701                 0x33398, 0x333c4,
1702                 0x333e4, 0x3342c,
1703                 0x33434, 0x33450,
1704                 0x33458, 0x33458,
1705                 0x33460, 0x3348c,
1706                 0x3349c, 0x334ac,
1707                 0x334c0, 0x334c0,
1708                 0x334c8, 0x334d0,
1709                 0x334d8, 0x334e0,
1710                 0x334ec, 0x3352c,
1711                 0x33534, 0x33550,
1712                 0x33558, 0x33558,
1713                 0x33560, 0x3358c,
1714                 0x3359c, 0x335ac,
1715                 0x335c0, 0x335c0,
1716                 0x335c8, 0x335d0,
1717                 0x335d8, 0x335e0,
1718                 0x335ec, 0x33690,
1719                 0x33698, 0x336c4,
1720                 0x336e4, 0x33790,
1721                 0x33798, 0x337c4,
1722                 0x337e4, 0x337fc,
1723                 0x33814, 0x33814,
1724                 0x33854, 0x33868,
1725                 0x33880, 0x3388c,
1726                 0x338c0, 0x338d0,
1727                 0x338e8, 0x338ec,
1728                 0x33900, 0x3392c,
1729                 0x33934, 0x33950,
1730                 0x33958, 0x33958,
1731                 0x33960, 0x3398c,
1732                 0x3399c, 0x339ac,
1733                 0x339c0, 0x339c0,
1734                 0x339c8, 0x339d0,
1735                 0x339d8, 0x339e0,
1736                 0x339ec, 0x33a90,
1737                 0x33a98, 0x33ac4,
1738                 0x33ae4, 0x33b10,
1739                 0x33b24, 0x33b28,
1740                 0x33b38, 0x33b50,
1741                 0x33bf0, 0x33c10,
1742                 0x33c24, 0x33c28,
1743                 0x33c38, 0x33c50,
1744                 0x33cf0, 0x33cfc,
1745                 0x34000, 0x34030,
1746                 0x34100, 0x34168,
1747                 0x34190, 0x341a0,
1748                 0x341a8, 0x341b8,
1749                 0x341c4, 0x341c8,
1750                 0x341d0, 0x341d0,
1751                 0x34200, 0x34320,
1752                 0x34400, 0x344b4,
1753                 0x344c0, 0x3452c,
1754                 0x34540, 0x3461c,
1755                 0x34800, 0x348a0,
1756                 0x348c0, 0x34908,
1757                 0x34910, 0x349b8,
1758                 0x34a00, 0x34a04,
1759                 0x34a0c, 0x34a14,
1760                 0x34a1c, 0x34a2c,
1761                 0x34a44, 0x34a50,
1762                 0x34a74, 0x34a74,
1763                 0x34a7c, 0x34afc,
1764                 0x34b08, 0x34c24,
1765                 0x34d00, 0x34d14,
1766                 0x34d1c, 0x34d3c,
1767                 0x34d44, 0x34d4c,
1768                 0x34d54, 0x34d74,
1769                 0x34d7c, 0x34d7c,
1770                 0x34de0, 0x34de0,
1771                 0x34e00, 0x34ed4,
1772                 0x34f00, 0x34fa4,
1773                 0x34fc0, 0x34fc4,
1774                 0x35000, 0x35004,
1775                 0x35080, 0x350fc,
1776                 0x35208, 0x35220,
1777                 0x3523c, 0x35254,
1778                 0x35300, 0x35300,
1779                 0x35308, 0x3531c,
1780                 0x35338, 0x3533c,
1781                 0x35380, 0x35380,
1782                 0x35388, 0x353a8,
1783                 0x353b4, 0x353b4,
1784                 0x35400, 0x35420,
1785                 0x35438, 0x3543c,
1786                 0x35480, 0x35480,
1787                 0x354a8, 0x354a8,
1788                 0x354b0, 0x354b4,
1789                 0x354c8, 0x354d4,
1790                 0x35a40, 0x35a4c,
1791                 0x35af0, 0x35b20,
1792                 0x35b38, 0x35b3c,
1793                 0x35b80, 0x35b80,
1794                 0x35ba8, 0x35ba8,
1795                 0x35bb0, 0x35bb4,
1796                 0x35bc8, 0x35bd4,
1797                 0x36140, 0x3618c,
1798                 0x361f0, 0x361f4,
1799                 0x36200, 0x36200,
1800                 0x36218, 0x36218,
1801                 0x36400, 0x36400,
1802                 0x36408, 0x3641c,
1803                 0x36618, 0x36620,
1804                 0x36664, 0x36664,
1805                 0x366a8, 0x366a8,
1806                 0x366ec, 0x366ec,
1807                 0x36a00, 0x36abc,
1808                 0x36b00, 0x36b38,
1809                 0x36b20, 0x36b38,
1810                 0x36b40, 0x36b58,
1811                 0x36b60, 0x36b78,
1812                 0x36c00, 0x36c00,
1813                 0x36c08, 0x36c3c,
1814                 0x37000, 0x3702c,
1815                 0x37034, 0x37050,
1816                 0x37058, 0x37058,
1817                 0x37060, 0x3708c,
1818                 0x3709c, 0x370ac,
1819                 0x370c0, 0x370c0,
1820                 0x370c8, 0x370d0,
1821                 0x370d8, 0x370e0,
1822                 0x370ec, 0x3712c,
1823                 0x37134, 0x37150,
1824                 0x37158, 0x37158,
1825                 0x37160, 0x3718c,
1826                 0x3719c, 0x371ac,
1827                 0x371c0, 0x371c0,
1828                 0x371c8, 0x371d0,
1829                 0x371d8, 0x371e0,
1830                 0x371ec, 0x37290,
1831                 0x37298, 0x372c4,
1832                 0x372e4, 0x37390,
1833                 0x37398, 0x373c4,
1834                 0x373e4, 0x3742c,
1835                 0x37434, 0x37450,
1836                 0x37458, 0x37458,
1837                 0x37460, 0x3748c,
1838                 0x3749c, 0x374ac,
1839                 0x374c0, 0x374c0,
1840                 0x374c8, 0x374d0,
1841                 0x374d8, 0x374e0,
1842                 0x374ec, 0x3752c,
1843                 0x37534, 0x37550,
1844                 0x37558, 0x37558,
1845                 0x37560, 0x3758c,
1846                 0x3759c, 0x375ac,
1847                 0x375c0, 0x375c0,
1848                 0x375c8, 0x375d0,
1849                 0x375d8, 0x375e0,
1850                 0x375ec, 0x37690,
1851                 0x37698, 0x376c4,
1852                 0x376e4, 0x37790,
1853                 0x37798, 0x377c4,
1854                 0x377e4, 0x377fc,
1855                 0x37814, 0x37814,
1856                 0x37854, 0x37868,
1857                 0x37880, 0x3788c,
1858                 0x378c0, 0x378d0,
1859                 0x378e8, 0x378ec,
1860                 0x37900, 0x3792c,
1861                 0x37934, 0x37950,
1862                 0x37958, 0x37958,
1863                 0x37960, 0x3798c,
1864                 0x3799c, 0x379ac,
1865                 0x379c0, 0x379c0,
1866                 0x379c8, 0x379d0,
1867                 0x379d8, 0x379e0,
1868                 0x379ec, 0x37a90,
1869                 0x37a98, 0x37ac4,
1870                 0x37ae4, 0x37b10,
1871                 0x37b24, 0x37b28,
1872                 0x37b38, 0x37b50,
1873                 0x37bf0, 0x37c10,
1874                 0x37c24, 0x37c28,
1875                 0x37c38, 0x37c50,
1876                 0x37cf0, 0x37cfc,
1877                 0x40040, 0x40040,
1878                 0x40080, 0x40084,
1879                 0x40100, 0x40100,
1880                 0x40140, 0x401bc,
1881                 0x40200, 0x40214,
1882                 0x40228, 0x40228,
1883                 0x40240, 0x40258,
1884                 0x40280, 0x40280,
1885                 0x40304, 0x40304,
1886                 0x40330, 0x4033c,
1887                 0x41304, 0x413c8,
1888                 0x413d0, 0x413dc,
1889                 0x413f0, 0x413f0,
1890                 0x41400, 0x4140c,
1891                 0x41414, 0x4141c,
1892                 0x41480, 0x414d0,
1893                 0x44000, 0x4407c,
1894                 0x440c0, 0x441ac,
1895                 0x441b4, 0x4427c,
1896                 0x442c0, 0x443ac,
1897                 0x443b4, 0x4447c,
1898                 0x444c0, 0x445ac,
1899                 0x445b4, 0x4467c,
1900                 0x446c0, 0x447ac,
1901                 0x447b4, 0x4487c,
1902                 0x448c0, 0x449ac,
1903                 0x449b4, 0x44a7c,
1904                 0x44ac0, 0x44bac,
1905                 0x44bb4, 0x44c7c,
1906                 0x44cc0, 0x44dac,
1907                 0x44db4, 0x44e7c,
1908                 0x44ec0, 0x44fac,
1909                 0x44fb4, 0x4507c,
1910                 0x450c0, 0x451ac,
1911                 0x451b4, 0x451fc,
1912                 0x45800, 0x45804,
1913                 0x45810, 0x45830,
1914                 0x45840, 0x45860,
1915                 0x45868, 0x45868,
1916                 0x45880, 0x45884,
1917                 0x458a0, 0x458b0,
1918                 0x45a00, 0x45a04,
1919                 0x45a10, 0x45a30,
1920                 0x45a40, 0x45a60,
1921                 0x45a68, 0x45a68,
1922                 0x45a80, 0x45a84,
1923                 0x45aa0, 0x45ab0,
1924                 0x460c0, 0x460e4,
1925                 0x47000, 0x4703c,
1926                 0x47044, 0x4708c,
1927                 0x47200, 0x47250,
1928                 0x47400, 0x47408,
1929                 0x47414, 0x47420,
1930                 0x47600, 0x47618,
1931                 0x47800, 0x47814,
1932                 0x47820, 0x4782c,
1933                 0x50000, 0x50084,
1934                 0x50090, 0x500cc,
1935                 0x50300, 0x50384,
1936                 0x50400, 0x50400,
1937                 0x50800, 0x50884,
1938                 0x50890, 0x508cc,
1939                 0x50b00, 0x50b84,
1940                 0x50c00, 0x50c00,
1941                 0x51000, 0x51020,
1942                 0x51028, 0x510b0,
1943                 0x51300, 0x51324,
1944         };
1945
1946         u32 *buf_end = (u32 *)((char *)buf + buf_size);
1947         const unsigned int *reg_ranges;
1948         int reg_ranges_size, range;
1949         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1950
1951         /* Select the right set of register ranges to dump depending on the
1952          * adapter chip type.
1953          */
1954         switch (chip_version) {
1955         case CHELSIO_T5:
1956                 reg_ranges = t5_reg_ranges;
1957                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1958                 break;
1959
1960         case CHELSIO_T6:
1961                 reg_ranges = t6_reg_ranges;
1962                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1963                 break;
1964
1965         default:
1966                 dev_err(adap,
1967                         "Unsupported chip version %d\n", chip_version);
1968                 return;
1969         }
1970
1971         /* Clear the register buffer and insert the appropriate register
1972          * values selected by the above register ranges.
1973          */
1974         memset(buf, 0, buf_size);
1975         for (range = 0; range < reg_ranges_size; range += 2) {
1976                 unsigned int reg = reg_ranges[range];
1977                 unsigned int last_reg = reg_ranges[range + 1];
1978                 u32 *bufp = (u32 *)((char *)buf + reg);
1979
1980                 /* Iterate across the register range filling in the register
1981                  * buffer but don't write past the end of the register buffer.
1982                  */
1983                 while (reg <= last_reg && bufp < buf_end) {
1984                         *bufp++ = t4_read_reg(adap, reg);
1985                         reg += sizeof(u32);
1986                 }
1987         }
1988 }
1989
1990 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1991 #define EEPROM_DELAY            10              /* 10us per poll spin */
1992 #define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
1993
1994 #define EEPROM_STAT_ADDR        0x7bfc
1995
1996 /**
1997  * Small utility function to wait till any outstanding VPD Access is complete.
1998  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1999  * VPD Access in flight.  This allows us to handle the problem of having a
2000  * previous VPD Access time out and prevent an attempt to inject a new VPD
2001  * Request before any in-flight VPD request has completed.
2002  */
2003 static int t4_seeprom_wait(struct adapter *adapter)
2004 {
2005         unsigned int base = adapter->params.pci.vpd_cap_addr;
2006         int max_poll;
2007
2008         /* If no VPD Access is in flight, we can just return success right
2009          * away.
2010          */
2011         if (!adapter->vpd_busy)
2012                 return 0;
2013
2014         /* Poll the VPD Capability Address/Flag register waiting for it
2015          * to indicate that the operation is complete.
2016          */
2017         max_poll = EEPROM_MAX_POLL;
2018         do {
2019                 u16 val;
2020
2021                 udelay(EEPROM_DELAY);
2022                 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2023
2024                 /* If the operation is complete, mark the VPD as no longer
2025                  * busy and return success.
2026                  */
2027                 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2028                         adapter->vpd_busy = 0;
2029                         return 0;
2030                 }
2031         } while (--max_poll);
2032
2033         /* Failure!  Note that we leave the VPD Busy status set in order to
2034          * avoid pushing a new VPD Access request into the VPD Capability till
2035          * the current operation eventually succeeds.  It's a bug to issue a
2036          * new request when an existing request is in flight and will result
2037          * in corrupt hardware state.
2038          */
2039         return -ETIMEDOUT;
2040 }
2041
2042 /**
2043  * t4_seeprom_read - read a serial EEPROM location
2044  * @adapter: adapter to read
2045  * @addr: EEPROM virtual address
2046  * @data: where to store the read data
2047  *
2048  * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2049  * VPD capability.  Note that this function must be called with a virtual
2050  * address.
2051  */
2052 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2053 {
2054         unsigned int base = adapter->params.pci.vpd_cap_addr;
2055         int ret;
2056
2057         /* VPD Accesses must alway be 4-byte aligned!
2058          */
2059         if (addr >= EEPROMVSIZE || (addr & 3))
2060                 return -EINVAL;
2061
2062         /* Wait for any previous operation which may still be in flight to
2063          * complete.
2064          */
2065         ret = t4_seeprom_wait(adapter);
2066         if (ret) {
2067                 dev_err(adapter, "VPD still busy from previous operation\n");
2068                 return ret;
2069         }
2070
2071         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2072          * for our request to complete.  If it doesn't complete, note the
2073          * error and return it to our caller.  Note that we do not reset the
2074          * VPD Busy status!
2075          */
2076         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2077         adapter->vpd_busy = 1;
2078         adapter->vpd_flag = PCI_VPD_ADDR_F;
2079         ret = t4_seeprom_wait(adapter);
2080         if (ret) {
2081                 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2082                 return ret;
2083         }
2084
2085         /* Grab the returned data, swizzle it into our endianness and
2086          * return success.
2087          */
2088         t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2089         *data = le32_to_cpu(*data);
2090         return 0;
2091 }
2092
2093 /**
2094  * t4_seeprom_write - write a serial EEPROM location
2095  * @adapter: adapter to write
2096  * @addr: virtual EEPROM address
2097  * @data: value to write
2098  *
2099  * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2100  * VPD capability.  Note that this function must be called with a virtual
2101  * address.
2102  */
2103 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2104 {
2105         unsigned int base = adapter->params.pci.vpd_cap_addr;
2106         int ret;
2107         u32 stats_reg = 0;
2108         int max_poll;
2109
2110         /* VPD Accesses must alway be 4-byte aligned!
2111          */
2112         if (addr >= EEPROMVSIZE || (addr & 3))
2113                 return -EINVAL;
2114
2115         /* Wait for any previous operation which may still be in flight to
2116          * complete.
2117          */
2118         ret = t4_seeprom_wait(adapter);
2119         if (ret) {
2120                 dev_err(adapter, "VPD still busy from previous operation\n");
2121                 return ret;
2122         }
2123
2124         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2125          * for our request to complete.  If it doesn't complete, note the
2126          * error and return it to our caller.  Note that we do not reset the
2127          * VPD Busy status!
2128          */
2129         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2130                              cpu_to_le32(data));
2131         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2132                              (u16)addr | PCI_VPD_ADDR_F);
2133         adapter->vpd_busy = 1;
2134         adapter->vpd_flag = 0;
2135         ret = t4_seeprom_wait(adapter);
2136         if (ret) {
2137                 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2138                 return ret;
2139         }
2140
2141         /* Reset PCI_VPD_DATA register after a transaction and wait for our
2142          * request to complete. If it doesn't complete, return error.
2143          */
2144         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2145         max_poll = EEPROM_MAX_POLL;
2146         do {
2147                 udelay(EEPROM_DELAY);
2148                 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2149         } while ((stats_reg & 0x1) && --max_poll);
2150         if (!max_poll)
2151                 return -ETIMEDOUT;
2152
2153         /* Return success! */
2154         return 0;
2155 }
2156
2157 /**
2158  * t4_seeprom_wp - enable/disable EEPROM write protection
2159  * @adapter: the adapter
2160  * @enable: whether to enable or disable write protection
2161  *
2162  * Enables or disables write protection on the serial EEPROM.
2163  */
2164 int t4_seeprom_wp(struct adapter *adapter, int enable)
2165 {
2166         return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2167 }
2168
2169 /**
2170  * t4_fw_tp_pio_rw - Access TP PIO through LDST
2171  * @adap: the adapter
2172  * @vals: where the indirect register values are stored/written
2173  * @nregs: how many indirect registers to read/write
2174  * @start_idx: index of first indirect register to read/write
2175  * @rw: Read (1) or Write (0)
2176  *
2177  * Access TP PIO registers through LDST
2178  */
2179 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
2180                      unsigned int start_index, unsigned int rw)
2181 {
2182         int cmd = FW_LDST_ADDRSPC_TP_PIO;
2183         struct fw_ldst_cmd c;
2184         unsigned int i;
2185         int ret;
2186
2187         for (i = 0 ; i < nregs; i++) {
2188                 memset(&c, 0, sizeof(c));
2189                 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
2190                                                 F_FW_CMD_REQUEST |
2191                                                 (rw ? F_FW_CMD_READ :
2192                                                       F_FW_CMD_WRITE) |
2193                                                 V_FW_LDST_CMD_ADDRSPACE(cmd));
2194                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
2195
2196                 c.u.addrval.addr = cpu_to_be32(start_index + i);
2197                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
2198                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2199                 if (ret == 0) {
2200                         if (rw)
2201                                 vals[i] = be32_to_cpu(c.u.addrval.val);
2202                 }
2203         }
2204 }
2205
2206 /**
2207  * t4_read_rss_key - read the global RSS key
2208  * @adap: the adapter
2209  * @key: 10-entry array holding the 320-bit RSS key
2210  *
2211  * Reads the global 320-bit RSS key.
2212  */
2213 void t4_read_rss_key(struct adapter *adap, u32 *key)
2214 {
2215         t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 1);
2216 }
2217
2218 /**
2219  * t4_write_rss_key - program one of the RSS keys
2220  * @adap: the adapter
2221  * @key: 10-entry array holding the 320-bit RSS key
2222  * @idx: which RSS key to write
2223  *
2224  * Writes one of the RSS keys with the given 320-bit value.  If @idx is
2225  * 0..15 the corresponding entry in the RSS key table is written,
2226  * otherwise the global RSS key is written.
2227  */
2228 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
2229 {
2230         u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
2231         u8 rss_key_addr_cnt = 16;
2232
2233         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
2234          * allows access to key addresses 16-63 by using KeyWrAddrX
2235          * as index[5:4](upper 2) into key table
2236          */
2237         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
2238             (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
2239                 rss_key_addr_cnt = 32;
2240
2241         t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
2242
2243         if (idx >= 0 && idx < rss_key_addr_cnt) {
2244                 if (rss_key_addr_cnt > 16)
2245                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2246                                      V_KEYWRADDRX(idx >> 4) |
2247                                      V_T6_VFWRADDR(idx) | F_KEYWREN);
2248                 else
2249                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2250                                      V_KEYWRADDR(idx) | F_KEYWREN);
2251         }
2252 }
2253
2254 /**
2255  * t4_config_rss_range - configure a portion of the RSS mapping table
2256  * @adapter: the adapter
2257  * @mbox: mbox to use for the FW command
2258  * @viid: virtual interface whose RSS subtable is to be written
2259  * @start: start entry in the table to write
2260  * @n: how many table entries to write
2261  * @rspq: values for the "response queue" (Ingress Queue) lookup table
2262  * @nrspq: number of values in @rspq
2263  *
2264  * Programs the selected part of the VI's RSS mapping table with the
2265  * provided values.  If @nrspq < @n the supplied values are used repeatedly
2266  * until the full table range is populated.
2267  *
2268  * The caller must ensure the values in @rspq are in the range allowed for
2269  * @viid.
2270  */
2271 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2272                         int start, int n, const u16 *rspq, unsigned int nrspq)
2273 {
2274         int ret;
2275         const u16 *rsp = rspq;
2276         const u16 *rsp_end = rspq + nrspq;
2277         struct fw_rss_ind_tbl_cmd cmd;
2278
2279         memset(&cmd, 0, sizeof(cmd));
2280         cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2281                                      F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2282                                      V_FW_RSS_IND_TBL_CMD_VIID(viid));
2283         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2284
2285         /*
2286          * Each firmware RSS command can accommodate up to 32 RSS Ingress
2287          * Queue Identifiers.  These Ingress Queue IDs are packed three to
2288          * a 32-bit word as 10-bit values with the upper remaining 2 bits
2289          * reserved.
2290          */
2291         while (n > 0) {
2292                 int nq = min(n, 32);
2293                 int nq_packed = 0;
2294                 __be32 *qp = &cmd.iq0_to_iq2;
2295
2296                 /*
2297                  * Set up the firmware RSS command header to send the next
2298                  * "nq" Ingress Queue IDs to the firmware.
2299                  */
2300                 cmd.niqid = cpu_to_be16(nq);
2301                 cmd.startidx = cpu_to_be16(start);
2302
2303                 /*
2304                  * "nq" more done for the start of the next loop.
2305                  */
2306                 start += nq;
2307                 n -= nq;
2308
2309                 /*
2310                  * While there are still Ingress Queue IDs to stuff into the
2311                  * current firmware RSS command, retrieve them from the
2312                  * Ingress Queue ID array and insert them into the command.
2313                  */
2314                 while (nq > 0) {
2315                         /*
2316                          * Grab up to the next 3 Ingress Queue IDs (wrapping
2317                          * around the Ingress Queue ID array if necessary) and
2318                          * insert them into the firmware RSS command at the
2319                          * current 3-tuple position within the commad.
2320                          */
2321                         u16 qbuf[3];
2322                         u16 *qbp = qbuf;
2323                         int nqbuf = min(3, nq);
2324
2325                         nq -= nqbuf;
2326                         qbuf[0] = 0;
2327                         qbuf[1] = 0;
2328                         qbuf[2] = 0;
2329                         while (nqbuf && nq_packed < 32) {
2330                                 nqbuf--;
2331                                 nq_packed++;
2332                                 *qbp++ = *rsp++;
2333                                 if (rsp >= rsp_end)
2334                                         rsp = rspq;
2335                         }
2336                         *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2337                                             V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2338                                             V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2339                 }
2340
2341                 /*
2342                  * Send this portion of the RRS table update to the firmware;
2343                  * bail out on any errors.
2344                  */
2345                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2346                 if (ret)
2347                         return ret;
2348         }
2349
2350         return 0;
2351 }
2352
2353 /**
2354  * t4_config_vi_rss - configure per VI RSS settings
2355  * @adapter: the adapter
2356  * @mbox: mbox to use for the FW command
2357  * @viid: the VI id
2358  * @flags: RSS flags
2359  * @defq: id of the default RSS queue for the VI.
2360  *
2361  * Configures VI-specific RSS properties.
2362  */
2363 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2364                      unsigned int flags, unsigned int defq)
2365 {
2366         struct fw_rss_vi_config_cmd c;
2367
2368         memset(&c, 0, sizeof(c));
2369         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2370                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2371                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2372         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2373         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2374                         V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2375         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2376 }
2377
2378 /**
2379  * t4_read_config_vi_rss - read the configured per VI RSS settings
2380  * @adapter: the adapter
2381  * @mbox: mbox to use for the FW command
2382  * @viid: the VI id
2383  * @flags: where to place the configured flags
2384  * @defq: where to place the id of the default RSS queue for the VI.
2385  *
2386  * Read configured VI-specific RSS properties.
2387  */
2388 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2389                           u64 *flags, unsigned int *defq)
2390 {
2391         struct fw_rss_vi_config_cmd c;
2392         unsigned int result;
2393         int ret;
2394
2395         memset(&c, 0, sizeof(c));
2396         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2397                                    F_FW_CMD_REQUEST | F_FW_CMD_READ |
2398                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2399         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2400         ret = t4_wr_mbox(adapter, mbox, &c, sizeof(c), &c);
2401         if (!ret) {
2402                 result = be32_to_cpu(c.u.basicvirtual.defaultq_to_udpen);
2403                 if (defq)
2404                         *defq = G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(result);
2405                 if (flags)
2406                         *flags = result & M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ;
2407         }
2408
2409         return ret;
2410 }
2411
2412 /**
2413  * init_cong_ctrl - initialize congestion control parameters
2414  * @a: the alpha values for congestion control
2415  * @b: the beta values for congestion control
2416  *
2417  * Initialize the congestion control parameters.
2418  */
2419 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2420 {
2421         int i;
2422
2423         for (i = 0; i < 9; i++) {
2424                 a[i] = 1;
2425                 b[i] = 0;
2426         }
2427
2428         a[9] = 2;
2429         a[10] = 3;
2430         a[11] = 4;
2431         a[12] = 5;
2432         a[13] = 6;
2433         a[14] = 7;
2434         a[15] = 8;
2435         a[16] = 9;
2436         a[17] = 10;
2437         a[18] = 14;
2438         a[19] = 17;
2439         a[20] = 21;
2440         a[21] = 25;
2441         a[22] = 30;
2442         a[23] = 35;
2443         a[24] = 45;
2444         a[25] = 60;
2445         a[26] = 80;
2446         a[27] = 100;
2447         a[28] = 200;
2448         a[29] = 300;
2449         a[30] = 400;
2450         a[31] = 500;
2451
2452         b[9] = 1;
2453         b[10] = 1;
2454         b[11] = 2;
2455         b[12] = 2;
2456         b[13] = 3;
2457         b[14] = 3;
2458         b[15] = 3;
2459         b[16] = 3;
2460         b[17] = 4;
2461         b[18] = 4;
2462         b[19] = 4;
2463         b[20] = 4;
2464         b[21] = 4;
2465         b[22] = 5;
2466         b[23] = 5;
2467         b[24] = 5;
2468         b[25] = 5;
2469         b[26] = 5;
2470         b[27] = 5;
2471         b[28] = 6;
2472         b[29] = 6;
2473         b[30] = 7;
2474         b[31] = 7;
2475 }
2476
2477 #define INIT_CMD(var, cmd, rd_wr) do { \
2478         (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2479                         F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2480         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2481 } while (0)
2482
2483 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2484 {
2485         u32 cclk_param, cclk_val;
2486         int ret;
2487
2488         /*
2489          * Ask firmware for the Core Clock since it knows how to translate the
2490          * Reference Clock ('V2') VPD field into a Core Clock value ...
2491          */
2492         cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2493                       V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2494         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2495                               1, &cclk_param, &cclk_val);
2496         if (ret) {
2497                 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2498                         __func__, ret);
2499                 return ret;
2500         }
2501
2502         p->cclk = cclk_val;
2503         dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2504         return 0;
2505 }
2506
2507 /* serial flash and firmware constants and flash config file constants */
2508 enum {
2509         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2510
2511         /* flash command opcodes */
2512         SF_PROG_PAGE    = 2,          /* program page */
2513         SF_WR_DISABLE   = 4,          /* disable writes */
2514         SF_RD_STATUS    = 5,          /* read status register */
2515         SF_WR_ENABLE    = 6,          /* enable writes */
2516         SF_RD_DATA_FAST = 0xb,        /* read flash */
2517         SF_RD_ID        = 0x9f,       /* read ID */
2518         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2519 };
2520
2521 /**
2522  * sf1_read - read data from the serial flash
2523  * @adapter: the adapter
2524  * @byte_cnt: number of bytes to read
2525  * @cont: whether another operation will be chained
2526  * @lock: whether to lock SF for PL access only
2527  * @valp: where to store the read data
2528  *
2529  * Reads up to 4 bytes of data from the serial flash.  The location of
2530  * the read needs to be specified prior to calling this by issuing the
2531  * appropriate commands to the serial flash.
2532  */
2533 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2534                     int lock, u32 *valp)
2535 {
2536         int ret;
2537
2538         if (!byte_cnt || byte_cnt > 4)
2539                 return -EINVAL;
2540         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2541                 return -EBUSY;
2542         t4_write_reg(adapter, A_SF_OP,
2543                      V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2544         ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2545         if (!ret)
2546                 *valp = t4_read_reg(adapter, A_SF_DATA);
2547         return ret;
2548 }
2549
2550 /**
2551  * sf1_write - write data to the serial flash
2552  * @adapter: the adapter
2553  * @byte_cnt: number of bytes to write
2554  * @cont: whether another operation will be chained
2555  * @lock: whether to lock SF for PL access only
2556  * @val: value to write
2557  *
2558  * Writes up to 4 bytes of data to the serial flash.  The location of
2559  * the write needs to be specified prior to calling this by issuing the
2560  * appropriate commands to the serial flash.
2561  */
2562 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2563                      int lock, u32 val)
2564 {
2565         if (!byte_cnt || byte_cnt > 4)
2566                 return -EINVAL;
2567         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2568                 return -EBUSY;
2569         t4_write_reg(adapter, A_SF_DATA, val);
2570         t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2571                      V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2572         return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2573 }
2574
2575 /**
2576  * t4_read_flash - read words from serial flash
2577  * @adapter: the adapter
2578  * @addr: the start address for the read
2579  * @nwords: how many 32-bit words to read
2580  * @data: where to store the read data
2581  * @byte_oriented: whether to store data as bytes or as words
2582  *
2583  * Read the specified number of 32-bit words from the serial flash.
2584  * If @byte_oriented is set the read data is stored as a byte array
2585  * (i.e., big-endian), otherwise as 32-bit words in the platform's
2586  * natural endianness.
2587  */
2588 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2589                   unsigned int nwords, u32 *data, int byte_oriented)
2590 {
2591         int ret;
2592
2593         if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2594             (addr & 3))
2595                 return -EINVAL;
2596
2597         addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2598
2599         ret = sf1_write(adapter, 4, 1, 0, addr);
2600         if (ret != 0)
2601                 return ret;
2602
2603         ret = sf1_read(adapter, 1, 1, 0, data);
2604         if (ret != 0)
2605                 return ret;
2606
2607         for ( ; nwords; nwords--, data++) {
2608                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2609                 if (nwords == 1)
2610                         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
2611                 if (ret)
2612                         return ret;
2613                 if (byte_oriented)
2614                         *data = cpu_to_be32(*data);
2615         }
2616         return 0;
2617 }
2618
2619 /**
2620  * t4_get_exprom_version - return the Expansion ROM version (if any)
2621  * @adapter: the adapter
2622  * @vers: where to place the version
2623  *
2624  * Reads the Expansion ROM header from FLASH and returns the version
2625  * number (if present) through the @vers return value pointer.  We return
2626  * this in the Firmware Version Format since it's convenient.  Return
2627  * 0 on success, -ENOENT if no Expansion ROM is present.
2628  */
2629 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2630 {
2631         struct exprom_header {
2632                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
2633                 unsigned char hdr_ver[4];       /* Expansion ROM version */
2634         } *hdr;
2635         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2636                                            sizeof(u32))];
2637         int ret;
2638
2639         ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2640                             ARRAY_SIZE(exprom_header_buf),
2641                             exprom_header_buf, 0);
2642         if (ret)
2643                 return ret;
2644
2645         hdr = (struct exprom_header *)exprom_header_buf;
2646         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2647                 return -ENOENT;
2648
2649         *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2650                  V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2651                  V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2652                  V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2653         return 0;
2654 }
2655
2656 /**
2657  * t4_get_fw_version - read the firmware version
2658  * @adapter: the adapter
2659  * @vers: where to place the version
2660  *
2661  * Reads the FW version from flash.
2662  */
2663 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2664 {
2665         return t4_read_flash(adapter, FLASH_FW_START +
2666                              offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2667 }
2668
2669 /**
2670  *     t4_get_bs_version - read the firmware bootstrap version
2671  *     @adapter: the adapter
2672  *     @vers: where to place the version
2673  *
2674  *     Reads the FW Bootstrap version from flash.
2675  */
2676 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2677 {
2678         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2679                              offsetof(struct fw_hdr, fw_ver), 1,
2680                              vers, 0);
2681 }
2682
2683 /**
2684  * t4_get_tp_version - read the TP microcode version
2685  * @adapter: the adapter
2686  * @vers: where to place the version
2687  *
2688  * Reads the TP microcode version from flash.
2689  */
2690 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2691 {
2692         return t4_read_flash(adapter, FLASH_FW_START +
2693                              offsetof(struct fw_hdr, tp_microcode_ver),
2694                              1, vers, 0);
2695 }
2696
2697 /**
2698  * t4_get_version_info - extract various chip/firmware version information
2699  * @adapter: the adapter
2700  *
2701  * Reads various chip/firmware version numbers and stores them into the
2702  * adapter Adapter Parameters structure.  If any of the efforts fails
2703  * the first failure will be returned, but all of the version numbers
2704  * will be read.
2705  */
2706 int t4_get_version_info(struct adapter *adapter)
2707 {
2708         int ret = 0;
2709
2710 #define FIRST_RET(__getvinfo) \
2711         do { \
2712                 int __ret = __getvinfo; \
2713                 if (__ret && !ret) \
2714                         ret = __ret; \
2715         } while (0)
2716
2717         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2718         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2719         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2720         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2721
2722 #undef FIRST_RET
2723
2724         return ret;
2725 }
2726
2727 /**
2728  * t4_dump_version_info - dump all of the adapter configuration IDs
2729  * @adapter: the adapter
2730  *
2731  * Dumps all of the various bits of adapter configuration version/revision
2732  * IDs information.  This is typically called at some point after
2733  * t4_get_version_info() has been called.
2734  */
2735 void t4_dump_version_info(struct adapter *adapter)
2736 {
2737         /**
2738          * Device information.
2739          */
2740         dev_info(adapter, "Chelsio rev %d\n",
2741                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
2742
2743         /**
2744          * Firmware Version.
2745          */
2746         if (!adapter->params.fw_vers)
2747                 dev_warn(adapter, "No firmware loaded\n");
2748         else
2749                 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2750                          G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2751                          G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2752                          G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2753                          G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2754
2755         /**
2756          * Bootstrap Firmware Version.
2757          */
2758         if (!adapter->params.bs_vers)
2759                 dev_warn(adapter, "No bootstrap loaded\n");
2760         else
2761                 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2762                          G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2763                          G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2764                          G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2765                          G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2766
2767         /**
2768          * TP Microcode Version.
2769          */
2770         if (!adapter->params.tp_vers)
2771                 dev_warn(adapter, "No TP Microcode loaded\n");
2772         else
2773                 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2774                          G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2775                          G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2776                          G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2777                          G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2778
2779         /**
2780          * Expansion ROM version.
2781          */
2782         if (!adapter->params.er_vers)
2783                 dev_info(adapter, "No Expansion ROM loaded\n");
2784         else
2785                 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2786                          G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2787                          G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2788                          G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2789                          G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2790 }
2791
2792 #define ADVERT_MASK (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) | \
2793                      FW_PORT_CAP32_ANEG)
2794 /**
2795  *     fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
2796  *     @caps32: a 32-bit Port Capabilities value
2797  *
2798  *     Returns the equivalent 16-bit Port Capabilities value.  Note that
2799  *     not all 32-bit Port Capabilities can be represented in the 16-bit
2800  *     Port Capabilities and some fields/values may not make it.
2801  */
2802 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
2803 {
2804         fw_port_cap16_t caps16 = 0;
2805
2806 #define CAP32_TO_CAP16(__cap) \
2807         do { \
2808                 if (caps32 & FW_PORT_CAP32_##__cap) \
2809                         caps16 |= FW_PORT_CAP_##__cap; \
2810         } while (0)
2811
2812         CAP32_TO_CAP16(SPEED_100M);
2813         CAP32_TO_CAP16(SPEED_1G);
2814         CAP32_TO_CAP16(SPEED_10G);
2815         CAP32_TO_CAP16(SPEED_25G);
2816         CAP32_TO_CAP16(SPEED_40G);
2817         CAP32_TO_CAP16(SPEED_100G);
2818         CAP32_TO_CAP16(FC_RX);
2819         CAP32_TO_CAP16(FC_TX);
2820         CAP32_TO_CAP16(802_3_PAUSE);
2821         CAP32_TO_CAP16(802_3_ASM_DIR);
2822         CAP32_TO_CAP16(ANEG);
2823         CAP32_TO_CAP16(MDIX);
2824         CAP32_TO_CAP16(MDIAUTO);
2825         CAP32_TO_CAP16(FEC_RS);
2826         CAP32_TO_CAP16(FEC_BASER_RS);
2827
2828 #undef CAP32_TO_CAP16
2829
2830         return caps16;
2831 }
2832
2833 /* Translate Firmware Pause specification to Common Code */
2834 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
2835 {
2836         enum cc_pause cc_pause = 0;
2837
2838         if (fw_pause & FW_PORT_CAP32_FC_RX)
2839                 cc_pause |= PAUSE_RX;
2840         if (fw_pause & FW_PORT_CAP32_FC_TX)
2841                 cc_pause |= PAUSE_TX;
2842
2843         return cc_pause;
2844 }
2845
2846 /* Translate Common Code Pause Frame specification into Firmware */
2847 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
2848 {
2849         fw_port_cap32_t fw_pause = 0;
2850
2851         if (cc_pause & PAUSE_RX)
2852                 fw_pause |= FW_PORT_CAP32_FC_RX;
2853         if (cc_pause & PAUSE_TX)
2854                 fw_pause |= FW_PORT_CAP32_FC_TX;
2855
2856         return fw_pause;
2857 }
2858
2859 /* Translate Firmware Forward Error Correction specification to Common Code */
2860 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
2861 {
2862         enum cc_fec cc_fec = 0;
2863
2864         if (fw_fec & FW_PORT_CAP32_FEC_RS)
2865                 cc_fec |= FEC_RS;
2866         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
2867                 cc_fec |= FEC_BASER_RS;
2868
2869         return cc_fec;
2870 }
2871
2872 /* Translate Common Code Forward Error Correction specification to Firmware */
2873 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
2874 {
2875         fw_port_cap32_t fw_fec = 0;
2876
2877         if (cc_fec & FEC_RS)
2878                 fw_fec |= FW_PORT_CAP32_FEC_RS;
2879         if (cc_fec & FEC_BASER_RS)
2880                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
2881
2882         return fw_fec;
2883 }
2884
2885 /**
2886  * t4_link_l1cfg - apply link configuration to MAC/PHY
2887  * @adapter: the adapter
2888  * @mbox: the Firmware Mailbox to use
2889  * @port: the Port ID
2890  * @lc: the Port's Link Configuration
2891  *
2892  * Set up a port's MAC and PHY according to a desired link configuration.
2893  * - If the PHY can auto-negotiate first decide what to advertise, then
2894  *   enable/disable auto-negotiation as desired, and reset.
2895  * - If the PHY does not auto-negotiate just reset it.
2896  * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2897  *   otherwise do it later based on the outcome of auto-negotiation.
2898  */
2899 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2900                   struct link_config *lc)
2901 {
2902         unsigned int fw_mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
2903         fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
2904         struct fw_port_cmd cmd;
2905
2906         lc->link_ok = 0;
2907
2908         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
2909
2910         /* Convert Common Code Forward Error Control settings into the
2911          * Firmware's API.  If the current Requested FEC has "Automatic"
2912          * (IEEE 802.3) specified, then we use whatever the Firmware
2913          * sent us as part of it's IEEE 802.3-based interpratation of
2914          * the Transceiver Module EPROM FEC parameters.  Otherwise we
2915          * use whatever is in the current Requested FEC settings.
2916          */
2917         if (lc->requested_fec & FEC_AUTO)
2918                 cc_fec = lc->auto_fec;
2919         else
2920                 cc_fec = lc->requested_fec;
2921         fw_fec = cc_to_fwcap_fec(cc_fec);
2922
2923         /* Figure out what our Requested Port Capabilities are going to be.
2924          */
2925         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
2926                 rcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
2927                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2928                 lc->fec = cc_fec;
2929         } else if (lc->autoneg == AUTONEG_DISABLE) {
2930                 rcap = lc->requested_speed | fw_fc | fw_fec | fw_mdi;
2931                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2932                 lc->fec = cc_fec;
2933         } else {
2934                 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
2935         }
2936
2937         /* And send that on to the Firmware ...
2938          */
2939         memset(&cmd, 0, sizeof(cmd));
2940         cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2941                                        F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2942                                        V_FW_PORT_CMD_PORTID(port));
2943         cmd.action_to_len16 =
2944                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2945                             FW_LEN16(cmd));
2946         cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
2947
2948         return t4_wr_mbox(adap, mbox, &cmd, sizeof(cmd), NULL);
2949 }
2950
2951 /**
2952  * t4_flash_cfg_addr - return the address of the flash configuration file
2953  * @adapter: the adapter
2954  *
2955  * Return the address within the flash where the Firmware Configuration
2956  * File is stored, or an error if the device FLASH is too small to contain
2957  * a Firmware Configuration File.
2958  */
2959 int t4_flash_cfg_addr(struct adapter *adapter)
2960 {
2961         /*
2962          * If the device FLASH isn't large enough to hold a Firmware
2963          * Configuration File, return an error.
2964          */
2965         if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2966                 return -ENOSPC;
2967
2968         return FLASH_CFG_START;
2969 }
2970
2971 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2972
2973 /**
2974  * t4_intr_enable - enable interrupts
2975  * @adapter: the adapter whose interrupts should be enabled
2976  *
2977  * Enable PF-specific interrupts for the calling function and the top-level
2978  * interrupt concentrator for global interrupts.  Interrupts are already
2979  * enabled at each module, here we just enable the roots of the interrupt
2980  * hierarchies.
2981  *
2982  * Note: this function should be called only when the driver manages
2983  * non PF-specific interrupts from the various HW modules.  Only one PCI
2984  * function at a time should be doing this.
2985  */
2986 void t4_intr_enable(struct adapter *adapter)
2987 {
2988         u32 val = 0;
2989         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2990         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2991                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2992
2993         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2994                 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2995         t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2996                      F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2997                      F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2998                      F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2999                      F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
3000                      F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
3001                      F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
3002         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
3003         t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
3004 }
3005
3006 /**
3007  * t4_intr_disable - disable interrupts
3008  * @adapter: the adapter whose interrupts should be disabled
3009  *
3010  * Disable interrupts.  We only disable the top-level interrupt
3011  * concentrators.  The caller must be a PCI function managing global
3012  * interrupts.
3013  */
3014 void t4_intr_disable(struct adapter *adapter)
3015 {
3016         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3017         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
3018                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
3019
3020         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
3021         t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
3022 }
3023
3024 /**
3025  * t4_get_port_type_description - return Port Type string description
3026  * @port_type: firmware Port Type enumeration
3027  */
3028 const char *t4_get_port_type_description(enum fw_port_type port_type)
3029 {
3030         static const char * const port_type_description[] = {
3031                 "Fiber_XFI",
3032                 "Fiber_XAUI",
3033                 "BT_SGMII",
3034                 "BT_XFI",
3035                 "BT_XAUI",
3036                 "KX4",
3037                 "CX4",
3038                 "KX",
3039                 "KR",
3040                 "SFP",
3041                 "BP_AP",
3042                 "BP4_AP",
3043                 "QSFP_10G",
3044                 "QSA",
3045                 "QSFP",
3046                 "BP40_BA",
3047                 "KR4_100G",
3048                 "CR4_QSFP",
3049                 "CR_QSFP",
3050                 "CR2_QSFP",
3051                 "SFP28",
3052                 "KR_SFP28",
3053         };
3054
3055         if (port_type < ARRAY_SIZE(port_type_description))
3056                 return port_type_description[port_type];
3057         return "UNKNOWN";
3058 }
3059
3060 /**
3061  * t4_get_mps_bg_map - return the buffer groups associated with a port
3062  * @adap: the adapter
3063  * @pidx: the port index
3064  *
3065  * Returns a bitmap indicating which MPS buffer groups are associated
3066  * with the given port.  Bit i is set if buffer group i is used by the
3067  * port.
3068  */
3069 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
3070 {
3071         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3072         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
3073                                                           A_MPS_CMN_CTL));
3074
3075         if (pidx >= nports) {
3076                 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
3077                          pidx, nports);
3078                 return 0;
3079         }
3080
3081         switch (chip_version) {
3082         case CHELSIO_T4:
3083         case CHELSIO_T5:
3084                 switch (nports) {
3085                 case 1: return 0xf;
3086                 case 2: return 3 << (2 * pidx);
3087                 case 4: return 1 << pidx;
3088                 }
3089                 break;
3090
3091         case CHELSIO_T6:
3092                 switch (nports) {
3093                 case 2: return 1 << (2 * pidx);
3094                 }
3095                 break;
3096         }
3097
3098         dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
3099                 chip_version, nports);
3100         return 0;
3101 }
3102
3103 /**
3104  * t4_get_tp_ch_map - return TP ingress channels associated with a port
3105  * @adapter: the adapter
3106  * @pidx: the port index
3107  *
3108  * Returns a bitmap indicating which TP Ingress Channels are associated with
3109  * a given Port.  Bit i is set if TP Ingress Channel i is used by the Port.
3110  */
3111 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
3112 {
3113         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
3114         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
3115                                                           A_MPS_CMN_CTL));
3116
3117         if (pidx >= nports) {
3118                 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
3119                          pidx, nports);
3120                 return 0;
3121         }
3122
3123         switch (chip_version) {
3124         case CHELSIO_T4:
3125         case CHELSIO_T5:
3126                 /* Note that this happens to be the same values as the MPS
3127                  * Buffer Group Map for these Chips.  But we replicate the code
3128                  * here because they're really separate concepts.
3129                  */
3130                 switch (nports) {
3131                 case 1: return 0xf;
3132                 case 2: return 3 << (2 * pidx);
3133                 case 4: return 1 << pidx;
3134                 }
3135                 break;
3136
3137         case CHELSIO_T6:
3138                 switch (nports) {
3139                 case 2: return 1 << pidx;
3140                 }
3141                 break;
3142         }
3143
3144         dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
3145                 chip_version, nports);
3146         return 0;
3147 }
3148
3149 /**
3150  * t4_get_port_stats - collect port statistics
3151  * @adap: the adapter
3152  * @idx: the port index
3153  * @p: the stats structure to fill
3154  *
3155  * Collect statistics related to the given port from HW.
3156  */
3157 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
3158 {
3159         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3160         u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
3161
3162 #define GET_STAT(name) \
3163         t4_read_reg64(adap, \
3164                       (is_t4(adap->params.chip) ? \
3165                        PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
3166                        T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
3167 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
3168
3169         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
3170         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
3171         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
3172         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
3173         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
3174         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
3175         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
3176         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
3177         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
3178         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
3179         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
3180         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
3181         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
3182         p->tx_drop             = GET_STAT(TX_PORT_DROP);
3183         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
3184         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
3185         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
3186         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
3187         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
3188         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
3189         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
3190         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
3191         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
3192
3193         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3194                 if (stat_ctl & F_COUNTPAUSESTATTX) {
3195                         p->tx_frames -= p->tx_pause;
3196                         p->tx_octets -= p->tx_pause * 64;
3197                 }
3198                 if (stat_ctl & F_COUNTPAUSEMCTX)
3199                         p->tx_mcast_frames -= p->tx_pause;
3200         }
3201
3202         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
3203         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
3204         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
3205         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
3206         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
3207         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
3208         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
3209         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
3210         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
3211         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
3212         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
3213         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
3214         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
3215         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
3216         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
3217         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
3218         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3219         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
3220         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
3221         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
3222         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
3223         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
3224         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
3225         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
3226         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
3227         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
3228         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
3229
3230         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3231                 if (stat_ctl & F_COUNTPAUSESTATRX) {
3232                         p->rx_frames -= p->rx_pause;
3233                         p->rx_octets -= p->rx_pause * 64;
3234                 }
3235                 if (stat_ctl & F_COUNTPAUSEMCRX)
3236                         p->rx_mcast_frames -= p->rx_pause;
3237         }
3238
3239         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3240         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3241         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3242         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3243         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3244         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3245         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3246         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3247
3248 #undef GET_STAT
3249 #undef GET_STAT_COM
3250 }
3251
3252 /**
3253  * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3254  * @adap: The adapter
3255  * @idx: The port
3256  * @stats: Current stats to fill
3257  * @offset: Previous stats snapshot
3258  */
3259 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3260                               struct port_stats *stats,
3261                               struct port_stats *offset)
3262 {
3263         u64 *s, *o;
3264         unsigned int i;
3265
3266         t4_get_port_stats(adap, idx, stats);
3267         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3268              i < (sizeof(struct port_stats) / sizeof(u64));
3269              i++, s++, o++)
3270                 *s -= *o;
3271 }
3272
3273 /**
3274  * t4_clr_port_stats - clear port statistics
3275  * @adap: the adapter
3276  * @idx: the port index
3277  *
3278  * Clear HW statistics for the given port.
3279  */
3280 void t4_clr_port_stats(struct adapter *adap, int idx)
3281 {
3282         unsigned int i;
3283         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3284         u32 port_base_addr;
3285
3286         if (is_t4(adap->params.chip))
3287                 port_base_addr = PORT_BASE(idx);
3288         else
3289                 port_base_addr = T5_PORT_BASE(idx);
3290
3291         for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3292              i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3293                 t4_write_reg(adap, port_base_addr + i, 0);
3294         for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3295              i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3296                 t4_write_reg(adap, port_base_addr + i, 0);
3297         for (i = 0; i < 4; i++)
3298                 if (bgmap & (1 << i)) {
3299                         t4_write_reg(adap,
3300                                      A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3301                                      i * 8, 0);
3302                         t4_write_reg(adap,
3303                                      A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3304                                      i * 8, 0);
3305                 }
3306 }
3307
3308 /**
3309  * t4_fw_hello - establish communication with FW
3310  * @adap: the adapter
3311  * @mbox: mailbox to use for the FW command
3312  * @evt_mbox: mailbox to receive async FW events
3313  * @master: specifies the caller's willingness to be the device master
3314  * @state: returns the current device state (if non-NULL)
3315  *
3316  * Issues a command to establish communication with FW.  Returns either
3317  * an error (negative integer) or the mailbox of the Master PF.
3318  */
3319 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3320                 enum dev_master master, enum dev_state *state)
3321 {
3322         int ret;
3323         struct fw_hello_cmd c;
3324         u32 v;
3325         unsigned int master_mbox;
3326         int retries = FW_CMD_HELLO_RETRIES;
3327
3328 retry:
3329         memset(&c, 0, sizeof(c));
3330         INIT_CMD(c, HELLO, WRITE);
3331         c.err_to_clearinit = cpu_to_be32(
3332                         V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3333                         V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3334                         V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3335                                                 M_FW_HELLO_CMD_MBMASTER) |
3336                         V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3337                         V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3338                         F_FW_HELLO_CMD_CLEARINIT);
3339
3340         /*
3341          * Issue the HELLO command to the firmware.  If it's not successful
3342          * but indicates that we got a "busy" or "timeout" condition, retry
3343          * the HELLO until we exhaust our retry limit.  If we do exceed our
3344          * retry limit, check to see if the firmware left us any error
3345          * information and report that if so ...
3346          */
3347         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3348         if (ret != FW_SUCCESS) {
3349                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3350                         goto retry;
3351                 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3352                         t4_report_fw_error(adap);
3353                 return ret;
3354         }
3355
3356         v = be32_to_cpu(c.err_to_clearinit);
3357         master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3358         if (state) {
3359                 if (v & F_FW_HELLO_CMD_ERR)
3360                         *state = DEV_STATE_ERR;
3361                 else if (v & F_FW_HELLO_CMD_INIT)
3362                         *state = DEV_STATE_INIT;
3363                 else
3364                         *state = DEV_STATE_UNINIT;
3365         }
3366
3367         /*
3368          * If we're not the Master PF then we need to wait around for the
3369          * Master PF Driver to finish setting up the adapter.
3370          *
3371          * Note that we also do this wait if we're a non-Master-capable PF and
3372          * there is no current Master PF; a Master PF may show up momentarily
3373          * and we wouldn't want to fail pointlessly.  (This can happen when an
3374          * OS loads lots of different drivers rapidly at the same time).  In
3375          * this case, the Master PF returned by the firmware will be
3376          * M_PCIE_FW_MASTER so the test below will work ...
3377          */
3378         if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3379             master_mbox != mbox) {
3380                 int waiting = FW_CMD_HELLO_TIMEOUT;
3381
3382                 /*
3383                  * Wait for the firmware to either indicate an error or
3384                  * initialized state.  If we see either of these we bail out
3385                  * and report the issue to the caller.  If we exhaust the
3386                  * "hello timeout" and we haven't exhausted our retries, try
3387                  * again.  Otherwise bail with a timeout error.
3388                  */
3389                 for (;;) {
3390                         u32 pcie_fw;
3391
3392                         msleep(50);
3393                         waiting -= 50;
3394
3395                         /*
3396                          * If neither Error nor Initialialized are indicated
3397                          * by the firmware keep waiting till we exaust our
3398                          * timeout ... and then retry if we haven't exhausted
3399                          * our retries ...
3400                          */
3401                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3402                         if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3403                                 if (waiting <= 0) {
3404                                         if (retries-- > 0)
3405                                                 goto retry;
3406
3407                                         return -ETIMEDOUT;
3408                                 }
3409                                 continue;
3410                         }
3411
3412                         /*
3413                          * We either have an Error or Initialized condition
3414                          * report errors preferentially.
3415                          */
3416                         if (state) {
3417                                 if (pcie_fw & F_PCIE_FW_ERR)
3418                                         *state = DEV_STATE_ERR;
3419                                 else if (pcie_fw & F_PCIE_FW_INIT)
3420                                         *state = DEV_STATE_INIT;
3421                         }
3422
3423                         /*
3424                          * If we arrived before a Master PF was selected and
3425                          * there's not a valid Master PF, grab its identity
3426                          * for our caller.
3427                          */
3428                         if (master_mbox == M_PCIE_FW_MASTER &&
3429                             (pcie_fw & F_PCIE_FW_MASTER_VLD))
3430                                 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3431                         break;
3432                 }
3433         }
3434
3435         return master_mbox;
3436 }
3437
3438 /**
3439  * t4_fw_bye - end communication with FW
3440  * @adap: the adapter
3441  * @mbox: mailbox to use for the FW command
3442  *
3443  * Issues a command to terminate communication with FW.
3444  */
3445 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3446 {
3447         struct fw_bye_cmd c;
3448
3449         memset(&c, 0, sizeof(c));
3450         INIT_CMD(c, BYE, WRITE);
3451         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3452 }
3453
3454 /**
3455  * t4_fw_reset - issue a reset to FW
3456  * @adap: the adapter
3457  * @mbox: mailbox to use for the FW command
3458  * @reset: specifies the type of reset to perform
3459  *
3460  * Issues a reset command of the specified type to FW.
3461  */
3462 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3463 {
3464         struct fw_reset_cmd c;
3465
3466         memset(&c, 0, sizeof(c));
3467         INIT_CMD(c, RESET, WRITE);
3468         c.val = cpu_to_be32(reset);
3469         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3470 }
3471
3472 /**
3473  * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3474  * @adap: the adapter
3475  * @mbox: mailbox to use for the FW RESET command (if desired)
3476  * @force: force uP into RESET even if FW RESET command fails
3477  *
3478  * Issues a RESET command to firmware (if desired) with a HALT indication
3479  * and then puts the microprocessor into RESET state.  The RESET command
3480  * will only be issued if a legitimate mailbox is provided (mbox <=
3481  * M_PCIE_FW_MASTER).
3482  *
3483  * This is generally used in order for the host to safely manipulate the
3484  * adapter without fear of conflicting with whatever the firmware might
3485  * be doing.  The only way out of this state is to RESTART the firmware
3486  * ...
3487  */
3488 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3489 {
3490         int ret = 0;
3491
3492         /*
3493          * If a legitimate mailbox is provided, issue a RESET command
3494          * with a HALT indication.
3495          */
3496         if (mbox <= M_PCIE_FW_MASTER) {
3497                 struct fw_reset_cmd c;
3498
3499                 memset(&c, 0, sizeof(c));
3500                 INIT_CMD(c, RESET, WRITE);
3501                 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3502                 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3503                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3504         }
3505
3506         /*
3507          * Normally we won't complete the operation if the firmware RESET
3508          * command fails but if our caller insists we'll go ahead and put the
3509          * uP into RESET.  This can be useful if the firmware is hung or even
3510          * missing ...  We'll have to take the risk of putting the uP into
3511          * RESET without the cooperation of firmware in that case.
3512          *
3513          * We also force the firmware's HALT flag to be on in case we bypassed
3514          * the firmware RESET command above or we're dealing with old firmware
3515          * which doesn't have the HALT capability.  This will serve as a flag
3516          * for the incoming firmware to know that it's coming out of a HALT
3517          * rather than a RESET ... if it's new enough to understand that ...
3518          */
3519         if (ret == 0 || force) {
3520                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3521                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3522                                  F_PCIE_FW_HALT);
3523         }
3524
3525         /*
3526          * And we always return the result of the firmware RESET command
3527          * even when we force the uP into RESET ...
3528          */
3529         return ret;
3530 }
3531
3532 /**
3533  * t4_fw_restart - restart the firmware by taking the uP out of RESET
3534  * @adap: the adapter
3535  * @mbox: mailbox to use for the FW RESET command (if desired)
3536  * @reset: if we want to do a RESET to restart things
3537  *
3538  * Restart firmware previously halted by t4_fw_halt().  On successful
3539  * return the previous PF Master remains as the new PF Master and there
3540  * is no need to issue a new HELLO command, etc.
3541  *
3542  * We do this in two ways:
3543  *
3544  * 1. If we're dealing with newer firmware we'll simply want to take
3545  *    the chip's microprocessor out of RESET.  This will cause the
3546  *    firmware to start up from its start vector.  And then we'll loop
3547  *    until the firmware indicates it's started again (PCIE_FW.HALT
3548  *    reset to 0) or we timeout.
3549  *
3550  * 2. If we're dealing with older firmware then we'll need to RESET
3551  *    the chip since older firmware won't recognize the PCIE_FW.HALT
3552  *    flag and automatically RESET itself on startup.
3553  */
3554 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3555 {
3556         if (reset) {
3557                 /*
3558                  * Since we're directing the RESET instead of the firmware
3559                  * doing it automatically, we need to clear the PCIE_FW.HALT
3560                  * bit.
3561                  */
3562                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3563
3564                 /*
3565                  * If we've been given a valid mailbox, first try to get the
3566                  * firmware to do the RESET.  If that works, great and we can
3567                  * return success.  Otherwise, if we haven't been given a
3568                  * valid mailbox or the RESET command failed, fall back to
3569                  * hitting the chip with a hammer.
3570                  */
3571                 if (mbox <= M_PCIE_FW_MASTER) {
3572                         t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3573                         msleep(100);
3574                         if (t4_fw_reset(adap, mbox,
3575                                         F_PIORST | F_PIORSTMODE) == 0)
3576                                 return 0;
3577                 }
3578
3579                 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3580                 msleep(2000);
3581         } else {
3582                 int ms;
3583
3584                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3585                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3586                         if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3587                                 return FW_SUCCESS;
3588                         msleep(100);
3589                         ms += 100;
3590                 }
3591                 return -ETIMEDOUT;
3592         }
3593         return 0;
3594 }
3595
3596 /**
3597  * t4_fl_pkt_align - return the fl packet alignment
3598  * @adap: the adapter
3599  *
3600  * T4 has a single field to specify the packing and padding boundary.
3601  * T5 onwards has separate fields for this and hence the alignment for
3602  * next packet offset is maximum of these two.
3603  */
3604 int t4_fl_pkt_align(struct adapter *adap)
3605 {
3606         u32 sge_control, sge_control2;
3607         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3608
3609         sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3610
3611         /* T4 uses a single control field to specify both the PCIe Padding and
3612          * Packing Boundary.  T5 introduced the ability to specify these
3613          * separately.  The actual Ingress Packet Data alignment boundary
3614          * within Packed Buffer Mode is the maximum of these two
3615          * specifications.
3616          */
3617         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3618                 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3619         else
3620                 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3621
3622         ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3623
3624         fl_align = ingpadboundary;
3625         if (!is_t4(adap->params.chip)) {
3626                 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3627                 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3628                 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3629                         ingpackboundary = 16;
3630                 else
3631                         ingpackboundary = 1 << (ingpackboundary +
3632                                         X_INGPACKBOUNDARY_SHIFT);
3633
3634                 fl_align = max(ingpadboundary, ingpackboundary);
3635         }
3636         return fl_align;
3637 }
3638
3639 /**
3640  * t4_fixup_host_params_compat - fix up host-dependent parameters
3641  * @adap: the adapter
3642  * @page_size: the host's Base Page Size
3643  * @cache_line_size: the host's Cache Line Size
3644  * @chip_compat: maintain compatibility with designated chip
3645  *
3646  * Various registers in the chip contain values which are dependent on the
3647  * host's Base Page and Cache Line Sizes.  This function will fix all of
3648  * those registers with the appropriate values as passed in ...
3649  *
3650  * @chip_compat is used to limit the set of changes that are made
3651  * to be compatible with the indicated chip release.  This is used by
3652  * drivers to maintain compatibility with chip register settings when
3653  * the drivers haven't [yet] been updated with new chip support.
3654  */
3655 int t4_fixup_host_params_compat(struct adapter *adap,
3656                                 unsigned int page_size,
3657                                 unsigned int cache_line_size,
3658                                 enum chip_type chip_compat)
3659 {
3660         unsigned int page_shift = cxgbe_fls(page_size) - 1;
3661         unsigned int sge_hps = page_shift - 10;
3662         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3663         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3664         unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3665
3666         t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3667                      V_HOSTPAGESIZEPF0(sge_hps) |
3668                      V_HOSTPAGESIZEPF1(sge_hps) |
3669                      V_HOSTPAGESIZEPF2(sge_hps) |
3670                      V_HOSTPAGESIZEPF3(sge_hps) |
3671                      V_HOSTPAGESIZEPF4(sge_hps) |
3672                      V_HOSTPAGESIZEPF5(sge_hps) |
3673                      V_HOSTPAGESIZEPF6(sge_hps) |
3674                      V_HOSTPAGESIZEPF7(sge_hps));
3675
3676         if (is_t4(adap->params.chip) || is_t4(chip_compat))
3677                 t4_set_reg_field(adap, A_SGE_CONTROL,
3678                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3679                                  F_EGRSTATUSPAGESIZE,
3680                                  V_INGPADBOUNDARY(fl_align_log -
3681                                                   X_INGPADBOUNDARY_SHIFT) |
3682                                 V_EGRSTATUSPAGESIZE(stat_len != 64));
3683         else {
3684                 unsigned int pack_align;
3685                 unsigned int ingpad, ingpack;
3686                 unsigned int pcie_cap;
3687
3688                 /*
3689                  * T5 introduced the separation of the Free List Padding and
3690                  * Packing Boundaries.  Thus, we can select a smaller Padding
3691                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
3692                  * Bandwidth, and use a Packing Boundary which is large enough
3693                  * to avoid false sharing between CPUs, etc.
3694                  *
3695                  * For the PCI Link, the smaller the Padding Boundary the
3696                  * better.  For the Memory Controller, a smaller Padding
3697                  * Boundary is better until we cross under the Memory Line
3698                  * Size (the minimum unit of transfer to/from Memory).  If we
3699                  * have a Padding Boundary which is smaller than the Memory
3700                  * Line Size, that'll involve a Read-Modify-Write cycle on the
3701                  * Memory Controller which is never good.
3702                  */
3703
3704                 /* We want the Packing Boundary to be based on the Cache Line
3705                  * Size in order to help avoid False Sharing performance
3706                  * issues between CPUs, etc.  We also want the Packing
3707                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
3708                  * get best performance when the Packing Boundary is a
3709                  * multiple of the Maximum Payload Size.
3710                  */
3711                 pack_align = fl_align;
3712                 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3713                 if (pcie_cap) {
3714                         unsigned int mps, mps_log;
3715                         u16 devctl;
3716
3717                         /* The PCIe Device Control Maximum Payload Size field
3718                          * [bits 7:5] encodes sizes as powers of 2 starting at
3719                          * 128 bytes.
3720                          */
3721                         t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3722                                             &devctl);
3723                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3724                         mps = 1 << mps_log;
3725                         if (mps > pack_align)
3726                                 pack_align = mps;
3727                 }
3728
3729                 /*
3730                  * N.B. T5 has a different interpretation of the "0" value for
3731                  * the Packing Boundary.  This corresponds to 16 bytes instead
3732                  * of the expected 32 bytes.  We never have a Packing Boundary
3733                  * less than 32 bytes so we can't use that special value but
3734                  * on the other hand, if we wanted 32 bytes, the best we can
3735                  * really do is 64 bytes ...
3736                  */
3737                 if (pack_align <= 16) {
3738                         ingpack = X_INGPACKBOUNDARY_16B;
3739                         fl_align = 16;
3740                 } else if (pack_align == 32) {
3741                         ingpack = X_INGPACKBOUNDARY_64B;
3742                         fl_align = 64;
3743                 } else {
3744                         unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3745
3746                         ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3747                         fl_align = pack_align;
3748                 }
3749
3750                 /* Use the smallest Ingress Padding which isn't smaller than
3751                  * the Memory Controller Read/Write Size.  We'll take that as
3752                  * being 8 bytes since we don't know of any system with a
3753                  * wider Memory Controller Bus Width.
3754                  */
3755                 if (is_t5(adap->params.chip))
3756                         ingpad = X_INGPADBOUNDARY_32B;
3757                 else
3758                         ingpad = X_T6_INGPADBOUNDARY_8B;
3759                 t4_set_reg_field(adap, A_SGE_CONTROL,
3760                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3761                                  F_EGRSTATUSPAGESIZE,
3762                                  V_INGPADBOUNDARY(ingpad) |
3763                                  V_EGRSTATUSPAGESIZE(stat_len != 64));
3764                 t4_set_reg_field(adap, A_SGE_CONTROL2,
3765                                  V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3766                                  V_INGPACKBOUNDARY(ingpack));
3767         }
3768
3769         /*
3770          * Adjust various SGE Free List Host Buffer Sizes.
3771          *
3772          * The first four entries are:
3773          *
3774          *   0: Host Page Size
3775          *   1: 64KB
3776          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3777          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3778          *
3779          * For the single-MTU buffers in unpacked mode we need to include
3780          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3781          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3782          * Padding boundary.  All of these are accommodated in the Factory
3783          * Default Firmware Configuration File but we need to adjust it for
3784          * this host's cache line size.
3785          */
3786         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3787         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3788                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3789                      & ~(fl_align - 1));
3790         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3791                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3792                      & ~(fl_align - 1));
3793
3794         t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3795
3796         return 0;
3797 }
3798
3799 /**
3800  * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3801  * @adap: the adapter
3802  * @page_size: the host's Base Page Size
3803  * @cache_line_size: the host's Cache Line Size
3804  *
3805  * Various registers in T4 contain values which are dependent on the
3806  * host's Base Page and Cache Line Sizes.  This function will fix all of
3807  * those registers with the appropriate values as passed in ...
3808  *
3809  * This routine makes changes which are compatible with T4 chips.
3810  */
3811 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3812                          unsigned int cache_line_size)
3813 {
3814         return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3815                                            T4_LAST_REV);
3816 }
3817
3818 /**
3819  * t4_fw_initialize - ask FW to initialize the device
3820  * @adap: the adapter
3821  * @mbox: mailbox to use for the FW command
3822  *
3823  * Issues a command to FW to partially initialize the device.  This
3824  * performs initialization that generally doesn't depend on user input.
3825  */
3826 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3827 {
3828         struct fw_initialize_cmd c;
3829
3830         memset(&c, 0, sizeof(c));
3831         INIT_CMD(c, INITIALIZE, WRITE);
3832         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3833 }
3834
3835 /**
3836  * t4_query_params_rw - query FW or device parameters
3837  * @adap: the adapter
3838  * @mbox: mailbox to use for the FW command
3839  * @pf: the PF
3840  * @vf: the VF
3841  * @nparams: the number of parameters
3842  * @params: the parameter names
3843  * @val: the parameter values
3844  * @rw: Write and read flag
3845  *
3846  * Reads the value of FW or device parameters.  Up to 7 parameters can be
3847  * queried at once.
3848  */
3849 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3850                               unsigned int pf, unsigned int vf,
3851                               unsigned int nparams, const u32 *params,
3852                               u32 *val, int rw)
3853 {
3854         unsigned int i;
3855         int ret;
3856         struct fw_params_cmd c;
3857         __be32 *p = &c.param[0].mnem;
3858
3859         if (nparams > 7)
3860                 return -EINVAL;
3861
3862         memset(&c, 0, sizeof(c));
3863         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3864                                   F_FW_CMD_REQUEST | F_FW_CMD_READ |
3865                                   V_FW_PARAMS_CMD_PFN(pf) |
3866                                   V_FW_PARAMS_CMD_VFN(vf));
3867         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3868
3869         for (i = 0; i < nparams; i++) {
3870                 *p++ = cpu_to_be32(*params++);
3871                 if (rw)
3872                         *p = cpu_to_be32(*(val + i));
3873                 p++;
3874         }
3875
3876         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3877         if (ret == 0)
3878                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3879                         *val++ = be32_to_cpu(*p);
3880         return ret;
3881 }
3882
3883 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3884                     unsigned int vf, unsigned int nparams, const u32 *params,
3885                     u32 *val)
3886 {
3887         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3888 }
3889
3890 /**
3891  * t4_set_params_timeout - sets FW or device parameters
3892  * @adap: the adapter
3893  * @mbox: mailbox to use for the FW command
3894  * @pf: the PF
3895  * @vf: the VF
3896  * @nparams: the number of parameters
3897  * @params: the parameter names
3898  * @val: the parameter values
3899  * @timeout: the timeout time
3900  *
3901  * Sets the value of FW or device parameters.  Up to 7 parameters can be
3902  * specified at once.
3903  */
3904 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3905                           unsigned int pf, unsigned int vf,
3906                           unsigned int nparams, const u32 *params,
3907                           const u32 *val, int timeout)
3908 {
3909         struct fw_params_cmd c;
3910         __be32 *p = &c.param[0].mnem;
3911
3912         if (nparams > 7)
3913                 return -EINVAL;
3914
3915         memset(&c, 0, sizeof(c));
3916         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3917                                   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3918                                   V_FW_PARAMS_CMD_PFN(pf) |
3919                                   V_FW_PARAMS_CMD_VFN(vf));
3920         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3921
3922         while (nparams--) {
3923                 *p++ = cpu_to_be32(*params++);
3924                 *p++ = cpu_to_be32(*val++);
3925         }
3926
3927         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3928 }
3929
3930 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3931                   unsigned int vf, unsigned int nparams, const u32 *params,
3932                   const u32 *val)
3933 {
3934         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3935                                      FW_CMD_MAX_TIMEOUT);
3936 }
3937
3938 /**
3939  * t4_alloc_vi_func - allocate a virtual interface
3940  * @adap: the adapter
3941  * @mbox: mailbox to use for the FW command
3942  * @port: physical port associated with the VI
3943  * @pf: the PF owning the VI
3944  * @vf: the VF owning the VI
3945  * @nmac: number of MAC addresses needed (1 to 5)
3946  * @mac: the MAC addresses of the VI
3947  * @rss_size: size of RSS table slice associated with this VI
3948  * @portfunc: which Port Application Function MAC Address is desired
3949  * @idstype: Intrusion Detection Type
3950  *
3951  * Allocates a virtual interface for the given physical port.  If @mac is
3952  * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3953  * @mac should be large enough to hold @nmac Ethernet addresses, they are
3954  * stored consecutively so the space needed is @nmac * 6 bytes.
3955  * Returns a negative error number or the non-negative VI id.
3956  */
3957 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3958                      unsigned int port, unsigned int pf, unsigned int vf,
3959                      unsigned int nmac, u8 *mac, unsigned int *rss_size,
3960                      unsigned int portfunc, unsigned int idstype)
3961 {
3962         int ret;
3963         struct fw_vi_cmd c;
3964
3965         memset(&c, 0, sizeof(c));
3966         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3967                                   F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3968                                   V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3969         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3970         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3971                                      V_FW_VI_CMD_FUNC(portfunc));
3972         c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3973         c.nmac = nmac - 1;
3974
3975         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3976         if (ret)
3977                 return ret;
3978
3979         if (mac) {
3980                 memcpy(mac, c.mac, sizeof(c.mac));
3981                 switch (nmac) {
3982                 case 5:
3983                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3984                         /* FALLTHROUGH */
3985                 case 4:
3986                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3987                         /* FALLTHROUGH */
3988                 case 3:
3989                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3990                         /* FALLTHROUGH */
3991                 case 2:
3992                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
3993                         /* FALLTHROUGH */
3994                 }
3995         }
3996         if (rss_size)
3997                 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3998         return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3999 }
4000
4001 /**
4002  * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
4003  * @adap: the adapter
4004  * @mbox: mailbox to use for the FW command
4005  * @port: physical port associated with the VI
4006  * @pf: the PF owning the VI
4007  * @vf: the VF owning the VI
4008  * @nmac: number of MAC addresses needed (1 to 5)
4009  * @mac: the MAC addresses of the VI
4010  * @rss_size: size of RSS table slice associated with this VI
4011  *
4012  * Backwards compatible and convieniance routine to allocate a Virtual
4013  * Interface with a Ethernet Port Application Function and Intrustion
4014  * Detection System disabled.
4015  */
4016 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
4017                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
4018                 unsigned int *rss_size)
4019 {
4020         return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
4021                                 FW_VI_FUNC_ETH, 0);
4022 }
4023
4024 /**
4025  * t4_free_vi - free a virtual interface
4026  * @adap: the adapter
4027  * @mbox: mailbox to use for the FW command
4028  * @pf: the PF owning the VI
4029  * @vf: the VF owning the VI
4030  * @viid: virtual interface identifiler
4031  *
4032  * Free a previously allocated virtual interface.
4033  */
4034 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
4035                unsigned int vf, unsigned int viid)
4036 {
4037         struct fw_vi_cmd c;
4038
4039         memset(&c, 0, sizeof(c));
4040         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
4041                                   F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
4042                                   V_FW_VI_CMD_VFN(vf));
4043         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
4044         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
4045
4046         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4047 }
4048
4049 /**
4050  * t4_set_rxmode - set Rx properties of a virtual interface
4051  * @adap: the adapter
4052  * @mbox: mailbox to use for the FW command
4053  * @viid: the VI id
4054  * @mtu: the new MTU or -1
4055  * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
4056  * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
4057  * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
4058  * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
4059  *          -1 no change
4060  * @sleep_ok: if true we may sleep while awaiting command completion
4061  *
4062  * Sets Rx properties of a virtual interface.
4063  */
4064 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
4065                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
4066                   bool sleep_ok)
4067 {
4068         struct fw_vi_rxmode_cmd c;
4069
4070         /* convert to FW values */
4071         if (mtu < 0)
4072                 mtu = M_FW_VI_RXMODE_CMD_MTU;
4073         if (promisc < 0)
4074                 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
4075         if (all_multi < 0)
4076                 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
4077         if (bcast < 0)
4078                 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
4079         if (vlanex < 0)
4080                 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
4081
4082         memset(&c, 0, sizeof(c));
4083         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
4084                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4085                                    V_FW_VI_RXMODE_CMD_VIID(viid));
4086         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4087         c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
4088                             V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
4089                             V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
4090                             V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
4091                             V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
4092         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
4093 }
4094
4095 /**
4096  * t4_change_mac - modifies the exact-match filter for a MAC address
4097  * @adap: the adapter
4098  * @mbox: mailbox to use for the FW command
4099  * @viid: the VI id
4100  * @idx: index of existing filter for old value of MAC address, or -1
4101  * @addr: the new MAC address value
4102  * @persist: whether a new MAC allocation should be persistent
4103  * @add_smt: if true also add the address to the HW SMT
4104  *
4105  * Modifies an exact-match filter and sets it to the new MAC address if
4106  * @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
4107  * latter case the address is added persistently if @persist is %true.
4108  *
4109  * Note that in general it is not possible to modify the value of a given
4110  * filter so the generic way to modify an address filter is to free the one
4111  * being used by the old address value and allocate a new filter for the
4112  * new address value.
4113  *
4114  * Returns a negative error number or the index of the filter with the new
4115  * MAC value.  Note that this index may differ from @idx.
4116  */
4117 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
4118                   int idx, const u8 *addr, bool persist, bool add_smt)
4119 {
4120         int ret, mode;
4121         struct fw_vi_mac_cmd c;
4122         struct fw_vi_mac_exact *p = c.u.exact;
4123         int max_mac_addr = adap->params.arch.mps_tcam_size;
4124
4125         if (idx < 0)                             /* new allocation */
4126                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
4127         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
4128
4129         memset(&c, 0, sizeof(c));
4130         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
4131                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4132                                    V_FW_VI_MAC_CMD_VIID(viid));
4133         c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
4134         p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
4135                                       V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
4136                                       V_FW_VI_MAC_CMD_IDX(idx));
4137         memcpy(p->macaddr, addr, sizeof(p->macaddr));
4138
4139         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4140         if (ret == 0) {
4141                 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
4142                 if (ret >= max_mac_addr)
4143                         ret = -ENOMEM;
4144         }
4145         return ret;
4146 }
4147
4148 /**
4149  * t4_enable_vi_params - enable/disable a virtual interface
4150  * @adap: the adapter
4151  * @mbox: mailbox to use for the FW command
4152  * @viid: the VI id
4153  * @rx_en: 1=enable Rx, 0=disable Rx
4154  * @tx_en: 1=enable Tx, 0=disable Tx
4155  * @dcb_en: 1=enable delivery of Data Center Bridging messages.
4156  *
4157  * Enables/disables a virtual interface.  Note that setting DCB Enable
4158  * only makes sense when enabling a Virtual Interface ...
4159  */
4160 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
4161                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
4162 {
4163         struct fw_vi_enable_cmd c;
4164
4165         memset(&c, 0, sizeof(c));
4166         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
4167                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4168                                    V_FW_VI_ENABLE_CMD_VIID(viid));
4169         c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
4170                                      V_FW_VI_ENABLE_CMD_EEN(tx_en) |
4171                                      V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
4172                                      FW_LEN16(c));
4173         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
4174 }
4175
4176 /**
4177  * t4_enable_vi - enable/disable a virtual interface
4178  * @adap: the adapter
4179  * @mbox: mailbox to use for the FW command
4180  * @viid: the VI id
4181  * @rx_en: 1=enable Rx, 0=disable Rx
4182  * @tx_en: 1=enable Tx, 0=disable Tx
4183  *
4184  * Enables/disables a virtual interface.  Note that setting DCB Enable
4185  * only makes sense when enabling a Virtual Interface ...
4186  */
4187 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
4188                  bool rx_en, bool tx_en)
4189 {
4190         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
4191 }
4192
4193 /**
4194  * t4_iq_start_stop - enable/disable an ingress queue and its FLs
4195  * @adap: the adapter
4196  * @mbox: mailbox to use for the FW command
4197  * @start: %true to enable the queues, %false to disable them
4198  * @pf: the PF owning the queues
4199  * @vf: the VF owning the queues
4200  * @iqid: ingress queue id
4201  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4202  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4203  *
4204  * Starts or stops an ingress queue and its associated FLs, if any.
4205  */
4206 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
4207                      unsigned int pf, unsigned int vf, unsigned int iqid,
4208                      unsigned int fl0id, unsigned int fl1id)
4209 {
4210         struct fw_iq_cmd c;
4211
4212         memset(&c, 0, sizeof(c));
4213         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4214                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4215                                   V_FW_IQ_CMD_VFN(vf));
4216         c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4217                                        V_FW_IQ_CMD_IQSTOP(!start) |
4218                                        FW_LEN16(c));
4219         c.iqid = cpu_to_be16(iqid);
4220         c.fl0id = cpu_to_be16(fl0id);
4221         c.fl1id = cpu_to_be16(fl1id);
4222         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4223 }
4224
4225 /**
4226  * t4_iq_free - free an ingress queue and its FLs
4227  * @adap: the adapter
4228  * @mbox: mailbox to use for the FW command
4229  * @pf: the PF owning the queues
4230  * @vf: the VF owning the queues
4231  * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4232  * @iqid: ingress queue id
4233  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4234  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4235  *
4236  * Frees an ingress queue and its associated FLs, if any.
4237  */
4238 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4239                unsigned int vf, unsigned int iqtype, unsigned int iqid,
4240                unsigned int fl0id, unsigned int fl1id)
4241 {
4242         struct fw_iq_cmd c;
4243
4244         memset(&c, 0, sizeof(c));
4245         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4246                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4247                                   V_FW_IQ_CMD_VFN(vf));
4248         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4249         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4250         c.iqid = cpu_to_be16(iqid);
4251         c.fl0id = cpu_to_be16(fl0id);
4252         c.fl1id = cpu_to_be16(fl1id);
4253         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4254 }
4255
4256 /**
4257  * t4_eth_eq_free - free an Ethernet egress queue
4258  * @adap: the adapter
4259  * @mbox: mailbox to use for the FW command
4260  * @pf: the PF owning the queue
4261  * @vf: the VF owning the queue
4262  * @eqid: egress queue id
4263  *
4264  * Frees an Ethernet egress queue.
4265  */
4266 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4267                    unsigned int vf, unsigned int eqid)
4268 {
4269         struct fw_eq_eth_cmd c;
4270
4271         memset(&c, 0, sizeof(c));
4272         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4273                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4274                                   V_FW_EQ_ETH_CMD_PFN(pf) |
4275                                   V_FW_EQ_ETH_CMD_VFN(vf));
4276         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4277         c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4278         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4279 }
4280
4281 /* Return the highest speed set in the port capabilities, in Mb/s. */
4282 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
4283 {
4284 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
4285         do { \
4286                 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
4287                         return __speed; \
4288         } while (0)
4289
4290         TEST_SPEED_RETURN(100G, 100000);
4291         TEST_SPEED_RETURN(50G,   50000);
4292         TEST_SPEED_RETURN(40G,   40000);
4293         TEST_SPEED_RETURN(25G,   25000);
4294         TEST_SPEED_RETURN(10G,   10000);
4295         TEST_SPEED_RETURN(1G,     1000);
4296         TEST_SPEED_RETURN(100M,    100);
4297
4298 #undef TEST_SPEED_RETURN
4299
4300         return 0;
4301 }
4302
4303 /**
4304  * t4_handle_fw_rpl - process a FW reply message
4305  * @adap: the adapter
4306  * @rpl: start of the FW message
4307  *
4308  * Processes a FW message, such as link state change messages.
4309  */
4310 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4311 {
4312         u8 opcode = *(const u8 *)rpl;
4313
4314         /*
4315          * This might be a port command ... this simplifies the following
4316          * conditionals ...  We can get away with pre-dereferencing
4317          * action_to_len16 because it's in the first 16 bytes and all messages
4318          * will be at least that long.
4319          */
4320         const struct fw_port_cmd *p = (const void *)rpl;
4321         unsigned int action =
4322                 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4323
4324         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
4325                 /* link/module state change message */
4326                 unsigned int speed = 0, fc = 0, i;
4327                 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4328                 struct port_info *pi = NULL;
4329                 struct link_config *lc;
4330                 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
4331                 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
4332                 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
4333                 unsigned int fec;
4334
4335                 fc = fwcap_to_cc_pause(stat);
4336                 fec = fwcap_to_cc_fec(stat);
4337
4338                 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4339                         speed = ETH_SPEED_NUM_100M;
4340                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4341                         speed = ETH_SPEED_NUM_1G;
4342                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4343                         speed = ETH_SPEED_NUM_10G;
4344                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4345                         speed = ETH_SPEED_NUM_25G;
4346                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4347                         speed = ETH_SPEED_NUM_40G;
4348                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4349                         speed = ETH_SPEED_NUM_100G;
4350
4351                 for_each_port(adap, i) {
4352                         pi = adap2pinfo(adap, i);
4353                         if (pi->tx_chan == chan)
4354                                 break;
4355                 }
4356                 lc = &pi->link_cfg;
4357
4358                 if (mod != pi->mod_type) {
4359                         lc->auto_fec = fec;
4360                         pi->mod_type = mod;
4361                         t4_os_portmod_changed(adap, i);
4362                 }
4363                 if (link_ok != lc->link_ok || speed != lc->speed ||
4364                     fc != lc->fc || fec != lc->fec) { /* something changed */
4365                         if (!link_ok && lc->link_ok) {
4366                                 static const char * const reason[] = {
4367                                         "Link Down",
4368                                         "Remote Fault",
4369                                         "Auto-negotiation Failure",
4370                                         "Reserved",
4371                                         "Insufficient Airflow",
4372                                         "Unable To Determine Reason",
4373                                         "No RX Signal Detected",
4374                                         "Reserved",
4375                                 };
4376                                 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
4377
4378                                 dev_warn(adap, "Port %d link down, reason: %s\n",
4379                                          chan, reason[rc]);
4380                         }
4381                         lc->link_ok = link_ok;
4382                         lc->speed = speed;
4383                         lc->fc = fc;
4384                         lc->fec = fec;
4385                         lc->pcaps = be16_to_cpu(p->u.info.pcap);
4386                         lc->acaps = be16_to_cpu(p->u.info.acap) & ADVERT_MASK;
4387                         if (lc->acaps & FW_PORT_CAP32_ANEG) {
4388                                 lc->autoneg = AUTONEG_ENABLE;
4389                         } else {
4390                                 /* When Autoneg is disabled, user needs to set
4391                                  * single speed.
4392                                  */
4393                                 lc->acaps = 0;
4394                                 lc->requested_speed =
4395                                         be16_to_cpu(p->u.info.acap);
4396                                 lc->requested_speed =
4397                                         fwcap_to_speed(lc->requested_speed);
4398                                 lc->autoneg = AUTONEG_DISABLE;
4399                         }
4400                 }
4401         } else {
4402                 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4403                 return -EINVAL;
4404         }
4405         return 0;
4406 }
4407
4408 void t4_reset_link_config(struct adapter *adap, int idx)
4409 {
4410         struct port_info *pi = adap2pinfo(adap, idx);
4411         struct link_config *lc = &pi->link_cfg;
4412
4413         lc->link_ok = 0;
4414         lc->requested_speed = 0;
4415         lc->requested_fc = 0;
4416         lc->speed = 0;
4417         lc->fc = 0;
4418 }
4419
4420 /**
4421  * init_link_config - initialize a link's SW state
4422  * @lc: structure holding the link state
4423  * @pcaps: link Port Capabilities
4424  * @acaps: link current Advertised Port Capabilities
4425  *
4426  * Initializes the SW state maintained for each link, including the link's
4427  * capabilities and default speed/flow-control/autonegotiation settings.
4428  */
4429 static void init_link_config(struct link_config *lc, unsigned int pcaps,
4430                              unsigned int acaps)
4431 {
4432         lc->pcaps = pcaps;
4433         lc->requested_speed = 0;
4434         lc->speed = 0;
4435         lc->requested_fc = 0;
4436         lc->fc = 0;
4437
4438         /**
4439          * For Forward Error Control, we default to whatever the Firmware
4440          * tells us the Link is currently advertising.
4441          */
4442         lc->auto_fec = fwcap_to_cc_fec(acaps);
4443         lc->requested_fec = FEC_AUTO;
4444         lc->fec = lc->auto_fec;
4445
4446         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
4447                 lc->acaps = lc->pcaps & ADVERT_MASK;
4448                 lc->autoneg = AUTONEG_ENABLE;
4449                 lc->requested_fc |= PAUSE_AUTONEG;
4450         } else {
4451                 lc->acaps = 0;
4452                 lc->autoneg = AUTONEG_DISABLE;
4453         }
4454 }
4455
4456 /**
4457  * t4_wait_dev_ready - wait till to reads of registers work
4458  *
4459  * Right after the device is RESET is can take a small amount of time
4460  * for it to respond to register reads.  Until then, all reads will
4461  * return either 0xff...ff or 0xee...ee.  Return an error if reads
4462  * don't work within a reasonable time frame.
4463  */
4464 static int t4_wait_dev_ready(struct adapter *adapter)
4465 {
4466         u32 whoami;
4467
4468         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4469
4470         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4471                 return 0;
4472
4473         msleep(500);
4474         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4475         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4476                 return 0;
4477
4478         dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4479                 whoami);
4480         return -EIO;
4481 }
4482
4483 struct flash_desc {
4484         u32 vendor_and_model_id;
4485         u32 size_mb;
4486 };
4487
4488 int t4_get_flash_params(struct adapter *adapter)
4489 {
4490         /*
4491          * Table for non-Numonix supported flash parts.  Numonix parts are left
4492          * to the preexisting well-tested code.  All flash parts have 64KB
4493          * sectors.
4494          */
4495         static struct flash_desc supported_flash[] = {
4496                 { 0x00150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
4497         };
4498
4499         int ret;
4500         u32 flashid = 0;
4501         unsigned int part, manufacturer;
4502         unsigned int density, size;
4503
4504         /**
4505          * Issue a Read ID Command to the Flash part.  We decode supported
4506          * Flash parts and their sizes from this.  There's a newer Query
4507          * Command which can retrieve detailed geometry information but
4508          * many Flash parts don't support it.
4509          */
4510         ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4511         if (!ret)
4512                 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4513         t4_write_reg(adapter, A_SF_OP, 0);               /* unlock SF */
4514         if (ret < 0)
4515                 return ret;
4516
4517         for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4518                 if (supported_flash[part].vendor_and_model_id == flashid) {
4519                         adapter->params.sf_size =
4520                                 supported_flash[part].size_mb;
4521                         adapter->params.sf_nsec =
4522                                 adapter->params.sf_size / SF_SEC_SIZE;
4523                         goto found;
4524                 }
4525         }
4526
4527         manufacturer = flashid & 0xff;
4528         switch (manufacturer) {
4529         case 0x20: { /* Micron/Numonix */
4530                 /**
4531                  * This Density -> Size decoding table is taken from Micron
4532                  * Data Sheets.
4533                  */
4534                 density = (flashid >> 16) & 0xff;
4535                 switch (density) {
4536                 case 0x14:
4537                         size = 1 << 20; /* 1MB */
4538                         break;
4539                 case 0x15:
4540                         size = 1 << 21; /* 2MB */
4541                         break;
4542                 case 0x16:
4543                         size = 1 << 22; /* 4MB */
4544                         break;
4545                 case 0x17:
4546                         size = 1 << 23; /* 8MB */
4547                         break;
4548                 case 0x18:
4549                         size = 1 << 24; /* 16MB */
4550                         break;
4551                 case 0x19:
4552                         size = 1 << 25; /* 32MB */
4553                         break;
4554                 case 0x20:
4555                         size = 1 << 26; /* 64MB */
4556                         break;
4557                 case 0x21:
4558                         size = 1 << 27; /* 128MB */
4559                         break;
4560                 case 0x22:
4561                         size = 1 << 28; /* 256MB */
4562                         break;
4563                 default:
4564                         dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4565                                 flashid, density);
4566                         return -EINVAL;
4567                 }
4568
4569                 adapter->params.sf_size = size;
4570                 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4571                 break;
4572         }
4573         default:
4574                 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4575                 return -EINVAL;
4576         }
4577
4578 found:
4579         /*
4580          * We should reject adapters with FLASHes which are too small. So, emit
4581          * a warning.
4582          */
4583         if (adapter->params.sf_size < FLASH_MIN_SIZE)
4584                 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4585                          flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4586
4587         return 0;
4588 }
4589
4590 static void set_pcie_completion_timeout(struct adapter *adapter,
4591                                         u8 range)
4592 {
4593         u32 pcie_cap;
4594         u16 val;
4595
4596         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4597         if (pcie_cap) {
4598                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4599                 val &= 0xfff0;
4600                 val |= range;
4601                 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4602         }
4603 }
4604
4605 /**
4606  * t4_get_chip_type - Determine chip type from device ID
4607  * @adap: the adapter
4608  * @ver: adapter version
4609  */
4610 int t4_get_chip_type(struct adapter *adap, int ver)
4611 {
4612         enum chip_type chip = 0;
4613         u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4614
4615         /* Retrieve adapter's device ID */
4616         switch (ver) {
4617         case CHELSIO_T5:
4618                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4619                 break;
4620         case CHELSIO_T6:
4621                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4622                 break;
4623         default:
4624                 dev_err(adap, "Device %d is not supported\n",
4625                         adap->params.pci.device_id);
4626                 return -EINVAL;
4627         }
4628
4629         return chip;
4630 }
4631
4632 /**
4633  * t4_prep_adapter - prepare SW and HW for operation
4634  * @adapter: the adapter
4635  *
4636  * Initialize adapter SW state for the various HW modules, set initial
4637  * values for some adapter tunables, take PHYs out of reset, and
4638  * initialize the MDIO interface.
4639  */
4640 int t4_prep_adapter(struct adapter *adapter)
4641 {
4642         int ret, ver;
4643         u32 pl_rev;
4644
4645         ret = t4_wait_dev_ready(adapter);
4646         if (ret < 0)
4647                 return ret;
4648
4649         pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4650         adapter->params.pci.device_id = adapter->pdev->id.device_id;
4651         adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4652
4653         /*
4654          * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4655          * ADAPTER (VERSION << 4 | REVISION)
4656          */
4657         ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4658         adapter->params.chip = 0;
4659         switch (ver) {
4660         case CHELSIO_T5:
4661                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4662                 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4663                 adapter->params.arch.mps_tcam_size =
4664                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4665                 adapter->params.arch.mps_rplc_size = 128;
4666                 adapter->params.arch.nchan = NCHAN;
4667                 adapter->params.arch.vfcount = 128;
4668                 break;
4669         case CHELSIO_T6:
4670                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4671                 adapter->params.arch.sge_fl_db = 0;
4672                 adapter->params.arch.mps_tcam_size =
4673                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4674                 adapter->params.arch.mps_rplc_size = 256;
4675                 adapter->params.arch.nchan = 2;
4676                 adapter->params.arch.vfcount = 256;
4677                 break;
4678         default:
4679                 dev_err(adapter, "%s: Device %d is not supported\n",
4680                         __func__, adapter->params.pci.device_id);
4681                 return -EINVAL;
4682         }
4683
4684         adapter->params.pci.vpd_cap_addr =
4685                 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4686
4687         ret = t4_get_flash_params(adapter);
4688         if (ret < 0) {
4689                 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4690                         -ret);
4691                 return ret;
4692         }
4693
4694         adapter->params.cim_la_size = CIMLA_SIZE;
4695
4696         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4697
4698         /*
4699          * Default port and clock for debugging in case we can't reach FW.
4700          */
4701         adapter->params.nports = 1;
4702         adapter->params.portvec = 1;
4703         adapter->params.vpd.cclk = 50000;
4704
4705         /* Set pci completion timeout value to 4 seconds. */
4706         set_pcie_completion_timeout(adapter, 0xd);
4707         return 0;
4708 }
4709
4710 /**
4711  * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4712  * @adapter: the adapter
4713  * @qid: the Queue ID
4714  * @qtype: the Ingress or Egress type for @qid
4715  * @pbar2_qoffset: BAR2 Queue Offset
4716  * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4717  *
4718  * Returns the BAR2 SGE Queue Registers information associated with the
4719  * indicated Absolute Queue ID.  These are passed back in return value
4720  * pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4721  * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4722  *
4723  * This may return an error which indicates that BAR2 SGE Queue
4724  * registers aren't available.  If an error is not returned, then the
4725  * following values are returned:
4726  *
4727  *   *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4728  *   *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4729  *
4730  * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4731  * require the "Inferred Queue ID" ability may be used.  E.g. the
4732  * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4733  * then these "Inferred Queue ID" register may not be used.
4734  */
4735 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4736                       enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4737                       unsigned int *pbar2_qid)
4738 {
4739         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4740         u64 bar2_page_offset, bar2_qoffset;
4741         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4742
4743         /*
4744          * T4 doesn't support BAR2 SGE Queue registers.
4745          */
4746         if (is_t4(adapter->params.chip))
4747                 return -EINVAL;
4748
4749         /*
4750          * Get our SGE Page Size parameters.
4751          */
4752         page_shift = adapter->params.sge.hps + 10;
4753         page_size = 1 << page_shift;
4754
4755         /*
4756          * Get the right Queues per Page parameters for our Queue.
4757          */
4758         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4759                               adapter->params.sge.eq_qpp :
4760                               adapter->params.sge.iq_qpp);
4761         qpp_mask = (1 << qpp_shift) - 1;
4762
4763         /*
4764          * Calculate the basics of the BAR2 SGE Queue register area:
4765          *  o The BAR2 page the Queue registers will be in.
4766          *  o The BAR2 Queue ID.
4767          *  o The BAR2 Queue ID Offset into the BAR2 page.
4768          */
4769         bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4770         bar2_qid = qid & qpp_mask;
4771         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4772
4773         /*
4774          * If the BAR2 Queue ID Offset is less than the Page Size, then the
4775          * hardware will infer the Absolute Queue ID simply from the writes to
4776          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4777          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
4778          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4779          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4780          * from the BAR2 Page and BAR2 Queue ID.
4781          *
4782          * One important censequence of this is that some BAR2 SGE registers
4783          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4784          * there.  But other registers synthesize the SGE Queue ID purely
4785          * from the writes to the registers -- the Write Combined Doorbell
4786          * Buffer is a good example.  These BAR2 SGE Registers are only
4787          * available for those BAR2 SGE Register areas where the SGE Absolute
4788          * Queue ID can be inferred from simple writes.
4789          */
4790         bar2_qoffset = bar2_page_offset;
4791         bar2_qinferred = (bar2_qid_offset < page_size);
4792         if (bar2_qinferred) {
4793                 bar2_qoffset += bar2_qid_offset;
4794                 bar2_qid = 0;
4795         }
4796
4797         *pbar2_qoffset = bar2_qoffset;
4798         *pbar2_qid = bar2_qid;
4799         return 0;
4800 }
4801
4802 /**
4803  * t4_init_sge_params - initialize adap->params.sge
4804  * @adapter: the adapter
4805  *
4806  * Initialize various fields of the adapter's SGE Parameters structure.
4807  */
4808 int t4_init_sge_params(struct adapter *adapter)
4809 {
4810         struct sge_params *sge_params = &adapter->params.sge;
4811         u32 hps, qpp;
4812         unsigned int s_hps, s_qpp;
4813
4814         /*
4815          * Extract the SGE Page Size for our PF.
4816          */
4817         hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4818         s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4819                  adapter->pf);
4820         sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4821
4822         /*
4823          * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4824          */
4825         s_qpp = (S_QUEUESPERPAGEPF0 +
4826                  (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4827         qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4828         sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4829         qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4830         sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4831
4832         return 0;
4833 }
4834
4835 /**
4836  * t4_init_tp_params - initialize adap->params.tp
4837  * @adap: the adapter
4838  *
4839  * Initialize various fields of the adapter's TP Parameters structure.
4840  */
4841 int t4_init_tp_params(struct adapter *adap)
4842 {
4843         int chan;
4844         u32 v;
4845
4846         v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4847         adap->params.tp.tre = G_TIMERRESOLUTION(v);
4848         adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4849
4850         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4851         for (chan = 0; chan < NCHAN; chan++)
4852                 adap->params.tp.tx_modq[chan] = chan;
4853
4854         /*
4855          * Cache the adapter's Compressed Filter Mode and global Incress
4856          * Configuration.
4857          */
4858         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4859                          &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4860         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4861                          &adap->params.tp.ingress_config, 1,
4862                          A_TP_INGRESS_CONFIG);
4863
4864         /* For T6, cache the adapter's compressed error vector
4865          * and passing outer header info for encapsulated packets.
4866          */
4867         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4868                 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
4869                 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
4870         }
4871
4872         /*
4873          * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4874          * shift positions of several elements of the Compressed Filter Tuple
4875          * for this adapter which we need frequently ...
4876          */
4877         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4878         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4879         adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4880         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4881                                                                F_PROTOCOL);
4882
4883         /*
4884          * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4885          * represents the presense of an Outer VLAN instead of a VNIC ID.
4886          */
4887         if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4888                 adap->params.tp.vnic_shift = -1;
4889
4890         return 0;
4891 }
4892
4893 /**
4894  * t4_filter_field_shift - calculate filter field shift
4895  * @adap: the adapter
4896  * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4897  *
4898  * Return the shift position of a filter field within the Compressed
4899  * Filter Tuple.  The filter field is specified via its selection bit
4900  * within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
4901  */
4902 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4903 {
4904         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4905         unsigned int sel;
4906         int field_shift;
4907
4908         if ((filter_mode & filter_sel) == 0)
4909                 return -1;
4910
4911         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4912                 switch (filter_mode & sel) {
4913                 case F_FCOE:
4914                         field_shift += W_FT_FCOE;
4915                         break;
4916                 case F_PORT:
4917                         field_shift += W_FT_PORT;
4918                         break;
4919                 case F_VNIC_ID:
4920                         field_shift += W_FT_VNIC_ID;
4921                         break;
4922                 case F_VLAN:
4923                         field_shift += W_FT_VLAN;
4924                         break;
4925                 case F_TOS:
4926                         field_shift += W_FT_TOS;
4927                         break;
4928                 case F_PROTOCOL:
4929                         field_shift += W_FT_PROTOCOL;
4930                         break;
4931                 case F_ETHERTYPE:
4932                         field_shift += W_FT_ETHERTYPE;
4933                         break;
4934                 case F_MACMATCH:
4935                         field_shift += W_FT_MACMATCH;
4936                         break;
4937                 case F_MPSHITTYPE:
4938                         field_shift += W_FT_MPSHITTYPE;
4939                         break;
4940                 case F_FRAGMENTATION:
4941                         field_shift += W_FT_FRAGMENTATION;
4942                         break;
4943                 }
4944         }
4945         return field_shift;
4946 }
4947
4948 int t4_init_rss_mode(struct adapter *adap, int mbox)
4949 {
4950         int i, ret;
4951         struct fw_rss_vi_config_cmd rvc;
4952
4953         memset(&rvc, 0, sizeof(rvc));
4954
4955         for_each_port(adap, i) {
4956                 struct port_info *p = adap2pinfo(adap, i);
4957
4958                 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4959                                        F_FW_CMD_REQUEST | F_FW_CMD_READ |
4960                                        V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4961                 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4962                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4963                 if (ret)
4964                         return ret;
4965                 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4966         }
4967         return 0;
4968 }
4969
4970 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4971 {
4972         u8 addr[6];
4973         int ret, i, j = 0;
4974         struct fw_port_cmd c;
4975
4976         memset(&c, 0, sizeof(c));
4977
4978         for_each_port(adap, i) {
4979                 unsigned int rss_size = 0;
4980                 struct port_info *p = adap2pinfo(adap, i);
4981
4982                 while ((adap->params.portvec & (1 << j)) == 0)
4983                         j++;
4984
4985                 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4986                                              F_FW_CMD_REQUEST | F_FW_CMD_READ |
4987                                              V_FW_PORT_CMD_PORTID(j));
4988                 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4989                                                 FW_PORT_ACTION_GET_PORT_INFO) |
4990                                                 FW_LEN16(c));
4991                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4992                 if (ret)
4993                         return ret;
4994
4995                 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4996                 if (ret < 0)
4997                         return ret;
4998
4999                 p->viid = ret;
5000                 p->tx_chan = j;
5001                 p->rss_size = rss_size;
5002                 t4_os_set_hw_addr(adap, i, addr);
5003
5004                 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
5005                 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
5006                                 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
5007                 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
5008                 p->mod_type = FW_PORT_MOD_TYPE_NA;
5009
5010                 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
5011                                  be16_to_cpu(c.u.info.acap));
5012                 j++;
5013         }
5014         return 0;
5015 }