4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <netinet/in.h>
36 #include <rte_interrupts.h>
38 #include <rte_debug.h>
40 #include <rte_atomic.h>
41 #include <rte_branch_prediction.h>
42 #include <rte_memory.h>
43 #include <rte_memzone.h>
44 #include <rte_tailq.h>
46 #include <rte_alarm.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_atomic.h>
50 #include <rte_malloc.h>
51 #include <rte_random.h>
53 #include <rte_byteorder.h>
57 #include "t4_regs_values.h"
58 #include "t4fw_interface.h"
60 static void init_link_config(struct link_config *lc, unsigned int caps);
63 * t4_read_mtu_tbl - returns the values in the HW path MTU table
65 * @mtus: where to store the MTU values
66 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
68 * Reads the HW path MTU table.
70 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
75 for (i = 0; i < NMTUS; ++i) {
76 t4_write_reg(adap, A_TP_MTU_TABLE,
77 V_MTUINDEX(0xff) | V_MTUVALUE(i));
78 v = t4_read_reg(adap, A_TP_MTU_TABLE);
79 mtus[i] = G_MTUVALUE(v);
81 mtu_log[i] = G_MTUWIDTH(v);
86 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
88 * @addr: the indirect TP register address
89 * @mask: specifies the field within the register to modify
90 * @val: new value for the field
92 * Sets a field of an indirect TP register to the given value.
94 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
95 unsigned int mask, unsigned int val)
97 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
98 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
99 t4_write_reg(adap, A_TP_PIO_DATA, val);
102 /* The minimum additive increment value for the congestion control table */
103 #define CC_MIN_INCR 2U
106 * t4_load_mtus - write the MTU and congestion control HW tables
108 * @mtus: the values for the MTU table
109 * @alpha: the values for the congestion control alpha parameter
110 * @beta: the values for the congestion control beta parameter
112 * Write the HW MTU table with the supplied MTUs and the high-speed
113 * congestion control table with the supplied alpha, beta, and MTUs.
114 * We write the two tables together because the additive increments
115 * depend on the MTUs.
117 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
118 const unsigned short *alpha, const unsigned short *beta)
120 static const unsigned int avg_pkts[NCCTRL_WIN] = {
121 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
122 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
123 28672, 40960, 57344, 81920, 114688, 163840, 229376
128 for (i = 0; i < NMTUS; ++i) {
129 unsigned int mtu = mtus[i];
130 unsigned int log2 = cxgbe_fls(mtu);
132 if (!(mtu & ((1 << log2) >> 2))) /* round */
134 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
135 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
137 for (w = 0; w < NCCTRL_WIN; ++w) {
140 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
143 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
144 (w << 16) | (beta[w] << 13) | inc);
150 * t4_wait_op_done_val - wait until an operation is completed
151 * @adapter: the adapter performing the operation
152 * @reg: the register to check for completion
153 * @mask: a single-bit field within @reg that indicates completion
154 * @polarity: the value of the field when the operation is completed
155 * @attempts: number of check iterations
156 * @delay: delay in usecs between iterations
157 * @valp: where to store the value of the register at completion time
159 * Wait until an operation is completed by checking a bit in a register
160 * up to @attempts times. If @valp is not NULL the value of the register
161 * at the time it indicated completion is stored there. Returns 0 if the
162 * operation completes and -EAGAIN otherwise.
164 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
165 int polarity, int attempts, int delay, u32 *valp)
168 u32 val = t4_read_reg(adapter, reg);
170 if (!!(val & mask) == polarity) {
183 * t4_set_reg_field - set a register field to a value
184 * @adapter: the adapter to program
185 * @addr: the register address
186 * @mask: specifies the portion of the register to modify
187 * @val: the new value for the register field
189 * Sets a register field specified by the supplied mask to the
192 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
195 u32 v = t4_read_reg(adapter, addr) & ~mask;
197 t4_write_reg(adapter, addr, v | val);
198 (void)t4_read_reg(adapter, addr); /* flush */
202 * t4_read_indirect - read indirectly addressed registers
204 * @addr_reg: register holding the indirect address
205 * @data_reg: register holding the value of the indirect register
206 * @vals: where the read register values are stored
207 * @nregs: how many indirect registers to read
208 * @start_idx: index of first indirect register to read
210 * Reads registers that are accessed indirectly through an address/data
213 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
214 unsigned int data_reg, u32 *vals, unsigned int nregs,
215 unsigned int start_idx)
218 t4_write_reg(adap, addr_reg, start_idx);
219 *vals++ = t4_read_reg(adap, data_reg);
225 * t4_write_indirect - write indirectly addressed registers
227 * @addr_reg: register holding the indirect addresses
228 * @data_reg: register holding the value for the indirect registers
229 * @vals: values to write
230 * @nregs: how many indirect registers to write
231 * @start_idx: address of first indirect register to write
233 * Writes a sequential block of registers that are accessed indirectly
234 * through an address/data register pair.
236 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
237 unsigned int data_reg, const u32 *vals,
238 unsigned int nregs, unsigned int start_idx)
241 t4_write_reg(adap, addr_reg, start_idx++);
242 t4_write_reg(adap, data_reg, *vals++);
247 * t4_report_fw_error - report firmware error
250 * The adapter firmware can indicate error conditions to the host.
251 * If the firmware has indicated an error, print out the reason for
252 * the firmware error.
254 static void t4_report_fw_error(struct adapter *adap)
256 static const char * const reason[] = {
257 "Crash", /* PCIE_FW_EVAL_CRASH */
258 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
259 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
260 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
261 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
262 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
263 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
264 "Reserved", /* reserved */
268 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
269 if (pcie_fw & F_PCIE_FW_ERR)
270 pr_err("%s: Firmware reports adapter error: %s\n",
271 __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
275 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
277 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
280 for ( ; nflit; nflit--, mbox_addr += 8)
281 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
285 * Handle a FW assertion reported in a mailbox.
287 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
289 struct fw_debug_cmd asrt;
291 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
292 pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
293 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
294 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
297 #define X_CIM_PF_NOACCESS 0xeeeeeeee
300 * If the Host OS Driver needs locking arround accesses to the mailbox, this
301 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
303 /* makes single-statement usage a bit cleaner ... */
304 #ifdef T4_OS_NEEDS_MBOX_LOCKING
305 #define T4_OS_MBOX_LOCKING(x) x
307 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
311 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
313 * @mbox: index of the mailbox to use
314 * @cmd: the command to write
315 * @size: command length in bytes
316 * @rpl: where to optionally store the reply
317 * @sleep_ok: if true we may sleep while awaiting command completion
318 * @timeout: time to wait for command to finish before timing out
319 * (negative implies @sleep_ok=false)
321 * Sends the given command to FW through the selected mailbox and waits
322 * for the FW to execute the command. If @rpl is not %NULL it is used to
323 * store the FW's reply to the command. The command and its optional
324 * reply are of the same length. Some FW commands like RESET and
325 * INITIALIZE can take a considerable amount of time to execute.
326 * @sleep_ok determines whether we may sleep while awaiting the response.
327 * If sleeping is allowed we use progressive backoff otherwise we spin.
328 * Note that passing in a negative @timeout is an alternate mechanism
329 * for specifying @sleep_ok=false. This is useful when a higher level
330 * interface allows for specification of @timeout but not @sleep_ok ...
332 * Returns 0 on success or a negative errno on failure. A
333 * failure can happen either because we are not able to execute the
334 * command or FW executes it but signals an error. In the latter case
335 * the return value is the error code indicated by FW (negated).
337 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
338 const void __attribute__((__may_alias__)) *cmd,
339 int size, void *rpl, bool sleep_ok, int timeout)
342 * We delay in small increments at first in an effort to maintain
343 * responsiveness for simple, fast executing commands but then back
344 * off to larger delays to a maximum retry delay.
346 static const int delay[] = {
347 1, 1, 3, 5, 10, 10, 20, 50, 100
353 unsigned int delay_idx;
354 __be64 *temp = (__be64 *)malloc(size * sizeof(char));
356 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
357 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
359 struct mbox_entry entry;
365 if ((size & 15) || size > MBOX_LEN) {
371 memcpy(p, (const __be64 *)cmd, size);
374 * If we have a negative timeout, that implies that we can't sleep.
381 #ifdef T4_OS_NEEDS_MBOX_LOCKING
383 * Queue ourselves onto the mailbox access list. When our entry is at
384 * the front of the list, we have rights to access the mailbox. So we
385 * wait [for a while] till we're at the front [or bail out with an
388 t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
393 for (i = 0; ; i += ms) {
395 * If we've waited too long, return a busy indication. This
396 * really ought to be based on our initial position in the
397 * mailbox access list but this is a start. We very rarely
398 * contend on access to the mailbox ... Also check for a
399 * firmware error which we'll report as a device error.
401 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
402 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
403 t4_os_atomic_list_del(&entry, &adap->mbox_list,
405 t4_report_fw_error(adap);
406 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
410 * If we're at the head, break out and start the mailbox
413 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
417 * Delay for a bit before checking again ...
420 ms = delay[delay_idx]; /* last element may repeat */
421 if (delay_idx < ARRAY_SIZE(delay) - 1)
428 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
431 * Attempt to gain access to the mailbox.
433 for (i = 0; i < 4; i++) {
434 ctl = t4_read_reg(adap, ctl_reg);
436 if (v != X_MBOWNER_NONE)
441 * If we were unable to gain access, dequeue ourselves from the
442 * mailbox atomic access list and report the error to our caller.
444 if (v != X_MBOWNER_PL) {
445 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
448 t4_report_fw_error(adap);
449 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
453 * If we gain ownership of the mailbox and there's a "valid" message
454 * in it, this is likely an asynchronous error message from the
455 * firmware. So we'll report that and then proceed on with attempting
456 * to issue our own command ... which may well fail if the error
457 * presaged the firmware crashing ...
459 if (ctl & F_MBMSGVALID) {
460 dev_err(adap, "found VALID command in mbox %u: "
461 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
462 (unsigned long long)t4_read_reg64(adap, data_reg),
463 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
464 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
465 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
466 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
467 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
468 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
469 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
473 * Copy in the new mailbox command and send it on its way ...
475 for (i = 0; i < size; i += 8, p++)
476 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
478 CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
479 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
480 (unsigned long long)t4_read_reg64(adap, data_reg),
481 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
482 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
483 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
484 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
485 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
486 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
487 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
489 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
490 t4_read_reg(adap, ctl_reg); /* flush write */
496 * Loop waiting for the reply; bail out if we time out or the firmware
499 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
500 for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
502 ms = delay[delay_idx]; /* last element may repeat */
503 if (delay_idx < ARRAY_SIZE(delay) - 1)
510 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
511 v = t4_read_reg(adap, ctl_reg);
512 if (v == X_CIM_PF_NOACCESS)
514 if (G_MBOWNER(v) == X_MBOWNER_PL) {
515 if (!(v & F_MBMSGVALID)) {
516 t4_write_reg(adap, ctl_reg,
517 V_MBOWNER(X_MBOWNER_NONE));
521 CXGBE_DEBUG_MBOX(adap,
522 "%s: mbox %u: %016llx %016llx %016llx %016llx "
523 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
524 (unsigned long long)t4_read_reg64(adap, data_reg),
525 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
526 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
527 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
528 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
529 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
530 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
531 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
533 CXGBE_DEBUG_MBOX(adap,
534 "command %#x completed in %d ms (%ssleeping)\n",
536 i + ms, sleep_ok ? "" : "non-");
538 res = t4_read_reg64(adap, data_reg);
539 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
540 fw_asrt(adap, data_reg);
541 res = V_FW_CMD_RETVAL(EIO);
543 get_mbox_rpl(adap, rpl, size / 8, data_reg);
545 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
547 t4_os_atomic_list_del(&entry, &adap->mbox_list,
549 return -G_FW_CMD_RETVAL((int)res);
554 * We timed out waiting for a reply to our mailbox command. Report
555 * the error and also check to see if the firmware reported any
558 dev_err(adap, "command %#x in mailbox %d timed out\n",
559 *(const u8 *)cmd, mbox);
560 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
563 t4_report_fw_error(adap);
565 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
568 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
569 void *rpl, bool sleep_ok)
571 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
576 * t4_get_regs_len - return the size of the chips register set
577 * @adapter: the adapter
579 * Returns the size of the chip's BAR0 register space.
581 unsigned int t4_get_regs_len(struct adapter *adapter)
583 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
585 switch (chip_version) {
588 return T5_REGMAP_SIZE;
592 "Unsupported chip version %d\n", chip_version);
597 * t4_get_regs - read chip registers into provided buffer
599 * @buf: register buffer
600 * @buf_size: size (in bytes) of register buffer
602 * If the provided register buffer isn't large enough for the chip's
603 * full register range, the register dump will be truncated to the
604 * register buffer's size.
606 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
608 static const unsigned int t5_reg_ranges[] = {
1383 static const unsigned int t6_reg_ranges[] = {
1944 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1945 const unsigned int *reg_ranges;
1946 int reg_ranges_size, range;
1947 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1949 /* Select the right set of register ranges to dump depending on the
1950 * adapter chip type.
1952 switch (chip_version) {
1954 reg_ranges = t5_reg_ranges;
1955 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1959 reg_ranges = t6_reg_ranges;
1960 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1965 "Unsupported chip version %d\n", chip_version);
1969 /* Clear the register buffer and insert the appropriate register
1970 * values selected by the above register ranges.
1972 memset(buf, 0, buf_size);
1973 for (range = 0; range < reg_ranges_size; range += 2) {
1974 unsigned int reg = reg_ranges[range];
1975 unsigned int last_reg = reg_ranges[range + 1];
1976 u32 *bufp = (u32 *)((char *)buf + reg);
1978 /* Iterate across the register range filling in the register
1979 * buffer but don't write past the end of the register buffer.
1981 while (reg <= last_reg && bufp < buf_end) {
1982 *bufp++ = t4_read_reg(adap, reg);
1988 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1989 #define EEPROM_DELAY 10 /* 10us per poll spin */
1990 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
1992 #define EEPROM_STAT_ADDR 0x7bfc
1995 * Small utility function to wait till any outstanding VPD Access is complete.
1996 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1997 * VPD Access in flight. This allows us to handle the problem of having a
1998 * previous VPD Access time out and prevent an attempt to inject a new VPD
1999 * Request before any in-flight VPD request has completed.
2001 static int t4_seeprom_wait(struct adapter *adapter)
2003 unsigned int base = adapter->params.pci.vpd_cap_addr;
2006 /* If no VPD Access is in flight, we can just return success right
2009 if (!adapter->vpd_busy)
2012 /* Poll the VPD Capability Address/Flag register waiting for it
2013 * to indicate that the operation is complete.
2015 max_poll = EEPROM_MAX_POLL;
2019 udelay(EEPROM_DELAY);
2020 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2022 /* If the operation is complete, mark the VPD as no longer
2023 * busy and return success.
2025 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2026 adapter->vpd_busy = 0;
2029 } while (--max_poll);
2031 /* Failure! Note that we leave the VPD Busy status set in order to
2032 * avoid pushing a new VPD Access request into the VPD Capability till
2033 * the current operation eventually succeeds. It's a bug to issue a
2034 * new request when an existing request is in flight and will result
2035 * in corrupt hardware state.
2041 * t4_seeprom_read - read a serial EEPROM location
2042 * @adapter: adapter to read
2043 * @addr: EEPROM virtual address
2044 * @data: where to store the read data
2046 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2047 * VPD capability. Note that this function must be called with a virtual
2050 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2052 unsigned int base = adapter->params.pci.vpd_cap_addr;
2055 /* VPD Accesses must alway be 4-byte aligned!
2057 if (addr >= EEPROMVSIZE || (addr & 3))
2060 /* Wait for any previous operation which may still be in flight to
2063 ret = t4_seeprom_wait(adapter);
2065 dev_err(adapter, "VPD still busy from previous operation\n");
2069 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2070 * for our request to complete. If it doesn't complete, note the
2071 * error and return it to our caller. Note that we do not reset the
2074 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2075 adapter->vpd_busy = 1;
2076 adapter->vpd_flag = PCI_VPD_ADDR_F;
2077 ret = t4_seeprom_wait(adapter);
2079 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2083 /* Grab the returned data, swizzle it into our endianness and
2086 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2087 *data = le32_to_cpu(*data);
2092 * t4_seeprom_write - write a serial EEPROM location
2093 * @adapter: adapter to write
2094 * @addr: virtual EEPROM address
2095 * @data: value to write
2097 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2098 * VPD capability. Note that this function must be called with a virtual
2101 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2103 unsigned int base = adapter->params.pci.vpd_cap_addr;
2108 /* VPD Accesses must alway be 4-byte aligned!
2110 if (addr >= EEPROMVSIZE || (addr & 3))
2113 /* Wait for any previous operation which may still be in flight to
2116 ret = t4_seeprom_wait(adapter);
2118 dev_err(adapter, "VPD still busy from previous operation\n");
2122 /* Issue our new VPD Read request, mark the VPD as being busy and wait
2123 * for our request to complete. If it doesn't complete, note the
2124 * error and return it to our caller. Note that we do not reset the
2127 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2129 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2130 (u16)addr | PCI_VPD_ADDR_F);
2131 adapter->vpd_busy = 1;
2132 adapter->vpd_flag = 0;
2133 ret = t4_seeprom_wait(adapter);
2135 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2139 /* Reset PCI_VPD_DATA register after a transaction and wait for our
2140 * request to complete. If it doesn't complete, return error.
2142 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2143 max_poll = EEPROM_MAX_POLL;
2145 udelay(EEPROM_DELAY);
2146 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2147 } while ((stats_reg & 0x1) && --max_poll);
2151 /* Return success! */
2156 * t4_seeprom_wp - enable/disable EEPROM write protection
2157 * @adapter: the adapter
2158 * @enable: whether to enable or disable write protection
2160 * Enables or disables write protection on the serial EEPROM.
2162 int t4_seeprom_wp(struct adapter *adapter, int enable)
2164 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2168 * t4_config_rss_range - configure a portion of the RSS mapping table
2169 * @adapter: the adapter
2170 * @mbox: mbox to use for the FW command
2171 * @viid: virtual interface whose RSS subtable is to be written
2172 * @start: start entry in the table to write
2173 * @n: how many table entries to write
2174 * @rspq: values for the "response queue" (Ingress Queue) lookup table
2175 * @nrspq: number of values in @rspq
2177 * Programs the selected part of the VI's RSS mapping table with the
2178 * provided values. If @nrspq < @n the supplied values are used repeatedly
2179 * until the full table range is populated.
2181 * The caller must ensure the values in @rspq are in the range allowed for
2184 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2185 int start, int n, const u16 *rspq, unsigned int nrspq)
2188 const u16 *rsp = rspq;
2189 const u16 *rsp_end = rspq + nrspq;
2190 struct fw_rss_ind_tbl_cmd cmd;
2192 memset(&cmd, 0, sizeof(cmd));
2193 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2194 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2195 V_FW_RSS_IND_TBL_CMD_VIID(viid));
2196 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2199 * Each firmware RSS command can accommodate up to 32 RSS Ingress
2200 * Queue Identifiers. These Ingress Queue IDs are packed three to
2201 * a 32-bit word as 10-bit values with the upper remaining 2 bits
2205 int nq = min(n, 32);
2207 __be32 *qp = &cmd.iq0_to_iq2;
2210 * Set up the firmware RSS command header to send the next
2211 * "nq" Ingress Queue IDs to the firmware.
2213 cmd.niqid = cpu_to_be16(nq);
2214 cmd.startidx = cpu_to_be16(start);
2217 * "nq" more done for the start of the next loop.
2223 * While there are still Ingress Queue IDs to stuff into the
2224 * current firmware RSS command, retrieve them from the
2225 * Ingress Queue ID array and insert them into the command.
2229 * Grab up to the next 3 Ingress Queue IDs (wrapping
2230 * around the Ingress Queue ID array if necessary) and
2231 * insert them into the firmware RSS command at the
2232 * current 3-tuple position within the commad.
2236 int nqbuf = min(3, nq);
2242 while (nqbuf && nq_packed < 32) {
2249 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2250 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2251 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2255 * Send this portion of the RRS table update to the firmware;
2256 * bail out on any errors.
2258 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2267 * t4_config_vi_rss - configure per VI RSS settings
2268 * @adapter: the adapter
2269 * @mbox: mbox to use for the FW command
2272 * @defq: id of the default RSS queue for the VI.
2274 * Configures VI-specific RSS properties.
2276 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2277 unsigned int flags, unsigned int defq)
2279 struct fw_rss_vi_config_cmd c;
2281 memset(&c, 0, sizeof(c));
2282 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2283 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2284 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2285 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2286 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2287 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2288 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2292 * init_cong_ctrl - initialize congestion control parameters
2293 * @a: the alpha values for congestion control
2294 * @b: the beta values for congestion control
2296 * Initialize the congestion control parameters.
2298 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2302 for (i = 0; i < 9; i++) {
2356 #define INIT_CMD(var, cmd, rd_wr) do { \
2357 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2358 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2359 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2362 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2364 u32 cclk_param, cclk_val;
2368 * Ask firmware for the Core Clock since it knows how to translate the
2369 * Reference Clock ('V2') VPD field into a Core Clock value ...
2371 cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2372 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2373 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2374 1, &cclk_param, &cclk_val);
2376 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2382 dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2386 /* serial flash and firmware constants and flash config file constants */
2388 SF_ATTEMPTS = 10, /* max retries for SF operations */
2390 /* flash command opcodes */
2391 SF_PROG_PAGE = 2, /* program page */
2392 SF_WR_DISABLE = 4, /* disable writes */
2393 SF_RD_STATUS = 5, /* read status register */
2394 SF_WR_ENABLE = 6, /* enable writes */
2395 SF_RD_DATA_FAST = 0xb, /* read flash */
2396 SF_RD_ID = 0x9f, /* read ID */
2397 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2401 * sf1_read - read data from the serial flash
2402 * @adapter: the adapter
2403 * @byte_cnt: number of bytes to read
2404 * @cont: whether another operation will be chained
2405 * @lock: whether to lock SF for PL access only
2406 * @valp: where to store the read data
2408 * Reads up to 4 bytes of data from the serial flash. The location of
2409 * the read needs to be specified prior to calling this by issuing the
2410 * appropriate commands to the serial flash.
2412 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2413 int lock, u32 *valp)
2417 if (!byte_cnt || byte_cnt > 4)
2419 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2421 t4_write_reg(adapter, A_SF_OP,
2422 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2423 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2425 *valp = t4_read_reg(adapter, A_SF_DATA);
2430 * sf1_write - write data to the serial flash
2431 * @adapter: the adapter
2432 * @byte_cnt: number of bytes to write
2433 * @cont: whether another operation will be chained
2434 * @lock: whether to lock SF for PL access only
2435 * @val: value to write
2437 * Writes up to 4 bytes of data to the serial flash. The location of
2438 * the write needs to be specified prior to calling this by issuing the
2439 * appropriate commands to the serial flash.
2441 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2444 if (!byte_cnt || byte_cnt > 4)
2446 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2448 t4_write_reg(adapter, A_SF_DATA, val);
2449 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2450 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2451 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2455 * t4_read_flash - read words from serial flash
2456 * @adapter: the adapter
2457 * @addr: the start address for the read
2458 * @nwords: how many 32-bit words to read
2459 * @data: where to store the read data
2460 * @byte_oriented: whether to store data as bytes or as words
2462 * Read the specified number of 32-bit words from the serial flash.
2463 * If @byte_oriented is set the read data is stored as a byte array
2464 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2465 * natural endianness.
2467 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2468 unsigned int nwords, u32 *data, int byte_oriented)
2472 if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2476 addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2478 ret = sf1_write(adapter, 4, 1, 0, addr);
2482 ret = sf1_read(adapter, 1, 1, 0, data);
2486 for ( ; nwords; nwords--, data++) {
2487 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2489 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
2493 *data = cpu_to_be32(*data);
2499 * t4_get_fw_version - read the firmware version
2500 * @adapter: the adapter
2501 * @vers: where to place the version
2503 * Reads the FW version from flash.
2505 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2507 return t4_read_flash(adapter, FLASH_FW_START +
2508 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2512 * t4_get_tp_version - read the TP microcode version
2513 * @adapter: the adapter
2514 * @vers: where to place the version
2516 * Reads the TP microcode version from flash.
2518 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2520 return t4_read_flash(adapter, FLASH_FW_START +
2521 offsetof(struct fw_hdr, tp_microcode_ver),
2525 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
2529 * t4_link_l1cfg - apply link configuration to MAC/PHY
2530 * @phy: the PHY to setup
2531 * @mac: the MAC to setup
2532 * @lc: the requested link configuration
2534 * Set up a port's MAC and PHY according to a desired link configuration.
2535 * - If the PHY can auto-negotiate first decide what to advertise, then
2536 * enable/disable auto-negotiation as desired, and reset.
2537 * - If the PHY does not auto-negotiate just reset it.
2538 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2539 * otherwise do it later based on the outcome of auto-negotiation.
2541 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2542 struct link_config *lc)
2544 struct fw_port_cmd c;
2545 unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
2548 if (lc->requested_fc & PAUSE_RX)
2549 fc |= FW_PORT_CAP_FC_RX;
2550 if (lc->requested_fc & PAUSE_TX)
2551 fc |= FW_PORT_CAP_FC_TX;
2553 memset(&c, 0, sizeof(c));
2554 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2555 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2556 V_FW_PORT_CMD_PORTID(port));
2558 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2561 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2562 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2564 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
2565 } else if (lc->autoneg == AUTONEG_DISABLE) {
2566 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
2567 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
2569 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
2572 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2576 * t4_flash_cfg_addr - return the address of the flash configuration file
2577 * @adapter: the adapter
2579 * Return the address within the flash where the Firmware Configuration
2580 * File is stored, or an error if the device FLASH is too small to contain
2581 * a Firmware Configuration File.
2583 int t4_flash_cfg_addr(struct adapter *adapter)
2586 * If the device FLASH isn't large enough to hold a Firmware
2587 * Configuration File, return an error.
2589 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2592 return FLASH_CFG_START;
2595 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2598 * t4_intr_enable - enable interrupts
2599 * @adapter: the adapter whose interrupts should be enabled
2601 * Enable PF-specific interrupts for the calling function and the top-level
2602 * interrupt concentrator for global interrupts. Interrupts are already
2603 * enabled at each module, here we just enable the roots of the interrupt
2606 * Note: this function should be called only when the driver manages
2607 * non PF-specific interrupts from the various HW modules. Only one PCI
2608 * function at a time should be doing this.
2610 void t4_intr_enable(struct adapter *adapter)
2613 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2614 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2615 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2617 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2618 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2619 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2620 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2621 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2622 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2623 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2624 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2625 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2626 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2627 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2631 * t4_intr_disable - disable interrupts
2632 * @adapter: the adapter whose interrupts should be disabled
2634 * Disable interrupts. We only disable the top-level interrupt
2635 * concentrators. The caller must be a PCI function managing global
2638 void t4_intr_disable(struct adapter *adapter)
2640 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2641 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2642 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2644 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2645 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2649 * t4_get_port_type_description - return Port Type string description
2650 * @port_type: firmware Port Type enumeration
2652 const char *t4_get_port_type_description(enum fw_port_type port_type)
2654 static const char * const port_type_description[] = {
2679 if (port_type < ARRAY_SIZE(port_type_description))
2680 return port_type_description[port_type];
2685 * t4_get_mps_bg_map - return the buffer groups associated with a port
2686 * @adap: the adapter
2687 * @idx: the port index
2689 * Returns a bitmap indicating which MPS buffer groups are associated
2690 * with the given port. Bit i is set if buffer group i is used by the
2693 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
2695 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
2698 return idx == 0 ? 0xf : 0;
2700 return idx < 2 ? (3 << (2 * idx)) : 0;
2705 * t4_get_port_stats - collect port statistics
2706 * @adap: the adapter
2707 * @idx: the port index
2708 * @p: the stats structure to fill
2710 * Collect statistics related to the given port from HW.
2712 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2714 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2716 #define GET_STAT(name) \
2717 t4_read_reg64(adap, \
2718 (is_t4(adap->params.chip) ? \
2719 PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2720 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2721 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2723 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2724 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2725 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2726 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2727 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2728 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2729 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2730 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2731 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2732 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2733 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2734 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2735 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2736 p->tx_drop = GET_STAT(TX_PORT_DROP);
2737 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2738 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2739 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2740 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2741 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2742 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2743 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2744 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2745 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2747 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2748 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2749 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2750 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2751 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2752 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2753 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2754 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2755 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2756 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2757 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2758 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2759 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2760 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2761 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2762 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2763 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2764 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2765 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2766 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2767 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2768 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2769 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2770 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2771 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2772 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2773 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2774 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2775 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2776 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2777 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2778 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2779 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2780 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2781 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2788 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
2789 * @adap: The adapter
2791 * @stats: Current stats to fill
2792 * @offset: Previous stats snapshot
2794 void t4_get_port_stats_offset(struct adapter *adap, int idx,
2795 struct port_stats *stats,
2796 struct port_stats *offset)
2801 t4_get_port_stats(adap, idx, stats);
2802 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
2803 i < (sizeof(struct port_stats) / sizeof(u64));
2809 * t4_clr_port_stats - clear port statistics
2810 * @adap: the adapter
2811 * @idx: the port index
2813 * Clear HW statistics for the given port.
2815 void t4_clr_port_stats(struct adapter *adap, int idx)
2818 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2821 if (is_t4(adap->params.chip))
2822 port_base_addr = PORT_BASE(idx);
2824 port_base_addr = T5_PORT_BASE(idx);
2826 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
2827 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
2828 t4_write_reg(adap, port_base_addr + i, 0);
2829 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
2830 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
2831 t4_write_reg(adap, port_base_addr + i, 0);
2832 for (i = 0; i < 4; i++)
2833 if (bgmap & (1 << i)) {
2835 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
2838 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
2844 * t4_fw_hello - establish communication with FW
2845 * @adap: the adapter
2846 * @mbox: mailbox to use for the FW command
2847 * @evt_mbox: mailbox to receive async FW events
2848 * @master: specifies the caller's willingness to be the device master
2849 * @state: returns the current device state (if non-NULL)
2851 * Issues a command to establish communication with FW. Returns either
2852 * an error (negative integer) or the mailbox of the Master PF.
2854 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2855 enum dev_master master, enum dev_state *state)
2858 struct fw_hello_cmd c;
2860 unsigned int master_mbox;
2861 int retries = FW_CMD_HELLO_RETRIES;
2864 memset(&c, 0, sizeof(c));
2865 INIT_CMD(c, HELLO, WRITE);
2866 c.err_to_clearinit = cpu_to_be32(
2867 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2868 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2869 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2870 M_FW_HELLO_CMD_MBMASTER) |
2871 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2872 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
2873 F_FW_HELLO_CMD_CLEARINIT);
2876 * Issue the HELLO command to the firmware. If it's not successful
2877 * but indicates that we got a "busy" or "timeout" condition, retry
2878 * the HELLO until we exhaust our retry limit. If we do exceed our
2879 * retry limit, check to see if the firmware left us any error
2880 * information and report that if so ...
2882 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2883 if (ret != FW_SUCCESS) {
2884 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2886 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
2887 t4_report_fw_error(adap);
2891 v = be32_to_cpu(c.err_to_clearinit);
2892 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
2894 if (v & F_FW_HELLO_CMD_ERR)
2895 *state = DEV_STATE_ERR;
2896 else if (v & F_FW_HELLO_CMD_INIT)
2897 *state = DEV_STATE_INIT;
2899 *state = DEV_STATE_UNINIT;
2903 * If we're not the Master PF then we need to wait around for the
2904 * Master PF Driver to finish setting up the adapter.
2906 * Note that we also do this wait if we're a non-Master-capable PF and
2907 * there is no current Master PF; a Master PF may show up momentarily
2908 * and we wouldn't want to fail pointlessly. (This can happen when an
2909 * OS loads lots of different drivers rapidly at the same time). In
2910 * this case, the Master PF returned by the firmware will be
2911 * M_PCIE_FW_MASTER so the test below will work ...
2913 if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
2914 master_mbox != mbox) {
2915 int waiting = FW_CMD_HELLO_TIMEOUT;
2918 * Wait for the firmware to either indicate an error or
2919 * initialized state. If we see either of these we bail out
2920 * and report the issue to the caller. If we exhaust the
2921 * "hello timeout" and we haven't exhausted our retries, try
2922 * again. Otherwise bail with a timeout error.
2931 * If neither Error nor Initialialized are indicated
2932 * by the firmware keep waiting till we exaust our
2933 * timeout ... and then retry if we haven't exhausted
2936 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
2937 if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
2948 * We either have an Error or Initialized condition
2949 * report errors preferentially.
2952 if (pcie_fw & F_PCIE_FW_ERR)
2953 *state = DEV_STATE_ERR;
2954 else if (pcie_fw & F_PCIE_FW_INIT)
2955 *state = DEV_STATE_INIT;
2959 * If we arrived before a Master PF was selected and
2960 * there's not a valid Master PF, grab its identity
2963 if (master_mbox == M_PCIE_FW_MASTER &&
2964 (pcie_fw & F_PCIE_FW_MASTER_VLD))
2965 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
2974 * t4_fw_bye - end communication with FW
2975 * @adap: the adapter
2976 * @mbox: mailbox to use for the FW command
2978 * Issues a command to terminate communication with FW.
2980 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2982 struct fw_bye_cmd c;
2984 memset(&c, 0, sizeof(c));
2985 INIT_CMD(c, BYE, WRITE);
2986 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2990 * t4_fw_reset - issue a reset to FW
2991 * @adap: the adapter
2992 * @mbox: mailbox to use for the FW command
2993 * @reset: specifies the type of reset to perform
2995 * Issues a reset command of the specified type to FW.
2997 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2999 struct fw_reset_cmd c;
3001 memset(&c, 0, sizeof(c));
3002 INIT_CMD(c, RESET, WRITE);
3003 c.val = cpu_to_be32(reset);
3004 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3008 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3009 * @adap: the adapter
3010 * @mbox: mailbox to use for the FW RESET command (if desired)
3011 * @force: force uP into RESET even if FW RESET command fails
3013 * Issues a RESET command to firmware (if desired) with a HALT indication
3014 * and then puts the microprocessor into RESET state. The RESET command
3015 * will only be issued if a legitimate mailbox is provided (mbox <=
3016 * M_PCIE_FW_MASTER).
3018 * This is generally used in order for the host to safely manipulate the
3019 * adapter without fear of conflicting with whatever the firmware might
3020 * be doing. The only way out of this state is to RESTART the firmware
3023 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3028 * If a legitimate mailbox is provided, issue a RESET command
3029 * with a HALT indication.
3031 if (mbox <= M_PCIE_FW_MASTER) {
3032 struct fw_reset_cmd c;
3034 memset(&c, 0, sizeof(c));
3035 INIT_CMD(c, RESET, WRITE);
3036 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3037 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3038 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3042 * Normally we won't complete the operation if the firmware RESET
3043 * command fails but if our caller insists we'll go ahead and put the
3044 * uP into RESET. This can be useful if the firmware is hung or even
3045 * missing ... We'll have to take the risk of putting the uP into
3046 * RESET without the cooperation of firmware in that case.
3048 * We also force the firmware's HALT flag to be on in case we bypassed
3049 * the firmware RESET command above or we're dealing with old firmware
3050 * which doesn't have the HALT capability. This will serve as a flag
3051 * for the incoming firmware to know that it's coming out of a HALT
3052 * rather than a RESET ... if it's new enough to understand that ...
3054 if (ret == 0 || force) {
3055 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3056 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3061 * And we always return the result of the firmware RESET command
3062 * even when we force the uP into RESET ...
3068 * t4_fw_restart - restart the firmware by taking the uP out of RESET
3069 * @adap: the adapter
3070 * @mbox: mailbox to use for the FW RESET command (if desired)
3071 * @reset: if we want to do a RESET to restart things
3073 * Restart firmware previously halted by t4_fw_halt(). On successful
3074 * return the previous PF Master remains as the new PF Master and there
3075 * is no need to issue a new HELLO command, etc.
3077 * We do this in two ways:
3079 * 1. If we're dealing with newer firmware we'll simply want to take
3080 * the chip's microprocessor out of RESET. This will cause the
3081 * firmware to start up from its start vector. And then we'll loop
3082 * until the firmware indicates it's started again (PCIE_FW.HALT
3083 * reset to 0) or we timeout.
3085 * 2. If we're dealing with older firmware then we'll need to RESET
3086 * the chip since older firmware won't recognize the PCIE_FW.HALT
3087 * flag and automatically RESET itself on startup.
3089 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3093 * Since we're directing the RESET instead of the firmware
3094 * doing it automatically, we need to clear the PCIE_FW.HALT
3097 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3100 * If we've been given a valid mailbox, first try to get the
3101 * firmware to do the RESET. If that works, great and we can
3102 * return success. Otherwise, if we haven't been given a
3103 * valid mailbox or the RESET command failed, fall back to
3104 * hitting the chip with a hammer.
3106 if (mbox <= M_PCIE_FW_MASTER) {
3107 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3109 if (t4_fw_reset(adap, mbox,
3110 F_PIORST | F_PIORSTMODE) == 0)
3114 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3119 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3120 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3121 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3132 * t4_fixup_host_params_compat - fix up host-dependent parameters
3133 * @adap: the adapter
3134 * @page_size: the host's Base Page Size
3135 * @cache_line_size: the host's Cache Line Size
3136 * @chip_compat: maintain compatibility with designated chip
3138 * Various registers in the chip contain values which are dependent on the
3139 * host's Base Page and Cache Line Sizes. This function will fix all of
3140 * those registers with the appropriate values as passed in ...
3142 * @chip_compat is used to limit the set of changes that are made
3143 * to be compatible with the indicated chip release. This is used by
3144 * drivers to maintain compatibility with chip register settings when
3145 * the drivers haven't [yet] been updated with new chip support.
3147 int t4_fixup_host_params_compat(struct adapter *adap,
3148 unsigned int page_size,
3149 unsigned int cache_line_size,
3150 enum chip_type chip_compat)
3152 unsigned int page_shift = cxgbe_fls(page_size) - 1;
3153 unsigned int sge_hps = page_shift - 10;
3154 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3155 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3156 unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3158 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3159 V_HOSTPAGESIZEPF0(sge_hps) |
3160 V_HOSTPAGESIZEPF1(sge_hps) |
3161 V_HOSTPAGESIZEPF2(sge_hps) |
3162 V_HOSTPAGESIZEPF3(sge_hps) |
3163 V_HOSTPAGESIZEPF4(sge_hps) |
3164 V_HOSTPAGESIZEPF5(sge_hps) |
3165 V_HOSTPAGESIZEPF6(sge_hps) |
3166 V_HOSTPAGESIZEPF7(sge_hps));
3168 if (is_t4(adap->params.chip) || is_t4(chip_compat))
3169 t4_set_reg_field(adap, A_SGE_CONTROL,
3170 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3171 F_EGRSTATUSPAGESIZE,
3172 V_INGPADBOUNDARY(fl_align_log -
3173 X_INGPADBOUNDARY_SHIFT) |
3174 V_EGRSTATUSPAGESIZE(stat_len != 64));
3177 * T5 introduced the separation of the Free List Padding and
3178 * Packing Boundaries. Thus, we can select a smaller Padding
3179 * Boundary to avoid uselessly chewing up PCIe Link and Memory
3180 * Bandwidth, and use a Packing Boundary which is large enough
3181 * to avoid false sharing between CPUs, etc.
3183 * For the PCI Link, the smaller the Padding Boundary the
3184 * better. For the Memory Controller, a smaller Padding
3185 * Boundary is better until we cross under the Memory Line
3186 * Size (the minimum unit of transfer to/from Memory). If we
3187 * have a Padding Boundary which is smaller than the Memory
3188 * Line Size, that'll involve a Read-Modify-Write cycle on the
3189 * Memory Controller which is never good. For T5 the smallest
3190 * Padding Boundary which we can select is 32 bytes which is
3191 * larger than any known Memory Controller Line Size so we'll
3196 * N.B. T5 has a different interpretation of the "0" value for
3197 * the Packing Boundary. This corresponds to 16 bytes instead
3198 * of the expected 32 bytes. We never have a Packing Boundary
3199 * less than 32 bytes so we can't use that special value but
3200 * on the other hand, if we wanted 32 bytes, the best we can
3201 * really do is 64 bytes ...
3203 if (fl_align <= 32) {
3207 t4_set_reg_field(adap, A_SGE_CONTROL,
3208 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3209 F_EGRSTATUSPAGESIZE,
3210 V_INGPADBOUNDARY(X_INGPCIEBOUNDARY_32B) |
3211 V_EGRSTATUSPAGESIZE(stat_len != 64));
3212 t4_set_reg_field(adap, A_SGE_CONTROL2,
3213 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3214 V_INGPACKBOUNDARY(fl_align_log -
3215 X_INGPACKBOUNDARY_SHIFT));
3219 * Adjust various SGE Free List Host Buffer Sizes.
3221 * The first four entries are:
3225 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3226 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3228 * For the single-MTU buffers in unpacked mode we need to include
3229 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3230 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3231 * Padding boundary. All of these are accommodated in the Factory
3232 * Default Firmware Configuration File but we need to adjust it for
3233 * this host's cache line size.
3235 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3236 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3237 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3239 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3240 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3243 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3249 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3250 * @adap: the adapter
3251 * @page_size: the host's Base Page Size
3252 * @cache_line_size: the host's Cache Line Size
3254 * Various registers in T4 contain values which are dependent on the
3255 * host's Base Page and Cache Line Sizes. This function will fix all of
3256 * those registers with the appropriate values as passed in ...
3258 * This routine makes changes which are compatible with T4 chips.
3260 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3261 unsigned int cache_line_size)
3263 return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3268 * t4_fw_initialize - ask FW to initialize the device
3269 * @adap: the adapter
3270 * @mbox: mailbox to use for the FW command
3272 * Issues a command to FW to partially initialize the device. This
3273 * performs initialization that generally doesn't depend on user input.
3275 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3277 struct fw_initialize_cmd c;
3279 memset(&c, 0, sizeof(c));
3280 INIT_CMD(c, INITIALIZE, WRITE);
3281 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3285 * t4_query_params_rw - query FW or device parameters
3286 * @adap: the adapter
3287 * @mbox: mailbox to use for the FW command
3290 * @nparams: the number of parameters
3291 * @params: the parameter names
3292 * @val: the parameter values
3293 * @rw: Write and read flag
3295 * Reads the value of FW or device parameters. Up to 7 parameters can be
3298 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3299 unsigned int pf, unsigned int vf,
3300 unsigned int nparams, const u32 *params,
3305 struct fw_params_cmd c;
3306 __be32 *p = &c.param[0].mnem;
3311 memset(&c, 0, sizeof(c));
3312 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3313 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3314 V_FW_PARAMS_CMD_PFN(pf) |
3315 V_FW_PARAMS_CMD_VFN(vf));
3316 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3318 for (i = 0; i < nparams; i++) {
3319 *p++ = cpu_to_be32(*params++);
3321 *p = cpu_to_be32(*(val + i));
3325 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3327 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3328 *val++ = be32_to_cpu(*p);
3332 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3333 unsigned int vf, unsigned int nparams, const u32 *params,
3336 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3340 * t4_set_params_timeout - sets FW or device parameters
3341 * @adap: the adapter
3342 * @mbox: mailbox to use for the FW command
3345 * @nparams: the number of parameters
3346 * @params: the parameter names
3347 * @val: the parameter values
3348 * @timeout: the timeout time
3350 * Sets the value of FW or device parameters. Up to 7 parameters can be
3351 * specified at once.
3353 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3354 unsigned int pf, unsigned int vf,
3355 unsigned int nparams, const u32 *params,
3356 const u32 *val, int timeout)
3358 struct fw_params_cmd c;
3359 __be32 *p = &c.param[0].mnem;
3364 memset(&c, 0, sizeof(c));
3365 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3366 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3367 V_FW_PARAMS_CMD_PFN(pf) |
3368 V_FW_PARAMS_CMD_VFN(vf));
3369 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3372 *p++ = cpu_to_be32(*params++);
3373 *p++ = cpu_to_be32(*val++);
3376 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3379 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3380 unsigned int vf, unsigned int nparams, const u32 *params,
3383 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3384 FW_CMD_MAX_TIMEOUT);
3388 * t4_alloc_vi_func - allocate a virtual interface
3389 * @adap: the adapter
3390 * @mbox: mailbox to use for the FW command
3391 * @port: physical port associated with the VI
3392 * @pf: the PF owning the VI
3393 * @vf: the VF owning the VI
3394 * @nmac: number of MAC addresses needed (1 to 5)
3395 * @mac: the MAC addresses of the VI
3396 * @rss_size: size of RSS table slice associated with this VI
3397 * @portfunc: which Port Application Function MAC Address is desired
3398 * @idstype: Intrusion Detection Type
3400 * Allocates a virtual interface for the given physical port. If @mac is
3401 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3402 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3403 * stored consecutively so the space needed is @nmac * 6 bytes.
3404 * Returns a negative error number or the non-negative VI id.
3406 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3407 unsigned int port, unsigned int pf, unsigned int vf,
3408 unsigned int nmac, u8 *mac, unsigned int *rss_size,
3409 unsigned int portfunc, unsigned int idstype)
3414 memset(&c, 0, sizeof(c));
3415 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3416 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3417 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3418 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3419 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3420 V_FW_VI_CMD_FUNC(portfunc));
3421 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3424 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3429 memcpy(mac, c.mac, sizeof(c.mac));
3432 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3435 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3438 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3441 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3446 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3447 return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3451 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3452 * @adap: the adapter
3453 * @mbox: mailbox to use for the FW command
3454 * @port: physical port associated with the VI
3455 * @pf: the PF owning the VI
3456 * @vf: the VF owning the VI
3457 * @nmac: number of MAC addresses needed (1 to 5)
3458 * @mac: the MAC addresses of the VI
3459 * @rss_size: size of RSS table slice associated with this VI
3461 * Backwards compatible and convieniance routine to allocate a Virtual
3462 * Interface with a Ethernet Port Application Function and Intrustion
3463 * Detection System disabled.
3465 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3466 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3467 unsigned int *rss_size)
3469 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3474 * t4_free_vi - free a virtual interface
3475 * @adap: the adapter
3476 * @mbox: mailbox to use for the FW command
3477 * @pf: the PF owning the VI
3478 * @vf: the VF owning the VI
3479 * @viid: virtual interface identifiler
3481 * Free a previously allocated virtual interface.
3483 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3484 unsigned int vf, unsigned int viid)
3488 memset(&c, 0, sizeof(c));
3489 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3490 F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
3491 V_FW_VI_CMD_VFN(vf));
3492 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
3493 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
3495 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3499 * t4_set_rxmode - set Rx properties of a virtual interface
3500 * @adap: the adapter
3501 * @mbox: mailbox to use for the FW command
3503 * @mtu: the new MTU or -1
3504 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3505 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3506 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3507 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
3509 * @sleep_ok: if true we may sleep while awaiting command completion
3511 * Sets Rx properties of a virtual interface.
3513 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3514 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3517 struct fw_vi_rxmode_cmd c;
3519 /* convert to FW values */
3521 mtu = M_FW_VI_RXMODE_CMD_MTU;
3523 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
3525 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
3527 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
3529 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
3531 memset(&c, 0, sizeof(c));
3532 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
3533 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3534 V_FW_VI_RXMODE_CMD_VIID(viid));
3535 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3536 c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
3537 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3538 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3539 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3540 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3541 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3545 * t4_change_mac - modifies the exact-match filter for a MAC address
3546 * @adap: the adapter
3547 * @mbox: mailbox to use for the FW command
3549 * @idx: index of existing filter for old value of MAC address, or -1
3550 * @addr: the new MAC address value
3551 * @persist: whether a new MAC allocation should be persistent
3552 * @add_smt: if true also add the address to the HW SMT
3554 * Modifies an exact-match filter and sets it to the new MAC address if
3555 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
3556 * latter case the address is added persistently if @persist is %true.
3558 * Note that in general it is not possible to modify the value of a given
3559 * filter so the generic way to modify an address filter is to free the one
3560 * being used by the old address value and allocate a new filter for the
3561 * new address value.
3563 * Returns a negative error number or the index of the filter with the new
3564 * MAC value. Note that this index may differ from @idx.
3566 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3567 int idx, const u8 *addr, bool persist, bool add_smt)
3570 struct fw_vi_mac_cmd c;
3571 struct fw_vi_mac_exact *p = c.u.exact;
3572 int max_mac_addr = adap->params.arch.mps_tcam_size;
3574 if (idx < 0) /* new allocation */
3575 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3576 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3578 memset(&c, 0, sizeof(c));
3579 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3580 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3581 V_FW_VI_MAC_CMD_VIID(viid));
3582 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3583 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3584 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3585 V_FW_VI_MAC_CMD_IDX(idx));
3586 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3588 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3590 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3591 if (ret >= max_mac_addr)
3598 * t4_enable_vi_params - enable/disable a virtual interface
3599 * @adap: the adapter
3600 * @mbox: mailbox to use for the FW command
3602 * @rx_en: 1=enable Rx, 0=disable Rx
3603 * @tx_en: 1=enable Tx, 0=disable Tx
3604 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3606 * Enables/disables a virtual interface. Note that setting DCB Enable
3607 * only makes sense when enabling a Virtual Interface ...
3609 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3610 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3612 struct fw_vi_enable_cmd c;
3614 memset(&c, 0, sizeof(c));
3615 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3616 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3617 V_FW_VI_ENABLE_CMD_VIID(viid));
3618 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3619 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3620 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3622 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3626 * t4_enable_vi - enable/disable a virtual interface
3627 * @adap: the adapter
3628 * @mbox: mailbox to use for the FW command
3630 * @rx_en: 1=enable Rx, 0=disable Rx
3631 * @tx_en: 1=enable Tx, 0=disable Tx
3633 * Enables/disables a virtual interface. Note that setting DCB Enable
3634 * only makes sense when enabling a Virtual Interface ...
3636 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3637 bool rx_en, bool tx_en)
3639 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3643 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3644 * @adap: the adapter
3645 * @mbox: mailbox to use for the FW command
3646 * @start: %true to enable the queues, %false to disable them
3647 * @pf: the PF owning the queues
3648 * @vf: the VF owning the queues
3649 * @iqid: ingress queue id
3650 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3651 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3653 * Starts or stops an ingress queue and its associated FLs, if any.
3655 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3656 unsigned int pf, unsigned int vf, unsigned int iqid,
3657 unsigned int fl0id, unsigned int fl1id)
3661 memset(&c, 0, sizeof(c));
3662 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3663 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3664 V_FW_IQ_CMD_VFN(vf));
3665 c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
3666 V_FW_IQ_CMD_IQSTOP(!start) |
3668 c.iqid = cpu_to_be16(iqid);
3669 c.fl0id = cpu_to_be16(fl0id);
3670 c.fl1id = cpu_to_be16(fl1id);
3671 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3675 * t4_iq_free - free an ingress queue and its FLs
3676 * @adap: the adapter
3677 * @mbox: mailbox to use for the FW command
3678 * @pf: the PF owning the queues
3679 * @vf: the VF owning the queues
3680 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
3681 * @iqid: ingress queue id
3682 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3683 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3685 * Frees an ingress queue and its associated FLs, if any.
3687 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3688 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3689 unsigned int fl0id, unsigned int fl1id)
3693 memset(&c, 0, sizeof(c));
3694 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3695 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3696 V_FW_IQ_CMD_VFN(vf));
3697 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
3698 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
3699 c.iqid = cpu_to_be16(iqid);
3700 c.fl0id = cpu_to_be16(fl0id);
3701 c.fl1id = cpu_to_be16(fl1id);
3702 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3706 * t4_eth_eq_free - free an Ethernet egress queue
3707 * @adap: the adapter
3708 * @mbox: mailbox to use for the FW command
3709 * @pf: the PF owning the queue
3710 * @vf: the VF owning the queue
3711 * @eqid: egress queue id
3713 * Frees an Ethernet egress queue.
3715 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3716 unsigned int vf, unsigned int eqid)
3718 struct fw_eq_eth_cmd c;
3720 memset(&c, 0, sizeof(c));
3721 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
3722 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3723 V_FW_EQ_ETH_CMD_PFN(pf) |
3724 V_FW_EQ_ETH_CMD_VFN(vf));
3725 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3726 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
3727 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3731 * t4_handle_fw_rpl - process a FW reply message
3732 * @adap: the adapter
3733 * @rpl: start of the FW message
3735 * Processes a FW message, such as link state change messages.
3737 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3739 u8 opcode = *(const u8 *)rpl;
3742 * This might be a port command ... this simplifies the following
3743 * conditionals ... We can get away with pre-dereferencing
3744 * action_to_len16 because it's in the first 16 bytes and all messages
3745 * will be at least that long.
3747 const struct fw_port_cmd *p = (const void *)rpl;
3748 unsigned int action =
3749 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
3751 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
3752 /* link/module state change message */
3753 unsigned int speed = 0, fc = 0, i;
3754 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
3755 struct port_info *pi = NULL;
3756 struct link_config *lc;
3757 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
3758 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
3759 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
3761 if (stat & F_FW_PORT_CMD_RXPAUSE)
3763 if (stat & F_FW_PORT_CMD_TXPAUSE)
3765 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3766 speed = ETH_SPEED_NUM_100M;
3767 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3768 speed = ETH_SPEED_NUM_1G;
3769 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3770 speed = ETH_SPEED_NUM_10G;
3771 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
3772 speed = ETH_SPEED_NUM_25G;
3773 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
3774 speed = ETH_SPEED_NUM_40G;
3775 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
3776 speed = ETH_SPEED_NUM_100G;
3778 for_each_port(adap, i) {
3779 pi = adap2pinfo(adap, i);
3780 if (pi->tx_chan == chan)
3785 if (mod != pi->mod_type) {
3787 t4_os_portmod_changed(adap, i);
3789 if (link_ok != lc->link_ok || speed != lc->speed ||
3790 fc != lc->fc) { /* something changed */
3791 if (!link_ok && lc->link_ok) {
3792 static const char * const reason[] = {
3795 "Auto-negotiation Failure",
3797 "Insufficient Airflow",
3798 "Unable To Determine Reason",
3799 "No RX Signal Detected",
3802 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
3804 dev_warn(adap, "Port %d link down, reason: %s\n",
3807 lc->link_ok = link_ok;
3810 lc->supported = be16_to_cpu(p->u.info.pcap);
3813 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
3819 void t4_reset_link_config(struct adapter *adap, int idx)
3821 struct port_info *pi = adap2pinfo(adap, idx);
3822 struct link_config *lc = &pi->link_cfg;
3825 lc->requested_speed = 0;
3826 lc->requested_fc = 0;
3832 * init_link_config - initialize a link's SW state
3833 * @lc: structure holding the link state
3834 * @caps: link capabilities
3836 * Initializes the SW state maintained for each link, including the link's
3837 * capabilities and default speed/flow-control/autonegotiation settings.
3839 static void init_link_config(struct link_config *lc,
3842 lc->supported = caps;
3843 lc->requested_speed = 0;
3845 lc->requested_fc = 0;
3847 if (lc->supported & FW_PORT_CAP_ANEG) {
3848 lc->advertising = lc->supported & ADVERT_MASK;
3849 lc->autoneg = AUTONEG_ENABLE;
3851 lc->advertising = 0;
3852 lc->autoneg = AUTONEG_DISABLE;
3857 * t4_wait_dev_ready - wait till to reads of registers work
3859 * Right after the device is RESET is can take a small amount of time
3860 * for it to respond to register reads. Until then, all reads will
3861 * return either 0xff...ff or 0xee...ee. Return an error if reads
3862 * don't work within a reasonable time frame.
3864 static int t4_wait_dev_ready(struct adapter *adapter)
3868 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3870 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
3874 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3875 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
3878 dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
3884 u32 vendor_and_model_id;
3888 int t4_get_flash_params(struct adapter *adapter)
3891 * Table for non-Numonix supported flash parts. Numonix parts are left
3892 * to the preexisting well-tested code. All flash parts have 64KB
3895 static struct flash_desc supported_flash[] = {
3896 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
3901 unsigned int part, manufacturer;
3902 unsigned int density, size;
3905 * Issue a Read ID Command to the Flash part. We decode supported
3906 * Flash parts and their sizes from this. There's a newer Query
3907 * Command which can retrieve detailed geometry information but
3908 * many Flash parts don't support it.
3910 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
3912 ret = sf1_read(adapter, 3, 0, 1, &flashid);
3913 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3917 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
3918 if (supported_flash[part].vendor_and_model_id == flashid) {
3919 adapter->params.sf_size =
3920 supported_flash[part].size_mb;
3921 adapter->params.sf_nsec =
3922 adapter->params.sf_size / SF_SEC_SIZE;
3927 manufacturer = flashid & 0xff;
3928 switch (manufacturer) {
3929 case 0x20: { /* Micron/Numonix */
3931 * This Density -> Size decoding table is taken from Micron
3934 density = (flashid >> 16) & 0xff;
3937 size = 1 << 20; /* 1MB */
3940 size = 1 << 21; /* 2MB */
3943 size = 1 << 22; /* 4MB */
3946 size = 1 << 23; /* 8MB */
3949 size = 1 << 24; /* 16MB */
3952 size = 1 << 25; /* 32MB */
3955 size = 1 << 26; /* 64MB */
3958 size = 1 << 27; /* 128MB */
3961 size = 1 << 28; /* 256MB */
3964 dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
3969 adapter->params.sf_size = size;
3970 adapter->params.sf_nsec = size / SF_SEC_SIZE;
3974 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
3980 * We should reject adapters with FLASHes which are too small. So, emit
3983 if (adapter->params.sf_size < FLASH_MIN_SIZE)
3984 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
3985 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
3990 static void set_pcie_completion_timeout(struct adapter *adapter,
3996 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
3998 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4001 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4006 * t4_get_chip_type - Determine chip type from device ID
4007 * @adap: the adapter
4008 * @ver: adapter version
4010 int t4_get_chip_type(struct adapter *adap, int ver)
4012 enum chip_type chip = 0;
4013 u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4015 /* Retrieve adapter's device ID */
4018 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4021 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4024 dev_err(adap, "Device %d is not supported\n",
4025 adap->params.pci.device_id);
4033 * t4_prep_adapter - prepare SW and HW for operation
4034 * @adapter: the adapter
4036 * Initialize adapter SW state for the various HW modules, set initial
4037 * values for some adapter tunables, take PHYs out of reset, and
4038 * initialize the MDIO interface.
4040 int t4_prep_adapter(struct adapter *adapter)
4045 ret = t4_wait_dev_ready(adapter);
4049 pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4050 adapter->params.pci.device_id = adapter->pdev->id.device_id;
4051 adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4054 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4055 * ADAPTER (VERSION << 4 | REVISION)
4057 ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4058 adapter->params.chip = 0;
4061 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4062 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4063 adapter->params.arch.mps_tcam_size =
4064 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4065 adapter->params.arch.mps_rplc_size = 128;
4066 adapter->params.arch.nchan = NCHAN;
4067 adapter->params.arch.vfcount = 128;
4070 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4071 adapter->params.arch.sge_fl_db = 0;
4072 adapter->params.arch.mps_tcam_size =
4073 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4074 adapter->params.arch.mps_rplc_size = 256;
4075 adapter->params.arch.nchan = 2;
4076 adapter->params.arch.vfcount = 256;
4079 dev_err(adapter, "%s: Device %d is not supported\n",
4080 __func__, adapter->params.pci.device_id);
4084 adapter->params.pci.vpd_cap_addr =
4085 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4087 ret = t4_get_flash_params(adapter);
4089 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4094 adapter->params.cim_la_size = CIMLA_SIZE;
4096 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4099 * Default port and clock for debugging in case we can't reach FW.
4101 adapter->params.nports = 1;
4102 adapter->params.portvec = 1;
4103 adapter->params.vpd.cclk = 50000;
4105 /* Set pci completion timeout value to 4 seconds. */
4106 set_pcie_completion_timeout(adapter, 0xd);
4111 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4112 * @adapter: the adapter
4113 * @qid: the Queue ID
4114 * @qtype: the Ingress or Egress type for @qid
4115 * @pbar2_qoffset: BAR2 Queue Offset
4116 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4118 * Returns the BAR2 SGE Queue Registers information associated with the
4119 * indicated Absolute Queue ID. These are passed back in return value
4120 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4121 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4123 * This may return an error which indicates that BAR2 SGE Queue
4124 * registers aren't available. If an error is not returned, then the
4125 * following values are returned:
4127 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4128 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4130 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4131 * require the "Inferred Queue ID" ability may be used. E.g. the
4132 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4133 * then these "Inferred Queue ID" register may not be used.
4135 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4136 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4137 unsigned int *pbar2_qid)
4139 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4140 u64 bar2_page_offset, bar2_qoffset;
4141 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4144 * T4 doesn't support BAR2 SGE Queue registers.
4146 if (is_t4(adapter->params.chip))
4150 * Get our SGE Page Size parameters.
4152 page_shift = adapter->params.sge.hps + 10;
4153 page_size = 1 << page_shift;
4156 * Get the right Queues per Page parameters for our Queue.
4158 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4159 adapter->params.sge.eq_qpp :
4160 adapter->params.sge.iq_qpp);
4161 qpp_mask = (1 << qpp_shift) - 1;
4164 * Calculate the basics of the BAR2 SGE Queue register area:
4165 * o The BAR2 page the Queue registers will be in.
4166 * o The BAR2 Queue ID.
4167 * o The BAR2 Queue ID Offset into the BAR2 page.
4169 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4170 bar2_qid = qid & qpp_mask;
4171 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4174 * If the BAR2 Queue ID Offset is less than the Page Size, then the
4175 * hardware will infer the Absolute Queue ID simply from the writes to
4176 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4177 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
4178 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4179 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4180 * from the BAR2 Page and BAR2 Queue ID.
4182 * One important censequence of this is that some BAR2 SGE registers
4183 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4184 * there. But other registers synthesize the SGE Queue ID purely
4185 * from the writes to the registers -- the Write Combined Doorbell
4186 * Buffer is a good example. These BAR2 SGE Registers are only
4187 * available for those BAR2 SGE Register areas where the SGE Absolute
4188 * Queue ID can be inferred from simple writes.
4190 bar2_qoffset = bar2_page_offset;
4191 bar2_qinferred = (bar2_qid_offset < page_size);
4192 if (bar2_qinferred) {
4193 bar2_qoffset += bar2_qid_offset;
4197 *pbar2_qoffset = bar2_qoffset;
4198 *pbar2_qid = bar2_qid;
4203 * t4_init_sge_params - initialize adap->params.sge
4204 * @adapter: the adapter
4206 * Initialize various fields of the adapter's SGE Parameters structure.
4208 int t4_init_sge_params(struct adapter *adapter)
4210 struct sge_params *sge_params = &adapter->params.sge;
4212 unsigned int s_hps, s_qpp;
4215 * Extract the SGE Page Size for our PF.
4217 hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4218 s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4220 sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4223 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4225 s_qpp = (S_QUEUESPERPAGEPF0 +
4226 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4227 qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4228 sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4229 qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4230 sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4236 * t4_init_tp_params - initialize adap->params.tp
4237 * @adap: the adapter
4239 * Initialize various fields of the adapter's TP Parameters structure.
4241 int t4_init_tp_params(struct adapter *adap)
4246 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4247 adap->params.tp.tre = G_TIMERRESOLUTION(v);
4248 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4250 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4251 for (chan = 0; chan < NCHAN; chan++)
4252 adap->params.tp.tx_modq[chan] = chan;
4255 * Cache the adapter's Compressed Filter Mode and global Incress
4258 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4259 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4260 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4261 &adap->params.tp.ingress_config, 1,
4262 A_TP_INGRESS_CONFIG);
4265 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4266 * shift positions of several elements of the Compressed Filter Tuple
4267 * for this adapter which we need frequently ...
4269 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4270 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4271 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4272 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4276 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4277 * represents the presense of an Outer VLAN instead of a VNIC ID.
4279 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4280 adap->params.tp.vnic_shift = -1;
4286 * t4_filter_field_shift - calculate filter field shift
4287 * @adap: the adapter
4288 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4290 * Return the shift position of a filter field within the Compressed
4291 * Filter Tuple. The filter field is specified via its selection bit
4292 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
4294 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4296 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4300 if ((filter_mode & filter_sel) == 0)
4303 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4304 switch (filter_mode & sel) {
4306 field_shift += W_FT_FCOE;
4309 field_shift += W_FT_PORT;
4312 field_shift += W_FT_VNIC_ID;
4315 field_shift += W_FT_VLAN;
4318 field_shift += W_FT_TOS;
4321 field_shift += W_FT_PROTOCOL;
4324 field_shift += W_FT_ETHERTYPE;
4327 field_shift += W_FT_MACMATCH;
4330 field_shift += W_FT_MPSHITTYPE;
4332 case F_FRAGMENTATION:
4333 field_shift += W_FT_FRAGMENTATION;
4340 int t4_init_rss_mode(struct adapter *adap, int mbox)
4343 struct fw_rss_vi_config_cmd rvc;
4345 memset(&rvc, 0, sizeof(rvc));
4347 for_each_port(adap, i) {
4348 struct port_info *p = adap2pinfo(adap, i);
4350 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4351 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4352 V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4353 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4354 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4357 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4362 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4366 struct fw_port_cmd c;
4368 memset(&c, 0, sizeof(c));
4370 for_each_port(adap, i) {
4371 unsigned int rss_size = 0;
4372 struct port_info *p = adap2pinfo(adap, i);
4374 while ((adap->params.portvec & (1 << j)) == 0)
4377 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4378 F_FW_CMD_REQUEST | F_FW_CMD_READ |
4379 V_FW_PORT_CMD_PORTID(j));
4380 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4381 FW_PORT_ACTION_GET_PORT_INFO) |
4383 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4387 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4393 p->rss_size = rss_size;
4394 t4_os_set_hw_addr(adap, i, addr);
4396 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
4397 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
4398 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
4399 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
4400 p->mod_type = FW_PORT_MOD_TYPE_NA;
4402 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));