1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
10 CPL_ACT_OPEN_REQ = 0x3,
11 CPL_SET_TCB_FIELD = 0x5,
14 CPL_L2T_WRITE_REQ = 0x12,
15 CPL_TID_RELEASE = 0x1A,
16 CPL_L2T_WRITE_RPL = 0x23,
17 CPL_ACT_OPEN_RPL = 0x25,
18 CPL_ABORT_RPL_RSS = 0x2D,
19 CPL_SET_TCB_RPL = 0x3A,
20 CPL_ACT_OPEN_REQ6 = 0x83,
21 CPL_SGE_EGR_UPDATE = 0xA5,
24 CPL_TX_PKT_LSO = 0xED,
30 CPL_ERR_TCAM_FULL = 3,
38 CPL_ABORT_SEND_RST = 0,
42 enum { /* TX_PKT_XT checksum types */
53 #define S_CPL_OPCODE 24
54 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
56 #define G_TID(x) ((x) & 0xFFFFFF)
58 /* tid is assumed to be 24-bits */
59 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid))
61 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
63 /* extract the TID from a CPL command */
64 #define GET_TID(cmd) (G_TID(be32_to_cpu(OPCODE_TID(cmd))))
66 /* partitioning of TID fields that also carry a queue id */
68 #define M_TID_TID 0x3fff
69 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID)
72 #define V_TID_QID(x) ((x) << S_TID_QID)
76 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
95 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)
96 #define RSS_HDR struct rss_header rss_hdr
102 struct work_request_hdr {
108 #define WR_HDR struct work_request_hdr wr
109 #define WR_HDR_SIZE sizeof(struct work_request_hdr)
112 #define WR_HDR_SIZE 0
117 #define V_COOKIE(x) ((x) << S_COOKIE)
118 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE)
120 /* option 0 fields */
122 #define V_TX_CHAN(x) ((x) << S_TX_CHAN)
125 #define V_DELACK(x) ((x) << S_DELACK)
127 #define S_NON_OFFLOAD 7
128 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
129 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U)
132 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
134 #define S_SMAC_SEL 28
135 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
137 #define S_TCAM_BYPASS 48
138 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
139 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL)
142 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX)
145 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE)
147 /* option 2 fields */
148 #define S_RSS_QUEUE 0
149 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
151 #define S_RSS_QUEUE_VALID 10
152 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
153 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U)
155 #define S_CONG_CNTRL 14
156 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
158 #define S_RX_CHANNEL 26
159 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
160 #define F_RX_CHANNEL V_RX_CHANNEL(1U)
162 #define S_CCTRL_ECN 27
163 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN)
165 #define S_T5_OPT_2_VALID 31
166 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID)
167 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U)
169 struct cpl_t6_act_open_req {
184 struct cpl_t6_act_open_req6 {
201 #define S_FILTER_TUPLE 24
202 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
204 struct cpl_act_open_rpl {
210 /* cpl_act_open_rpl.atid_status fields */
211 #define S_AOPEN_STATUS 0
212 #define M_AOPEN_STATUS 0xFF
213 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS)
215 #define S_AOPEN_ATID 8
216 #define M_AOPEN_ATID 0xFFFFFF
217 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID)
219 struct cpl_set_tcb_field {
228 /* cpl_set_tcb_field.word_cookie fields */
230 #define V_WORD(x) ((x) << S_WORD)
232 /* cpl_get_tcb.reply_ctrl fields */
234 #define V_QUEUENO(x) ((x) << S_QUEUENO)
236 #define S_REPLY_CHAN 14
237 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
239 #define S_NO_REPLY 15
240 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
242 struct cpl_set_tcb_rpl {
251 /* cpl_abort_req status command code
253 struct cpl_abort_req {
262 struct cpl_abort_rpl_rss {
269 struct cpl_abort_rpl {
278 struct cpl_tid_release {
291 struct cpl_tx_pkt_core {
300 struct cpl_tx_pkt_core c;
303 /* cpl_tx_pkt_core.ctrl0 fields */
305 #define M_TXPKT_PF 0x7
306 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
307 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
309 #define S_TXPKT_INTF 16
310 #define M_TXPKT_INTF 0xF
311 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
312 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
314 #define S_TXPKT_OPCODE 24
315 #define M_TXPKT_OPCODE 0xFF
316 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
317 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
319 /* cpl_tx_pkt_core.ctrl1 fields */
320 #define S_TXPKT_IPHDR_LEN 20
321 #define M_TXPKT_IPHDR_LEN 0x3FFF
322 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
323 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
325 #define S_TXPKT_ETHHDR_LEN 34
326 #define M_TXPKT_ETHHDR_LEN 0x3F
327 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
328 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
330 #define S_T6_TXPKT_ETHHDR_LEN 32
331 #define M_T6_TXPKT_ETHHDR_LEN 0xFF
332 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
333 #define G_T6_TXPKT_ETHHDR_LEN(x) \
334 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
336 #define S_TXPKT_CSUM_TYPE 40
337 #define M_TXPKT_CSUM_TYPE 0xF
338 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
339 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
341 #define S_TXPKT_VLAN 44
342 #define M_TXPKT_VLAN 0xFFFF
343 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
344 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
346 #define S_TXPKT_VLAN_VLD 60
347 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
348 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
350 #define S_TXPKT_IPCSUM_DIS 62
351 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
352 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
354 #define S_TXPKT_L4CSUM_DIS 63
355 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
356 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
358 struct cpl_tx_pkt_lso_core {
364 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
367 struct cpl_tx_pkt_lso {
369 struct cpl_tx_pkt_lso_core c;
370 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
373 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
374 #define S_LSO_TCPHDR_LEN 0
375 #define M_LSO_TCPHDR_LEN 0xF
376 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
377 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
379 #define S_LSO_IPHDR_LEN 4
380 #define M_LSO_IPHDR_LEN 0xFFF
381 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
382 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
384 #define S_LSO_ETHHDR_LEN 16
385 #define M_LSO_ETHHDR_LEN 0xF
386 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
387 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
389 #define S_LSO_IPV6 20
390 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
391 #define F_LSO_IPV6 V_LSO_IPV6(1U)
393 #define S_LSO_LAST_SLICE 22
394 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
395 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
397 #define S_LSO_FIRST_SLICE 23
398 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
399 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
401 #define S_LSO_OPCODE 24
402 #define M_LSO_OPCODE 0xFF
403 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
404 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
406 #define S_LSO_T5_XFER_SIZE 0
407 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF
408 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
409 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
414 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
435 struct cpl_l2t_write_req {
444 /* cpl_l2t_write_req.params fields */
445 #define S_L2T_W_PORT 8
446 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
448 #define S_L2T_W_LPBK 10
449 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK)
451 #define S_L2T_W_ARPMISS 11
452 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS)
454 #define S_L2T_W_NOREPLY 15
455 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
457 struct cpl_l2t_write_rpl {
464 /* rx_pkt.l2info fields */
466 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
467 #define F_RXF_UDP V_RXF_UDP(1U)
470 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
471 #define F_RXF_TCP V_RXF_TCP(1U)
474 #define V_RXF_IP(x) ((x) << S_RXF_IP)
475 #define F_RXF_IP V_RXF_IP(1U)
478 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
479 #define F_RXF_IP6 V_RXF_IP6(1U)
481 /* rx_pkt.err_vec fields */
482 /* In T6, rx_pkt.err_vec indicates
483 * RxError Error vector (16b) or
484 * Encapsulating header length (8b),
485 * Outer encapsulation type (2b) and
486 * compressed error vector (6b) if CRxPktEnc is
487 * enabled in TP_OUT_CONFIG
489 #define S_T6_COMPR_RXERR_VEC 0
490 #define M_T6_COMPR_RXERR_VEC 0x3F
491 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
492 #define G_T6_COMPR_RXERR_VEC(x) \
493 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
495 /* cpl_fw*.type values */
524 ULP_TX_SC_NOOP = 0x80,
525 ULP_TX_SC_IMM = 0x81,
526 ULP_TX_SC_DSGL = 0x82,
527 ULP_TX_SC_ISGL = 0x83
530 #define S_ULPTX_CMD 24
531 #define M_ULPTX_CMD 0xFF
532 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
534 #define S_ULP_TX_SC_MORE 23
535 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
536 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
538 struct ulptx_sge_pair {
548 #if !(defined C99_NOT_SUPPORTED)
549 struct ulptx_sge_pair sge[0];
559 #define S_ULPTX_NSGE 0
560 #define M_ULPTX_NSGE 0xFFFF
561 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
568 /* ulp_txpkt.cmd_dest fields */
569 #define S_ULP_TXPKT_DEST 16
570 #define M_ULP_TXPKT_DEST 0x3
571 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
573 #define S_ULP_TXPKT_FID 4
574 #define M_ULP_TXPKT_FID 0x7ff
575 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
577 #define S_ULP_TXPKT_RO 3
578 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
579 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
581 #endif /* T4_MSG_H */