1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
10 CPL_ACT_OPEN_REQ = 0x3,
11 CPL_ACT_OPEN_RPL = 0x25,
12 CPL_SET_TCB_RPL = 0x3A,
13 CPL_ACT_OPEN_REQ6 = 0x83,
14 CPL_SGE_EGR_UPDATE = 0xA5,
17 CPL_TX_PKT_LSO = 0xED,
23 CPL_ERR_TCAM_FULL = 3,
30 enum { /* TX_PKT_XT checksum types */
41 #define S_CPL_OPCODE 24
42 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
44 #define G_TID(x) ((x) & 0xFFFFFF)
46 /* tid is assumed to be 24-bits */
47 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid))
49 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
51 /* extract the TID from a CPL command */
52 #define GET_TID(cmd) (G_TID(be32_to_cpu(OPCODE_TID(cmd))))
54 /* partitioning of TID fields that also carry a queue id */
56 #define M_TID_TID 0x3fff
57 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID)
61 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
80 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)
81 #define RSS_HDR struct rss_header rss_hdr
87 struct work_request_hdr {
93 #define WR_HDR struct work_request_hdr wr
94 #define WR_HDR_SIZE sizeof(struct work_request_hdr)
102 #define V_COOKIE(x) ((x) << S_COOKIE)
103 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE)
105 /* option 0 fields */
107 #define V_DELACK(x) ((x) << S_DELACK)
109 #define S_NON_OFFLOAD 7
110 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
111 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U)
114 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
116 #define S_SMAC_SEL 28
117 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
119 #define S_TCAM_BYPASS 48
120 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
121 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL)
123 /* option 2 fields */
124 #define S_RSS_QUEUE 0
125 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
127 #define S_RSS_QUEUE_VALID 10
128 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
129 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U)
131 #define S_CONG_CNTRL 14
132 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
134 #define S_RX_CHANNEL 26
135 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
136 #define F_RX_CHANNEL V_RX_CHANNEL(1U)
138 #define S_T5_OPT_2_VALID 31
139 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID)
140 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U)
142 struct cpl_t6_act_open_req {
157 struct cpl_t6_act_open_req6 {
174 #define S_FILTER_TUPLE 24
175 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
177 struct cpl_act_open_rpl {
183 /* cpl_act_open_rpl.atid_status fields */
184 #define S_AOPEN_STATUS 0
185 #define M_AOPEN_STATUS 0xFF
186 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS)
188 #define S_AOPEN_ATID 8
189 #define M_AOPEN_ATID 0xFFFFFF
190 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID)
192 struct cpl_set_tcb_rpl {
208 struct cpl_tx_pkt_core {
217 struct cpl_tx_pkt_core c;
220 /* cpl_tx_pkt_core.ctrl0 fields */
222 #define M_TXPKT_PF 0x7
223 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
224 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
226 #define S_TXPKT_INTF 16
227 #define M_TXPKT_INTF 0xF
228 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
229 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
231 #define S_TXPKT_OPCODE 24
232 #define M_TXPKT_OPCODE 0xFF
233 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
234 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
236 /* cpl_tx_pkt_core.ctrl1 fields */
237 #define S_TXPKT_IPHDR_LEN 20
238 #define M_TXPKT_IPHDR_LEN 0x3FFF
239 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
240 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
242 #define S_TXPKT_ETHHDR_LEN 34
243 #define M_TXPKT_ETHHDR_LEN 0x3F
244 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
245 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
247 #define S_T6_TXPKT_ETHHDR_LEN 32
248 #define M_T6_TXPKT_ETHHDR_LEN 0xFF
249 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
250 #define G_T6_TXPKT_ETHHDR_LEN(x) \
251 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
253 #define S_TXPKT_CSUM_TYPE 40
254 #define M_TXPKT_CSUM_TYPE 0xF
255 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
256 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
258 #define S_TXPKT_VLAN 44
259 #define M_TXPKT_VLAN 0xFFFF
260 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
261 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
263 #define S_TXPKT_VLAN_VLD 60
264 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
265 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
267 #define S_TXPKT_IPCSUM_DIS 62
268 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
269 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
271 #define S_TXPKT_L4CSUM_DIS 63
272 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
273 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
275 struct cpl_tx_pkt_lso_core {
281 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
284 struct cpl_tx_pkt_lso {
286 struct cpl_tx_pkt_lso_core c;
287 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
290 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
291 #define S_LSO_TCPHDR_LEN 0
292 #define M_LSO_TCPHDR_LEN 0xF
293 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
294 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
296 #define S_LSO_IPHDR_LEN 4
297 #define M_LSO_IPHDR_LEN 0xFFF
298 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
299 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
301 #define S_LSO_ETHHDR_LEN 16
302 #define M_LSO_ETHHDR_LEN 0xF
303 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
304 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
306 #define S_LSO_IPV6 20
307 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
308 #define F_LSO_IPV6 V_LSO_IPV6(1U)
310 #define S_LSO_LAST_SLICE 22
311 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
312 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
314 #define S_LSO_FIRST_SLICE 23
315 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
316 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
318 #define S_LSO_OPCODE 24
319 #define M_LSO_OPCODE 0xFF
320 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
321 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
323 #define S_LSO_T5_XFER_SIZE 0
324 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF
325 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
326 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
331 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
352 /* rx_pkt.l2info fields */
354 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
355 #define F_RXF_UDP V_RXF_UDP(1U)
358 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
359 #define F_RXF_TCP V_RXF_TCP(1U)
362 #define V_RXF_IP(x) ((x) << S_RXF_IP)
363 #define F_RXF_IP V_RXF_IP(1U)
366 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
367 #define F_RXF_IP6 V_RXF_IP6(1U)
369 /* rx_pkt.err_vec fields */
370 /* In T6, rx_pkt.err_vec indicates
371 * RxError Error vector (16b) or
372 * Encapsulating header length (8b),
373 * Outer encapsulation type (2b) and
374 * compressed error vector (6b) if CRxPktEnc is
375 * enabled in TP_OUT_CONFIG
377 #define S_T6_COMPR_RXERR_VEC 0
378 #define M_T6_COMPR_RXERR_VEC 0x3F
379 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
380 #define G_T6_COMPR_RXERR_VEC(x) \
381 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
383 /* cpl_fw*.type values */
407 ULP_TX_SC_IMM = 0x81,
408 ULP_TX_SC_DSGL = 0x82,
409 ULP_TX_SC_ISGL = 0x83
412 #define S_ULPTX_CMD 24
413 #define M_ULPTX_CMD 0xFF
414 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
416 #define S_ULP_TX_SC_MORE 23
417 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
418 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
420 struct ulptx_sge_pair {
430 #if !(defined C99_NOT_SUPPORTED)
431 struct ulptx_sge_pair sge[0];
441 #define S_ULPTX_NSGE 0
442 #define M_ULPTX_NSGE 0xFFFF
443 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
450 /* ulp_txpkt.cmd_dest fields */
451 #define S_ULP_TXPKT_DEST 16
452 #define M_ULP_TXPKT_DEST 0x3
453 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
455 #define S_ULP_TXPKT_FID 4
456 #define M_ULP_TXPKT_FID 0x7ff
457 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
459 #define S_ULP_TXPKT_RO 3
460 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
461 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
463 #endif /* T4_MSG_H */