1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
10 CPL_ACT_OPEN_REQ = 0x3,
11 CPL_SET_TCB_FIELD = 0x5,
14 CPL_TID_RELEASE = 0x1A,
15 CPL_ACT_OPEN_RPL = 0x25,
16 CPL_ABORT_RPL_RSS = 0x2D,
17 CPL_SET_TCB_RPL = 0x3A,
18 CPL_ACT_OPEN_REQ6 = 0x83,
19 CPL_SGE_EGR_UPDATE = 0xA5,
22 CPL_TX_PKT_LSO = 0xED,
28 CPL_ERR_TCAM_FULL = 3,
36 CPL_ABORT_SEND_RST = 0,
40 enum { /* TX_PKT_XT checksum types */
51 #define S_CPL_OPCODE 24
52 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
54 #define G_TID(x) ((x) & 0xFFFFFF)
56 /* tid is assumed to be 24-bits */
57 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid))
59 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
61 /* extract the TID from a CPL command */
62 #define GET_TID(cmd) (G_TID(be32_to_cpu(OPCODE_TID(cmd))))
64 /* partitioning of TID fields that also carry a queue id */
66 #define M_TID_TID 0x3fff
67 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID)
71 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
90 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)
91 #define RSS_HDR struct rss_header rss_hdr
97 struct work_request_hdr {
103 #define WR_HDR struct work_request_hdr wr
104 #define WR_HDR_SIZE sizeof(struct work_request_hdr)
107 #define WR_HDR_SIZE 0
112 #define V_COOKIE(x) ((x) << S_COOKIE)
113 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE)
115 /* option 0 fields */
117 #define V_TX_CHAN(x) ((x) << S_TX_CHAN)
120 #define V_DELACK(x) ((x) << S_DELACK)
122 #define S_NON_OFFLOAD 7
123 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
124 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U)
127 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
129 #define S_SMAC_SEL 28
130 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
132 #define S_TCAM_BYPASS 48
133 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
134 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL)
136 /* option 2 fields */
137 #define S_RSS_QUEUE 0
138 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
140 #define S_RSS_QUEUE_VALID 10
141 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
142 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U)
144 #define S_CONG_CNTRL 14
145 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
147 #define S_RX_CHANNEL 26
148 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
149 #define F_RX_CHANNEL V_RX_CHANNEL(1U)
151 #define S_CCTRL_ECN 27
152 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN)
154 #define S_T5_OPT_2_VALID 31
155 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID)
156 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U)
158 struct cpl_t6_act_open_req {
173 struct cpl_t6_act_open_req6 {
190 #define S_FILTER_TUPLE 24
191 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
193 struct cpl_act_open_rpl {
199 /* cpl_act_open_rpl.atid_status fields */
200 #define S_AOPEN_STATUS 0
201 #define M_AOPEN_STATUS 0xFF
202 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS)
204 #define S_AOPEN_ATID 8
205 #define M_AOPEN_ATID 0xFFFFFF
206 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID)
208 struct cpl_set_tcb_field {
217 /* cpl_set_tcb_field.word_cookie fields */
219 #define V_WORD(x) ((x) << S_WORD)
221 /* cpl_get_tcb.reply_ctrl fields */
223 #define V_QUEUENO(x) ((x) << S_QUEUENO)
225 #define S_REPLY_CHAN 14
226 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
228 #define S_NO_REPLY 15
229 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
231 struct cpl_set_tcb_rpl {
240 /* cpl_abort_req status command code
242 struct cpl_abort_req {
251 struct cpl_abort_rpl_rss {
258 struct cpl_abort_rpl {
267 struct cpl_tid_release {
280 struct cpl_tx_pkt_core {
289 struct cpl_tx_pkt_core c;
292 /* cpl_tx_pkt_core.ctrl0 fields */
294 #define M_TXPKT_PF 0x7
295 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
296 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
298 #define S_TXPKT_INTF 16
299 #define M_TXPKT_INTF 0xF
300 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
301 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
303 #define S_TXPKT_OPCODE 24
304 #define M_TXPKT_OPCODE 0xFF
305 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
306 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
308 /* cpl_tx_pkt_core.ctrl1 fields */
309 #define S_TXPKT_IPHDR_LEN 20
310 #define M_TXPKT_IPHDR_LEN 0x3FFF
311 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
312 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
314 #define S_TXPKT_ETHHDR_LEN 34
315 #define M_TXPKT_ETHHDR_LEN 0x3F
316 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
317 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
319 #define S_T6_TXPKT_ETHHDR_LEN 32
320 #define M_T6_TXPKT_ETHHDR_LEN 0xFF
321 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
322 #define G_T6_TXPKT_ETHHDR_LEN(x) \
323 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
325 #define S_TXPKT_CSUM_TYPE 40
326 #define M_TXPKT_CSUM_TYPE 0xF
327 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
328 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
330 #define S_TXPKT_VLAN 44
331 #define M_TXPKT_VLAN 0xFFFF
332 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
333 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
335 #define S_TXPKT_VLAN_VLD 60
336 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
337 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
339 #define S_TXPKT_IPCSUM_DIS 62
340 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
341 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
343 #define S_TXPKT_L4CSUM_DIS 63
344 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
345 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
347 struct cpl_tx_pkt_lso_core {
353 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
356 struct cpl_tx_pkt_lso {
358 struct cpl_tx_pkt_lso_core c;
359 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
362 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
363 #define S_LSO_TCPHDR_LEN 0
364 #define M_LSO_TCPHDR_LEN 0xF
365 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
366 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
368 #define S_LSO_IPHDR_LEN 4
369 #define M_LSO_IPHDR_LEN 0xFFF
370 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
371 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
373 #define S_LSO_ETHHDR_LEN 16
374 #define M_LSO_ETHHDR_LEN 0xF
375 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
376 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
378 #define S_LSO_IPV6 20
379 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
380 #define F_LSO_IPV6 V_LSO_IPV6(1U)
382 #define S_LSO_LAST_SLICE 22
383 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
384 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
386 #define S_LSO_FIRST_SLICE 23
387 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
388 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
390 #define S_LSO_OPCODE 24
391 #define M_LSO_OPCODE 0xFF
392 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
393 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
395 #define S_LSO_T5_XFER_SIZE 0
396 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF
397 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
398 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
403 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
424 /* rx_pkt.l2info fields */
426 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
427 #define F_RXF_UDP V_RXF_UDP(1U)
430 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
431 #define F_RXF_TCP V_RXF_TCP(1U)
434 #define V_RXF_IP(x) ((x) << S_RXF_IP)
435 #define F_RXF_IP V_RXF_IP(1U)
438 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
439 #define F_RXF_IP6 V_RXF_IP6(1U)
441 /* rx_pkt.err_vec fields */
442 /* In T6, rx_pkt.err_vec indicates
443 * RxError Error vector (16b) or
444 * Encapsulating header length (8b),
445 * Outer encapsulation type (2b) and
446 * compressed error vector (6b) if CRxPktEnc is
447 * enabled in TP_OUT_CONFIG
449 #define S_T6_COMPR_RXERR_VEC 0
450 #define M_T6_COMPR_RXERR_VEC 0x3F
451 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
452 #define G_T6_COMPR_RXERR_VEC(x) \
453 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
455 /* cpl_fw*.type values */
484 ULP_TX_SC_NOOP = 0x80,
485 ULP_TX_SC_IMM = 0x81,
486 ULP_TX_SC_DSGL = 0x82,
487 ULP_TX_SC_ISGL = 0x83
490 #define S_ULPTX_CMD 24
491 #define M_ULPTX_CMD 0xFF
492 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
494 #define S_ULP_TX_SC_MORE 23
495 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
496 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
498 struct ulptx_sge_pair {
508 #if !(defined C99_NOT_SUPPORTED)
509 struct ulptx_sge_pair sge[0];
519 #define S_ULPTX_NSGE 0
520 #define M_ULPTX_NSGE 0xFFFF
521 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
528 /* ulp_txpkt.cmd_dest fields */
529 #define S_ULP_TXPKT_DEST 16
530 #define M_ULP_TXPKT_DEST 0x3
531 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
533 #define S_ULP_TXPKT_FID 4
534 #define M_ULP_TXPKT_FID 0x7ff
535 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
537 #define S_ULP_TXPKT_RO 3
538 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
539 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
541 #endif /* T4_MSG_H */