4 * Copyright(c) 2014-2017 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #define MYPF_BASE 0x1b000
35 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
37 #define PF0_BASE 0x1e000
38 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
40 #define PF_STRIDE 0x400
41 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
42 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
44 #define MYPORT_BASE 0x1c000
45 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
47 #define PORT0_BASE 0x20000
48 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
50 #define PORT_STRIDE 0x2000
51 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
52 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
54 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
55 #define NUM_PCIE_MEM_ACCESS_INSTANCES 8
57 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
58 #define NUM_PCIE_FW_INSTANCES 8
60 #define T5_MYPORT_BASE 0x2c000
61 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
63 #define T5_PORT0_BASE 0x30000
64 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
66 #define T5_PORT_STRIDE 0x4000
67 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
68 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
70 #define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
71 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
73 #define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
74 #define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
76 /* registers for module SGE */
77 #define SGE_BASE_ADDR 0x1000
79 #define A_SGE_PF_KDOORBELL 0x0
82 #define M_QID 0x1ffffU
83 #define V_QID(x) ((x) << S_QID)
84 #define G_QID(x) (((x) >> S_QID) & M_QID)
87 #define V_DBPRIO(x) ((x) << S_DBPRIO)
88 #define F_DBPRIO V_DBPRIO(1U)
91 #define M_PIDX 0x3fffU
92 #define V_PIDX(x) ((x) << S_PIDX)
93 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
96 #define V_DBTYPE(x) ((x) << S_DBTYPE)
97 #define F_DBTYPE V_DBTYPE(1U)
100 #define M_PIDX_T5 0x1fffU
101 #define V_PIDX_T5(x) ((x) << S_PIDX_T5)
102 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
104 #define A_SGE_PF_GTS 0x4
106 #define S_INGRESSQID 16
107 #define M_INGRESSQID 0xffffU
108 #define V_INGRESSQID(x) ((x) << S_INGRESSQID)
109 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
111 #define S_SEINTARM 12
112 #define V_SEINTARM(x) ((x) << S_SEINTARM)
113 #define F_SEINTARM V_SEINTARM(1U)
116 #define M_CIDXINC 0xfffU
117 #define V_CIDXINC(x) ((x) << S_CIDXINC)
118 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
120 #define A_SGE_CONTROL 0x1008
122 #define S_RXPKTCPLMODE 18
123 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
124 #define F_RXPKTCPLMODE V_RXPKTCPLMODE(1U)
126 #define S_EGRSTATUSPAGESIZE 17
127 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
128 #define F_EGRSTATUSPAGESIZE V_EGRSTATUSPAGESIZE(1U)
130 #define S_PKTSHIFT 10
131 #define M_PKTSHIFT 0x7U
132 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
133 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
135 #define S_INGPADBOUNDARY 4
136 #define M_INGPADBOUNDARY 0x7U
137 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
138 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
140 #define A_SGE_HOST_PAGE_SIZE 0x100c
142 #define S_HOSTPAGESIZEPF7 28
143 #define M_HOSTPAGESIZEPF7 0xfU
144 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
145 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
147 #define S_HOSTPAGESIZEPF6 24
148 #define M_HOSTPAGESIZEPF6 0xfU
149 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
150 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
152 #define S_HOSTPAGESIZEPF5 20
153 #define M_HOSTPAGESIZEPF5 0xfU
154 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
155 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
157 #define S_HOSTPAGESIZEPF4 16
158 #define M_HOSTPAGESIZEPF4 0xfU
159 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
160 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
162 #define S_HOSTPAGESIZEPF3 12
163 #define M_HOSTPAGESIZEPF3 0xfU
164 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
165 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
167 #define S_HOSTPAGESIZEPF2 8
168 #define M_HOSTPAGESIZEPF2 0xfU
169 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
170 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
172 #define S_HOSTPAGESIZEPF1 4
173 #define M_HOSTPAGESIZEPF1 0xfU
174 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
175 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
177 #define S_HOSTPAGESIZEPF0 0
178 #define M_HOSTPAGESIZEPF0 0xfU
179 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
180 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
182 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
184 #define S_QUEUESPERPAGEPF1 4
185 #define M_QUEUESPERPAGEPF1 0xfU
186 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
187 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
189 #define S_QUEUESPERPAGEPF0 0
190 #define M_QUEUESPERPAGEPF0 0xfU
191 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
192 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
194 #define S_ERR_CPL_EXCEED_IQE_SIZE 22
195 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
196 #define F_ERR_CPL_EXCEED_IQE_SIZE V_ERR_CPL_EXCEED_IQE_SIZE(1U)
198 #define S_ERR_INVALID_CIDX_INC 21
199 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
200 #define F_ERR_INVALID_CIDX_INC V_ERR_INVALID_CIDX_INC(1U)
202 #define S_ERR_CPL_OPCODE_0 19
203 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
204 #define F_ERR_CPL_OPCODE_0 V_ERR_CPL_OPCODE_0(1U)
206 #define S_ERR_DROPPED_DB 18
207 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
208 #define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U)
210 #define S_ERR_DATA_CPL_ON_HIGH_QID1 17
211 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
212 #define F_ERR_DATA_CPL_ON_HIGH_QID1 V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
214 #define S_ERR_DATA_CPL_ON_HIGH_QID0 16
215 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
216 #define F_ERR_DATA_CPL_ON_HIGH_QID0 V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
218 #define S_ERR_BAD_DB_PIDX3 15
219 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
220 #define F_ERR_BAD_DB_PIDX3 V_ERR_BAD_DB_PIDX3(1U)
222 #define S_ERR_BAD_DB_PIDX2 14
223 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
224 #define F_ERR_BAD_DB_PIDX2 V_ERR_BAD_DB_PIDX2(1U)
226 #define S_ERR_BAD_DB_PIDX1 13
227 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
228 #define F_ERR_BAD_DB_PIDX1 V_ERR_BAD_DB_PIDX1(1U)
230 #define S_ERR_BAD_DB_PIDX0 12
231 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
232 #define F_ERR_BAD_DB_PIDX0 V_ERR_BAD_DB_PIDX0(1U)
234 #define S_ERR_ING_PCIE_CHAN 11
235 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
236 #define F_ERR_ING_PCIE_CHAN V_ERR_ING_PCIE_CHAN(1U)
238 #define S_ERR_ING_CTXT_PRIO 10
239 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
240 #define F_ERR_ING_CTXT_PRIO V_ERR_ING_CTXT_PRIO(1U)
242 #define S_ERR_EGR_CTXT_PRIO 9
243 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
244 #define F_ERR_EGR_CTXT_PRIO V_ERR_EGR_CTXT_PRIO(1U)
246 #define S_DBFIFO_HP_INT 8
247 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
248 #define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U)
250 #define S_DBFIFO_LP_INT 7
251 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
252 #define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U)
254 #define S_INGRESS_SIZE_ERR 5
255 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
256 #define F_INGRESS_SIZE_ERR V_INGRESS_SIZE_ERR(1U)
258 #define S_EGRESS_SIZE_ERR 4
259 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
260 #define F_EGRESS_SIZE_ERR V_EGRESS_SIZE_ERR(1U)
262 #define A_SGE_INT_ENABLE3 0x1040
264 #define A_SGE_FL_BUFFER_SIZE0 0x1044
265 #define A_SGE_FL_BUFFER_SIZE1 0x1048
266 #define A_SGE_FL_BUFFER_SIZE2 0x104c
267 #define A_SGE_FL_BUFFER_SIZE3 0x1050
269 #define A_SGE_FLM_CFG 0x1090
271 #define S_CREDITCNT 4
272 #define M_CREDITCNT 0x3U
273 #define V_CREDITCNT(x) ((x) << S_CREDITCNT)
274 #define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
276 #define S_CREDITCNTPACKING 2
277 #define M_CREDITCNTPACKING 0x3U
278 #define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
279 #define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
281 #define A_SGE_CONM_CTRL 0x1094
283 #define S_EGRTHRESHOLD 8
284 #define M_EGRTHRESHOLD 0x3fU
285 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
286 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
288 #define S_EGRTHRESHOLDPACKING 14
289 #define M_EGRTHRESHOLDPACKING 0x3fU
290 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
291 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & \
292 M_EGRTHRESHOLDPACKING)
294 #define S_INGTHRESHOLD 2
295 #define M_INGTHRESHOLD 0x3fU
296 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
297 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
299 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
301 #define S_THRESHOLD_0 24
302 #define M_THRESHOLD_0 0x3fU
303 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
304 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
306 #define S_THRESHOLD_1 16
307 #define M_THRESHOLD_1 0x3fU
308 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
309 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
311 #define S_THRESHOLD_2 8
312 #define M_THRESHOLD_2 0x3fU
313 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
314 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
316 #define S_THRESHOLD_3 0
317 #define M_THRESHOLD_3 0x3fU
318 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
319 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
321 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
323 #define S_TIMERVALUE0 16
324 #define M_TIMERVALUE0 0xffffU
325 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
326 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
328 #define S_TIMERVALUE1 0
329 #define M_TIMERVALUE1 0xffffU
330 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
331 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
333 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
335 #define S_TIMERVALUE2 16
336 #define M_TIMERVALUE2 0xffffU
337 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
338 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
340 #define S_TIMERVALUE3 0
341 #define M_TIMERVALUE3 0xffffU
342 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
343 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
345 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
347 #define S_TIMERVALUE4 16
348 #define M_TIMERVALUE4 0xffffU
349 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
350 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
352 #define S_TIMERVALUE5 0
353 #define M_TIMERVALUE5 0xffffU
354 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
355 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
357 #define A_SGE_DEBUG_INDEX 0x10cc
358 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
359 #define A_SGE_DEBUG_DATA_LOW 0x10d4
360 #define A_SGE_STAT_CFG 0x10ec
363 #define M_STATMODE 0x3U
364 #define V_STATMODE(x) ((x) << S_STATMODE)
365 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
367 #define S_STATSOURCE_T5 9
368 #define M_STATSOURCE_T5 0xfU
369 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
370 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
372 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
374 #define A_SGE_CONTROL2 0x1124
376 #define S_IDMAARBROUNDROBIN 19
377 #define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
378 #define F_IDMAARBROUNDROBIN V_IDMAARBROUNDROBIN(1U)
380 #define S_INGPACKBOUNDARY 16
381 #define M_INGPACKBOUNDARY 0x7U
382 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
383 #define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
386 #define V_BUSY(x) ((x) << S_BUSY)
387 #define F_BUSY V_BUSY(1U)
389 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
390 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
391 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
393 /* registers for module PCIE */
394 #define PCIE_BASE_ADDR 0x3000
396 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
398 #define S_PCIEOFST 10
399 #define M_PCIEOFST 0x3fffffU
400 #define V_PCIEOFST(x) ((x) << S_PCIEOFST)
401 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
405 #define V_BIR(x) ((x) << S_BIR)
406 #define G_BIR(x) (((x) >> S_BIR) & M_BIR)
409 #define M_WINDOW 0xffU
410 #define V_WINDOW(x) ((x) << S_WINDOW)
411 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
413 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
417 #define V_PFNUM(x) ((x) << S_PFNUM)
418 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
420 #define A_PCIE_FW 0x30b8
421 #define A_PCIE_FW_PF 0x30bc
423 #define A_PCIE_CFG2 0x3018
425 #define S_TOTMAXTAG 0
426 #define M_TOTMAXTAG 0x3U
427 #define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
429 #define S_T6_TOTMAXTAG 0
430 #define M_T6_TOTMAXTAG 0x7U
431 #define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG)
433 #define A_PCIE_CMD_CFG 0x5980
436 #define M_MINTAG 0xffU
437 #define V_MINTAG(x) ((x) << S_MINTAG)
439 #define S_T6_MINTAG 0
440 #define M_T6_MINTAG 0xffU
441 #define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
443 /* registers for module CIM */
444 #define CIM_BASE_ADDR 0x7b00
446 #define A_CIM_PF_MAILBOX_DATA 0x240
447 #define A_CIM_PF_MAILBOX_CTRL 0x280
449 #define S_MBMSGVALID 3
450 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
451 #define F_MBMSGVALID V_MBMSGVALID(1U)
454 #define M_MBOWNER 0x3U
455 #define V_MBOWNER(x) ((x) << S_MBOWNER)
456 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
458 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
459 #define A_CIM_BOOT_CFG 0x7b00
462 #define V_UPCRST(x) ((x) << S_UPCRST)
463 #define F_UPCRST V_UPCRST(1U)
465 /* registers for module TP */
466 #define A_TP_OUT_CONFIG 0x7d04
468 #define S_CRXPKTENC 3
469 #define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
470 #define F_CRXPKTENC V_CRXPKTENC(1U)
472 #define TP_BASE_ADDR 0x7d00
474 #define A_TP_TIMER_RESOLUTION 0x7d90
476 #define S_TIMERRESOLUTION 16
477 #define M_TIMERRESOLUTION 0xffU
478 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
479 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
481 #define S_DELAYEDACKRESOLUTION 0
482 #define M_DELAYEDACKRESOLUTION 0xffU
483 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
484 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & \
485 M_DELAYEDACKRESOLUTION)
487 #define A_TP_CCTRL_TABLE 0x7ddc
489 #define A_TP_MTU_TABLE 0x7de4
491 #define S_MTUINDEX 24
492 #define M_MTUINDEX 0xffU
493 #define V_MTUINDEX(x) ((x) << S_MTUINDEX)
494 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
496 #define S_MTUWIDTH 16
497 #define M_MTUWIDTH 0xfU
498 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
499 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
502 #define M_MTUVALUE 0x3fffU
503 #define V_MTUVALUE(x) ((x) << S_MTUVALUE)
504 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
506 #define A_TP_PIO_ADDR 0x7e40
507 #define A_TP_PIO_DATA 0x7e44
509 #define A_TP_VLAN_PRI_MAP 0x140
511 #define S_FRAGMENTATION 9
512 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
513 #define F_FRAGMENTATION V_FRAGMENTATION(1U)
515 #define S_MPSHITTYPE 8
516 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
517 #define F_MPSHITTYPE V_MPSHITTYPE(1U)
520 #define V_MACMATCH(x) ((x) << S_MACMATCH)
521 #define F_MACMATCH V_MACMATCH(1U)
523 #define S_ETHERTYPE 6
524 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
525 #define F_ETHERTYPE V_ETHERTYPE(1U)
528 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
529 #define F_PROTOCOL V_PROTOCOL(1U)
532 #define V_TOS(x) ((x) << S_TOS)
533 #define F_TOS V_TOS(1U)
536 #define V_VLAN(x) ((x) << S_VLAN)
537 #define F_VLAN V_VLAN(1U)
540 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
541 #define F_VNIC_ID V_VNIC_ID(1U)
544 #define V_PORT(x) ((x) << S_PORT)
545 #define F_PORT V_PORT(1U)
548 #define V_FCOE(x) ((x) << S_FCOE)
549 #define F_FCOE V_FCOE(1U)
551 #define A_TP_INGRESS_CONFIG 0x141
554 #define V_VNIC(x) ((x) << S_VNIC)
555 #define F_VNIC V_VNIC(1U)
557 #define S_CSUM_HAS_PSEUDO_HDR 10
558 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
559 #define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U)
561 /* registers for module MPS */
562 #define MPS_BASE_ADDR 0x9000
564 #define S_REPLICATE 11
565 #define V_REPLICATE(x) ((x) << S_REPLICATE)
566 #define F_REPLICATE V_REPLICATE(1U)
570 #define V_PF(x) ((x) << S_PF)
571 #define G_PF(x) (((x) >> S_PF) & M_PF)
574 #define V_VF_VALID(x) ((x) << S_VF_VALID)
575 #define F_VF_VALID V_VF_VALID(1U)
579 #define V_VF(x) ((x) << S_VF)
580 #define G_VF(x) (((x) >> S_VF) & M_VF)
582 #define A_MPS_STAT_CTL 0x9600
584 #define S_COUNTPAUSEMCRX 5
585 #define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
586 #define F_COUNTPAUSEMCRX V_COUNTPAUSEMCRX(1U)
588 #define S_COUNTPAUSESTATRX 4
589 #define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
590 #define F_COUNTPAUSESTATRX V_COUNTPAUSESTATRX(1U)
592 #define S_COUNTPAUSEMCTX 3
593 #define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
594 #define F_COUNTPAUSEMCTX V_COUNTPAUSEMCTX(1U)
596 #define S_COUNTPAUSESTATTX 2
597 #define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
598 #define F_COUNTPAUSESTATTX V_COUNTPAUSESTATTX(1U)
600 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
601 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
602 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
603 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
604 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
605 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
606 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
607 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
608 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
609 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
610 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
611 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
612 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
613 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
614 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
615 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
616 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
617 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
618 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
619 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
620 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
621 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
622 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
623 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
624 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
625 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
626 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
627 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
628 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
629 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
630 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
631 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
632 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
633 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
634 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
635 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
636 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
637 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
638 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
639 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
640 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
641 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
642 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
643 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
644 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
645 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
646 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
647 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
648 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
649 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
650 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
651 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
652 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
653 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
654 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
655 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
656 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
657 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
658 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
659 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
660 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
661 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
662 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
663 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
664 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
665 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
666 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
667 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
668 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
669 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
670 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
671 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
672 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
673 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
674 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
675 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
676 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
677 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
678 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
679 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
680 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
681 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
682 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
683 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
684 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
685 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
686 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
687 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
688 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
689 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
690 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
691 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
692 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
693 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
694 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
695 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
696 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
697 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
698 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
699 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
700 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
701 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
702 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
703 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
704 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
705 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
706 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
707 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
708 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
709 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
710 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
711 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
712 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
713 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
714 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
715 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
716 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
717 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
718 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
719 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
720 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
721 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
722 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
723 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
724 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
725 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
726 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
727 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
728 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
729 #define A_MPS_CMN_CTL 0x9000
732 #define M_NUMPORTS 0x3U
733 #define V_NUMPORTS(x) ((x) << S_NUMPORTS)
734 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
736 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
737 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
738 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
739 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
740 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
741 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
742 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
743 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
744 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
745 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
746 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
747 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
748 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
749 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
750 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
751 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
752 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
753 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
754 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
755 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
756 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
757 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
758 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
759 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
760 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
761 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
762 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
763 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
764 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
765 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
766 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
767 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
769 /* registers for module ULP_RX */
770 #define ULP_RX_BASE_ADDR 0x19150
774 #define V_HPZ0(x) ((x) << S_HPZ0)
775 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
777 #define A_ULP_RX_TDDP_PSZ 0x19178
779 /* registers for module SF */
780 #define SF_BASE_ADDR 0x193f8
782 #define A_SF_DATA 0x193f8
783 #define A_SF_OP 0x193fc
786 #define V_SF_LOCK(x) ((x) << S_SF_LOCK)
787 #define F_SF_LOCK V_SF_LOCK(1U)
790 #define V_CONT(x) ((x) << S_CONT)
791 #define F_CONT V_CONT(1U)
794 #define M_BYTECNT 0x3U
795 #define V_BYTECNT(x) ((x) << S_BYTECNT)
796 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
799 #define V_OP(x) ((x) << S_OP)
800 #define F_OP V_OP(1U)
802 /* registers for module PL */
803 #define PL_BASE_ADDR 0x19400
806 #define M_SOURCEPF 0x7U
807 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
808 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
810 #define S_T6_SOURCEPF 9
811 #define M_T6_SOURCEPF 0x7U
812 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
813 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
815 #define A_PL_PF_INT_ENABLE 0x3c4
818 #define V_PFSW(x) ((x) << S_PFSW)
819 #define F_PFSW V_PFSW(1U)
822 #define V_PFCIM(x) ((x) << S_PFCIM)
823 #define F_PFCIM V_PFCIM(1U)
825 #define A_PL_WHOAMI 0x19400
827 #define A_PL_RST 0x19428
829 #define A_PL_INT_MAP0 0x19414
832 #define V_PIORST(x) ((x) << S_PIORST)
833 #define F_PIORST V_PIORST(1U)
835 #define S_PIORSTMODE 0
836 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
837 #define F_PIORSTMODE V_PIORSTMODE(1U)
839 #define A_PL_REV 0x1943c
843 #define V_REV(x) ((x) << S_REV)
844 #define G_REV(x) (((x) >> S_REV) & M_REV)