4 * Copyright(c) 2014-2015 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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34 #define MYPF_BASE 0x1b000
35 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
37 #define PF0_BASE 0x1e000
38 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
40 #define PF_STRIDE 0x400
41 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
42 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
44 #define MYPORT_BASE 0x1c000
45 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
47 #define PORT0_BASE 0x20000
48 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
50 #define PORT_STRIDE 0x2000
51 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
52 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
54 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
55 #define NUM_PCIE_MEM_ACCESS_INSTANCES 8
57 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
58 #define NUM_PCIE_FW_INSTANCES 8
60 #define T5_MYPORT_BASE 0x2c000
61 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
63 #define T5_PORT0_BASE 0x30000
64 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
66 #define T5_PORT_STRIDE 0x4000
67 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
68 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
70 #define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
71 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
73 #define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
74 #define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
76 /* registers for module SGE */
77 #define SGE_BASE_ADDR 0x1000
79 #define A_SGE_PF_KDOORBELL 0x0
82 #define M_QID 0x1ffffU
83 #define V_QID(x) ((x) << S_QID)
84 #define G_QID(x) (((x) >> S_QID) & M_QID)
87 #define V_DBPRIO(x) ((x) << S_DBPRIO)
88 #define F_DBPRIO V_DBPRIO(1U)
91 #define M_PIDX 0x3fffU
92 #define V_PIDX(x) ((x) << S_PIDX)
93 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
96 #define V_DBTYPE(x) ((x) << S_DBTYPE)
97 #define F_DBTYPE V_DBTYPE(1U)
100 #define M_PIDX_T5 0x1fffU
101 #define V_PIDX_T5(x) ((x) << S_PIDX_T5)
102 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
104 #define A_SGE_PF_GTS 0x4
106 #define S_INGRESSQID 16
107 #define M_INGRESSQID 0xffffU
108 #define V_INGRESSQID(x) ((x) << S_INGRESSQID)
109 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
111 #define S_SEINTARM 12
112 #define V_SEINTARM(x) ((x) << S_SEINTARM)
113 #define F_SEINTARM V_SEINTARM(1U)
116 #define M_CIDXINC 0xfffU
117 #define V_CIDXINC(x) ((x) << S_CIDXINC)
118 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
120 #define A_SGE_CONTROL 0x1008
122 #define S_RXPKTCPLMODE 18
123 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
124 #define F_RXPKTCPLMODE V_RXPKTCPLMODE(1U)
126 #define S_EGRSTATUSPAGESIZE 17
127 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
128 #define F_EGRSTATUSPAGESIZE V_EGRSTATUSPAGESIZE(1U)
130 #define S_PKTSHIFT 10
131 #define M_PKTSHIFT 0x7U
132 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
133 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
135 #define S_INGPADBOUNDARY 4
136 #define M_INGPADBOUNDARY 0x7U
137 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
138 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
140 #define A_SGE_HOST_PAGE_SIZE 0x100c
142 #define S_HOSTPAGESIZEPF7 28
143 #define M_HOSTPAGESIZEPF7 0xfU
144 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
145 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
147 #define S_HOSTPAGESIZEPF6 24
148 #define M_HOSTPAGESIZEPF6 0xfU
149 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
150 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
152 #define S_HOSTPAGESIZEPF5 20
153 #define M_HOSTPAGESIZEPF5 0xfU
154 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
155 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
157 #define S_HOSTPAGESIZEPF4 16
158 #define M_HOSTPAGESIZEPF4 0xfU
159 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
160 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
162 #define S_HOSTPAGESIZEPF3 12
163 #define M_HOSTPAGESIZEPF3 0xfU
164 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
165 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
167 #define S_HOSTPAGESIZEPF2 8
168 #define M_HOSTPAGESIZEPF2 0xfU
169 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
170 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
172 #define S_HOSTPAGESIZEPF1 4
173 #define M_HOSTPAGESIZEPF1 0xfU
174 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
175 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
177 #define S_HOSTPAGESIZEPF0 0
178 #define M_HOSTPAGESIZEPF0 0xfU
179 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
180 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
182 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
184 #define S_QUEUESPERPAGEPF1 4
185 #define M_QUEUESPERPAGEPF1 0xfU
186 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
187 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
189 #define S_QUEUESPERPAGEPF0 0
190 #define M_QUEUESPERPAGEPF0 0xfU
191 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
192 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
194 #define S_ERR_CPL_EXCEED_IQE_SIZE 22
195 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
196 #define F_ERR_CPL_EXCEED_IQE_SIZE V_ERR_CPL_EXCEED_IQE_SIZE(1U)
198 #define S_ERR_INVALID_CIDX_INC 21
199 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
200 #define F_ERR_INVALID_CIDX_INC V_ERR_INVALID_CIDX_INC(1U)
202 #define S_ERR_CPL_OPCODE_0 19
203 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
204 #define F_ERR_CPL_OPCODE_0 V_ERR_CPL_OPCODE_0(1U)
206 #define S_ERR_DROPPED_DB 18
207 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
208 #define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U)
210 #define S_ERR_DATA_CPL_ON_HIGH_QID1 17
211 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
212 #define F_ERR_DATA_CPL_ON_HIGH_QID1 V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
214 #define S_ERR_DATA_CPL_ON_HIGH_QID0 16
215 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
216 #define F_ERR_DATA_CPL_ON_HIGH_QID0 V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
218 #define S_ERR_BAD_DB_PIDX3 15
219 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
220 #define F_ERR_BAD_DB_PIDX3 V_ERR_BAD_DB_PIDX3(1U)
222 #define S_ERR_BAD_DB_PIDX2 14
223 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
224 #define F_ERR_BAD_DB_PIDX2 V_ERR_BAD_DB_PIDX2(1U)
226 #define S_ERR_BAD_DB_PIDX1 13
227 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
228 #define F_ERR_BAD_DB_PIDX1 V_ERR_BAD_DB_PIDX1(1U)
230 #define S_ERR_BAD_DB_PIDX0 12
231 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
232 #define F_ERR_BAD_DB_PIDX0 V_ERR_BAD_DB_PIDX0(1U)
234 #define S_ERR_ING_PCIE_CHAN 11
235 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
236 #define F_ERR_ING_PCIE_CHAN V_ERR_ING_PCIE_CHAN(1U)
238 #define S_ERR_ING_CTXT_PRIO 10
239 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
240 #define F_ERR_ING_CTXT_PRIO V_ERR_ING_CTXT_PRIO(1U)
242 #define S_ERR_EGR_CTXT_PRIO 9
243 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
244 #define F_ERR_EGR_CTXT_PRIO V_ERR_EGR_CTXT_PRIO(1U)
246 #define S_DBFIFO_HP_INT 8
247 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
248 #define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U)
250 #define S_DBFIFO_LP_INT 7
251 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
252 #define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U)
254 #define S_INGRESS_SIZE_ERR 5
255 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
256 #define F_INGRESS_SIZE_ERR V_INGRESS_SIZE_ERR(1U)
258 #define S_EGRESS_SIZE_ERR 4
259 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
260 #define F_EGRESS_SIZE_ERR V_EGRESS_SIZE_ERR(1U)
262 #define A_SGE_INT_ENABLE3 0x1040
264 #define A_SGE_FL_BUFFER_SIZE0 0x1044
265 #define A_SGE_FL_BUFFER_SIZE1 0x1048
266 #define A_SGE_FL_BUFFER_SIZE2 0x104c
267 #define A_SGE_FL_BUFFER_SIZE3 0x1050
269 #define A_SGE_CONM_CTRL 0x1094
271 #define S_EGRTHRESHOLD 8
272 #define M_EGRTHRESHOLD 0x3fU
273 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
274 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
276 #define S_EGRTHRESHOLDPACKING 14
277 #define M_EGRTHRESHOLDPACKING 0x3fU
278 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
279 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & \
280 M_EGRTHRESHOLDPACKING)
282 #define S_INGTHRESHOLD 2
283 #define M_INGTHRESHOLD 0x3fU
284 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
285 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
287 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
289 #define S_THRESHOLD_0 24
290 #define M_THRESHOLD_0 0x3fU
291 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
292 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
294 #define S_THRESHOLD_1 16
295 #define M_THRESHOLD_1 0x3fU
296 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
297 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
299 #define S_THRESHOLD_2 8
300 #define M_THRESHOLD_2 0x3fU
301 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
302 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
304 #define S_THRESHOLD_3 0
305 #define M_THRESHOLD_3 0x3fU
306 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
307 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
309 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
311 #define S_TIMERVALUE0 16
312 #define M_TIMERVALUE0 0xffffU
313 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
314 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
316 #define S_TIMERVALUE1 0
317 #define M_TIMERVALUE1 0xffffU
318 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
319 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
321 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
323 #define S_TIMERVALUE2 16
324 #define M_TIMERVALUE2 0xffffU
325 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
326 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
328 #define S_TIMERVALUE3 0
329 #define M_TIMERVALUE3 0xffffU
330 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
331 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
333 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
335 #define S_TIMERVALUE4 16
336 #define M_TIMERVALUE4 0xffffU
337 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
338 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
340 #define S_TIMERVALUE5 0
341 #define M_TIMERVALUE5 0xffffU
342 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
343 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
345 #define A_SGE_DEBUG_INDEX 0x10cc
346 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
347 #define A_SGE_DEBUG_DATA_LOW 0x10d4
348 #define A_SGE_STAT_CFG 0x10ec
351 #define M_STATMODE 0x3U
352 #define V_STATMODE(x) ((x) << S_STATMODE)
353 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
355 #define S_STATSOURCE_T5 9
356 #define M_STATSOURCE_T5 0xfU
357 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
358 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
360 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
362 #define A_SGE_CONTROL2 0x1124
364 #define S_INGPACKBOUNDARY 16
365 #define M_INGPACKBOUNDARY 0x7U
366 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
367 #define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
370 #define V_BUSY(x) ((x) << S_BUSY)
371 #define F_BUSY V_BUSY(1U)
373 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
374 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
375 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
377 /* registers for module PCIE */
378 #define PCIE_BASE_ADDR 0x3000
380 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
382 #define S_PCIEOFST 10
383 #define M_PCIEOFST 0x3fffffU
384 #define V_PCIEOFST(x) ((x) << S_PCIEOFST)
385 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
389 #define V_BIR(x) ((x) << S_BIR)
390 #define G_BIR(x) (((x) >> S_BIR) & M_BIR)
393 #define M_WINDOW 0xffU
394 #define V_WINDOW(x) ((x) << S_WINDOW)
395 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
397 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
401 #define V_PFNUM(x) ((x) << S_PFNUM)
402 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
404 #define A_PCIE_FW 0x30b8
405 #define A_PCIE_FW_PF 0x30bc
407 /* registers for module CIM */
408 #define CIM_BASE_ADDR 0x7b00
410 #define A_CIM_PF_MAILBOX_DATA 0x240
411 #define A_CIM_PF_MAILBOX_CTRL 0x280
413 #define S_MBMSGVALID 3
414 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
415 #define F_MBMSGVALID V_MBMSGVALID(1U)
418 #define M_MBOWNER 0x3U
419 #define V_MBOWNER(x) ((x) << S_MBOWNER)
420 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
422 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
423 #define A_CIM_BOOT_CFG 0x7b00
426 #define V_UPCRST(x) ((x) << S_UPCRST)
427 #define F_UPCRST V_UPCRST(1U)
429 /* registers for module TP */
430 #define TP_BASE_ADDR 0x7d00
432 #define A_TP_TIMER_RESOLUTION 0x7d90
434 #define S_TIMERRESOLUTION 16
435 #define M_TIMERRESOLUTION 0xffU
436 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
437 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
439 #define S_DELAYEDACKRESOLUTION 0
440 #define M_DELAYEDACKRESOLUTION 0xffU
441 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
442 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & \
443 M_DELAYEDACKRESOLUTION)
445 #define A_TP_CCTRL_TABLE 0x7ddc
447 #define A_TP_MTU_TABLE 0x7de4
449 #define S_MTUINDEX 24
450 #define M_MTUINDEX 0xffU
451 #define V_MTUINDEX(x) ((x) << S_MTUINDEX)
452 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
454 #define S_MTUWIDTH 16
455 #define M_MTUWIDTH 0xfU
456 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
457 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
460 #define M_MTUVALUE 0x3fffU
461 #define V_MTUVALUE(x) ((x) << S_MTUVALUE)
462 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
464 #define A_TP_PIO_ADDR 0x7e40
465 #define A_TP_PIO_DATA 0x7e44
467 #define A_TP_VLAN_PRI_MAP 0x140
469 #define S_FRAGMENTATION 9
470 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
471 #define F_FRAGMENTATION V_FRAGMENTATION(1U)
473 #define S_MPSHITTYPE 8
474 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
475 #define F_MPSHITTYPE V_MPSHITTYPE(1U)
478 #define V_MACMATCH(x) ((x) << S_MACMATCH)
479 #define F_MACMATCH V_MACMATCH(1U)
481 #define S_ETHERTYPE 6
482 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
483 #define F_ETHERTYPE V_ETHERTYPE(1U)
486 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
487 #define F_PROTOCOL V_PROTOCOL(1U)
490 #define V_TOS(x) ((x) << S_TOS)
491 #define F_TOS V_TOS(1U)
494 #define V_VLAN(x) ((x) << S_VLAN)
495 #define F_VLAN V_VLAN(1U)
498 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
499 #define F_VNIC_ID V_VNIC_ID(1U)
502 #define V_PORT(x) ((x) << S_PORT)
503 #define F_PORT V_PORT(1U)
506 #define V_FCOE(x) ((x) << S_FCOE)
507 #define F_FCOE V_FCOE(1U)
509 #define A_TP_INGRESS_CONFIG 0x141
512 #define V_VNIC(x) ((x) << S_VNIC)
513 #define F_VNIC V_VNIC(1U)
515 #define S_CSUM_HAS_PSEUDO_HDR 10
516 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
517 #define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U)
519 /* registers for module MPS */
520 #define MPS_BASE_ADDR 0x9000
522 #define S_REPLICATE 11
523 #define V_REPLICATE(x) ((x) << S_REPLICATE)
524 #define F_REPLICATE V_REPLICATE(1U)
528 #define V_PF(x) ((x) << S_PF)
529 #define G_PF(x) (((x) >> S_PF) & M_PF)
532 #define V_VF_VALID(x) ((x) << S_VF_VALID)
533 #define F_VF_VALID V_VF_VALID(1U)
537 #define V_VF(x) ((x) << S_VF)
538 #define G_VF(x) (((x) >> S_VF) & M_VF)
540 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
541 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
542 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
543 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
544 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
545 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
546 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
547 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
548 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
549 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
550 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
551 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
552 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
553 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
554 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
555 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
556 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
557 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
558 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
559 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
560 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
561 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
562 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
563 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
564 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
565 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
566 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
567 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
568 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
569 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
570 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
571 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
572 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
573 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
574 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
575 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
576 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
577 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
578 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
579 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
580 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
581 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
582 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
583 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
584 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
585 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
586 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
587 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
588 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
589 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
590 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
591 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
592 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
593 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
594 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
595 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
596 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
597 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
598 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
599 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
600 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
601 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
602 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
603 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
604 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
605 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
606 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
607 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
608 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
609 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
610 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
611 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
612 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
613 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
614 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
615 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
616 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
617 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
618 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
619 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
620 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
621 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
622 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
623 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
624 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
625 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
626 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
627 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
628 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
629 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
630 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
631 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
632 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
633 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
634 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
635 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
636 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
637 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
638 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
639 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
640 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
641 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
642 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
643 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
644 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
645 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
646 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
647 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
648 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
649 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
650 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
651 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
652 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
653 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
654 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
655 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
656 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
657 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
658 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
659 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
660 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
661 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
662 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
663 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
664 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
665 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
666 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
667 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
668 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
669 #define A_MPS_CMN_CTL 0x9000
672 #define M_NUMPORTS 0x3U
673 #define V_NUMPORTS(x) ((x) << S_NUMPORTS)
674 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
676 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
677 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
678 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
679 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
680 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
681 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
682 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
683 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
684 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
685 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
686 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
687 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
688 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
689 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
690 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
691 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
692 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
693 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
694 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
695 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
696 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
697 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
698 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
699 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
700 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
701 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
702 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
703 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
704 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
705 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
706 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
707 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
709 /* registers for module ULP_RX */
710 #define ULP_RX_BASE_ADDR 0x19150
714 #define V_HPZ0(x) ((x) << S_HPZ0)
715 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
717 #define A_ULP_RX_TDDP_PSZ 0x19178
719 /* registers for module SF */
720 #define SF_BASE_ADDR 0x193f8
722 #define A_SF_DATA 0x193f8
723 #define A_SF_OP 0x193fc
726 #define V_SF_LOCK(x) ((x) << S_SF_LOCK)
727 #define F_SF_LOCK V_SF_LOCK(1U)
730 #define V_CONT(x) ((x) << S_CONT)
731 #define F_CONT V_CONT(1U)
734 #define M_BYTECNT 0x3U
735 #define V_BYTECNT(x) ((x) << S_BYTECNT)
736 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
739 #define V_OP(x) ((x) << S_OP)
740 #define F_OP V_OP(1U)
742 /* registers for module PL */
743 #define PL_BASE_ADDR 0x19400
746 #define M_SOURCEPF 0x7U
747 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
748 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
750 #define A_PL_PF_INT_ENABLE 0x3c4
753 #define V_PFSW(x) ((x) << S_PFSW)
754 #define F_PFSW V_PFSW(1U)
757 #define V_PFCIM(x) ((x) << S_PFCIM)
758 #define F_PFCIM V_PFCIM(1U)
760 #define A_PL_WHOAMI 0x19400
762 #define A_PL_RST 0x19428
764 #define A_PL_INT_MAP0 0x19414
767 #define V_PIORST(x) ((x) << S_PIORST)
768 #define F_PIORST V_PIORST(1U)
770 #define S_PIORSTMODE 0
771 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
772 #define F_PIORSTMODE V_PIORSTMODE(1U)
774 #define A_PL_REV 0x1943c
778 #define V_REV(x) ((x) << S_REV)
779 #define G_REV(x) (((x) >> S_REV) & M_REV)