4 * Copyright(c) 2014-2017 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #define MYPF_BASE 0x1b000
35 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
37 #define PF0_BASE 0x1e000
38 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
40 #define PF_STRIDE 0x400
41 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
42 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
44 #define MYPORT_BASE 0x1c000
45 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
47 #define PORT0_BASE 0x20000
48 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
50 #define PORT_STRIDE 0x2000
51 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
52 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
54 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
55 #define NUM_PCIE_MEM_ACCESS_INSTANCES 8
57 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
58 #define NUM_PCIE_FW_INSTANCES 8
60 #define T5_MYPORT_BASE 0x2c000
61 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
63 #define T5_PORT0_BASE 0x30000
64 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
66 #define T5_PORT_STRIDE 0x4000
67 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
68 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
70 #define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
71 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
73 #define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
74 #define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
76 /* registers for module SGE */
77 #define SGE_BASE_ADDR 0x1000
79 #define A_SGE_PF_KDOORBELL 0x0
80 #define A_SGE_VF_KDOORBELL 0x0
83 #define M_QID 0x1ffffU
84 #define V_QID(x) ((x) << S_QID)
85 #define G_QID(x) (((x) >> S_QID) & M_QID)
88 #define V_DBPRIO(x) ((x) << S_DBPRIO)
89 #define F_DBPRIO V_DBPRIO(1U)
92 #define M_PIDX 0x3fffU
93 #define V_PIDX(x) ((x) << S_PIDX)
94 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
97 #define V_DBTYPE(x) ((x) << S_DBTYPE)
98 #define F_DBTYPE V_DBTYPE(1U)
101 #define M_PIDX_T5 0x1fffU
102 #define V_PIDX_T5(x) ((x) << S_PIDX_T5)
103 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
105 #define A_SGE_PF_GTS 0x4
107 #define T4VF_SGE_BASE_ADDR 0x0000
108 #define A_SGE_VF_GTS 0x4
110 #define S_INGRESSQID 16
111 #define M_INGRESSQID 0xffffU
112 #define V_INGRESSQID(x) ((x) << S_INGRESSQID)
113 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
115 #define S_SEINTARM 12
116 #define V_SEINTARM(x) ((x) << S_SEINTARM)
117 #define F_SEINTARM V_SEINTARM(1U)
120 #define M_CIDXINC 0xfffU
121 #define V_CIDXINC(x) ((x) << S_CIDXINC)
122 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
124 #define A_SGE_CONTROL 0x1008
126 #define S_RXPKTCPLMODE 18
127 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
128 #define F_RXPKTCPLMODE V_RXPKTCPLMODE(1U)
130 #define S_EGRSTATUSPAGESIZE 17
131 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
132 #define F_EGRSTATUSPAGESIZE V_EGRSTATUSPAGESIZE(1U)
134 #define S_PKTSHIFT 10
135 #define M_PKTSHIFT 0x7U
136 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
137 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
139 #define S_INGPADBOUNDARY 4
140 #define M_INGPADBOUNDARY 0x7U
141 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
142 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
144 #define A_SGE_HOST_PAGE_SIZE 0x100c
146 #define S_HOSTPAGESIZEPF7 28
147 #define M_HOSTPAGESIZEPF7 0xfU
148 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
149 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
151 #define S_HOSTPAGESIZEPF6 24
152 #define M_HOSTPAGESIZEPF6 0xfU
153 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
154 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
156 #define S_HOSTPAGESIZEPF5 20
157 #define M_HOSTPAGESIZEPF5 0xfU
158 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
159 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
161 #define S_HOSTPAGESIZEPF4 16
162 #define M_HOSTPAGESIZEPF4 0xfU
163 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
164 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
166 #define S_HOSTPAGESIZEPF3 12
167 #define M_HOSTPAGESIZEPF3 0xfU
168 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
169 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
171 #define S_HOSTPAGESIZEPF2 8
172 #define M_HOSTPAGESIZEPF2 0xfU
173 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
174 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
176 #define S_HOSTPAGESIZEPF1 4
177 #define M_HOSTPAGESIZEPF1 0xfU
178 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
179 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
181 #define S_HOSTPAGESIZEPF0 0
182 #define M_HOSTPAGESIZEPF0 0xfU
183 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
184 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
186 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
188 #define S_QUEUESPERPAGEPF1 4
189 #define M_QUEUESPERPAGEPF1 0xfU
190 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
191 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
193 #define S_QUEUESPERPAGEPF0 0
194 #define M_QUEUESPERPAGEPF0 0xfU
195 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
196 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
198 #define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
200 #define S_ERR_CPL_EXCEED_IQE_SIZE 22
201 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
202 #define F_ERR_CPL_EXCEED_IQE_SIZE V_ERR_CPL_EXCEED_IQE_SIZE(1U)
204 #define S_ERR_INVALID_CIDX_INC 21
205 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
206 #define F_ERR_INVALID_CIDX_INC V_ERR_INVALID_CIDX_INC(1U)
208 #define S_ERR_CPL_OPCODE_0 19
209 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
210 #define F_ERR_CPL_OPCODE_0 V_ERR_CPL_OPCODE_0(1U)
212 #define S_ERR_DROPPED_DB 18
213 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
214 #define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U)
216 #define S_ERR_DATA_CPL_ON_HIGH_QID1 17
217 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
218 #define F_ERR_DATA_CPL_ON_HIGH_QID1 V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
220 #define S_ERR_DATA_CPL_ON_HIGH_QID0 16
221 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
222 #define F_ERR_DATA_CPL_ON_HIGH_QID0 V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
224 #define S_ERR_BAD_DB_PIDX3 15
225 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
226 #define F_ERR_BAD_DB_PIDX3 V_ERR_BAD_DB_PIDX3(1U)
228 #define S_ERR_BAD_DB_PIDX2 14
229 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
230 #define F_ERR_BAD_DB_PIDX2 V_ERR_BAD_DB_PIDX2(1U)
232 #define S_ERR_BAD_DB_PIDX1 13
233 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
234 #define F_ERR_BAD_DB_PIDX1 V_ERR_BAD_DB_PIDX1(1U)
236 #define S_ERR_BAD_DB_PIDX0 12
237 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
238 #define F_ERR_BAD_DB_PIDX0 V_ERR_BAD_DB_PIDX0(1U)
240 #define S_ERR_ING_PCIE_CHAN 11
241 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
242 #define F_ERR_ING_PCIE_CHAN V_ERR_ING_PCIE_CHAN(1U)
244 #define S_ERR_ING_CTXT_PRIO 10
245 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
246 #define F_ERR_ING_CTXT_PRIO V_ERR_ING_CTXT_PRIO(1U)
248 #define S_ERR_EGR_CTXT_PRIO 9
249 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
250 #define F_ERR_EGR_CTXT_PRIO V_ERR_EGR_CTXT_PRIO(1U)
252 #define S_DBFIFO_HP_INT 8
253 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
254 #define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U)
256 #define S_DBFIFO_LP_INT 7
257 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
258 #define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U)
260 #define S_INGRESS_SIZE_ERR 5
261 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
262 #define F_INGRESS_SIZE_ERR V_INGRESS_SIZE_ERR(1U)
264 #define S_EGRESS_SIZE_ERR 4
265 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
266 #define F_EGRESS_SIZE_ERR V_EGRESS_SIZE_ERR(1U)
268 #define A_SGE_INT_ENABLE3 0x1040
270 #define A_SGE_FL_BUFFER_SIZE0 0x1044
271 #define A_SGE_FL_BUFFER_SIZE1 0x1048
272 #define A_SGE_FL_BUFFER_SIZE2 0x104c
273 #define A_SGE_FL_BUFFER_SIZE3 0x1050
275 #define A_SGE_FLM_CFG 0x1090
277 #define S_CREDITCNT 4
278 #define M_CREDITCNT 0x3U
279 #define V_CREDITCNT(x) ((x) << S_CREDITCNT)
280 #define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
282 #define S_CREDITCNTPACKING 2
283 #define M_CREDITCNTPACKING 0x3U
284 #define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
285 #define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
287 #define A_SGE_CONM_CTRL 0x1094
289 #define S_T6_EGRTHRESHOLDPACKING 16
290 #define M_T6_EGRTHRESHOLDPACKING 0xffU
291 #define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & \
292 M_T6_EGRTHRESHOLDPACKING)
294 #define S_EGRTHRESHOLD 8
295 #define M_EGRTHRESHOLD 0x3fU
296 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
297 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
299 #define S_EGRTHRESHOLDPACKING 14
300 #define M_EGRTHRESHOLDPACKING 0x3fU
301 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
302 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & \
303 M_EGRTHRESHOLDPACKING)
305 #define S_INGTHRESHOLD 2
306 #define M_INGTHRESHOLD 0x3fU
307 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
308 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
310 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
312 #define S_THRESHOLD_0 24
313 #define M_THRESHOLD_0 0x3fU
314 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
315 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
317 #define S_THRESHOLD_1 16
318 #define M_THRESHOLD_1 0x3fU
319 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
320 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
322 #define S_THRESHOLD_2 8
323 #define M_THRESHOLD_2 0x3fU
324 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
325 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
327 #define S_THRESHOLD_3 0
328 #define M_THRESHOLD_3 0x3fU
329 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
330 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
332 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
334 #define S_TIMERVALUE0 16
335 #define M_TIMERVALUE0 0xffffU
336 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
337 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
339 #define S_TIMERVALUE1 0
340 #define M_TIMERVALUE1 0xffffU
341 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
342 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
344 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
346 #define S_TIMERVALUE2 16
347 #define M_TIMERVALUE2 0xffffU
348 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
349 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
351 #define S_TIMERVALUE3 0
352 #define M_TIMERVALUE3 0xffffU
353 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
354 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
356 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
358 #define S_TIMERVALUE4 16
359 #define M_TIMERVALUE4 0xffffU
360 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
361 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
363 #define S_TIMERVALUE5 0
364 #define M_TIMERVALUE5 0xffffU
365 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
366 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
368 #define A_SGE_DEBUG_INDEX 0x10cc
369 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
370 #define A_SGE_DEBUG_DATA_LOW 0x10d4
371 #define A_SGE_STAT_CFG 0x10ec
374 #define M_STATMODE 0x3U
375 #define V_STATMODE(x) ((x) << S_STATMODE)
376 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
378 #define S_STATSOURCE_T5 9
379 #define M_STATSOURCE_T5 0xfU
380 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
381 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
383 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
384 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
386 #define A_SGE_CONTROL2 0x1124
388 #define S_IDMAARBROUNDROBIN 19
389 #define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
390 #define F_IDMAARBROUNDROBIN V_IDMAARBROUNDROBIN(1U)
392 #define S_INGPACKBOUNDARY 16
393 #define M_INGPACKBOUNDARY 0x7U
394 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
395 #define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
398 #define V_BUSY(x) ((x) << S_BUSY)
399 #define F_BUSY V_BUSY(1U)
401 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
402 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
403 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
405 /* registers for module PCIE */
406 #define PCIE_BASE_ADDR 0x3000
408 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
410 #define S_PCIEOFST 10
411 #define M_PCIEOFST 0x3fffffU
412 #define V_PCIEOFST(x) ((x) << S_PCIEOFST)
413 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
417 #define V_BIR(x) ((x) << S_BIR)
418 #define G_BIR(x) (((x) >> S_BIR) & M_BIR)
421 #define M_WINDOW 0xffU
422 #define V_WINDOW(x) ((x) << S_WINDOW)
423 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
425 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
429 #define V_PFNUM(x) ((x) << S_PFNUM)
430 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
432 #define A_PCIE_FW 0x30b8
433 #define A_PCIE_FW_PF 0x30bc
435 #define A_PCIE_CFG2 0x3018
437 #define S_TOTMAXTAG 0
438 #define M_TOTMAXTAG 0x3U
439 #define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
441 #define S_T6_TOTMAXTAG 0
442 #define M_T6_TOTMAXTAG 0x7U
443 #define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG)
445 #define A_PCIE_CMD_CFG 0x5980
448 #define M_MINTAG 0xffU
449 #define V_MINTAG(x) ((x) << S_MINTAG)
451 #define S_T6_MINTAG 0
452 #define M_T6_MINTAG 0xffU
453 #define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
455 /* registers for module CIM */
456 #define CIM_BASE_ADDR 0x7b00
458 #define A_CIM_VF_EXT_MAILBOX_CTRL 0x0
460 #define A_CIM_PF_MAILBOX_DATA 0x240
461 #define A_CIM_PF_MAILBOX_CTRL 0x280
463 #define S_MBMSGVALID 3
464 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
465 #define F_MBMSGVALID V_MBMSGVALID(1U)
468 #define M_MBOWNER 0x3U
469 #define V_MBOWNER(x) ((x) << S_MBOWNER)
470 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
472 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
473 #define A_CIM_BOOT_CFG 0x7b00
476 #define V_UPCRST(x) ((x) << S_UPCRST)
477 #define F_UPCRST V_UPCRST(1U)
479 #define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16
481 /* registers for module TP */
482 #define A_TP_OUT_CONFIG 0x7d04
484 #define S_CRXPKTENC 3
485 #define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
486 #define F_CRXPKTENC V_CRXPKTENC(1U)
488 #define TP_BASE_ADDR 0x7d00
490 #define A_TP_TIMER_RESOLUTION 0x7d90
492 #define S_TIMERRESOLUTION 16
493 #define M_TIMERRESOLUTION 0xffU
494 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
495 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
497 #define S_DELAYEDACKRESOLUTION 0
498 #define M_DELAYEDACKRESOLUTION 0xffU
499 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
500 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & \
501 M_DELAYEDACKRESOLUTION)
503 #define A_TP_CCTRL_TABLE 0x7ddc
505 #define A_TP_MTU_TABLE 0x7de4
507 #define S_MTUINDEX 24
508 #define M_MTUINDEX 0xffU
509 #define V_MTUINDEX(x) ((x) << S_MTUINDEX)
510 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
512 #define S_MTUWIDTH 16
513 #define M_MTUWIDTH 0xfU
514 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
515 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
518 #define M_MTUVALUE 0x3fffU
519 #define V_MTUVALUE(x) ((x) << S_MTUVALUE)
520 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
522 #define A_TP_RSS_CONFIG_VRT 0x7e00
525 #define M_KEYMODE 0x3U
526 #define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)
528 #define S_KEYWRADDR 0
529 #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
532 #define V_KEYWREN(x) ((x) << S_KEYWREN)
533 #define F_KEYWREN V_KEYWREN(1U)
535 #define S_KEYWRADDRX 30
536 #define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX)
538 #define S_KEYEXTEND 26
539 #define V_KEYEXTEND(x) ((x) << S_KEYEXTEND)
540 #define F_KEYEXTEND V_KEYEXTEND(1U)
542 #define S_T6_VFWRADDR 8
543 #define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR)
545 #define A_TP_PIO_ADDR 0x7e40
546 #define A_TP_PIO_DATA 0x7e44
548 #define A_TP_RSS_SECRET_KEY0 0x40
550 #define A_TP_VLAN_PRI_MAP 0x140
552 #define S_FRAGMENTATION 9
553 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
554 #define F_FRAGMENTATION V_FRAGMENTATION(1U)
556 #define S_MPSHITTYPE 8
557 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
558 #define F_MPSHITTYPE V_MPSHITTYPE(1U)
561 #define V_MACMATCH(x) ((x) << S_MACMATCH)
562 #define F_MACMATCH V_MACMATCH(1U)
564 #define S_ETHERTYPE 6
565 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
566 #define F_ETHERTYPE V_ETHERTYPE(1U)
569 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
570 #define F_PROTOCOL V_PROTOCOL(1U)
573 #define V_TOS(x) ((x) << S_TOS)
574 #define F_TOS V_TOS(1U)
577 #define V_VLAN(x) ((x) << S_VLAN)
578 #define F_VLAN V_VLAN(1U)
581 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
582 #define F_VNIC_ID V_VNIC_ID(1U)
585 #define V_PORT(x) ((x) << S_PORT)
586 #define F_PORT V_PORT(1U)
589 #define V_FCOE(x) ((x) << S_FCOE)
590 #define F_FCOE V_FCOE(1U)
592 #define A_TP_INGRESS_CONFIG 0x141
595 #define V_VNIC(x) ((x) << S_VNIC)
596 #define F_VNIC V_VNIC(1U)
598 #define S_CSUM_HAS_PSEUDO_HDR 10
599 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
600 #define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U)
602 /* registers for module MPS */
603 #define MPS_BASE_ADDR 0x9000
605 #define S_REPLICATE 11
606 #define V_REPLICATE(x) ((x) << S_REPLICATE)
607 #define F_REPLICATE V_REPLICATE(1U)
611 #define V_PF(x) ((x) << S_PF)
612 #define G_PF(x) (((x) >> S_PF) & M_PF)
615 #define V_VF_VALID(x) ((x) << S_VF_VALID)
616 #define F_VF_VALID V_VF_VALID(1U)
620 #define V_VF(x) ((x) << S_VF)
621 #define G_VF(x) (((x) >> S_VF) & M_VF)
623 #define A_MPS_STAT_CTL 0x9600
625 #define S_COUNTPAUSEMCRX 5
626 #define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
627 #define F_COUNTPAUSEMCRX V_COUNTPAUSEMCRX(1U)
629 #define S_COUNTPAUSESTATRX 4
630 #define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
631 #define F_COUNTPAUSESTATRX V_COUNTPAUSESTATRX(1U)
633 #define S_COUNTPAUSEMCTX 3
634 #define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
635 #define F_COUNTPAUSEMCTX V_COUNTPAUSEMCTX(1U)
637 #define S_COUNTPAUSESTATTX 2
638 #define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
639 #define F_COUNTPAUSESTATTX V_COUNTPAUSESTATTX(1U)
641 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
642 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
643 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
644 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
645 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
646 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
647 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
648 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
649 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
650 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
651 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
652 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
653 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
654 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
655 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
656 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
657 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
658 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
659 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
660 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
661 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
662 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
663 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
664 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
665 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
666 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
667 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
668 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
669 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
670 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
671 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
672 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
673 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
674 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
675 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
676 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
677 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
678 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
679 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
680 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
681 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
682 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
683 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
684 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
685 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
686 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
687 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
688 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
689 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
690 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
691 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
692 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
693 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
694 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
695 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
696 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
697 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
698 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
699 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
700 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
701 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
702 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
703 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
704 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
705 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
706 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
707 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
708 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
709 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
710 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
711 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
712 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
713 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
714 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
715 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
716 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
717 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
718 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
719 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
720 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
721 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
722 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
723 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
724 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
725 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
726 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
727 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
728 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
729 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
730 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
731 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
732 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
733 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
734 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
735 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
736 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
737 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
738 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
739 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
740 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
741 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
742 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
743 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
744 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
745 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
746 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
747 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
748 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
749 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
750 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
751 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
752 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
753 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
754 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
755 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
756 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
757 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
758 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
759 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
760 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
761 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
762 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
763 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
764 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
765 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
766 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
767 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
768 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
769 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
770 #define A_MPS_CMN_CTL 0x9000
773 #define M_NUMPORTS 0x3U
774 #define V_NUMPORTS(x) ((x) << S_NUMPORTS)
775 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
777 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
778 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
779 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
780 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
781 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
782 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
783 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
784 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
785 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
786 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
787 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
788 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
789 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
790 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
791 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
792 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
793 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
794 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
795 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
796 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
797 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
798 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
799 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
800 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
801 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
802 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
803 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
804 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
805 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
806 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
807 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
808 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
810 /* registers for module ULP_RX */
811 #define ULP_RX_BASE_ADDR 0x19150
815 #define V_HPZ0(x) ((x) << S_HPZ0)
816 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
818 #define A_ULP_RX_TDDP_PSZ 0x19178
820 /* registers for module SF */
821 #define SF_BASE_ADDR 0x193f8
823 #define A_SF_DATA 0x193f8
824 #define A_SF_OP 0x193fc
827 #define V_SF_LOCK(x) ((x) << S_SF_LOCK)
828 #define F_SF_LOCK V_SF_LOCK(1U)
831 #define V_CONT(x) ((x) << S_CONT)
832 #define F_CONT V_CONT(1U)
835 #define M_BYTECNT 0x3U
836 #define V_BYTECNT(x) ((x) << S_BYTECNT)
837 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
840 #define V_OP(x) ((x) << S_OP)
841 #define F_OP V_OP(1U)
843 /* registers for module PL */
844 #define PL_BASE_ADDR 0x19400
847 #define M_SOURCEPF 0x7U
848 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
849 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
851 #define S_T6_SOURCEPF 9
852 #define M_T6_SOURCEPF 0x7U
853 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
854 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
856 #define A_PL_PF_INT_ENABLE 0x3c4
859 #define V_PFSW(x) ((x) << S_PFSW)
860 #define F_PFSW V_PFSW(1U)
863 #define V_PFCIM(x) ((x) << S_PFCIM)
864 #define F_PFCIM V_PFCIM(1U)
866 #define A_PL_WHOAMI 0x19400
867 #define A_PL_VF_WHOAMI 0x0
869 #define A_PL_RST 0x19428
871 #define A_PL_INT_MAP0 0x19414
874 #define V_PIORST(x) ((x) << S_PIORST)
875 #define F_PIORST V_PIORST(1U)
877 #define S_PIORSTMODE 0
878 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
879 #define F_PIORSTMODE V_PIORSTMODE(1U)
881 #define A_PL_REV 0x1943c
882 #define A_PL_VF_REV 0x4
886 #define V_REV(x) ((x) << S_REV)
887 #define G_REV(x) (((x) >> S_REV) & M_REV)