1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
60 FW_ETH_TX_PKT_WR = 0x08,
61 FW_ETH_TX_PKTS_WR = 0x09,
62 FW_ETH_TX_PKT_VM_WR = 0x11,
63 FW_ETH_TX_PKTS_VM_WR = 0x12,
65 FW_ETH_TX_PKTS2_WR = 0x78,
69 * Generic work request header flit0
76 /* work request opcode (hi)
79 #define M_FW_WR_OP 0xff
80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
81 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
83 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
85 #define S_FW_WR_ATOMIC 23
86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
88 /* work request immediate data length (hi)
90 #define S_FW_WR_IMMDLEN 0
91 #define M_FW_WR_IMMDLEN 0xff
92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
93 #define G_FW_WR_IMMDLEN(x) \
94 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
96 /* egress queue status update to egress queue status entry (lo)
98 #define S_FW_WR_EQUEQ 30
99 #define M_FW_WR_EQUEQ 0x1
100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
101 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
102 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
104 /* flow context identifier (lo)
106 #define S_FW_WR_FLOWID 8
107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
109 /* length in units of 16-bytes (lo)
111 #define S_FW_WR_LEN16 0
112 #define M_FW_WR_LEN16 0xff
113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
114 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
116 struct fw_eth_tx_pkt_wr {
118 __be32 equiq_to_len16;
122 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
123 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
124 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
125 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
126 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
128 struct fw_eth_tx_pkts_wr {
130 __be32 equiq_to_len16;
137 struct fw_eth_tx_pkt_vm_wr {
139 __be32 equiq_to_len16;
147 struct fw_eth_tx_pkts_vm_wr {
149 __be32 equiq_to_len16;
160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
161 enum fw_filter_wr_cookie {
162 FW_FILTER_WR_SUCCESS,
163 FW_FILTER_WR_FLT_ADDED,
164 FW_FILTER_WR_FLT_DELETED,
165 FW_FILTER_WR_SMT_TBL_FULL,
169 struct fw_filter2_wr {
174 __be32 del_filter_to_l2tix;
177 __u8 frag_to_ovlan_vldm;
179 __be16 rx_chan_rx_rpl_iq;
180 __be32 maci_to_matchtypem;
200 __u8 filter_type_swapmac;
201 __u8 natmode_to_ulp_type;
214 #define S_FW_FILTER_WR_TID 12
215 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
217 #define S_FW_FILTER_WR_RQTYPE 11
218 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
220 #define S_FW_FILTER_WR_NOREPLY 10
221 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
223 #define S_FW_FILTER_WR_IQ 0
224 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
226 #define S_FW_FILTER_WR_DEL_FILTER 31
227 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
228 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
230 #define S_FW_FILTER_WR_RPTTID 25
231 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
233 #define S_FW_FILTER_WR_DROP 24
234 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
236 #define S_FW_FILTER_WR_DIRSTEER 23
237 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
239 #define S_FW_FILTER_WR_MASKHASH 22
240 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
242 #define S_FW_FILTER_WR_DIRSTEERHASH 21
243 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
245 #define S_FW_FILTER_WR_LPBK 20
246 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
248 #define S_FW_FILTER_WR_DMAC 19
249 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
251 #define S_FW_FILTER_WR_INSVLAN 17
252 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
254 #define S_FW_FILTER_WR_RMVLAN 16
255 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
257 #define S_FW_FILTER_WR_HITCNTS 15
258 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
260 #define S_FW_FILTER_WR_TXCHAN 13
261 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
263 #define S_FW_FILTER_WR_PRIO 12
264 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
266 #define S_FW_FILTER_WR_L2TIX 0
267 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
269 #define S_FW_FILTER_WR_FRAG 7
270 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
272 #define S_FW_FILTER_WR_FRAGM 6
273 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
275 #define S_FW_FILTER_WR_IVLAN_VLD 5
276 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
278 #define S_FW_FILTER_WR_OVLAN_VLD 4
279 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
281 #define S_FW_FILTER_WR_IVLAN_VLDM 3
282 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
284 #define S_FW_FILTER_WR_OVLAN_VLDM 2
285 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
287 #define S_FW_FILTER_WR_RX_CHAN 15
288 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
290 #define S_FW_FILTER_WR_RX_RPL_IQ 0
291 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
293 #define S_FW_FILTER_WR_MACI 23
294 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
296 #define S_FW_FILTER_WR_MACIM 14
297 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
299 #define S_FW_FILTER_WR_FCOE 13
300 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
302 #define S_FW_FILTER_WR_FCOEM 12
303 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
305 #define S_FW_FILTER_WR_PORT 9
306 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
308 #define S_FW_FILTER_WR_PORTM 6
309 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
311 #define S_FW_FILTER_WR_MATCHTYPE 3
312 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
314 #define S_FW_FILTER_WR_MATCHTYPEM 0
315 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
317 #define S_FW_FILTER2_WR_SWAPMAC 0
318 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
320 #define S_FW_FILTER2_WR_NATMODE 5
321 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
323 #define S_FW_FILTER2_WR_ULP_TYPE 0
324 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
326 /******************************************************************************
328 *********************/
331 * The maximum length of time, in miliseconds, that we expect any firmware
332 * command to take to execute and return a reply to the host. The RESET
333 * and INITIALIZE commands can take a fair amount of time to execute but
334 * most execute in far less time than this maximum. This constant is used
335 * by host software to determine how long to wait for a firmware command
336 * reply before declaring the firmware as dead/unreachable ...
338 #define FW_CMD_MAX_TIMEOUT 10000
341 * If a host driver does a HELLO and discovers that there's already a MASTER
342 * selected, we may have to wait for that MASTER to finish issuing RESET,
343 * configuration and INITIALIZE commands. Also, there's a possibility that
344 * our own HELLO may get lost if it happens right as the MASTER is issuign a
345 * RESET command, so we need to be willing to make a few retries of our HELLO.
347 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
348 #define FW_CMD_HELLO_RETRIES 3
350 enum fw_cmd_opcodes {
355 FW_INITIALIZE_CMD = 0x06,
356 FW_CAPS_CONFIG_CMD = 0x07,
357 FW_PARAMS_CMD = 0x08,
360 FW_EQ_ETH_CMD = 0x12,
361 FW_EQ_CTRL_CMD = 0x13,
363 FW_VI_MAC_CMD = 0x15,
364 FW_VI_RXMODE_CMD = 0x16,
365 FW_VI_ENABLE_CMD = 0x17,
366 FW_VI_STATS_CMD = 0x1a,
368 FW_RSS_IND_TBL_CMD = 0x20,
369 FW_RSS_GLB_CONFIG_CMD = 0x22,
370 FW_RSS_VI_CONFIG_CMD = 0x23,
376 FW_CMD_CAP_PORT = 0x04,
380 * Generic command header flit0
387 #define S_FW_CMD_OP 24
388 #define M_FW_CMD_OP 0xff
389 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
390 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
392 #define S_FW_CMD_REQUEST 23
393 #define M_FW_CMD_REQUEST 0x1
394 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
395 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
396 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
398 #define S_FW_CMD_READ 22
399 #define M_FW_CMD_READ 0x1
400 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
401 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
402 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
404 #define S_FW_CMD_WRITE 21
405 #define M_FW_CMD_WRITE 0x1
406 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
407 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
408 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
410 #define S_FW_CMD_EXEC 20
411 #define M_FW_CMD_EXEC 0x1
412 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
413 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
414 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
416 #define S_FW_CMD_RETVAL 8
417 #define M_FW_CMD_RETVAL 0xff
418 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
419 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
421 #define S_FW_CMD_LEN16 0
422 #define M_FW_CMD_LEN16 0xff
423 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
424 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
426 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
430 enum fw_ldst_addrspc {
431 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
435 __be32 op_to_addrspace;
436 __be32 cycles_to_len16;
438 struct fw_ldst_addrval {
442 struct fw_ldst_idctxt {
444 __be32 msg_ctxtflush;
454 struct fw_ldst_mdio {
470 struct fw_ldst_func {
478 struct fw_ldst_pcie {
488 struct fw_ldst_i2c_deprecated {
512 #define S_FW_LDST_CMD_ADDRSPACE 0
513 #define M_FW_LDST_CMD_ADDRSPACE 0xff
514 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
516 struct fw_reset_cmd {
523 #define S_FW_RESET_CMD_HALT 31
524 #define M_FW_RESET_CMD_HALT 0x1
525 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
526 #define G_FW_RESET_CMD_HALT(x) \
527 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
528 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
531 FW_HELLO_CMD_STAGE_OS = 0,
534 struct fw_hello_cmd {
537 __be32 err_to_clearinit;
541 #define S_FW_HELLO_CMD_ERR 31
542 #define M_FW_HELLO_CMD_ERR 0x1
543 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
544 #define G_FW_HELLO_CMD_ERR(x) \
545 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
546 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
548 #define S_FW_HELLO_CMD_INIT 30
549 #define M_FW_HELLO_CMD_INIT 0x1
550 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
551 #define G_FW_HELLO_CMD_INIT(x) \
552 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
553 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
555 #define S_FW_HELLO_CMD_MASTERDIS 29
556 #define M_FW_HELLO_CMD_MASTERDIS 0x1
557 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
558 #define G_FW_HELLO_CMD_MASTERDIS(x) \
559 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
560 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
562 #define S_FW_HELLO_CMD_MASTERFORCE 28
563 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
564 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
565 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
566 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
567 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
569 #define S_FW_HELLO_CMD_MBMASTER 24
570 #define M_FW_HELLO_CMD_MBMASTER 0xf
571 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
572 #define G_FW_HELLO_CMD_MBMASTER(x) \
573 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
575 #define S_FW_HELLO_CMD_MBASYNCNOT 20
576 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
577 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
578 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
579 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
581 #define S_FW_HELLO_CMD_STAGE 17
582 #define M_FW_HELLO_CMD_STAGE 0x7
583 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
584 #define G_FW_HELLO_CMD_STAGE(x) \
585 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
587 #define S_FW_HELLO_CMD_CLEARINIT 16
588 #define M_FW_HELLO_CMD_CLEARINIT 0x1
589 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
590 #define G_FW_HELLO_CMD_CLEARINIT(x) \
591 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
592 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
600 struct fw_initialize_cmd {
606 enum fw_caps_config_nic {
607 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
608 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
612 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
615 struct fw_caps_config_cmd {
617 __be32 cfvalid_to_len16;
635 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
636 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
637 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
638 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
639 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
640 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
642 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
643 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
644 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
645 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
646 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
647 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
648 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
650 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
651 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
652 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
653 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
654 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
655 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
656 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
659 * params command mnemonics
661 enum fw_params_mnem {
662 FW_PARAMS_MNEM_DEV = 1, /* device params */
663 FW_PARAMS_MNEM_PFVF = 2, /* function params */
664 FW_PARAMS_MNEM_REG = 3, /* limited register access */
665 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
671 enum fw_params_param_dev {
672 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
673 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
674 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
675 * allocated by the device's
678 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
679 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
680 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
681 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
685 * physical and virtual function parameters
687 enum fw_params_param_pfvf {
688 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
689 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
690 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
691 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
692 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
693 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
694 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
695 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
699 * dma queue parameters
701 enum fw_params_param_dmaq {
702 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
703 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
706 #define S_FW_PARAMS_MNEM 24
707 #define M_FW_PARAMS_MNEM 0xff
708 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
709 #define G_FW_PARAMS_MNEM(x) \
710 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
712 #define S_FW_PARAMS_PARAM_X 16
713 #define M_FW_PARAMS_PARAM_X 0xff
714 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
715 #define G_FW_PARAMS_PARAM_X(x) \
716 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
718 #define S_FW_PARAMS_PARAM_Y 8
719 #define M_FW_PARAMS_PARAM_Y 0xff
720 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
721 #define G_FW_PARAMS_PARAM_Y(x) \
722 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
724 #define S_FW_PARAMS_PARAM_Z 0
725 #define M_FW_PARAMS_PARAM_Z 0xff
726 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
727 #define G_FW_PARAMS_PARAM_Z(x) \
728 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
730 #define S_FW_PARAMS_PARAM_YZ 0
731 #define M_FW_PARAMS_PARAM_YZ 0xffff
732 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
733 #define G_FW_PARAMS_PARAM_YZ(x) \
734 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
736 #define S_FW_PARAMS_PARAM_XYZ 0
737 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
738 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
740 struct fw_params_cmd {
743 struct fw_params_param {
749 #define S_FW_PARAMS_CMD_PFN 8
750 #define M_FW_PARAMS_CMD_PFN 0x7
751 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
752 #define G_FW_PARAMS_CMD_PFN(x) \
753 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
755 #define S_FW_PARAMS_CMD_VFN 0
756 #define M_FW_PARAMS_CMD_VFN 0xff
757 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
758 #define G_FW_PARAMS_CMD_VFN(x) \
759 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
766 __be32 tc_to_nexactf;
767 __be32 r_caps_to_nethctrl;
773 #define S_FW_PFVF_CMD_PFN 8
774 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
776 #define S_FW_PFVF_CMD_VFN 0
777 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
779 #define S_FW_PFVF_CMD_NIQFLINT 20
780 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
781 #define G_FW_PFVF_CMD_NIQFLINT(x) \
782 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
784 #define S_FW_PFVF_CMD_NIQ 0
785 #define M_FW_PFVF_CMD_NIQ 0xfffff
786 #define G_FW_PFVF_CMD_NIQ(x) \
787 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
789 #define S_FW_PFVF_CMD_PMASK 20
790 #define M_FW_PFVF_CMD_PMASK 0xf
791 #define G_FW_PFVF_CMD_PMASK(x) \
792 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
794 #define S_FW_PFVF_CMD_NEQ 0
795 #define M_FW_PFVF_CMD_NEQ 0xfffff
796 #define G_FW_PFVF_CMD_NEQ(x) \
797 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
799 #define S_FW_PFVF_CMD_TC 24
800 #define M_FW_PFVF_CMD_TC 0xff
801 #define G_FW_PFVF_CMD_TC(x) \
802 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
804 #define S_FW_PFVF_CMD_NVI 16
805 #define M_FW_PFVF_CMD_NVI 0xff
806 #define G_FW_PFVF_CMD_NVI(x) \
807 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
809 #define S_FW_PFVF_CMD_NEXACTF 0
810 #define M_FW_PFVF_CMD_NEXACTF 0xffff
811 #define G_FW_PFVF_CMD_NEXACTF(x) \
812 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
814 #define S_FW_PFVF_CMD_R_CAPS 24
815 #define M_FW_PFVF_CMD_R_CAPS 0xff
816 #define G_FW_PFVF_CMD_R_CAPS(x) \
817 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
819 #define S_FW_PFVF_CMD_WX_CAPS 16
820 #define M_FW_PFVF_CMD_WX_CAPS 0xff
821 #define G_FW_PFVF_CMD_WX_CAPS(x) \
822 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
824 #define S_FW_PFVF_CMD_NETHCTRL 0
825 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
826 #define G_FW_PFVF_CMD_NETHCTRL(x) \
827 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
830 * ingress queue type; the first 1K ingress queues can have associated 0,
831 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
835 FW_IQ_TYPE_FL_INT_CAP,
839 FW_IQ_IQTYPE_NIC = 1,
845 __be32 alloc_to_len16;
850 __be32 type_to_iqandstindex;
851 __be16 iqdroprss_to_iqesize;
854 __be32 iqns_to_fl0congen;
855 __be16 fl0dcaen_to_fl0cidxfthresh;
858 __be32 fl1cngchmap_to_fl1congen;
859 __be16 fl1dcaen_to_fl1cidxfthresh;
864 #define S_FW_IQ_CMD_PFN 8
865 #define M_FW_IQ_CMD_PFN 0x7
866 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
867 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
869 #define S_FW_IQ_CMD_VFN 0
870 #define M_FW_IQ_CMD_VFN 0xff
871 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
872 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
874 #define S_FW_IQ_CMD_ALLOC 31
875 #define M_FW_IQ_CMD_ALLOC 0x1
876 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
877 #define G_FW_IQ_CMD_ALLOC(x) \
878 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
879 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
881 #define S_FW_IQ_CMD_FREE 30
882 #define M_FW_IQ_CMD_FREE 0x1
883 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
884 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
885 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
887 #define S_FW_IQ_CMD_IQSTART 28
888 #define M_FW_IQ_CMD_IQSTART 0x1
889 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
890 #define G_FW_IQ_CMD_IQSTART(x) \
891 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
892 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
894 #define S_FW_IQ_CMD_IQSTOP 27
895 #define M_FW_IQ_CMD_IQSTOP 0x1
896 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
897 #define G_FW_IQ_CMD_IQSTOP(x) \
898 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
899 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
901 #define S_FW_IQ_CMD_TYPE 29
902 #define M_FW_IQ_CMD_TYPE 0x7
903 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
904 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
906 #define S_FW_IQ_CMD_IQASYNCH 28
907 #define M_FW_IQ_CMD_IQASYNCH 0x1
908 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
909 #define G_FW_IQ_CMD_IQASYNCH(x) \
910 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
911 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
913 #define S_FW_IQ_CMD_VIID 16
914 #define M_FW_IQ_CMD_VIID 0xfff
915 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
916 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
918 #define S_FW_IQ_CMD_IQANDST 15
919 #define M_FW_IQ_CMD_IQANDST 0x1
920 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
921 #define G_FW_IQ_CMD_IQANDST(x) \
922 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
923 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
925 #define S_FW_IQ_CMD_IQANUD 12
926 #define M_FW_IQ_CMD_IQANUD 0x3
927 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
928 #define G_FW_IQ_CMD_IQANUD(x) \
929 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
931 #define S_FW_IQ_CMD_IQANDSTINDEX 0
932 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
933 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
934 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
935 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
937 #define S_FW_IQ_CMD_IQGTSMODE 14
938 #define M_FW_IQ_CMD_IQGTSMODE 0x1
939 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
940 #define G_FW_IQ_CMD_IQGTSMODE(x) \
941 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
942 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
944 #define S_FW_IQ_CMD_IQPCIECH 12
945 #define M_FW_IQ_CMD_IQPCIECH 0x3
946 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
947 #define G_FW_IQ_CMD_IQPCIECH(x) \
948 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
950 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
951 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
952 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
953 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
954 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
956 #define S_FW_IQ_CMD_IQESIZE 0
957 #define M_FW_IQ_CMD_IQESIZE 0x3
958 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
959 #define G_FW_IQ_CMD_IQESIZE(x) \
960 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
962 #define S_FW_IQ_CMD_IQRO 30
963 #define M_FW_IQ_CMD_IQRO 0x1
964 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
965 #define G_FW_IQ_CMD_IQRO(x) \
966 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
967 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
969 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
970 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
971 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
972 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
973 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
974 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
976 #define S_FW_IQ_CMD_IQTYPE 24
977 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
979 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
980 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
981 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
982 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
983 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
985 #define S_FW_IQ_CMD_FL0DATARO 12
986 #define M_FW_IQ_CMD_FL0DATARO 0x1
987 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
988 #define G_FW_IQ_CMD_FL0DATARO(x) \
989 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
990 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
992 #define S_FW_IQ_CMD_FL0CONGCIF 11
993 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
994 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
995 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
996 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
997 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
999 #define S_FW_IQ_CMD_FL0FETCHRO 6
1000 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
1001 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
1002 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
1003 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
1004 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
1006 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
1007 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
1008 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
1009 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
1010 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
1012 #define S_FW_IQ_CMD_FL0PADEN 2
1013 #define M_FW_IQ_CMD_FL0PADEN 0x1
1014 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
1015 #define G_FW_IQ_CMD_FL0PADEN(x) \
1016 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
1017 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
1019 #define S_FW_IQ_CMD_FL0PACKEN 1
1020 #define M_FW_IQ_CMD_FL0PACKEN 0x1
1021 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
1022 #define G_FW_IQ_CMD_FL0PACKEN(x) \
1023 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
1024 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
1026 #define S_FW_IQ_CMD_FL0CONGEN 0
1027 #define M_FW_IQ_CMD_FL0CONGEN 0x1
1028 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
1029 #define G_FW_IQ_CMD_FL0CONGEN(x) \
1030 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
1031 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
1033 #define S_FW_IQ_CMD_FL0FBMIN 7
1034 #define M_FW_IQ_CMD_FL0FBMIN 0x7
1035 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
1036 #define G_FW_IQ_CMD_FL0FBMIN(x) \
1037 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
1039 #define S_FW_IQ_CMD_FL0FBMAX 4
1040 #define M_FW_IQ_CMD_FL0FBMAX 0x7
1041 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
1042 #define G_FW_IQ_CMD_FL0FBMAX(x) \
1043 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
1045 struct fw_eq_eth_cmd {
1047 __be32 alloc_to_len16;
1049 __be32 physeqid_pkd;
1050 __be32 fetchszm_to_iqid;
1051 __be32 dcaen_to_eqsize;
1053 __be32 autoequiqe_to_viid;
1058 #define S_FW_EQ_ETH_CMD_PFN 8
1059 #define M_FW_EQ_ETH_CMD_PFN 0x7
1060 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
1061 #define G_FW_EQ_ETH_CMD_PFN(x) \
1062 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
1064 #define S_FW_EQ_ETH_CMD_VFN 0
1065 #define M_FW_EQ_ETH_CMD_VFN 0xff
1066 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
1067 #define G_FW_EQ_ETH_CMD_VFN(x) \
1068 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
1070 #define S_FW_EQ_ETH_CMD_ALLOC 31
1071 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
1072 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
1073 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
1074 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
1075 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
1077 #define S_FW_EQ_ETH_CMD_FREE 30
1078 #define M_FW_EQ_ETH_CMD_FREE 0x1
1079 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
1080 #define G_FW_EQ_ETH_CMD_FREE(x) \
1081 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
1082 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
1084 #define S_FW_EQ_ETH_CMD_EQSTART 28
1085 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
1086 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
1087 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
1088 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
1089 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
1091 #define S_FW_EQ_ETH_CMD_EQID 0
1092 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
1093 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
1094 #define G_FW_EQ_ETH_CMD_EQID(x) \
1095 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
1097 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
1098 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
1099 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
1100 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
1102 #define S_FW_EQ_ETH_CMD_FETCHRO 22
1103 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
1104 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
1105 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
1106 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
1107 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
1109 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
1110 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
1111 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
1112 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
1113 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
1115 #define S_FW_EQ_ETH_CMD_PCIECHN 16
1116 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
1117 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
1118 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
1119 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
1121 #define S_FW_EQ_ETH_CMD_IQID 0
1122 #define M_FW_EQ_ETH_CMD_IQID 0xffff
1123 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
1124 #define G_FW_EQ_ETH_CMD_IQID(x) \
1125 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
1127 #define S_FW_EQ_ETH_CMD_FBMIN 23
1128 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
1129 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
1130 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
1131 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
1133 #define S_FW_EQ_ETH_CMD_FBMAX 20
1134 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
1135 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
1136 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
1137 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
1139 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
1140 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
1141 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
1142 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
1143 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
1145 #define S_FW_EQ_ETH_CMD_EQSIZE 0
1146 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
1147 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
1148 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
1149 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
1151 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
1152 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
1153 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
1154 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
1155 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
1156 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
1158 #define S_FW_EQ_ETH_CMD_VIID 16
1159 #define M_FW_EQ_ETH_CMD_VIID 0xfff
1160 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
1161 #define G_FW_EQ_ETH_CMD_VIID(x) \
1162 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
1164 struct fw_eq_ctrl_cmd {
1166 __be32 alloc_to_len16;
1167 __be32 cmpliqid_eqid;
1168 __be32 physeqid_pkd;
1169 __be32 fetchszm_to_iqid;
1170 __be32 dcaen_to_eqsize;
1174 #define S_FW_EQ_CTRL_CMD_PFN 8
1175 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
1177 #define S_FW_EQ_CTRL_CMD_VFN 0
1178 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
1180 #define S_FW_EQ_CTRL_CMD_ALLOC 31
1181 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
1182 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
1184 #define S_FW_EQ_CTRL_CMD_FREE 30
1185 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
1186 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
1188 #define S_FW_EQ_CTRL_CMD_EQSTART 28
1189 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
1190 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
1192 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
1193 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
1195 #define S_FW_EQ_CTRL_CMD_EQID 0
1196 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
1197 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
1198 #define G_FW_EQ_CTRL_CMD_EQID(x) \
1199 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1201 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1202 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1203 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1204 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1205 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1207 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1208 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1209 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1211 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1212 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1213 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1215 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1216 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1218 #define S_FW_EQ_CTRL_CMD_IQID 0
1219 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1221 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1222 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1224 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1225 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1227 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1228 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1230 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1231 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1239 __be32 alloc_to_len16;
1240 __be16 type_to_viid;
1245 __be16 norss_rsssize;
1255 #define S_FW_VI_CMD_PFN 8
1256 #define M_FW_VI_CMD_PFN 0x7
1257 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1258 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1260 #define S_FW_VI_CMD_VFN 0
1261 #define M_FW_VI_CMD_VFN 0xff
1262 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1263 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1265 #define S_FW_VI_CMD_ALLOC 31
1266 #define M_FW_VI_CMD_ALLOC 0x1
1267 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1268 #define G_FW_VI_CMD_ALLOC(x) \
1269 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1270 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1272 #define S_FW_VI_CMD_FREE 30
1273 #define M_FW_VI_CMD_FREE 0x1
1274 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1275 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1276 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1278 #define S_FW_VI_CMD_TYPE 15
1279 #define M_FW_VI_CMD_TYPE 0x1
1280 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1281 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1282 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1284 #define S_FW_VI_CMD_FUNC 12
1285 #define M_FW_VI_CMD_FUNC 0x7
1286 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1287 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1289 #define S_FW_VI_CMD_VIID 0
1290 #define M_FW_VI_CMD_VIID 0xfff
1291 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1292 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1294 #define S_FW_VI_CMD_PORTID 4
1295 #define M_FW_VI_CMD_PORTID 0xf
1296 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1297 #define G_FW_VI_CMD_PORTID(x) \
1298 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1300 #define S_FW_VI_CMD_RSSSIZE 0
1301 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1302 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1303 #define G_FW_VI_CMD_RSSSIZE(x) \
1304 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1306 /* Special VI_MAC command index ids */
1307 #define FW_VI_MAC_ADD_MAC 0x3FF
1308 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1309 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
1311 enum fw_vi_mac_smac {
1312 FW_VI_MAC_MPS_TCAM_ENTRY,
1313 FW_VI_MAC_SMT_AND_MPSTCAM
1316 enum fw_vi_mac_entry_types {
1317 FW_VI_MAC_TYPE_RAW = 0x2,
1320 struct fw_vi_mac_cmd {
1322 __be32 freemacs_to_len16;
1324 struct fw_vi_mac_exact {
1325 __be16 valid_to_idx;
1328 struct fw_vi_mac_hash {
1331 struct fw_vi_mac_raw {
1341 #define S_FW_VI_MAC_CMD_VIID 0
1342 #define M_FW_VI_MAC_CMD_VIID 0xfff
1343 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1344 #define G_FW_VI_MAC_CMD_VIID(x) \
1345 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1347 #define S_FW_VI_MAC_CMD_FREEMACS 31
1348 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
1350 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
1351 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
1353 #define S_FW_VI_MAC_CMD_VALID 15
1354 #define M_FW_VI_MAC_CMD_VALID 0x1
1355 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1356 #define G_FW_VI_MAC_CMD_VALID(x) \
1357 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1358 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1360 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1361 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1362 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1363 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1364 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1366 #define S_FW_VI_MAC_CMD_IDX 0
1367 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1368 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1369 #define G_FW_VI_MAC_CMD_IDX(x) \
1370 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1372 #define S_FW_VI_MAC_CMD_RAW_IDX 16
1373 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
1374 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
1375 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
1376 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
1378 struct fw_vi_rxmode_cmd {
1380 __be32 retval_len16;
1381 __be32 mtu_to_vlanexen;
1385 #define S_FW_VI_RXMODE_CMD_VIID 0
1386 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1387 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1388 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1389 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1391 #define S_FW_VI_RXMODE_CMD_MTU 16
1392 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1393 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1394 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1395 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1397 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1398 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1399 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1400 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1401 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1403 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1404 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1405 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1406 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1407 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1408 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1410 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1411 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1412 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1413 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1414 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1415 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1416 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1418 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1419 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1420 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1421 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1422 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1424 struct fw_vi_enable_cmd {
1426 __be32 ien_to_len16;
1432 #define S_FW_VI_ENABLE_CMD_VIID 0
1433 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1434 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1435 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1436 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1438 #define S_FW_VI_ENABLE_CMD_IEN 31
1439 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1440 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1441 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1442 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1443 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1445 #define S_FW_VI_ENABLE_CMD_EEN 30
1446 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1447 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1448 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1449 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1450 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1452 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1453 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1454 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1455 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1456 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1457 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1459 /* VI VF stats offset definitions */
1460 #define VI_VF_NUM_STATS 16
1462 /* VI PF stats offset definitions */
1463 #define VI_PF_NUM_STATS 17
1464 enum fw_vi_stats_pf_index {
1465 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1466 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1467 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1468 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1469 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1470 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1471 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1472 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1473 FW_VI_PF_STAT_RX_BYTES_IX,
1474 FW_VI_PF_STAT_RX_FRAMES_IX,
1475 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1476 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1477 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1478 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1479 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1480 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1481 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1484 struct fw_vi_stats_cmd {
1486 __be32 retval_len16;
1488 struct fw_vi_stats_ctl {
1499 struct fw_vi_stats_pf {
1500 __be64 tx_bcast_bytes;
1501 __be64 tx_bcast_frames;
1502 __be64 tx_mcast_bytes;
1503 __be64 tx_mcast_frames;
1504 __be64 tx_ucast_bytes;
1505 __be64 tx_ucast_frames;
1506 __be64 tx_offload_bytes;
1507 __be64 tx_offload_frames;
1509 __be64 rx_pf_frames;
1510 __be64 rx_bcast_bytes;
1511 __be64 rx_bcast_frames;
1512 __be64 rx_mcast_bytes;
1513 __be64 rx_mcast_frames;
1514 __be64 rx_ucast_bytes;
1515 __be64 rx_ucast_frames;
1516 __be64 rx_err_frames;
1518 struct fw_vi_stats_vf {
1519 __be64 tx_bcast_bytes;
1520 __be64 tx_bcast_frames;
1521 __be64 tx_mcast_bytes;
1522 __be64 tx_mcast_frames;
1523 __be64 tx_ucast_bytes;
1524 __be64 tx_ucast_frames;
1525 __be64 tx_drop_frames;
1526 __be64 tx_offload_bytes;
1527 __be64 tx_offload_frames;
1528 __be64 rx_bcast_bytes;
1529 __be64 rx_bcast_frames;
1530 __be64 rx_mcast_bytes;
1531 __be64 rx_mcast_frames;
1532 __be64 rx_ucast_bytes;
1533 __be64 rx_ucast_frames;
1534 __be64 rx_err_frames;
1539 #define S_FW_VI_STATS_CMD_VIID 0
1540 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1542 #define S_FW_VI_STATS_CMD_NSTATS 12
1543 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1545 #define S_FW_VI_STATS_CMD_IX 0
1546 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1548 /* old 16-bit port capabilities bitmap */
1550 FW_PORT_CAP_SPEED_100M = 0x0001,
1551 FW_PORT_CAP_SPEED_1G = 0x0002,
1552 FW_PORT_CAP_SPEED_25G = 0x0004,
1553 FW_PORT_CAP_SPEED_10G = 0x0008,
1554 FW_PORT_CAP_SPEED_40G = 0x0010,
1555 FW_PORT_CAP_SPEED_100G = 0x0020,
1556 FW_PORT_CAP_FC_RX = 0x0040,
1557 FW_PORT_CAP_FC_TX = 0x0080,
1558 FW_PORT_CAP_ANEG = 0x0100,
1559 FW_PORT_CAP_MDIX = 0x0200,
1560 FW_PORT_CAP_MDIAUTO = 0x0400,
1561 FW_PORT_CAP_FEC_RS = 0x0800,
1562 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1563 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1564 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1565 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1568 #define S_FW_PORT_CAP_SPEED 0
1569 #define M_FW_PORT_CAP_SPEED 0x3f
1570 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1571 #define G_FW_PORT_CAP_SPEED(x) \
1572 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1575 FW_PORT_CAP_MDI_AUTO,
1578 #define S_FW_PORT_CAP_MDI 9
1579 #define M_FW_PORT_CAP_MDI 3
1580 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1581 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1583 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1584 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1585 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1586 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1587 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1588 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1589 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1590 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1591 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1592 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1593 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1594 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1595 #define FW_PORT_CAP32_ANEG 0x00100000UL
1596 #define FW_PORT_CAP32_MDIX 0x00200000UL
1597 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1598 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1599 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1601 #define S_FW_PORT_CAP32_SPEED 0
1602 #define M_FW_PORT_CAP32_SPEED 0xfff
1603 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1604 #define G_FW_PORT_CAP32_SPEED(x) \
1605 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1607 enum fw_port_mdi32 {
1608 FW_PORT_CAP32_MDI_AUTO,
1611 #define S_FW_PORT_CAP32_MDI 21
1612 #define M_FW_PORT_CAP32_MDI 3
1613 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1614 #define G_FW_PORT_CAP32_MDI(x) \
1615 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1617 enum fw_port_action {
1618 FW_PORT_ACTION_L1_CFG = 0x0001,
1619 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1620 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1621 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1624 struct fw_port_cmd {
1625 __be32 op_to_portid;
1626 __be32 action_to_len16;
1628 struct fw_port_l1cfg {
1632 struct fw_port_l2cfg {
1634 __u8 ovlan3_to_ivlan0;
1636 __be16 txipg_force_pinfo;
1647 struct fw_port_info {
1648 __be32 lstatus_to_modtype;
1659 struct fw_port_diags {
1665 struct fw_port_dcb_pgid {
1672 struct fw_port_dcb_pgrate {
1676 __u8 num_tcs_supported;
1680 struct fw_port_dcb_priorate {
1684 __u8 strict_priorate[8];
1686 struct fw_port_dcb_pfc {
1693 struct fw_port_app_priority {
1702 struct fw_port_dcb_control {
1705 __be16 dcb_version_to_app_state;
1710 struct fw_port_l1cfg32 {
1714 struct fw_port_info32 {
1715 __be32 lstatus32_to_cbllen32;
1716 __be32 auxlinfo32_mtu32;
1725 #define S_FW_PORT_CMD_PORTID 0
1726 #define M_FW_PORT_CMD_PORTID 0xf
1727 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1728 #define G_FW_PORT_CMD_PORTID(x) \
1729 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1731 #define S_FW_PORT_CMD_ACTION 16
1732 #define M_FW_PORT_CMD_ACTION 0xffff
1733 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1734 #define G_FW_PORT_CMD_ACTION(x) \
1735 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1737 #define S_FW_PORT_CMD_LSTATUS 31
1738 #define M_FW_PORT_CMD_LSTATUS 0x1
1739 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1740 #define G_FW_PORT_CMD_LSTATUS(x) \
1741 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1742 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1744 #define S_FW_PORT_CMD_LSPEED 24
1745 #define M_FW_PORT_CMD_LSPEED 0x3f
1746 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1747 #define G_FW_PORT_CMD_LSPEED(x) \
1748 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1750 #define S_FW_PORT_CMD_TXPAUSE 23
1751 #define M_FW_PORT_CMD_TXPAUSE 0x1
1752 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1753 #define G_FW_PORT_CMD_TXPAUSE(x) \
1754 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1755 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1757 #define S_FW_PORT_CMD_RXPAUSE 22
1758 #define M_FW_PORT_CMD_RXPAUSE 0x1
1759 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1760 #define G_FW_PORT_CMD_RXPAUSE(x) \
1761 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1762 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1764 #define S_FW_PORT_CMD_MDIOCAP 21
1765 #define M_FW_PORT_CMD_MDIOCAP 0x1
1766 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1767 #define G_FW_PORT_CMD_MDIOCAP(x) \
1768 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1769 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1771 #define S_FW_PORT_CMD_MDIOADDR 16
1772 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1773 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1774 #define G_FW_PORT_CMD_MDIOADDR(x) \
1775 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1777 #define S_FW_PORT_CMD_PTYPE 8
1778 #define M_FW_PORT_CMD_PTYPE 0x1f
1779 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1780 #define G_FW_PORT_CMD_PTYPE(x) \
1781 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1783 #define S_FW_PORT_CMD_LINKDNRC 5
1784 #define M_FW_PORT_CMD_LINKDNRC 0x7
1785 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1786 #define G_FW_PORT_CMD_LINKDNRC(x) \
1787 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1789 #define S_FW_PORT_CMD_MODTYPE 0
1790 #define M_FW_PORT_CMD_MODTYPE 0x1f
1791 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1792 #define G_FW_PORT_CMD_MODTYPE(x) \
1793 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1795 #define S_FW_PORT_CMD_LSTATUS32 31
1796 #define M_FW_PORT_CMD_LSTATUS32 0x1
1797 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1798 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1800 #define S_FW_PORT_CMD_LINKDNRC32 28
1801 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1802 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1803 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1805 #define S_FW_PORT_CMD_MDIOCAP32 26
1806 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1807 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1808 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1810 #define S_FW_PORT_CMD_MDIOADDR32 21
1811 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1812 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1813 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1815 #define S_FW_PORT_CMD_PORTTYPE32 13
1816 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1817 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1818 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1820 #define S_FW_PORT_CMD_MODTYPE32 8
1821 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1822 #define G_FW_PORT_CMD_MODTYPE32(x) \
1823 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1826 * These are configured into the VPD and hence tools that generate
1827 * VPD may use this enumeration.
1828 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1831 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1832 * with any new Firmware Port Technology Types!
1835 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1836 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1837 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1838 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1839 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1840 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1841 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1842 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1843 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1844 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1845 FW_PORT_TYPE_BP_AP = 10,
1846 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1847 FW_PORT_TYPE_BP4_AP = 11,
1848 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1849 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1850 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1851 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1852 FW_PORT_TYPE_BP40_BA = 15,
1853 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1854 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1855 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1856 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1857 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1858 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1859 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1860 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1863 /* These are read from module's EEPROM and determined once the
1864 * module is inserted.
1866 enum fw_port_module_type {
1867 FW_PORT_MOD_TYPE_NA = 0x0,
1868 FW_PORT_MOD_TYPE_LR = 0x1,
1869 FW_PORT_MOD_TYPE_SR = 0x2,
1870 FW_PORT_MOD_TYPE_ER = 0x3,
1871 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1872 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1873 FW_PORT_MOD_TYPE_LRM = 0x6,
1874 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1875 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1876 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1877 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1880 /* used by FW and tools may use this to generate VPD */
1881 enum fw_port_mod_sub_type {
1882 FW_PORT_MOD_SUB_TYPE_NA,
1883 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1884 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1885 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1886 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1887 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1888 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1889 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1890 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1893 * The following will never been in the VPD. They are TWINAX cable
1894 * lengths decoded from SFP+ module i2c PROMs. These should almost
1895 * certainly go somewhere else ...
1897 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1898 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1899 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1900 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1903 /* link down reason codes (3b) */
1904 enum fw_port_link_dn_rc {
1905 FW_PORT_LINK_DN_RC_NONE,
1906 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1907 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1908 FW_PORT_LINK_DN_RESERVED3,
1909 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1910 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1911 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1912 FW_PORT_LINK_DN_RESERVED7
1916 #define FW_NUM_PORT_STATS 50
1917 #define FW_NUM_PORT_TX_STATS 23
1918 #define FW_NUM_PORT_RX_STATS 27
1920 enum fw_port_stats_tx_index {
1921 FW_STAT_TX_PORT_BYTES_IX,
1922 FW_STAT_TX_PORT_FRAMES_IX,
1923 FW_STAT_TX_PORT_BCAST_IX,
1924 FW_STAT_TX_PORT_MCAST_IX,
1925 FW_STAT_TX_PORT_UCAST_IX,
1926 FW_STAT_TX_PORT_ERROR_IX,
1927 FW_STAT_TX_PORT_64B_IX,
1928 FW_STAT_TX_PORT_65B_127B_IX,
1929 FW_STAT_TX_PORT_128B_255B_IX,
1930 FW_STAT_TX_PORT_256B_511B_IX,
1931 FW_STAT_TX_PORT_512B_1023B_IX,
1932 FW_STAT_TX_PORT_1024B_1518B_IX,
1933 FW_STAT_TX_PORT_1519B_MAX_IX,
1934 FW_STAT_TX_PORT_DROP_IX,
1935 FW_STAT_TX_PORT_PAUSE_IX,
1936 FW_STAT_TX_PORT_PPP0_IX,
1937 FW_STAT_TX_PORT_PPP1_IX,
1938 FW_STAT_TX_PORT_PPP2_IX,
1939 FW_STAT_TX_PORT_PPP3_IX,
1940 FW_STAT_TX_PORT_PPP4_IX,
1941 FW_STAT_TX_PORT_PPP5_IX,
1942 FW_STAT_TX_PORT_PPP6_IX,
1943 FW_STAT_TX_PORT_PPP7_IX
1946 enum fw_port_stat_rx_index {
1947 FW_STAT_RX_PORT_BYTES_IX,
1948 FW_STAT_RX_PORT_FRAMES_IX,
1949 FW_STAT_RX_PORT_BCAST_IX,
1950 FW_STAT_RX_PORT_MCAST_IX,
1951 FW_STAT_RX_PORT_UCAST_IX,
1952 FW_STAT_RX_PORT_MTU_ERROR_IX,
1953 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1954 FW_STAT_RX_PORT_CRC_ERROR_IX,
1955 FW_STAT_RX_PORT_LEN_ERROR_IX,
1956 FW_STAT_RX_PORT_SYM_ERROR_IX,
1957 FW_STAT_RX_PORT_64B_IX,
1958 FW_STAT_RX_PORT_65B_127B_IX,
1959 FW_STAT_RX_PORT_128B_255B_IX,
1960 FW_STAT_RX_PORT_256B_511B_IX,
1961 FW_STAT_RX_PORT_512B_1023B_IX,
1962 FW_STAT_RX_PORT_1024B_1518B_IX,
1963 FW_STAT_RX_PORT_1519B_MAX_IX,
1964 FW_STAT_RX_PORT_PAUSE_IX,
1965 FW_STAT_RX_PORT_PPP0_IX,
1966 FW_STAT_RX_PORT_PPP1_IX,
1967 FW_STAT_RX_PORT_PPP2_IX,
1968 FW_STAT_RX_PORT_PPP3_IX,
1969 FW_STAT_RX_PORT_PPP4_IX,
1970 FW_STAT_RX_PORT_PPP5_IX,
1971 FW_STAT_RX_PORT_PPP6_IX,
1972 FW_STAT_RX_PORT_PPP7_IX,
1973 FW_STAT_RX_PORT_LESS_64B_IX
1976 struct fw_port_stats_cmd {
1977 __be32 op_to_portid;
1978 __be32 retval_len16;
1979 union fw_port_stats {
1980 struct fw_port_stats_ctl {
1992 struct fw_port_stats_all {
2001 __be64 tx_128b_255b;
2002 __be64 tx_256b_511b;
2003 __be64 tx_512b_1023b;
2004 __be64 tx_1024b_1518b;
2005 __be64 tx_1519b_max;
2021 __be64 rx_mtu_error;
2022 __be64 rx_mtu_crc_error;
2023 __be64 rx_crc_error;
2024 __be64 rx_len_error;
2025 __be64 rx_sym_error;
2028 __be64 rx_128b_255b;
2029 __be64 rx_256b_511b;
2030 __be64 rx_512b_1023b;
2031 __be64 rx_1024b_1518b;
2032 __be64 rx_1519b_max;
2049 struct fw_rss_ind_tbl_cmd {
2051 __be32 retval_len16;
2059 __be32 iq12_to_iq14;
2060 __be32 iq15_to_iq17;
2061 __be32 iq18_to_iq20;
2062 __be32 iq21_to_iq23;
2063 __be32 iq24_to_iq26;
2064 __be32 iq27_to_iq29;
2069 #define S_FW_RSS_IND_TBL_CMD_VIID 0
2070 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
2071 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
2072 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
2073 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
2075 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
2076 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
2077 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
2078 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
2079 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
2081 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
2082 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
2083 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
2084 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
2085 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
2087 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
2088 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
2089 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
2090 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
2091 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
2093 struct fw_rss_glb_config_cmd {
2095 __be32 retval_len16;
2096 union fw_rss_glb_config {
2097 struct fw_rss_glb_config_manual {
2103 struct fw_rss_glb_config_basicvirtual {
2104 __be32 mode_keymode;
2105 __be32 synmapen_to_hashtoeplitz;
2112 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
2113 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
2114 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
2115 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
2117 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2119 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
2120 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
2121 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
2122 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
2124 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
2125 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
2126 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
2127 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
2128 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
2130 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
2131 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
2132 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
2133 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
2134 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
2136 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
2137 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
2138 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
2139 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
2140 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
2142 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
2143 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
2144 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
2145 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
2146 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
2148 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
2149 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
2150 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
2151 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
2153 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
2154 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
2155 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
2156 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
2158 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
2159 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
2160 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
2161 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
2162 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
2164 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
2165 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
2166 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
2167 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
2168 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
2170 struct fw_rss_vi_config_cmd {
2172 __be32 retval_len16;
2173 union fw_rss_vi_config {
2174 struct fw_rss_vi_config_manual {
2179 struct fw_rss_vi_config_basicvirtual {
2181 __be32 defaultq_to_udpen;
2188 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
2189 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
2190 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
2191 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
2192 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
2194 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
2195 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
2196 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2197 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2198 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2199 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
2200 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2202 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
2203 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
2204 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2205 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2206 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2207 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
2208 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2209 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
2210 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
2212 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
2213 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
2214 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2215 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2216 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2217 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
2218 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2219 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
2220 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
2222 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
2223 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2224 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2225 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2226 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2227 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2228 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2229 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2230 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2232 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2233 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2234 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2235 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2236 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2237 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2238 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2239 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2240 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2242 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2243 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2244 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2245 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2246 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2247 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2249 struct fw_clip_cmd {
2251 __be32 alloc_to_len16;
2257 #define S_FW_CLIP_CMD_ALLOC 31
2258 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
2259 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
2261 #define S_FW_CLIP_CMD_FREE 30
2262 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
2263 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
2265 /******************************************************************************
2266 * D E B U G C O M M A N D s
2267 ******************************************************/
2269 struct fw_debug_cmd {
2273 struct fw_debug_assert {
2278 __u8 filename_0_7[8];
2279 __u8 filename_8_15[8];
2282 struct fw_debug_prt {
2285 __be32 dprtstrparam0;
2286 __be32 dprtstrparam1;
2287 __be32 dprtstrparam2;
2288 __be32 dprtstrparam3;
2293 #define S_FW_DEBUG_CMD_TYPE 0
2294 #define M_FW_DEBUG_CMD_TYPE 0xff
2295 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2296 #define G_FW_DEBUG_CMD_TYPE(x) \
2297 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2299 /******************************************************************************
2300 * P C I E F W R E G I S T E R
2301 **************************************/
2304 * Register definitions for the PCIE_FW register which the firmware uses
2305 * to retain status across RESETs. This register should be considered
2306 * as a READ-ONLY register for Host Software and only to be used to
2307 * track firmware initialization/error state, etc.
2309 #define S_PCIE_FW_ERR 31
2310 #define M_PCIE_FW_ERR 0x1
2311 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2312 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2313 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2315 #define S_PCIE_FW_INIT 30
2316 #define M_PCIE_FW_INIT 0x1
2317 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2318 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2319 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2321 #define S_PCIE_FW_HALT 29
2322 #define M_PCIE_FW_HALT 0x1
2323 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2324 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2325 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2327 #define S_PCIE_FW_EVAL 24
2328 #define M_PCIE_FW_EVAL 0x7
2329 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2330 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2332 #define S_PCIE_FW_MASTER_VLD 15
2333 #define M_PCIE_FW_MASTER_VLD 0x1
2334 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2335 #define G_PCIE_FW_MASTER_VLD(x) \
2336 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2337 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2339 #define S_PCIE_FW_MASTER 12
2340 #define M_PCIE_FW_MASTER 0x7
2341 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2342 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2344 /******************************************************************************
2345 * B I N A R Y H E A D E R F O R M A T
2346 **********************************************/
2349 * firmware binary header format
2353 __u8 chip; /* terminator chip family */
2354 __be16 len512; /* bin length in units of 512-bytes */
2355 __be32 fw_ver; /* firmware version */
2356 __be32 tp_microcode_ver; /* tcp processor microcode version */
2361 __u8 intfver_iscsipdu;
2363 __u8 intfver_fcoepdu;
2367 __u32 magic; /* runtime or bootstrap fw */
2369 __be32 reserved6[23];
2372 #define S_FW_HDR_FW_VER_MAJOR 24
2373 #define M_FW_HDR_FW_VER_MAJOR 0xff
2374 #define V_FW_HDR_FW_VER_MAJOR(x) \
2375 ((x) << S_FW_HDR_FW_VER_MAJOR)
2376 #define G_FW_HDR_FW_VER_MAJOR(x) \
2377 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2379 #define S_FW_HDR_FW_VER_MINOR 16
2380 #define M_FW_HDR_FW_VER_MINOR 0xff
2381 #define V_FW_HDR_FW_VER_MINOR(x) \
2382 ((x) << S_FW_HDR_FW_VER_MINOR)
2383 #define G_FW_HDR_FW_VER_MINOR(x) \
2384 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2386 #define S_FW_HDR_FW_VER_MICRO 8
2387 #define M_FW_HDR_FW_VER_MICRO 0xff
2388 #define V_FW_HDR_FW_VER_MICRO(x) \
2389 ((x) << S_FW_HDR_FW_VER_MICRO)
2390 #define G_FW_HDR_FW_VER_MICRO(x) \
2391 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2393 #define S_FW_HDR_FW_VER_BUILD 0
2394 #define M_FW_HDR_FW_VER_BUILD 0xff
2395 #define V_FW_HDR_FW_VER_BUILD(x) \
2396 ((x) << S_FW_HDR_FW_VER_BUILD)
2397 #define G_FW_HDR_FW_VER_BUILD(x) \
2398 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2400 #endif /* _T4FW_INTERFACE_H_ */