4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _T4FW_INTERFACE_H_
35 #define _T4FW_INTERFACE_H_
37 /******************************************************************************
38 * R E T U R N V A L U E S
39 ********************************/
42 FW_SUCCESS = 0, /* completed successfully */
43 FW_EPERM = 1, /* operation not permitted */
44 FW_ENOENT = 2, /* no such file or directory */
45 FW_EIO = 5, /* input/output error; hw bad */
46 FW_ENOEXEC = 8, /* exec format error; inv microcode */
47 FW_EAGAIN = 11, /* try again */
48 FW_ENOMEM = 12, /* out of memory */
49 FW_EFAULT = 14, /* bad address; fw bad */
50 FW_EBUSY = 16, /* resource busy */
51 FW_EEXIST = 17, /* file exists */
52 FW_ENODEV = 19, /* no such device */
53 FW_EINVAL = 22, /* invalid argument */
54 FW_ENOSPC = 28, /* no space left on device */
55 FW_ENOSYS = 38, /* functionality not implemented */
56 FW_ENODATA = 61, /* no data available */
57 FW_EPROTO = 71, /* protocol error */
58 FW_EADDRINUSE = 98, /* address already in use */
59 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
60 FW_ENETDOWN = 100, /* network is down */
61 FW_ENETUNREACH = 101, /* network is unreachable */
62 FW_ENOBUFS = 105, /* no buffer space available */
63 FW_ETIMEDOUT = 110, /* timeout */
64 FW_EINPROGRESS = 115, /* fw internal */
67 /******************************************************************************
68 * M E M O R Y T Y P E s
69 ******************************/
72 FW_MEMTYPE_EDC0 = 0x0,
73 FW_MEMTYPE_EDC1 = 0x1,
74 FW_MEMTYPE_EXTMEM = 0x2,
75 FW_MEMTYPE_FLASH = 0x4,
76 FW_MEMTYPE_INTERNAL = 0x5,
77 FW_MEMTYPE_EXTMEM1 = 0x6,
80 /******************************************************************************
81 * W O R K R E Q U E S T s
82 ********************************/
85 FW_ETH_TX_PKT_WR = 0x08,
86 FW_ETH_TX_PKTS_WR = 0x09,
87 FW_ETH_TX_PKT_VM_WR = 0x11,
88 FW_ETH_TX_PKTS_VM_WR = 0x12,
89 FW_ETH_TX_PKTS2_WR = 0x78,
93 * Generic work request header flit0
100 /* work request opcode (hi)
102 #define S_FW_WR_OP 24
103 #define M_FW_WR_OP 0xff
104 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
105 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
107 /* work request immediate data length (hi)
109 #define S_FW_WR_IMMDLEN 0
110 #define M_FW_WR_IMMDLEN 0xff
111 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
112 #define G_FW_WR_IMMDLEN(x) \
113 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
115 /* egress queue status update to egress queue status entry (lo)
117 #define S_FW_WR_EQUEQ 30
118 #define M_FW_WR_EQUEQ 0x1
119 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
120 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
121 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
123 /* length in units of 16-bytes (lo)
125 #define S_FW_WR_LEN16 0
126 #define M_FW_WR_LEN16 0xff
127 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
128 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
130 struct fw_eth_tx_pkt_wr {
132 __be32 equiq_to_len16;
136 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
137 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
138 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
139 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
140 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
142 struct fw_eth_tx_pkts_wr {
144 __be32 equiq_to_len16;
151 struct fw_eth_tx_pkt_vm_wr {
153 __be32 equiq_to_len16;
161 struct fw_eth_tx_pkts_vm_wr {
163 __be32 equiq_to_len16;
174 /******************************************************************************
176 *********************/
179 * The maximum length of time, in miliseconds, that we expect any firmware
180 * command to take to execute and return a reply to the host. The RESET
181 * and INITIALIZE commands can take a fair amount of time to execute but
182 * most execute in far less time than this maximum. This constant is used
183 * by host software to determine how long to wait for a firmware command
184 * reply before declaring the firmware as dead/unreachable ...
186 #define FW_CMD_MAX_TIMEOUT 10000
189 * If a host driver does a HELLO and discovers that there's already a MASTER
190 * selected, we may have to wait for that MASTER to finish issuing RESET,
191 * configuration and INITIALIZE commands. Also, there's a possibility that
192 * our own HELLO may get lost if it happens right as the MASTER is issuign a
193 * RESET command, so we need to be willing to make a few retries of our HELLO.
195 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
196 #define FW_CMD_HELLO_RETRIES 3
198 enum fw_cmd_opcodes {
203 FW_INITIALIZE_CMD = 0x06,
204 FW_CAPS_CONFIG_CMD = 0x07,
205 FW_PARAMS_CMD = 0x08,
208 FW_EQ_ETH_CMD = 0x12,
210 FW_VI_MAC_CMD = 0x15,
211 FW_VI_RXMODE_CMD = 0x16,
212 FW_VI_ENABLE_CMD = 0x17,
214 FW_RSS_IND_TBL_CMD = 0x20,
215 FW_RSS_GLB_CONFIG_CMD = 0x22,
216 FW_RSS_VI_CONFIG_CMD = 0x23,
221 FW_CMD_CAP_PORT = 0x04,
225 * Generic command header flit0
232 #define S_FW_CMD_OP 24
233 #define M_FW_CMD_OP 0xff
234 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
235 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
237 #define S_FW_CMD_REQUEST 23
238 #define M_FW_CMD_REQUEST 0x1
239 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
240 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
241 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
243 #define S_FW_CMD_READ 22
244 #define M_FW_CMD_READ 0x1
245 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
246 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
247 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
249 #define S_FW_CMD_WRITE 21
250 #define M_FW_CMD_WRITE 0x1
251 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
252 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
253 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
255 #define S_FW_CMD_EXEC 20
256 #define M_FW_CMD_EXEC 0x1
257 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
258 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
259 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
261 #define S_FW_CMD_RETVAL 8
262 #define M_FW_CMD_RETVAL 0xff
263 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
264 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
266 #define S_FW_CMD_LEN16 0
267 #define M_FW_CMD_LEN16 0xff
268 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
269 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
271 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
275 enum fw_ldst_addrspc {
276 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
280 __be32 op_to_addrspace;
281 __be32 cycles_to_len16;
283 struct fw_ldst_addrval {
287 struct fw_ldst_idctxt {
289 __be32 msg_ctxtflush;
299 struct fw_ldst_mdio {
315 struct fw_ldst_func {
323 struct fw_ldst_pcie {
333 struct fw_ldst_i2c_deprecated {
357 #define S_FW_LDST_CMD_ADDRSPACE 0
358 #define M_FW_LDST_CMD_ADDRSPACE 0xff
359 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
361 struct fw_reset_cmd {
368 #define S_FW_RESET_CMD_HALT 31
369 #define M_FW_RESET_CMD_HALT 0x1
370 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
371 #define G_FW_RESET_CMD_HALT(x) \
372 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
373 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
376 FW_HELLO_CMD_STAGE_OS = 0,
379 struct fw_hello_cmd {
382 __be32 err_to_clearinit;
386 #define S_FW_HELLO_CMD_ERR 31
387 #define M_FW_HELLO_CMD_ERR 0x1
388 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
389 #define G_FW_HELLO_CMD_ERR(x) \
390 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
391 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
393 #define S_FW_HELLO_CMD_INIT 30
394 #define M_FW_HELLO_CMD_INIT 0x1
395 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
396 #define G_FW_HELLO_CMD_INIT(x) \
397 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
398 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
400 #define S_FW_HELLO_CMD_MASTERDIS 29
401 #define M_FW_HELLO_CMD_MASTERDIS 0x1
402 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
403 #define G_FW_HELLO_CMD_MASTERDIS(x) \
404 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
405 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
407 #define S_FW_HELLO_CMD_MASTERFORCE 28
408 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
409 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
410 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
411 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
412 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
414 #define S_FW_HELLO_CMD_MBMASTER 24
415 #define M_FW_HELLO_CMD_MBMASTER 0xf
416 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
417 #define G_FW_HELLO_CMD_MBMASTER(x) \
418 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
420 #define S_FW_HELLO_CMD_MBASYNCNOT 20
421 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
422 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
423 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
424 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
426 #define S_FW_HELLO_CMD_STAGE 17
427 #define M_FW_HELLO_CMD_STAGE 0x7
428 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
429 #define G_FW_HELLO_CMD_STAGE(x) \
430 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
432 #define S_FW_HELLO_CMD_CLEARINIT 16
433 #define M_FW_HELLO_CMD_CLEARINIT 0x1
434 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
435 #define G_FW_HELLO_CMD_CLEARINIT(x) \
436 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
437 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
445 struct fw_initialize_cmd {
451 enum fw_caps_config_nic {
452 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
453 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
457 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
460 struct fw_caps_config_cmd {
462 __be32 cfvalid_to_len16;
480 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
481 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
482 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
483 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
484 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
485 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
487 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
488 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
489 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
490 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
491 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
492 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
493 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
495 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
496 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
497 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
498 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
499 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
500 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
501 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
504 * params command mnemonics
506 enum fw_params_mnem {
507 FW_PARAMS_MNEM_DEV = 1, /* device params */
508 FW_PARAMS_MNEM_PFVF = 2, /* function params */
509 FW_PARAMS_MNEM_REG = 3, /* limited register access */
510 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
516 enum fw_params_param_dev {
517 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
518 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
519 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
520 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
521 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
525 * physical and virtual function parameters
527 enum fw_params_param_pfvf {
528 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
529 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
533 * dma queue parameters
535 enum fw_params_param_dmaq {
536 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
537 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
540 #define S_FW_PARAMS_MNEM 24
541 #define M_FW_PARAMS_MNEM 0xff
542 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
543 #define G_FW_PARAMS_MNEM(x) \
544 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
546 #define S_FW_PARAMS_PARAM_X 16
547 #define M_FW_PARAMS_PARAM_X 0xff
548 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
549 #define G_FW_PARAMS_PARAM_X(x) \
550 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
552 #define S_FW_PARAMS_PARAM_Y 8
553 #define M_FW_PARAMS_PARAM_Y 0xff
554 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
555 #define G_FW_PARAMS_PARAM_Y(x) \
556 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
558 #define S_FW_PARAMS_PARAM_Z 0
559 #define M_FW_PARAMS_PARAM_Z 0xff
560 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
561 #define G_FW_PARAMS_PARAM_Z(x) \
562 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
564 #define S_FW_PARAMS_PARAM_YZ 0
565 #define M_FW_PARAMS_PARAM_YZ 0xffff
566 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
567 #define G_FW_PARAMS_PARAM_YZ(x) \
568 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
570 #define S_FW_PARAMS_PARAM_XYZ 0
571 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
572 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
574 struct fw_params_cmd {
577 struct fw_params_param {
583 #define S_FW_PARAMS_CMD_PFN 8
584 #define M_FW_PARAMS_CMD_PFN 0x7
585 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
586 #define G_FW_PARAMS_CMD_PFN(x) \
587 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
589 #define S_FW_PARAMS_CMD_VFN 0
590 #define M_FW_PARAMS_CMD_VFN 0xff
591 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
592 #define G_FW_PARAMS_CMD_VFN(x) \
593 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
600 __be32 tc_to_nexactf;
601 __be32 r_caps_to_nethctrl;
607 #define S_FW_PFVF_CMD_NIQFLINT 20
608 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
609 #define G_FW_PFVF_CMD_NIQFLINT(x) \
610 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
612 #define S_FW_PFVF_CMD_NIQ 0
613 #define M_FW_PFVF_CMD_NIQ 0xfffff
614 #define G_FW_PFVF_CMD_NIQ(x) \
615 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
617 #define S_FW_PFVF_CMD_PMASK 20
618 #define M_FW_PFVF_CMD_PMASK 0xf
619 #define G_FW_PFVF_CMD_PMASK(x) \
620 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
622 #define S_FW_PFVF_CMD_NEQ 0
623 #define M_FW_PFVF_CMD_NEQ 0xfffff
624 #define G_FW_PFVF_CMD_NEQ(x) \
625 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
627 #define S_FW_PFVF_CMD_TC 24
628 #define M_FW_PFVF_CMD_TC 0xff
629 #define G_FW_PFVF_CMD_TC(x) \
630 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
632 #define S_FW_PFVF_CMD_NVI 16
633 #define M_FW_PFVF_CMD_NVI 0xff
634 #define G_FW_PFVF_CMD_NVI(x) \
635 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
637 #define S_FW_PFVF_CMD_NEXACTF 0
638 #define M_FW_PFVF_CMD_NEXACTF 0xffff
639 #define G_FW_PFVF_CMD_NEXACTF(x) \
640 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
642 #define S_FW_PFVF_CMD_R_CAPS 24
643 #define M_FW_PFVF_CMD_R_CAPS 0xff
644 #define G_FW_PFVF_CMD_R_CAPS(x) \
645 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
647 #define S_FW_PFVF_CMD_WX_CAPS 16
648 #define M_FW_PFVF_CMD_WX_CAPS 0xff
649 #define G_FW_PFVF_CMD_WX_CAPS(x) \
650 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
652 #define S_FW_PFVF_CMD_NETHCTRL 0
653 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
654 #define G_FW_PFVF_CMD_NETHCTRL(x) \
655 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
658 * ingress queue type; the first 1K ingress queues can have associated 0,
659 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
663 FW_IQ_TYPE_FL_INT_CAP,
668 __be32 alloc_to_len16;
673 __be32 type_to_iqandstindex;
674 __be16 iqdroprss_to_iqesize;
677 __be32 iqns_to_fl0congen;
678 __be16 fl0dcaen_to_fl0cidxfthresh;
681 __be32 fl1cngchmap_to_fl1congen;
682 __be16 fl1dcaen_to_fl1cidxfthresh;
687 #define S_FW_IQ_CMD_PFN 8
688 #define M_FW_IQ_CMD_PFN 0x7
689 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
690 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
692 #define S_FW_IQ_CMD_VFN 0
693 #define M_FW_IQ_CMD_VFN 0xff
694 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
695 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
697 #define S_FW_IQ_CMD_ALLOC 31
698 #define M_FW_IQ_CMD_ALLOC 0x1
699 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
700 #define G_FW_IQ_CMD_ALLOC(x) \
701 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
702 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
704 #define S_FW_IQ_CMD_FREE 30
705 #define M_FW_IQ_CMD_FREE 0x1
706 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
707 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
708 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
710 #define S_FW_IQ_CMD_IQSTART 28
711 #define M_FW_IQ_CMD_IQSTART 0x1
712 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
713 #define G_FW_IQ_CMD_IQSTART(x) \
714 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
715 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
717 #define S_FW_IQ_CMD_IQSTOP 27
718 #define M_FW_IQ_CMD_IQSTOP 0x1
719 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
720 #define G_FW_IQ_CMD_IQSTOP(x) \
721 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
722 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
724 #define S_FW_IQ_CMD_TYPE 29
725 #define M_FW_IQ_CMD_TYPE 0x7
726 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
727 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
729 #define S_FW_IQ_CMD_IQASYNCH 28
730 #define M_FW_IQ_CMD_IQASYNCH 0x1
731 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
732 #define G_FW_IQ_CMD_IQASYNCH(x) \
733 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
734 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
736 #define S_FW_IQ_CMD_VIID 16
737 #define M_FW_IQ_CMD_VIID 0xfff
738 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
739 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
741 #define S_FW_IQ_CMD_IQANDST 15
742 #define M_FW_IQ_CMD_IQANDST 0x1
743 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
744 #define G_FW_IQ_CMD_IQANDST(x) \
745 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
746 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
748 #define S_FW_IQ_CMD_IQANUD 12
749 #define M_FW_IQ_CMD_IQANUD 0x3
750 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
751 #define G_FW_IQ_CMD_IQANUD(x) \
752 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
754 #define S_FW_IQ_CMD_IQANDSTINDEX 0
755 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
756 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
757 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
758 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
760 #define S_FW_IQ_CMD_IQGTSMODE 14
761 #define M_FW_IQ_CMD_IQGTSMODE 0x1
762 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
763 #define G_FW_IQ_CMD_IQGTSMODE(x) \
764 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
765 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
767 #define S_FW_IQ_CMD_IQPCIECH 12
768 #define M_FW_IQ_CMD_IQPCIECH 0x3
769 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
770 #define G_FW_IQ_CMD_IQPCIECH(x) \
771 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
773 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
774 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
775 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
776 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
777 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
779 #define S_FW_IQ_CMD_IQESIZE 0
780 #define M_FW_IQ_CMD_IQESIZE 0x3
781 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
782 #define G_FW_IQ_CMD_IQESIZE(x) \
783 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
785 #define S_FW_IQ_CMD_IQRO 30
786 #define M_FW_IQ_CMD_IQRO 0x1
787 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
788 #define G_FW_IQ_CMD_IQRO(x) \
789 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
790 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
792 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
793 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
794 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
795 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
796 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
797 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
799 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
800 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
801 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
802 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
803 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
805 #define S_FW_IQ_CMD_FL0DATARO 12
806 #define M_FW_IQ_CMD_FL0DATARO 0x1
807 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
808 #define G_FW_IQ_CMD_FL0DATARO(x) \
809 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
810 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
812 #define S_FW_IQ_CMD_FL0CONGCIF 11
813 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
814 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
815 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
816 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
817 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
819 #define S_FW_IQ_CMD_FL0FETCHRO 6
820 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
821 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
822 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
823 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
824 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
826 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
827 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
828 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
829 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
830 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
832 #define S_FW_IQ_CMD_FL0PADEN 2
833 #define M_FW_IQ_CMD_FL0PADEN 0x1
834 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
835 #define G_FW_IQ_CMD_FL0PADEN(x) \
836 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
837 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
839 #define S_FW_IQ_CMD_FL0PACKEN 1
840 #define M_FW_IQ_CMD_FL0PACKEN 0x1
841 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
842 #define G_FW_IQ_CMD_FL0PACKEN(x) \
843 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
844 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
846 #define S_FW_IQ_CMD_FL0CONGEN 0
847 #define M_FW_IQ_CMD_FL0CONGEN 0x1
848 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
849 #define G_FW_IQ_CMD_FL0CONGEN(x) \
850 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
851 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
853 #define S_FW_IQ_CMD_FL0FBMIN 7
854 #define M_FW_IQ_CMD_FL0FBMIN 0x7
855 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
856 #define G_FW_IQ_CMD_FL0FBMIN(x) \
857 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
859 #define S_FW_IQ_CMD_FL0FBMAX 4
860 #define M_FW_IQ_CMD_FL0FBMAX 0x7
861 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
862 #define G_FW_IQ_CMD_FL0FBMAX(x) \
863 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
865 struct fw_eq_eth_cmd {
867 __be32 alloc_to_len16;
870 __be32 fetchszm_to_iqid;
871 __be32 dcaen_to_eqsize;
873 __be32 autoequiqe_to_viid;
878 #define S_FW_EQ_ETH_CMD_PFN 8
879 #define M_FW_EQ_ETH_CMD_PFN 0x7
880 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
881 #define G_FW_EQ_ETH_CMD_PFN(x) \
882 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
884 #define S_FW_EQ_ETH_CMD_VFN 0
885 #define M_FW_EQ_ETH_CMD_VFN 0xff
886 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
887 #define G_FW_EQ_ETH_CMD_VFN(x) \
888 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
890 #define S_FW_EQ_ETH_CMD_ALLOC 31
891 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
892 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
893 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
894 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
895 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
897 #define S_FW_EQ_ETH_CMD_FREE 30
898 #define M_FW_EQ_ETH_CMD_FREE 0x1
899 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
900 #define G_FW_EQ_ETH_CMD_FREE(x) \
901 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
902 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
904 #define S_FW_EQ_ETH_CMD_EQSTART 28
905 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
906 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
907 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
908 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
909 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
911 #define S_FW_EQ_ETH_CMD_EQID 0
912 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
913 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
914 #define G_FW_EQ_ETH_CMD_EQID(x) \
915 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
917 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
918 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
919 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
920 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
922 #define S_FW_EQ_ETH_CMD_FETCHRO 22
923 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
924 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
925 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
926 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
927 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
929 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
930 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
931 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
932 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
933 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
935 #define S_FW_EQ_ETH_CMD_PCIECHN 16
936 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
937 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
938 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
939 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
941 #define S_FW_EQ_ETH_CMD_IQID 0
942 #define M_FW_EQ_ETH_CMD_IQID 0xffff
943 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
944 #define G_FW_EQ_ETH_CMD_IQID(x) \
945 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
947 #define S_FW_EQ_ETH_CMD_FBMIN 23
948 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
949 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
950 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
951 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
953 #define S_FW_EQ_ETH_CMD_FBMAX 20
954 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
955 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
956 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
957 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
959 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
960 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
961 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
962 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
963 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
965 #define S_FW_EQ_ETH_CMD_EQSIZE 0
966 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
967 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
968 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
969 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
971 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
972 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
973 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
974 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
975 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
976 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
978 #define S_FW_EQ_ETH_CMD_VIID 16
979 #define M_FW_EQ_ETH_CMD_VIID 0xfff
980 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
981 #define G_FW_EQ_ETH_CMD_VIID(x) \
982 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
990 __be32 alloc_to_len16;
996 __be16 norss_rsssize;
1006 #define S_FW_VI_CMD_PFN 8
1007 #define M_FW_VI_CMD_PFN 0x7
1008 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1009 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1011 #define S_FW_VI_CMD_VFN 0
1012 #define M_FW_VI_CMD_VFN 0xff
1013 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1014 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1016 #define S_FW_VI_CMD_ALLOC 31
1017 #define M_FW_VI_CMD_ALLOC 0x1
1018 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1019 #define G_FW_VI_CMD_ALLOC(x) \
1020 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1021 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1023 #define S_FW_VI_CMD_FREE 30
1024 #define M_FW_VI_CMD_FREE 0x1
1025 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1026 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1027 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1029 #define S_FW_VI_CMD_TYPE 15
1030 #define M_FW_VI_CMD_TYPE 0x1
1031 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1032 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1033 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1035 #define S_FW_VI_CMD_FUNC 12
1036 #define M_FW_VI_CMD_FUNC 0x7
1037 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1038 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1040 #define S_FW_VI_CMD_VIID 0
1041 #define M_FW_VI_CMD_VIID 0xfff
1042 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1043 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1045 #define S_FW_VI_CMD_PORTID 4
1046 #define M_FW_VI_CMD_PORTID 0xf
1047 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1048 #define G_FW_VI_CMD_PORTID(x) \
1049 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1051 #define S_FW_VI_CMD_RSSSIZE 0
1052 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1053 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1054 #define G_FW_VI_CMD_RSSSIZE(x) \
1055 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1057 /* Special VI_MAC command index ids */
1058 #define FW_VI_MAC_ADD_MAC 0x3FF
1059 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1061 enum fw_vi_mac_smac {
1062 FW_VI_MAC_MPS_TCAM_ENTRY,
1063 FW_VI_MAC_SMT_AND_MPSTCAM
1066 struct fw_vi_mac_cmd {
1068 __be32 freemacs_to_len16;
1070 struct fw_vi_mac_exact {
1071 __be16 valid_to_idx;
1074 struct fw_vi_mac_hash {
1080 #define S_FW_VI_MAC_CMD_VIID 0
1081 #define M_FW_VI_MAC_CMD_VIID 0xfff
1082 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1083 #define G_FW_VI_MAC_CMD_VIID(x) \
1084 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1086 #define S_FW_VI_MAC_CMD_VALID 15
1087 #define M_FW_VI_MAC_CMD_VALID 0x1
1088 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1089 #define G_FW_VI_MAC_CMD_VALID(x) \
1090 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1091 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1093 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1094 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1095 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1096 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1097 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1099 #define S_FW_VI_MAC_CMD_IDX 0
1100 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1101 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1102 #define G_FW_VI_MAC_CMD_IDX(x) \
1103 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1105 struct fw_vi_rxmode_cmd {
1107 __be32 retval_len16;
1108 __be32 mtu_to_vlanexen;
1112 #define S_FW_VI_RXMODE_CMD_VIID 0
1113 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1114 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1115 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1116 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1118 #define S_FW_VI_RXMODE_CMD_MTU 16
1119 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1120 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1121 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1122 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1124 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1125 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1126 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1127 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1128 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1130 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1131 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1132 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1133 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1134 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1135 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1137 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1138 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1139 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1140 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1141 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1142 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1143 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1145 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1146 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1147 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1148 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1149 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1151 struct fw_vi_enable_cmd {
1153 __be32 ien_to_len16;
1159 #define S_FW_VI_ENABLE_CMD_VIID 0
1160 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1161 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1162 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1163 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1165 #define S_FW_VI_ENABLE_CMD_IEN 31
1166 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1167 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1168 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1169 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1170 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1172 #define S_FW_VI_ENABLE_CMD_EEN 30
1173 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1174 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1175 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1176 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1177 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1179 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1180 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1181 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1182 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1183 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1184 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1186 /* VI PF stats offset definitions */
1187 #define VI_PF_NUM_STATS 17
1188 enum fw_vi_stats_pf_index {
1189 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1190 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1191 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1192 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1193 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1194 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1195 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1196 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1197 FW_VI_PF_STAT_RX_BYTES_IX,
1198 FW_VI_PF_STAT_RX_FRAMES_IX,
1199 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1200 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1201 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1202 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1203 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1204 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1205 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1208 struct fw_vi_stats_cmd {
1210 __be32 retval_len16;
1212 struct fw_vi_stats_ctl {
1223 struct fw_vi_stats_pf {
1224 __be64 tx_bcast_bytes;
1225 __be64 tx_bcast_frames;
1226 __be64 tx_mcast_bytes;
1227 __be64 tx_mcast_frames;
1228 __be64 tx_ucast_bytes;
1229 __be64 tx_ucast_frames;
1230 __be64 tx_offload_bytes;
1231 __be64 tx_offload_frames;
1233 __be64 rx_pf_frames;
1234 __be64 rx_bcast_bytes;
1235 __be64 rx_bcast_frames;
1236 __be64 rx_mcast_bytes;
1237 __be64 rx_mcast_frames;
1238 __be64 rx_ucast_bytes;
1239 __be64 rx_ucast_frames;
1240 __be64 rx_err_frames;
1242 struct fw_vi_stats_vf {
1243 __be64 tx_bcast_bytes;
1244 __be64 tx_bcast_frames;
1245 __be64 tx_mcast_bytes;
1246 __be64 tx_mcast_frames;
1247 __be64 tx_ucast_bytes;
1248 __be64 tx_ucast_frames;
1249 __be64 tx_drop_frames;
1250 __be64 tx_offload_bytes;
1251 __be64 tx_offload_frames;
1252 __be64 rx_bcast_bytes;
1253 __be64 rx_bcast_frames;
1254 __be64 rx_mcast_bytes;
1255 __be64 rx_mcast_frames;
1256 __be64 rx_ucast_bytes;
1257 __be64 rx_ucast_frames;
1258 __be64 rx_err_frames;
1263 /* old 16-bit port capabilities bitmap */
1265 FW_PORT_CAP_SPEED_100M = 0x0001,
1266 FW_PORT_CAP_SPEED_1G = 0x0002,
1267 FW_PORT_CAP_SPEED_25G = 0x0004,
1268 FW_PORT_CAP_SPEED_10G = 0x0008,
1269 FW_PORT_CAP_SPEED_40G = 0x0010,
1270 FW_PORT_CAP_SPEED_100G = 0x0020,
1271 FW_PORT_CAP_FC_RX = 0x0040,
1272 FW_PORT_CAP_FC_TX = 0x0080,
1273 FW_PORT_CAP_ANEG = 0x0100,
1274 FW_PORT_CAP_MDIX = 0x0200,
1275 FW_PORT_CAP_MDIAUTO = 0x0400,
1276 FW_PORT_CAP_FEC_RS = 0x0800,
1277 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1278 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1279 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1280 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1283 #define S_FW_PORT_CAP_SPEED 0
1284 #define M_FW_PORT_CAP_SPEED 0x3f
1285 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1286 #define G_FW_PORT_CAP_SPEED(x) \
1287 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1290 FW_PORT_CAP_MDI_AUTO,
1293 #define S_FW_PORT_CAP_MDI 9
1294 #define M_FW_PORT_CAP_MDI 3
1295 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1296 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1298 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1299 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1300 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1301 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1302 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1303 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1304 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1305 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1306 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1307 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1308 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1309 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1310 #define FW_PORT_CAP32_ANEG 0x00100000UL
1311 #define FW_PORT_CAP32_MDIX 0x00200000UL
1312 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1313 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1314 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1316 #define S_FW_PORT_CAP32_SPEED 0
1317 #define M_FW_PORT_CAP32_SPEED 0xfff
1318 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1319 #define G_FW_PORT_CAP32_SPEED(x) \
1320 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1322 enum fw_port_mdi32 {
1323 FW_PORT_CAP32_MDI_AUTO,
1326 #define S_FW_PORT_CAP32_MDI 21
1327 #define M_FW_PORT_CAP32_MDI 3
1328 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1329 #define G_FW_PORT_CAP32_MDI(x) \
1330 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1332 enum fw_port_action {
1333 FW_PORT_ACTION_L1_CFG = 0x0001,
1334 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1335 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1336 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1339 struct fw_port_cmd {
1340 __be32 op_to_portid;
1341 __be32 action_to_len16;
1343 struct fw_port_l1cfg {
1347 struct fw_port_l2cfg {
1349 __u8 ovlan3_to_ivlan0;
1351 __be16 txipg_force_pinfo;
1362 struct fw_port_info {
1363 __be32 lstatus_to_modtype;
1374 struct fw_port_diags {
1380 struct fw_port_dcb_pgid {
1387 struct fw_port_dcb_pgrate {
1391 __u8 num_tcs_supported;
1395 struct fw_port_dcb_priorate {
1399 __u8 strict_priorate[8];
1401 struct fw_port_dcb_pfc {
1408 struct fw_port_app_priority {
1417 struct fw_port_dcb_control {
1420 __be16 dcb_version_to_app_state;
1425 struct fw_port_l1cfg32 {
1429 struct fw_port_info32 {
1430 __be32 lstatus32_to_cbllen32;
1431 __be32 auxlinfo32_mtu32;
1440 #define S_FW_PORT_CMD_PORTID 0
1441 #define M_FW_PORT_CMD_PORTID 0xf
1442 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1443 #define G_FW_PORT_CMD_PORTID(x) \
1444 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1446 #define S_FW_PORT_CMD_ACTION 16
1447 #define M_FW_PORT_CMD_ACTION 0xffff
1448 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1449 #define G_FW_PORT_CMD_ACTION(x) \
1450 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1452 #define S_FW_PORT_CMD_LSTATUS 31
1453 #define M_FW_PORT_CMD_LSTATUS 0x1
1454 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1455 #define G_FW_PORT_CMD_LSTATUS(x) \
1456 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1457 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1459 #define S_FW_PORT_CMD_LSPEED 24
1460 #define M_FW_PORT_CMD_LSPEED 0x3f
1461 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1462 #define G_FW_PORT_CMD_LSPEED(x) \
1463 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1465 #define S_FW_PORT_CMD_TXPAUSE 23
1466 #define M_FW_PORT_CMD_TXPAUSE 0x1
1467 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1468 #define G_FW_PORT_CMD_TXPAUSE(x) \
1469 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1470 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1472 #define S_FW_PORT_CMD_RXPAUSE 22
1473 #define M_FW_PORT_CMD_RXPAUSE 0x1
1474 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1475 #define G_FW_PORT_CMD_RXPAUSE(x) \
1476 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1477 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1479 #define S_FW_PORT_CMD_MDIOCAP 21
1480 #define M_FW_PORT_CMD_MDIOCAP 0x1
1481 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1482 #define G_FW_PORT_CMD_MDIOCAP(x) \
1483 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1484 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1486 #define S_FW_PORT_CMD_MDIOADDR 16
1487 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1488 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1489 #define G_FW_PORT_CMD_MDIOADDR(x) \
1490 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1492 #define S_FW_PORT_CMD_PTYPE 8
1493 #define M_FW_PORT_CMD_PTYPE 0x1f
1494 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1495 #define G_FW_PORT_CMD_PTYPE(x) \
1496 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1498 #define S_FW_PORT_CMD_LINKDNRC 5
1499 #define M_FW_PORT_CMD_LINKDNRC 0x7
1500 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1501 #define G_FW_PORT_CMD_LINKDNRC(x) \
1502 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1504 #define S_FW_PORT_CMD_MODTYPE 0
1505 #define M_FW_PORT_CMD_MODTYPE 0x1f
1506 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1507 #define G_FW_PORT_CMD_MODTYPE(x) \
1508 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1510 #define S_FW_PORT_CMD_LSTATUS32 31
1511 #define M_FW_PORT_CMD_LSTATUS32 0x1
1512 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1513 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1515 #define S_FW_PORT_CMD_LINKDNRC32 28
1516 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1517 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1518 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1520 #define S_FW_PORT_CMD_MDIOCAP32 26
1521 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1522 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1523 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1525 #define S_FW_PORT_CMD_MDIOADDR32 21
1526 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1527 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1528 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1530 #define S_FW_PORT_CMD_PORTTYPE32 13
1531 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1532 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1533 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1535 #define S_FW_PORT_CMD_MODTYPE32 8
1536 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1537 #define G_FW_PORT_CMD_MODTYPE32(x) \
1538 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1541 * These are configured into the VPD and hence tools that generate
1542 * VPD may use this enumeration.
1543 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1546 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1547 * with any new Firmware Port Technology Types!
1550 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1551 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1552 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1553 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1554 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1555 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1556 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1557 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1558 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1559 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1560 FW_PORT_TYPE_BP_AP = 10,
1561 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1562 FW_PORT_TYPE_BP4_AP = 11,
1563 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1564 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1565 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1566 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1567 FW_PORT_TYPE_BP40_BA = 15,
1568 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1569 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1570 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1571 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1572 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1573 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1574 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1575 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1578 /* These are read from module's EEPROM and determined once the
1579 * module is inserted.
1581 enum fw_port_module_type {
1582 FW_PORT_MOD_TYPE_NA = 0x0,
1583 FW_PORT_MOD_TYPE_LR = 0x1,
1584 FW_PORT_MOD_TYPE_SR = 0x2,
1585 FW_PORT_MOD_TYPE_ER = 0x3,
1586 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1587 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1588 FW_PORT_MOD_TYPE_LRM = 0x6,
1589 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1590 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1591 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1592 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1595 /* used by FW and tools may use this to generate VPD */
1596 enum fw_port_mod_sub_type {
1597 FW_PORT_MOD_SUB_TYPE_NA,
1598 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1599 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1600 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1601 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1602 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1603 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1604 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1605 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1608 * The following will never been in the VPD. They are TWINAX cable
1609 * lengths decoded from SFP+ module i2c PROMs. These should almost
1610 * certainly go somewhere else ...
1612 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1613 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1614 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1615 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1618 /* link down reason codes (3b) */
1619 enum fw_port_link_dn_rc {
1620 FW_PORT_LINK_DN_RC_NONE,
1621 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1622 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1623 FW_PORT_LINK_DN_RESERVED3,
1624 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1625 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1626 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1627 FW_PORT_LINK_DN_RESERVED7
1631 #define FW_NUM_PORT_STATS 50
1632 #define FW_NUM_PORT_TX_STATS 23
1633 #define FW_NUM_PORT_RX_STATS 27
1635 enum fw_port_stats_tx_index {
1636 FW_STAT_TX_PORT_BYTES_IX,
1637 FW_STAT_TX_PORT_FRAMES_IX,
1638 FW_STAT_TX_PORT_BCAST_IX,
1639 FW_STAT_TX_PORT_MCAST_IX,
1640 FW_STAT_TX_PORT_UCAST_IX,
1641 FW_STAT_TX_PORT_ERROR_IX,
1642 FW_STAT_TX_PORT_64B_IX,
1643 FW_STAT_TX_PORT_65B_127B_IX,
1644 FW_STAT_TX_PORT_128B_255B_IX,
1645 FW_STAT_TX_PORT_256B_511B_IX,
1646 FW_STAT_TX_PORT_512B_1023B_IX,
1647 FW_STAT_TX_PORT_1024B_1518B_IX,
1648 FW_STAT_TX_PORT_1519B_MAX_IX,
1649 FW_STAT_TX_PORT_DROP_IX,
1650 FW_STAT_TX_PORT_PAUSE_IX,
1651 FW_STAT_TX_PORT_PPP0_IX,
1652 FW_STAT_TX_PORT_PPP1_IX,
1653 FW_STAT_TX_PORT_PPP2_IX,
1654 FW_STAT_TX_PORT_PPP3_IX,
1655 FW_STAT_TX_PORT_PPP4_IX,
1656 FW_STAT_TX_PORT_PPP5_IX,
1657 FW_STAT_TX_PORT_PPP6_IX,
1658 FW_STAT_TX_PORT_PPP7_IX
1661 enum fw_port_stat_rx_index {
1662 FW_STAT_RX_PORT_BYTES_IX,
1663 FW_STAT_RX_PORT_FRAMES_IX,
1664 FW_STAT_RX_PORT_BCAST_IX,
1665 FW_STAT_RX_PORT_MCAST_IX,
1666 FW_STAT_RX_PORT_UCAST_IX,
1667 FW_STAT_RX_PORT_MTU_ERROR_IX,
1668 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1669 FW_STAT_RX_PORT_CRC_ERROR_IX,
1670 FW_STAT_RX_PORT_LEN_ERROR_IX,
1671 FW_STAT_RX_PORT_SYM_ERROR_IX,
1672 FW_STAT_RX_PORT_64B_IX,
1673 FW_STAT_RX_PORT_65B_127B_IX,
1674 FW_STAT_RX_PORT_128B_255B_IX,
1675 FW_STAT_RX_PORT_256B_511B_IX,
1676 FW_STAT_RX_PORT_512B_1023B_IX,
1677 FW_STAT_RX_PORT_1024B_1518B_IX,
1678 FW_STAT_RX_PORT_1519B_MAX_IX,
1679 FW_STAT_RX_PORT_PAUSE_IX,
1680 FW_STAT_RX_PORT_PPP0_IX,
1681 FW_STAT_RX_PORT_PPP1_IX,
1682 FW_STAT_RX_PORT_PPP2_IX,
1683 FW_STAT_RX_PORT_PPP3_IX,
1684 FW_STAT_RX_PORT_PPP4_IX,
1685 FW_STAT_RX_PORT_PPP5_IX,
1686 FW_STAT_RX_PORT_PPP6_IX,
1687 FW_STAT_RX_PORT_PPP7_IX,
1688 FW_STAT_RX_PORT_LESS_64B_IX
1691 struct fw_port_stats_cmd {
1692 __be32 op_to_portid;
1693 __be32 retval_len16;
1694 union fw_port_stats {
1695 struct fw_port_stats_ctl {
1707 struct fw_port_stats_all {
1716 __be64 tx_128b_255b;
1717 __be64 tx_256b_511b;
1718 __be64 tx_512b_1023b;
1719 __be64 tx_1024b_1518b;
1720 __be64 tx_1519b_max;
1736 __be64 rx_mtu_error;
1737 __be64 rx_mtu_crc_error;
1738 __be64 rx_crc_error;
1739 __be64 rx_len_error;
1740 __be64 rx_sym_error;
1743 __be64 rx_128b_255b;
1744 __be64 rx_256b_511b;
1745 __be64 rx_512b_1023b;
1746 __be64 rx_1024b_1518b;
1747 __be64 rx_1519b_max;
1764 struct fw_rss_ind_tbl_cmd {
1766 __be32 retval_len16;
1774 __be32 iq12_to_iq14;
1775 __be32 iq15_to_iq17;
1776 __be32 iq18_to_iq20;
1777 __be32 iq21_to_iq23;
1778 __be32 iq24_to_iq26;
1779 __be32 iq27_to_iq29;
1784 #define S_FW_RSS_IND_TBL_CMD_VIID 0
1785 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
1786 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
1787 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
1788 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
1790 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
1791 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
1792 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
1793 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
1794 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
1796 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
1797 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
1798 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
1799 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
1800 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
1802 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
1803 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
1804 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
1805 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
1806 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
1808 struct fw_rss_glb_config_cmd {
1810 __be32 retval_len16;
1811 union fw_rss_glb_config {
1812 struct fw_rss_glb_config_manual {
1818 struct fw_rss_glb_config_basicvirtual {
1819 __be32 mode_keymode;
1820 __be32 synmapen_to_hashtoeplitz;
1827 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
1828 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
1829 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
1830 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
1832 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
1834 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
1835 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
1836 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
1837 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
1839 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
1840 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
1841 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
1842 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
1843 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
1845 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
1846 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
1847 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
1848 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
1849 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
1851 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
1852 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
1853 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
1854 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
1855 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
1857 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
1858 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
1859 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
1860 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
1861 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
1863 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
1864 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
1865 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
1866 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
1868 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
1869 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
1870 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
1871 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
1873 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
1874 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
1875 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
1876 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
1877 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
1879 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
1880 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
1881 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
1882 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
1883 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
1885 struct fw_rss_vi_config_cmd {
1887 __be32 retval_len16;
1888 union fw_rss_vi_config {
1889 struct fw_rss_vi_config_manual {
1894 struct fw_rss_vi_config_basicvirtual {
1896 __be32 defaultq_to_udpen;
1903 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
1904 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
1905 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
1906 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
1907 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
1909 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
1910 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
1911 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1912 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1913 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1914 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
1915 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1917 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
1918 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
1919 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1920 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1921 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1922 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
1923 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1924 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
1925 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
1927 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
1928 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
1929 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1930 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1931 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1932 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
1933 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1934 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
1935 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
1937 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
1938 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
1939 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
1940 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1941 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
1942 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
1943 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1944 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
1945 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
1947 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
1948 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
1949 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
1950 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1951 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
1952 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
1953 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1954 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
1955 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
1957 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
1958 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
1959 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
1960 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
1961 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
1962 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
1964 /******************************************************************************
1965 * D E B U G C O M M A N D s
1966 ******************************************************/
1968 struct fw_debug_cmd {
1972 struct fw_debug_assert {
1977 __u8 filename_0_7[8];
1978 __u8 filename_8_15[8];
1981 struct fw_debug_prt {
1984 __be32 dprtstrparam0;
1985 __be32 dprtstrparam1;
1986 __be32 dprtstrparam2;
1987 __be32 dprtstrparam3;
1992 #define S_FW_DEBUG_CMD_TYPE 0
1993 #define M_FW_DEBUG_CMD_TYPE 0xff
1994 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
1995 #define G_FW_DEBUG_CMD_TYPE(x) \
1996 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
1998 /******************************************************************************
1999 * P C I E F W R E G I S T E R
2000 **************************************/
2003 * Register definitions for the PCIE_FW register which the firmware uses
2004 * to retain status across RESETs. This register should be considered
2005 * as a READ-ONLY register for Host Software and only to be used to
2006 * track firmware initialization/error state, etc.
2008 #define S_PCIE_FW_ERR 31
2009 #define M_PCIE_FW_ERR 0x1
2010 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2011 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2012 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2014 #define S_PCIE_FW_INIT 30
2015 #define M_PCIE_FW_INIT 0x1
2016 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2017 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2018 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2020 #define S_PCIE_FW_HALT 29
2021 #define M_PCIE_FW_HALT 0x1
2022 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2023 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2024 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2026 #define S_PCIE_FW_EVAL 24
2027 #define M_PCIE_FW_EVAL 0x7
2028 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2029 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2031 #define S_PCIE_FW_MASTER_VLD 15
2032 #define M_PCIE_FW_MASTER_VLD 0x1
2033 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2034 #define G_PCIE_FW_MASTER_VLD(x) \
2035 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2036 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2038 #define S_PCIE_FW_MASTER 12
2039 #define M_PCIE_FW_MASTER 0x7
2040 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2041 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2043 /******************************************************************************
2044 * B I N A R Y H E A D E R F O R M A T
2045 **********************************************/
2048 * firmware binary header format
2052 __u8 chip; /* terminator chip family */
2053 __be16 len512; /* bin length in units of 512-bytes */
2054 __be32 fw_ver; /* firmware version */
2055 __be32 tp_microcode_ver; /* tcp processor microcode version */
2060 __u8 intfver_iscsipdu;
2062 __u8 intfver_fcoepdu;
2066 __u32 magic; /* runtime or bootstrap fw */
2068 __be32 reserved6[23];
2071 #define S_FW_HDR_FW_VER_MAJOR 24
2072 #define M_FW_HDR_FW_VER_MAJOR 0xff
2073 #define V_FW_HDR_FW_VER_MAJOR(x) \
2074 ((x) << S_FW_HDR_FW_VER_MAJOR)
2075 #define G_FW_HDR_FW_VER_MAJOR(x) \
2076 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2078 #define S_FW_HDR_FW_VER_MINOR 16
2079 #define M_FW_HDR_FW_VER_MINOR 0xff
2080 #define V_FW_HDR_FW_VER_MINOR(x) \
2081 ((x) << S_FW_HDR_FW_VER_MINOR)
2082 #define G_FW_HDR_FW_VER_MINOR(x) \
2083 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2085 #define S_FW_HDR_FW_VER_MICRO 8
2086 #define M_FW_HDR_FW_VER_MICRO 0xff
2087 #define V_FW_HDR_FW_VER_MICRO(x) \
2088 ((x) << S_FW_HDR_FW_VER_MICRO)
2089 #define G_FW_HDR_FW_VER_MICRO(x) \
2090 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2092 #define S_FW_HDR_FW_VER_BUILD 0
2093 #define M_FW_HDR_FW_VER_BUILD 0xff
2094 #define V_FW_HDR_FW_VER_BUILD(x) \
2095 ((x) << S_FW_HDR_FW_VER_BUILD)
2096 #define G_FW_HDR_FW_VER_BUILD(x) \
2097 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2099 #endif /* _T4FW_INTERFACE_H_ */