1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
57 FW_ETH_TX_PKT_WR = 0x08,
58 FW_ETH_TX_PKTS_WR = 0x09,
59 FW_ETH_TX_PKT_VM_WR = 0x11,
60 FW_ETH_TX_PKTS_VM_WR = 0x12,
61 FW_ETH_TX_PKTS2_WR = 0x78,
65 * Generic work request header flit0
72 /* work request opcode (hi)
75 #define M_FW_WR_OP 0xff
76 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
77 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
79 /* work request immediate data length (hi)
81 #define S_FW_WR_IMMDLEN 0
82 #define M_FW_WR_IMMDLEN 0xff
83 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
84 #define G_FW_WR_IMMDLEN(x) \
85 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
87 /* egress queue status update to egress queue status entry (lo)
89 #define S_FW_WR_EQUEQ 30
90 #define M_FW_WR_EQUEQ 0x1
91 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
92 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
93 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
95 /* length in units of 16-bytes (lo)
97 #define S_FW_WR_LEN16 0
98 #define M_FW_WR_LEN16 0xff
99 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
100 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
102 struct fw_eth_tx_pkt_wr {
104 __be32 equiq_to_len16;
108 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
109 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
110 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
111 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
112 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
114 struct fw_eth_tx_pkts_wr {
116 __be32 equiq_to_len16;
123 struct fw_eth_tx_pkt_vm_wr {
125 __be32 equiq_to_len16;
133 struct fw_eth_tx_pkts_vm_wr {
135 __be32 equiq_to_len16;
146 /******************************************************************************
148 *********************/
151 * The maximum length of time, in miliseconds, that we expect any firmware
152 * command to take to execute and return a reply to the host. The RESET
153 * and INITIALIZE commands can take a fair amount of time to execute but
154 * most execute in far less time than this maximum. This constant is used
155 * by host software to determine how long to wait for a firmware command
156 * reply before declaring the firmware as dead/unreachable ...
158 #define FW_CMD_MAX_TIMEOUT 10000
161 * If a host driver does a HELLO and discovers that there's already a MASTER
162 * selected, we may have to wait for that MASTER to finish issuing RESET,
163 * configuration and INITIALIZE commands. Also, there's a possibility that
164 * our own HELLO may get lost if it happens right as the MASTER is issuign a
165 * RESET command, so we need to be willing to make a few retries of our HELLO.
167 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
168 #define FW_CMD_HELLO_RETRIES 3
170 enum fw_cmd_opcodes {
175 FW_INITIALIZE_CMD = 0x06,
176 FW_CAPS_CONFIG_CMD = 0x07,
177 FW_PARAMS_CMD = 0x08,
180 FW_EQ_ETH_CMD = 0x12,
181 FW_EQ_CTRL_CMD = 0x13,
183 FW_VI_MAC_CMD = 0x15,
184 FW_VI_RXMODE_CMD = 0x16,
185 FW_VI_ENABLE_CMD = 0x17,
186 FW_VI_STATS_CMD = 0x1a,
188 FW_RSS_IND_TBL_CMD = 0x20,
189 FW_RSS_GLB_CONFIG_CMD = 0x22,
190 FW_RSS_VI_CONFIG_CMD = 0x23,
195 FW_CMD_CAP_PORT = 0x04,
199 * Generic command header flit0
206 #define S_FW_CMD_OP 24
207 #define M_FW_CMD_OP 0xff
208 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
209 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
211 #define S_FW_CMD_REQUEST 23
212 #define M_FW_CMD_REQUEST 0x1
213 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
214 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
215 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
217 #define S_FW_CMD_READ 22
218 #define M_FW_CMD_READ 0x1
219 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
220 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
221 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
223 #define S_FW_CMD_WRITE 21
224 #define M_FW_CMD_WRITE 0x1
225 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
226 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
227 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
229 #define S_FW_CMD_EXEC 20
230 #define M_FW_CMD_EXEC 0x1
231 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
232 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
233 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
235 #define S_FW_CMD_RETVAL 8
236 #define M_FW_CMD_RETVAL 0xff
237 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
238 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
240 #define S_FW_CMD_LEN16 0
241 #define M_FW_CMD_LEN16 0xff
242 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
243 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
245 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
249 enum fw_ldst_addrspc {
250 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
254 __be32 op_to_addrspace;
255 __be32 cycles_to_len16;
257 struct fw_ldst_addrval {
261 struct fw_ldst_idctxt {
263 __be32 msg_ctxtflush;
273 struct fw_ldst_mdio {
289 struct fw_ldst_func {
297 struct fw_ldst_pcie {
307 struct fw_ldst_i2c_deprecated {
331 #define S_FW_LDST_CMD_ADDRSPACE 0
332 #define M_FW_LDST_CMD_ADDRSPACE 0xff
333 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
335 struct fw_reset_cmd {
342 #define S_FW_RESET_CMD_HALT 31
343 #define M_FW_RESET_CMD_HALT 0x1
344 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
345 #define G_FW_RESET_CMD_HALT(x) \
346 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
347 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
350 FW_HELLO_CMD_STAGE_OS = 0,
353 struct fw_hello_cmd {
356 __be32 err_to_clearinit;
360 #define S_FW_HELLO_CMD_ERR 31
361 #define M_FW_HELLO_CMD_ERR 0x1
362 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
363 #define G_FW_HELLO_CMD_ERR(x) \
364 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
365 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
367 #define S_FW_HELLO_CMD_INIT 30
368 #define M_FW_HELLO_CMD_INIT 0x1
369 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
370 #define G_FW_HELLO_CMD_INIT(x) \
371 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
372 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
374 #define S_FW_HELLO_CMD_MASTERDIS 29
375 #define M_FW_HELLO_CMD_MASTERDIS 0x1
376 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
377 #define G_FW_HELLO_CMD_MASTERDIS(x) \
378 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
379 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
381 #define S_FW_HELLO_CMD_MASTERFORCE 28
382 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
383 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
384 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
385 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
386 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
388 #define S_FW_HELLO_CMD_MBMASTER 24
389 #define M_FW_HELLO_CMD_MBMASTER 0xf
390 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
391 #define G_FW_HELLO_CMD_MBMASTER(x) \
392 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
394 #define S_FW_HELLO_CMD_MBASYNCNOT 20
395 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
396 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
397 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
398 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
400 #define S_FW_HELLO_CMD_STAGE 17
401 #define M_FW_HELLO_CMD_STAGE 0x7
402 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
403 #define G_FW_HELLO_CMD_STAGE(x) \
404 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
406 #define S_FW_HELLO_CMD_CLEARINIT 16
407 #define M_FW_HELLO_CMD_CLEARINIT 0x1
408 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
409 #define G_FW_HELLO_CMD_CLEARINIT(x) \
410 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
411 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
419 struct fw_initialize_cmd {
425 enum fw_caps_config_nic {
426 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
427 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
431 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
434 struct fw_caps_config_cmd {
436 __be32 cfvalid_to_len16;
454 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
455 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
456 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
457 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
458 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
459 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
461 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
462 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
463 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
464 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
465 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
466 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
467 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
469 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
470 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
471 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
472 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
473 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
474 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
475 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
478 * params command mnemonics
480 enum fw_params_mnem {
481 FW_PARAMS_MNEM_DEV = 1, /* device params */
482 FW_PARAMS_MNEM_PFVF = 2, /* function params */
483 FW_PARAMS_MNEM_REG = 3, /* limited register access */
484 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
490 enum fw_params_param_dev {
491 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
492 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
493 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
494 * allocated by the device's
497 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
498 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
499 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
503 * physical and virtual function parameters
505 enum fw_params_param_pfvf {
506 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
507 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
508 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
509 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
513 * dma queue parameters
515 enum fw_params_param_dmaq {
516 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
517 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
520 #define S_FW_PARAMS_MNEM 24
521 #define M_FW_PARAMS_MNEM 0xff
522 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
523 #define G_FW_PARAMS_MNEM(x) \
524 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
526 #define S_FW_PARAMS_PARAM_X 16
527 #define M_FW_PARAMS_PARAM_X 0xff
528 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
529 #define G_FW_PARAMS_PARAM_X(x) \
530 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
532 #define S_FW_PARAMS_PARAM_Y 8
533 #define M_FW_PARAMS_PARAM_Y 0xff
534 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
535 #define G_FW_PARAMS_PARAM_Y(x) \
536 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
538 #define S_FW_PARAMS_PARAM_Z 0
539 #define M_FW_PARAMS_PARAM_Z 0xff
540 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
541 #define G_FW_PARAMS_PARAM_Z(x) \
542 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
544 #define S_FW_PARAMS_PARAM_YZ 0
545 #define M_FW_PARAMS_PARAM_YZ 0xffff
546 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
547 #define G_FW_PARAMS_PARAM_YZ(x) \
548 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
550 #define S_FW_PARAMS_PARAM_XYZ 0
551 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
552 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
554 struct fw_params_cmd {
557 struct fw_params_param {
563 #define S_FW_PARAMS_CMD_PFN 8
564 #define M_FW_PARAMS_CMD_PFN 0x7
565 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
566 #define G_FW_PARAMS_CMD_PFN(x) \
567 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
569 #define S_FW_PARAMS_CMD_VFN 0
570 #define M_FW_PARAMS_CMD_VFN 0xff
571 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
572 #define G_FW_PARAMS_CMD_VFN(x) \
573 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
580 __be32 tc_to_nexactf;
581 __be32 r_caps_to_nethctrl;
587 #define S_FW_PFVF_CMD_NIQFLINT 20
588 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
589 #define G_FW_PFVF_CMD_NIQFLINT(x) \
590 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
592 #define S_FW_PFVF_CMD_NIQ 0
593 #define M_FW_PFVF_CMD_NIQ 0xfffff
594 #define G_FW_PFVF_CMD_NIQ(x) \
595 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
597 #define S_FW_PFVF_CMD_PMASK 20
598 #define M_FW_PFVF_CMD_PMASK 0xf
599 #define G_FW_PFVF_CMD_PMASK(x) \
600 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
602 #define S_FW_PFVF_CMD_NEQ 0
603 #define M_FW_PFVF_CMD_NEQ 0xfffff
604 #define G_FW_PFVF_CMD_NEQ(x) \
605 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
607 #define S_FW_PFVF_CMD_TC 24
608 #define M_FW_PFVF_CMD_TC 0xff
609 #define G_FW_PFVF_CMD_TC(x) \
610 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
612 #define S_FW_PFVF_CMD_NVI 16
613 #define M_FW_PFVF_CMD_NVI 0xff
614 #define G_FW_PFVF_CMD_NVI(x) \
615 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
617 #define S_FW_PFVF_CMD_NEXACTF 0
618 #define M_FW_PFVF_CMD_NEXACTF 0xffff
619 #define G_FW_PFVF_CMD_NEXACTF(x) \
620 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
622 #define S_FW_PFVF_CMD_R_CAPS 24
623 #define M_FW_PFVF_CMD_R_CAPS 0xff
624 #define G_FW_PFVF_CMD_R_CAPS(x) \
625 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
627 #define S_FW_PFVF_CMD_WX_CAPS 16
628 #define M_FW_PFVF_CMD_WX_CAPS 0xff
629 #define G_FW_PFVF_CMD_WX_CAPS(x) \
630 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
632 #define S_FW_PFVF_CMD_NETHCTRL 0
633 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
634 #define G_FW_PFVF_CMD_NETHCTRL(x) \
635 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
638 * ingress queue type; the first 1K ingress queues can have associated 0,
639 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
643 FW_IQ_TYPE_FL_INT_CAP,
648 __be32 alloc_to_len16;
653 __be32 type_to_iqandstindex;
654 __be16 iqdroprss_to_iqesize;
657 __be32 iqns_to_fl0congen;
658 __be16 fl0dcaen_to_fl0cidxfthresh;
661 __be32 fl1cngchmap_to_fl1congen;
662 __be16 fl1dcaen_to_fl1cidxfthresh;
667 #define S_FW_IQ_CMD_PFN 8
668 #define M_FW_IQ_CMD_PFN 0x7
669 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
670 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
672 #define S_FW_IQ_CMD_VFN 0
673 #define M_FW_IQ_CMD_VFN 0xff
674 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
675 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
677 #define S_FW_IQ_CMD_ALLOC 31
678 #define M_FW_IQ_CMD_ALLOC 0x1
679 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
680 #define G_FW_IQ_CMD_ALLOC(x) \
681 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
682 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
684 #define S_FW_IQ_CMD_FREE 30
685 #define M_FW_IQ_CMD_FREE 0x1
686 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
687 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
688 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
690 #define S_FW_IQ_CMD_IQSTART 28
691 #define M_FW_IQ_CMD_IQSTART 0x1
692 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
693 #define G_FW_IQ_CMD_IQSTART(x) \
694 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
695 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
697 #define S_FW_IQ_CMD_IQSTOP 27
698 #define M_FW_IQ_CMD_IQSTOP 0x1
699 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
700 #define G_FW_IQ_CMD_IQSTOP(x) \
701 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
702 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
704 #define S_FW_IQ_CMD_TYPE 29
705 #define M_FW_IQ_CMD_TYPE 0x7
706 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
707 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
709 #define S_FW_IQ_CMD_IQASYNCH 28
710 #define M_FW_IQ_CMD_IQASYNCH 0x1
711 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
712 #define G_FW_IQ_CMD_IQASYNCH(x) \
713 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
714 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
716 #define S_FW_IQ_CMD_VIID 16
717 #define M_FW_IQ_CMD_VIID 0xfff
718 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
719 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
721 #define S_FW_IQ_CMD_IQANDST 15
722 #define M_FW_IQ_CMD_IQANDST 0x1
723 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
724 #define G_FW_IQ_CMD_IQANDST(x) \
725 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
726 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
728 #define S_FW_IQ_CMD_IQANUD 12
729 #define M_FW_IQ_CMD_IQANUD 0x3
730 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
731 #define G_FW_IQ_CMD_IQANUD(x) \
732 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
734 #define S_FW_IQ_CMD_IQANDSTINDEX 0
735 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
736 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
737 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
738 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
740 #define S_FW_IQ_CMD_IQGTSMODE 14
741 #define M_FW_IQ_CMD_IQGTSMODE 0x1
742 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
743 #define G_FW_IQ_CMD_IQGTSMODE(x) \
744 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
745 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
747 #define S_FW_IQ_CMD_IQPCIECH 12
748 #define M_FW_IQ_CMD_IQPCIECH 0x3
749 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
750 #define G_FW_IQ_CMD_IQPCIECH(x) \
751 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
753 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
754 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
755 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
756 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
757 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
759 #define S_FW_IQ_CMD_IQESIZE 0
760 #define M_FW_IQ_CMD_IQESIZE 0x3
761 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
762 #define G_FW_IQ_CMD_IQESIZE(x) \
763 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
765 #define S_FW_IQ_CMD_IQRO 30
766 #define M_FW_IQ_CMD_IQRO 0x1
767 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
768 #define G_FW_IQ_CMD_IQRO(x) \
769 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
770 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
772 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
773 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
774 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
775 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
776 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
777 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
779 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
780 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
781 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
782 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
783 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
785 #define S_FW_IQ_CMD_FL0DATARO 12
786 #define M_FW_IQ_CMD_FL0DATARO 0x1
787 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
788 #define G_FW_IQ_CMD_FL0DATARO(x) \
789 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
790 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
792 #define S_FW_IQ_CMD_FL0CONGCIF 11
793 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
794 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
795 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
796 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
797 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
799 #define S_FW_IQ_CMD_FL0FETCHRO 6
800 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
801 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
802 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
803 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
804 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
806 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
807 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
808 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
809 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
810 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
812 #define S_FW_IQ_CMD_FL0PADEN 2
813 #define M_FW_IQ_CMD_FL0PADEN 0x1
814 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
815 #define G_FW_IQ_CMD_FL0PADEN(x) \
816 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
817 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
819 #define S_FW_IQ_CMD_FL0PACKEN 1
820 #define M_FW_IQ_CMD_FL0PACKEN 0x1
821 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
822 #define G_FW_IQ_CMD_FL0PACKEN(x) \
823 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
824 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
826 #define S_FW_IQ_CMD_FL0CONGEN 0
827 #define M_FW_IQ_CMD_FL0CONGEN 0x1
828 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
829 #define G_FW_IQ_CMD_FL0CONGEN(x) \
830 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
831 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
833 #define S_FW_IQ_CMD_FL0FBMIN 7
834 #define M_FW_IQ_CMD_FL0FBMIN 0x7
835 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
836 #define G_FW_IQ_CMD_FL0FBMIN(x) \
837 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
839 #define S_FW_IQ_CMD_FL0FBMAX 4
840 #define M_FW_IQ_CMD_FL0FBMAX 0x7
841 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
842 #define G_FW_IQ_CMD_FL0FBMAX(x) \
843 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
845 struct fw_eq_eth_cmd {
847 __be32 alloc_to_len16;
850 __be32 fetchszm_to_iqid;
851 __be32 dcaen_to_eqsize;
853 __be32 autoequiqe_to_viid;
858 #define S_FW_EQ_ETH_CMD_PFN 8
859 #define M_FW_EQ_ETH_CMD_PFN 0x7
860 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
861 #define G_FW_EQ_ETH_CMD_PFN(x) \
862 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
864 #define S_FW_EQ_ETH_CMD_VFN 0
865 #define M_FW_EQ_ETH_CMD_VFN 0xff
866 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
867 #define G_FW_EQ_ETH_CMD_VFN(x) \
868 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
870 #define S_FW_EQ_ETH_CMD_ALLOC 31
871 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
872 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
873 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
874 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
875 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
877 #define S_FW_EQ_ETH_CMD_FREE 30
878 #define M_FW_EQ_ETH_CMD_FREE 0x1
879 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
880 #define G_FW_EQ_ETH_CMD_FREE(x) \
881 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
882 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
884 #define S_FW_EQ_ETH_CMD_EQSTART 28
885 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
886 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
887 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
888 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
889 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
891 #define S_FW_EQ_ETH_CMD_EQID 0
892 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
893 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
894 #define G_FW_EQ_ETH_CMD_EQID(x) \
895 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
897 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
898 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
899 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
900 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
902 #define S_FW_EQ_ETH_CMD_FETCHRO 22
903 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
904 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
905 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
906 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
907 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
909 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
910 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
911 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
912 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
913 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
915 #define S_FW_EQ_ETH_CMD_PCIECHN 16
916 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
917 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
918 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
919 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
921 #define S_FW_EQ_ETH_CMD_IQID 0
922 #define M_FW_EQ_ETH_CMD_IQID 0xffff
923 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
924 #define G_FW_EQ_ETH_CMD_IQID(x) \
925 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
927 #define S_FW_EQ_ETH_CMD_FBMIN 23
928 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
929 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
930 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
931 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
933 #define S_FW_EQ_ETH_CMD_FBMAX 20
934 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
935 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
936 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
937 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
939 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
940 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
941 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
942 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
943 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
945 #define S_FW_EQ_ETH_CMD_EQSIZE 0
946 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
947 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
948 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
949 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
951 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
952 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
953 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
954 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
955 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
956 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
958 #define S_FW_EQ_ETH_CMD_VIID 16
959 #define M_FW_EQ_ETH_CMD_VIID 0xfff
960 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
961 #define G_FW_EQ_ETH_CMD_VIID(x) \
962 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
964 struct fw_eq_ctrl_cmd {
966 __be32 alloc_to_len16;
967 __be32 cmpliqid_eqid;
969 __be32 fetchszm_to_iqid;
970 __be32 dcaen_to_eqsize;
974 #define S_FW_EQ_CTRL_CMD_PFN 8
975 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
977 #define S_FW_EQ_CTRL_CMD_VFN 0
978 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
980 #define S_FW_EQ_CTRL_CMD_ALLOC 31
981 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
982 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
984 #define S_FW_EQ_CTRL_CMD_FREE 30
985 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
986 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
988 #define S_FW_EQ_CTRL_CMD_EQSTART 28
989 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
990 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
992 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
993 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
995 #define S_FW_EQ_CTRL_CMD_EQID 0
996 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
997 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
998 #define G_FW_EQ_CTRL_CMD_EQID(x) \
999 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1001 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1002 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1003 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1004 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1005 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1007 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1008 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1009 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1011 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1012 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1013 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1015 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1016 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1018 #define S_FW_EQ_CTRL_CMD_IQID 0
1019 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1021 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1022 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1024 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1025 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1027 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1028 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1030 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1031 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1039 __be32 alloc_to_len16;
1040 __be16 type_to_viid;
1045 __be16 norss_rsssize;
1055 #define S_FW_VI_CMD_PFN 8
1056 #define M_FW_VI_CMD_PFN 0x7
1057 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1058 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1060 #define S_FW_VI_CMD_VFN 0
1061 #define M_FW_VI_CMD_VFN 0xff
1062 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1063 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1065 #define S_FW_VI_CMD_ALLOC 31
1066 #define M_FW_VI_CMD_ALLOC 0x1
1067 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1068 #define G_FW_VI_CMD_ALLOC(x) \
1069 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1070 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1072 #define S_FW_VI_CMD_FREE 30
1073 #define M_FW_VI_CMD_FREE 0x1
1074 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1075 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1076 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1078 #define S_FW_VI_CMD_TYPE 15
1079 #define M_FW_VI_CMD_TYPE 0x1
1080 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1081 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1082 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1084 #define S_FW_VI_CMD_FUNC 12
1085 #define M_FW_VI_CMD_FUNC 0x7
1086 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1087 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1089 #define S_FW_VI_CMD_VIID 0
1090 #define M_FW_VI_CMD_VIID 0xfff
1091 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1092 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1094 #define S_FW_VI_CMD_PORTID 4
1095 #define M_FW_VI_CMD_PORTID 0xf
1096 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1097 #define G_FW_VI_CMD_PORTID(x) \
1098 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1100 #define S_FW_VI_CMD_RSSSIZE 0
1101 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1102 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1103 #define G_FW_VI_CMD_RSSSIZE(x) \
1104 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1106 /* Special VI_MAC command index ids */
1107 #define FW_VI_MAC_ADD_MAC 0x3FF
1108 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1110 enum fw_vi_mac_smac {
1111 FW_VI_MAC_MPS_TCAM_ENTRY,
1112 FW_VI_MAC_SMT_AND_MPSTCAM
1115 struct fw_vi_mac_cmd {
1117 __be32 freemacs_to_len16;
1119 struct fw_vi_mac_exact {
1120 __be16 valid_to_idx;
1123 struct fw_vi_mac_hash {
1129 #define S_FW_VI_MAC_CMD_VIID 0
1130 #define M_FW_VI_MAC_CMD_VIID 0xfff
1131 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1132 #define G_FW_VI_MAC_CMD_VIID(x) \
1133 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1135 #define S_FW_VI_MAC_CMD_VALID 15
1136 #define M_FW_VI_MAC_CMD_VALID 0x1
1137 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1138 #define G_FW_VI_MAC_CMD_VALID(x) \
1139 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1140 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1142 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1143 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1144 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1145 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1146 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1148 #define S_FW_VI_MAC_CMD_IDX 0
1149 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1150 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1151 #define G_FW_VI_MAC_CMD_IDX(x) \
1152 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1154 struct fw_vi_rxmode_cmd {
1156 __be32 retval_len16;
1157 __be32 mtu_to_vlanexen;
1161 #define S_FW_VI_RXMODE_CMD_VIID 0
1162 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1163 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1164 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1165 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1167 #define S_FW_VI_RXMODE_CMD_MTU 16
1168 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1169 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1170 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1171 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1173 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1174 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1175 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1176 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1177 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1179 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1180 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1181 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1182 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1183 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1184 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1186 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1187 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1188 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1189 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1190 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1191 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1192 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1194 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1195 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1196 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1197 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1198 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1200 struct fw_vi_enable_cmd {
1202 __be32 ien_to_len16;
1208 #define S_FW_VI_ENABLE_CMD_VIID 0
1209 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1210 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1211 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1212 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1214 #define S_FW_VI_ENABLE_CMD_IEN 31
1215 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1216 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1217 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1218 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1219 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1221 #define S_FW_VI_ENABLE_CMD_EEN 30
1222 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1223 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1224 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1225 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1226 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1228 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1229 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1230 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1231 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1232 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1233 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1235 /* VI VF stats offset definitions */
1236 #define VI_VF_NUM_STATS 16
1238 /* VI PF stats offset definitions */
1239 #define VI_PF_NUM_STATS 17
1240 enum fw_vi_stats_pf_index {
1241 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1242 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1243 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1244 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1245 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1246 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1247 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1248 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1249 FW_VI_PF_STAT_RX_BYTES_IX,
1250 FW_VI_PF_STAT_RX_FRAMES_IX,
1251 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1252 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1253 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1254 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1255 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1256 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1257 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1260 struct fw_vi_stats_cmd {
1262 __be32 retval_len16;
1264 struct fw_vi_stats_ctl {
1275 struct fw_vi_stats_pf {
1276 __be64 tx_bcast_bytes;
1277 __be64 tx_bcast_frames;
1278 __be64 tx_mcast_bytes;
1279 __be64 tx_mcast_frames;
1280 __be64 tx_ucast_bytes;
1281 __be64 tx_ucast_frames;
1282 __be64 tx_offload_bytes;
1283 __be64 tx_offload_frames;
1285 __be64 rx_pf_frames;
1286 __be64 rx_bcast_bytes;
1287 __be64 rx_bcast_frames;
1288 __be64 rx_mcast_bytes;
1289 __be64 rx_mcast_frames;
1290 __be64 rx_ucast_bytes;
1291 __be64 rx_ucast_frames;
1292 __be64 rx_err_frames;
1294 struct fw_vi_stats_vf {
1295 __be64 tx_bcast_bytes;
1296 __be64 tx_bcast_frames;
1297 __be64 tx_mcast_bytes;
1298 __be64 tx_mcast_frames;
1299 __be64 tx_ucast_bytes;
1300 __be64 tx_ucast_frames;
1301 __be64 tx_drop_frames;
1302 __be64 tx_offload_bytes;
1303 __be64 tx_offload_frames;
1304 __be64 rx_bcast_bytes;
1305 __be64 rx_bcast_frames;
1306 __be64 rx_mcast_bytes;
1307 __be64 rx_mcast_frames;
1308 __be64 rx_ucast_bytes;
1309 __be64 rx_ucast_frames;
1310 __be64 rx_err_frames;
1315 #define S_FW_VI_STATS_CMD_VIID 0
1316 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1318 #define S_FW_VI_STATS_CMD_NSTATS 12
1319 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1321 #define S_FW_VI_STATS_CMD_IX 0
1322 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1324 /* old 16-bit port capabilities bitmap */
1326 FW_PORT_CAP_SPEED_100M = 0x0001,
1327 FW_PORT_CAP_SPEED_1G = 0x0002,
1328 FW_PORT_CAP_SPEED_25G = 0x0004,
1329 FW_PORT_CAP_SPEED_10G = 0x0008,
1330 FW_PORT_CAP_SPEED_40G = 0x0010,
1331 FW_PORT_CAP_SPEED_100G = 0x0020,
1332 FW_PORT_CAP_FC_RX = 0x0040,
1333 FW_PORT_CAP_FC_TX = 0x0080,
1334 FW_PORT_CAP_ANEG = 0x0100,
1335 FW_PORT_CAP_MDIX = 0x0200,
1336 FW_PORT_CAP_MDIAUTO = 0x0400,
1337 FW_PORT_CAP_FEC_RS = 0x0800,
1338 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1339 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1340 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1341 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1344 #define S_FW_PORT_CAP_SPEED 0
1345 #define M_FW_PORT_CAP_SPEED 0x3f
1346 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1347 #define G_FW_PORT_CAP_SPEED(x) \
1348 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1351 FW_PORT_CAP_MDI_AUTO,
1354 #define S_FW_PORT_CAP_MDI 9
1355 #define M_FW_PORT_CAP_MDI 3
1356 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1357 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1359 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1360 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1361 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1362 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1363 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1364 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1365 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1366 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1367 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1368 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1369 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1370 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1371 #define FW_PORT_CAP32_ANEG 0x00100000UL
1372 #define FW_PORT_CAP32_MDIX 0x00200000UL
1373 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1374 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1375 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1377 #define S_FW_PORT_CAP32_SPEED 0
1378 #define M_FW_PORT_CAP32_SPEED 0xfff
1379 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1380 #define G_FW_PORT_CAP32_SPEED(x) \
1381 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1383 enum fw_port_mdi32 {
1384 FW_PORT_CAP32_MDI_AUTO,
1387 #define S_FW_PORT_CAP32_MDI 21
1388 #define M_FW_PORT_CAP32_MDI 3
1389 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1390 #define G_FW_PORT_CAP32_MDI(x) \
1391 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1393 enum fw_port_action {
1394 FW_PORT_ACTION_L1_CFG = 0x0001,
1395 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1396 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1397 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1400 struct fw_port_cmd {
1401 __be32 op_to_portid;
1402 __be32 action_to_len16;
1404 struct fw_port_l1cfg {
1408 struct fw_port_l2cfg {
1410 __u8 ovlan3_to_ivlan0;
1412 __be16 txipg_force_pinfo;
1423 struct fw_port_info {
1424 __be32 lstatus_to_modtype;
1435 struct fw_port_diags {
1441 struct fw_port_dcb_pgid {
1448 struct fw_port_dcb_pgrate {
1452 __u8 num_tcs_supported;
1456 struct fw_port_dcb_priorate {
1460 __u8 strict_priorate[8];
1462 struct fw_port_dcb_pfc {
1469 struct fw_port_app_priority {
1478 struct fw_port_dcb_control {
1481 __be16 dcb_version_to_app_state;
1486 struct fw_port_l1cfg32 {
1490 struct fw_port_info32 {
1491 __be32 lstatus32_to_cbllen32;
1492 __be32 auxlinfo32_mtu32;
1501 #define S_FW_PORT_CMD_PORTID 0
1502 #define M_FW_PORT_CMD_PORTID 0xf
1503 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1504 #define G_FW_PORT_CMD_PORTID(x) \
1505 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1507 #define S_FW_PORT_CMD_ACTION 16
1508 #define M_FW_PORT_CMD_ACTION 0xffff
1509 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1510 #define G_FW_PORT_CMD_ACTION(x) \
1511 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1513 #define S_FW_PORT_CMD_LSTATUS 31
1514 #define M_FW_PORT_CMD_LSTATUS 0x1
1515 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1516 #define G_FW_PORT_CMD_LSTATUS(x) \
1517 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1518 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1520 #define S_FW_PORT_CMD_LSPEED 24
1521 #define M_FW_PORT_CMD_LSPEED 0x3f
1522 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1523 #define G_FW_PORT_CMD_LSPEED(x) \
1524 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1526 #define S_FW_PORT_CMD_TXPAUSE 23
1527 #define M_FW_PORT_CMD_TXPAUSE 0x1
1528 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1529 #define G_FW_PORT_CMD_TXPAUSE(x) \
1530 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1531 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1533 #define S_FW_PORT_CMD_RXPAUSE 22
1534 #define M_FW_PORT_CMD_RXPAUSE 0x1
1535 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1536 #define G_FW_PORT_CMD_RXPAUSE(x) \
1537 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1538 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1540 #define S_FW_PORT_CMD_MDIOCAP 21
1541 #define M_FW_PORT_CMD_MDIOCAP 0x1
1542 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1543 #define G_FW_PORT_CMD_MDIOCAP(x) \
1544 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1545 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1547 #define S_FW_PORT_CMD_MDIOADDR 16
1548 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1549 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1550 #define G_FW_PORT_CMD_MDIOADDR(x) \
1551 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1553 #define S_FW_PORT_CMD_PTYPE 8
1554 #define M_FW_PORT_CMD_PTYPE 0x1f
1555 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1556 #define G_FW_PORT_CMD_PTYPE(x) \
1557 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1559 #define S_FW_PORT_CMD_LINKDNRC 5
1560 #define M_FW_PORT_CMD_LINKDNRC 0x7
1561 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1562 #define G_FW_PORT_CMD_LINKDNRC(x) \
1563 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1565 #define S_FW_PORT_CMD_MODTYPE 0
1566 #define M_FW_PORT_CMD_MODTYPE 0x1f
1567 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1568 #define G_FW_PORT_CMD_MODTYPE(x) \
1569 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1571 #define S_FW_PORT_CMD_LSTATUS32 31
1572 #define M_FW_PORT_CMD_LSTATUS32 0x1
1573 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1574 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1576 #define S_FW_PORT_CMD_LINKDNRC32 28
1577 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1578 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1579 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1581 #define S_FW_PORT_CMD_MDIOCAP32 26
1582 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1583 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1584 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1586 #define S_FW_PORT_CMD_MDIOADDR32 21
1587 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1588 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1589 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1591 #define S_FW_PORT_CMD_PORTTYPE32 13
1592 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1593 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1594 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1596 #define S_FW_PORT_CMD_MODTYPE32 8
1597 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1598 #define G_FW_PORT_CMD_MODTYPE32(x) \
1599 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1602 * These are configured into the VPD and hence tools that generate
1603 * VPD may use this enumeration.
1604 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1607 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1608 * with any new Firmware Port Technology Types!
1611 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1612 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1613 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1614 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1615 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1616 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1617 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1618 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1619 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1620 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1621 FW_PORT_TYPE_BP_AP = 10,
1622 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1623 FW_PORT_TYPE_BP4_AP = 11,
1624 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1625 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1626 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1627 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1628 FW_PORT_TYPE_BP40_BA = 15,
1629 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1630 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1631 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1632 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1633 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1634 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1635 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1636 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1639 /* These are read from module's EEPROM and determined once the
1640 * module is inserted.
1642 enum fw_port_module_type {
1643 FW_PORT_MOD_TYPE_NA = 0x0,
1644 FW_PORT_MOD_TYPE_LR = 0x1,
1645 FW_PORT_MOD_TYPE_SR = 0x2,
1646 FW_PORT_MOD_TYPE_ER = 0x3,
1647 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1648 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1649 FW_PORT_MOD_TYPE_LRM = 0x6,
1650 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1651 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1652 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1653 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1656 /* used by FW and tools may use this to generate VPD */
1657 enum fw_port_mod_sub_type {
1658 FW_PORT_MOD_SUB_TYPE_NA,
1659 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1660 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1661 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1662 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1663 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1664 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1665 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1666 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1669 * The following will never been in the VPD. They are TWINAX cable
1670 * lengths decoded from SFP+ module i2c PROMs. These should almost
1671 * certainly go somewhere else ...
1673 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1674 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1675 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1676 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1679 /* link down reason codes (3b) */
1680 enum fw_port_link_dn_rc {
1681 FW_PORT_LINK_DN_RC_NONE,
1682 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1683 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1684 FW_PORT_LINK_DN_RESERVED3,
1685 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1686 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1687 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1688 FW_PORT_LINK_DN_RESERVED7
1692 #define FW_NUM_PORT_STATS 50
1693 #define FW_NUM_PORT_TX_STATS 23
1694 #define FW_NUM_PORT_RX_STATS 27
1696 enum fw_port_stats_tx_index {
1697 FW_STAT_TX_PORT_BYTES_IX,
1698 FW_STAT_TX_PORT_FRAMES_IX,
1699 FW_STAT_TX_PORT_BCAST_IX,
1700 FW_STAT_TX_PORT_MCAST_IX,
1701 FW_STAT_TX_PORT_UCAST_IX,
1702 FW_STAT_TX_PORT_ERROR_IX,
1703 FW_STAT_TX_PORT_64B_IX,
1704 FW_STAT_TX_PORT_65B_127B_IX,
1705 FW_STAT_TX_PORT_128B_255B_IX,
1706 FW_STAT_TX_PORT_256B_511B_IX,
1707 FW_STAT_TX_PORT_512B_1023B_IX,
1708 FW_STAT_TX_PORT_1024B_1518B_IX,
1709 FW_STAT_TX_PORT_1519B_MAX_IX,
1710 FW_STAT_TX_PORT_DROP_IX,
1711 FW_STAT_TX_PORT_PAUSE_IX,
1712 FW_STAT_TX_PORT_PPP0_IX,
1713 FW_STAT_TX_PORT_PPP1_IX,
1714 FW_STAT_TX_PORT_PPP2_IX,
1715 FW_STAT_TX_PORT_PPP3_IX,
1716 FW_STAT_TX_PORT_PPP4_IX,
1717 FW_STAT_TX_PORT_PPP5_IX,
1718 FW_STAT_TX_PORT_PPP6_IX,
1719 FW_STAT_TX_PORT_PPP7_IX
1722 enum fw_port_stat_rx_index {
1723 FW_STAT_RX_PORT_BYTES_IX,
1724 FW_STAT_RX_PORT_FRAMES_IX,
1725 FW_STAT_RX_PORT_BCAST_IX,
1726 FW_STAT_RX_PORT_MCAST_IX,
1727 FW_STAT_RX_PORT_UCAST_IX,
1728 FW_STAT_RX_PORT_MTU_ERROR_IX,
1729 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1730 FW_STAT_RX_PORT_CRC_ERROR_IX,
1731 FW_STAT_RX_PORT_LEN_ERROR_IX,
1732 FW_STAT_RX_PORT_SYM_ERROR_IX,
1733 FW_STAT_RX_PORT_64B_IX,
1734 FW_STAT_RX_PORT_65B_127B_IX,
1735 FW_STAT_RX_PORT_128B_255B_IX,
1736 FW_STAT_RX_PORT_256B_511B_IX,
1737 FW_STAT_RX_PORT_512B_1023B_IX,
1738 FW_STAT_RX_PORT_1024B_1518B_IX,
1739 FW_STAT_RX_PORT_1519B_MAX_IX,
1740 FW_STAT_RX_PORT_PAUSE_IX,
1741 FW_STAT_RX_PORT_PPP0_IX,
1742 FW_STAT_RX_PORT_PPP1_IX,
1743 FW_STAT_RX_PORT_PPP2_IX,
1744 FW_STAT_RX_PORT_PPP3_IX,
1745 FW_STAT_RX_PORT_PPP4_IX,
1746 FW_STAT_RX_PORT_PPP5_IX,
1747 FW_STAT_RX_PORT_PPP6_IX,
1748 FW_STAT_RX_PORT_PPP7_IX,
1749 FW_STAT_RX_PORT_LESS_64B_IX
1752 struct fw_port_stats_cmd {
1753 __be32 op_to_portid;
1754 __be32 retval_len16;
1755 union fw_port_stats {
1756 struct fw_port_stats_ctl {
1768 struct fw_port_stats_all {
1777 __be64 tx_128b_255b;
1778 __be64 tx_256b_511b;
1779 __be64 tx_512b_1023b;
1780 __be64 tx_1024b_1518b;
1781 __be64 tx_1519b_max;
1797 __be64 rx_mtu_error;
1798 __be64 rx_mtu_crc_error;
1799 __be64 rx_crc_error;
1800 __be64 rx_len_error;
1801 __be64 rx_sym_error;
1804 __be64 rx_128b_255b;
1805 __be64 rx_256b_511b;
1806 __be64 rx_512b_1023b;
1807 __be64 rx_1024b_1518b;
1808 __be64 rx_1519b_max;
1825 struct fw_rss_ind_tbl_cmd {
1827 __be32 retval_len16;
1835 __be32 iq12_to_iq14;
1836 __be32 iq15_to_iq17;
1837 __be32 iq18_to_iq20;
1838 __be32 iq21_to_iq23;
1839 __be32 iq24_to_iq26;
1840 __be32 iq27_to_iq29;
1845 #define S_FW_RSS_IND_TBL_CMD_VIID 0
1846 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
1847 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
1848 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
1849 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
1851 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
1852 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
1853 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
1854 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
1855 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
1857 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
1858 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
1859 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
1860 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
1861 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
1863 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
1864 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
1865 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
1866 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
1867 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
1869 struct fw_rss_glb_config_cmd {
1871 __be32 retval_len16;
1872 union fw_rss_glb_config {
1873 struct fw_rss_glb_config_manual {
1879 struct fw_rss_glb_config_basicvirtual {
1880 __be32 mode_keymode;
1881 __be32 synmapen_to_hashtoeplitz;
1888 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
1889 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
1890 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
1891 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
1893 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
1895 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
1896 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
1897 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
1898 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
1900 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
1901 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
1902 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
1903 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
1904 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
1906 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
1907 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
1908 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
1909 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
1910 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
1912 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
1913 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
1914 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
1915 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
1916 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
1918 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
1919 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
1920 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
1921 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
1922 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
1924 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
1925 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
1926 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
1927 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
1929 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
1930 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
1931 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
1932 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
1934 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
1935 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
1936 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
1937 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
1938 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
1940 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
1941 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
1942 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
1943 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
1944 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
1946 struct fw_rss_vi_config_cmd {
1948 __be32 retval_len16;
1949 union fw_rss_vi_config {
1950 struct fw_rss_vi_config_manual {
1955 struct fw_rss_vi_config_basicvirtual {
1957 __be32 defaultq_to_udpen;
1964 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
1965 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
1966 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
1967 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
1968 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
1970 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
1971 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
1972 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1973 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1974 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1975 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
1976 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1978 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
1979 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
1980 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1981 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1982 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1983 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
1984 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1985 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
1986 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
1988 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
1989 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
1990 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1991 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1992 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1993 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
1994 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1995 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
1996 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
1998 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
1999 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2000 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2001 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2002 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2003 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2004 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2005 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2006 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2008 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2009 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2010 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2011 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2012 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2013 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2014 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2015 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2016 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2018 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2019 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2020 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2021 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2022 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2023 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2025 /******************************************************************************
2026 * D E B U G C O M M A N D s
2027 ******************************************************/
2029 struct fw_debug_cmd {
2033 struct fw_debug_assert {
2038 __u8 filename_0_7[8];
2039 __u8 filename_8_15[8];
2042 struct fw_debug_prt {
2045 __be32 dprtstrparam0;
2046 __be32 dprtstrparam1;
2047 __be32 dprtstrparam2;
2048 __be32 dprtstrparam3;
2053 #define S_FW_DEBUG_CMD_TYPE 0
2054 #define M_FW_DEBUG_CMD_TYPE 0xff
2055 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2056 #define G_FW_DEBUG_CMD_TYPE(x) \
2057 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2059 /******************************************************************************
2060 * P C I E F W R E G I S T E R
2061 **************************************/
2064 * Register definitions for the PCIE_FW register which the firmware uses
2065 * to retain status across RESETs. This register should be considered
2066 * as a READ-ONLY register for Host Software and only to be used to
2067 * track firmware initialization/error state, etc.
2069 #define S_PCIE_FW_ERR 31
2070 #define M_PCIE_FW_ERR 0x1
2071 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2072 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2073 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2075 #define S_PCIE_FW_INIT 30
2076 #define M_PCIE_FW_INIT 0x1
2077 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2078 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2079 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2081 #define S_PCIE_FW_HALT 29
2082 #define M_PCIE_FW_HALT 0x1
2083 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2084 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2085 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2087 #define S_PCIE_FW_EVAL 24
2088 #define M_PCIE_FW_EVAL 0x7
2089 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2090 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2092 #define S_PCIE_FW_MASTER_VLD 15
2093 #define M_PCIE_FW_MASTER_VLD 0x1
2094 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2095 #define G_PCIE_FW_MASTER_VLD(x) \
2096 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2097 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2099 #define S_PCIE_FW_MASTER 12
2100 #define M_PCIE_FW_MASTER 0x7
2101 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2102 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2104 /******************************************************************************
2105 * B I N A R Y H E A D E R F O R M A T
2106 **********************************************/
2109 * firmware binary header format
2113 __u8 chip; /* terminator chip family */
2114 __be16 len512; /* bin length in units of 512-bytes */
2115 __be32 fw_ver; /* firmware version */
2116 __be32 tp_microcode_ver; /* tcp processor microcode version */
2121 __u8 intfver_iscsipdu;
2123 __u8 intfver_fcoepdu;
2127 __u32 magic; /* runtime or bootstrap fw */
2129 __be32 reserved6[23];
2132 #define S_FW_HDR_FW_VER_MAJOR 24
2133 #define M_FW_HDR_FW_VER_MAJOR 0xff
2134 #define V_FW_HDR_FW_VER_MAJOR(x) \
2135 ((x) << S_FW_HDR_FW_VER_MAJOR)
2136 #define G_FW_HDR_FW_VER_MAJOR(x) \
2137 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2139 #define S_FW_HDR_FW_VER_MINOR 16
2140 #define M_FW_HDR_FW_VER_MINOR 0xff
2141 #define V_FW_HDR_FW_VER_MINOR(x) \
2142 ((x) << S_FW_HDR_FW_VER_MINOR)
2143 #define G_FW_HDR_FW_VER_MINOR(x) \
2144 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2146 #define S_FW_HDR_FW_VER_MICRO 8
2147 #define M_FW_HDR_FW_VER_MICRO 0xff
2148 #define V_FW_HDR_FW_VER_MICRO(x) \
2149 ((x) << S_FW_HDR_FW_VER_MICRO)
2150 #define G_FW_HDR_FW_VER_MICRO(x) \
2151 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2153 #define S_FW_HDR_FW_VER_BUILD 0
2154 #define M_FW_HDR_FW_VER_BUILD 0xff
2155 #define V_FW_HDR_FW_VER_BUILD(x) \
2156 ((x) << S_FW_HDR_FW_VER_BUILD)
2157 #define G_FW_HDR_FW_VER_BUILD(x) \
2158 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2160 #endif /* _T4FW_INTERFACE_H_ */