1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
60 FW_ETH_TX_PKT_WR = 0x08,
61 FW_ETH_TX_PKTS_WR = 0x09,
62 FW_ETH_TX_PKT_VM_WR = 0x11,
63 FW_ETH_TX_PKTS_VM_WR = 0x12,
65 FW_ETH_TX_PKTS2_WR = 0x78,
69 * Generic work request header flit0
76 /* work request opcode (hi)
79 #define M_FW_WR_OP 0xff
80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
81 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
83 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
85 #define S_FW_WR_ATOMIC 23
86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
88 /* work request immediate data length (hi)
90 #define S_FW_WR_IMMDLEN 0
91 #define M_FW_WR_IMMDLEN 0xff
92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
93 #define G_FW_WR_IMMDLEN(x) \
94 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
96 /* egress queue status update to egress queue status entry (lo)
98 #define S_FW_WR_EQUEQ 30
99 #define M_FW_WR_EQUEQ 0x1
100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
101 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
102 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
104 /* flow context identifier (lo)
106 #define S_FW_WR_FLOWID 8
107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
109 /* length in units of 16-bytes (lo)
111 #define S_FW_WR_LEN16 0
112 #define M_FW_WR_LEN16 0xff
113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
114 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
116 struct fw_eth_tx_pkt_wr {
118 __be32 equiq_to_len16;
122 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
123 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
124 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
125 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
126 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
128 struct fw_eth_tx_pkts_wr {
130 __be32 equiq_to_len16;
137 struct fw_eth_tx_pkt_vm_wr {
139 __be32 equiq_to_len16;
147 struct fw_eth_tx_pkts_vm_wr {
149 __be32 equiq_to_len16;
160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
161 enum fw_filter_wr_cookie {
162 FW_FILTER_WR_SUCCESS,
163 FW_FILTER_WR_FLT_ADDED,
164 FW_FILTER_WR_FLT_DELETED,
165 FW_FILTER_WR_SMT_TBL_FULL,
169 struct fw_filter2_wr {
174 __be32 del_filter_to_l2tix;
177 __u8 frag_to_ovlan_vldm;
179 __be16 rx_chan_rx_rpl_iq;
180 __be32 maci_to_matchtypem;
200 __u8 filter_type_swapmac;
201 __u8 natmode_to_ulp_type;
214 #define S_FW_FILTER_WR_TID 12
215 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
217 #define S_FW_FILTER_WR_RQTYPE 11
218 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
220 #define S_FW_FILTER_WR_NOREPLY 10
221 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
223 #define S_FW_FILTER_WR_IQ 0
224 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
226 #define S_FW_FILTER_WR_DEL_FILTER 31
227 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
228 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
230 #define S_FW_FILTER_WR_RPTTID 25
231 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
233 #define S_FW_FILTER_WR_DROP 24
234 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
236 #define S_FW_FILTER_WR_DIRSTEER 23
237 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
239 #define S_FW_FILTER_WR_MASKHASH 22
240 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
242 #define S_FW_FILTER_WR_DIRSTEERHASH 21
243 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
245 #define S_FW_FILTER_WR_LPBK 20
246 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
248 #define S_FW_FILTER_WR_DMAC 19
249 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
251 #define S_FW_FILTER_WR_SMAC 18
252 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC)
254 #define S_FW_FILTER_WR_INSVLAN 17
255 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
257 #define S_FW_FILTER_WR_RMVLAN 16
258 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
260 #define S_FW_FILTER_WR_HITCNTS 15
261 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
263 #define S_FW_FILTER_WR_TXCHAN 13
264 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
266 #define S_FW_FILTER_WR_PRIO 12
267 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
269 #define S_FW_FILTER_WR_L2TIX 0
270 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
272 #define S_FW_FILTER_WR_FRAG 7
273 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
275 #define S_FW_FILTER_WR_FRAGM 6
276 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
278 #define S_FW_FILTER_WR_IVLAN_VLD 5
279 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
281 #define S_FW_FILTER_WR_OVLAN_VLD 4
282 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
284 #define S_FW_FILTER_WR_IVLAN_VLDM 3
285 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
287 #define S_FW_FILTER_WR_OVLAN_VLDM 2
288 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
290 #define S_FW_FILTER_WR_RX_CHAN 15
291 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
293 #define S_FW_FILTER_WR_RX_RPL_IQ 0
294 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
296 #define S_FW_FILTER_WR_MACI 23
297 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
299 #define S_FW_FILTER_WR_MACIM 14
300 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
302 #define S_FW_FILTER_WR_FCOE 13
303 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
305 #define S_FW_FILTER_WR_FCOEM 12
306 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
308 #define S_FW_FILTER_WR_PORT 9
309 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
311 #define S_FW_FILTER_WR_PORTM 6
312 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
314 #define S_FW_FILTER_WR_MATCHTYPE 3
315 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
317 #define S_FW_FILTER_WR_MATCHTYPEM 0
318 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
320 #define S_FW_FILTER2_WR_SWAPMAC 0
321 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
323 #define S_FW_FILTER2_WR_NATMODE 5
324 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
326 #define S_FW_FILTER2_WR_ULP_TYPE 0
327 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
329 /******************************************************************************
331 *********************/
334 * The maximum length of time, in miliseconds, that we expect any firmware
335 * command to take to execute and return a reply to the host. The RESET
336 * and INITIALIZE commands can take a fair amount of time to execute but
337 * most execute in far less time than this maximum. This constant is used
338 * by host software to determine how long to wait for a firmware command
339 * reply before declaring the firmware as dead/unreachable ...
341 #define FW_CMD_MAX_TIMEOUT 10000
344 * If a host driver does a HELLO and discovers that there's already a MASTER
345 * selected, we may have to wait for that MASTER to finish issuing RESET,
346 * configuration and INITIALIZE commands. Also, there's a possibility that
347 * our own HELLO may get lost if it happens right as the MASTER is issuign a
348 * RESET command, so we need to be willing to make a few retries of our HELLO.
350 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
351 #define FW_CMD_HELLO_RETRIES 3
353 enum fw_cmd_opcodes {
358 FW_INITIALIZE_CMD = 0x06,
359 FW_CAPS_CONFIG_CMD = 0x07,
360 FW_PARAMS_CMD = 0x08,
363 FW_EQ_ETH_CMD = 0x12,
364 FW_EQ_CTRL_CMD = 0x13,
366 FW_VI_MAC_CMD = 0x15,
367 FW_VI_RXMODE_CMD = 0x16,
368 FW_VI_ENABLE_CMD = 0x17,
369 FW_VI_STATS_CMD = 0x1a,
371 FW_RSS_IND_TBL_CMD = 0x20,
372 FW_RSS_GLB_CONFIG_CMD = 0x22,
373 FW_RSS_VI_CONFIG_CMD = 0x23,
379 FW_CMD_CAP_PORT = 0x04,
383 * Generic command header flit0
390 #define S_FW_CMD_OP 24
391 #define M_FW_CMD_OP 0xff
392 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
393 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
395 #define S_FW_CMD_REQUEST 23
396 #define M_FW_CMD_REQUEST 0x1
397 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
398 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
399 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
401 #define S_FW_CMD_READ 22
402 #define M_FW_CMD_READ 0x1
403 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
404 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
405 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
407 #define S_FW_CMD_WRITE 21
408 #define M_FW_CMD_WRITE 0x1
409 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
410 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
411 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
413 #define S_FW_CMD_EXEC 20
414 #define M_FW_CMD_EXEC 0x1
415 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
416 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
417 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
419 #define S_FW_CMD_RETVAL 8
420 #define M_FW_CMD_RETVAL 0xff
421 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
422 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
424 #define S_FW_CMD_LEN16 0
425 #define M_FW_CMD_LEN16 0xff
426 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
427 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
429 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
433 enum fw_ldst_addrspc {
434 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
438 __be32 op_to_addrspace;
439 __be32 cycles_to_len16;
441 struct fw_ldst_addrval {
445 struct fw_ldst_idctxt {
447 __be32 msg_ctxtflush;
457 struct fw_ldst_mdio {
473 struct fw_ldst_func {
481 struct fw_ldst_pcie {
491 struct fw_ldst_i2c_deprecated {
515 #define S_FW_LDST_CMD_ADDRSPACE 0
516 #define M_FW_LDST_CMD_ADDRSPACE 0xff
517 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
519 struct fw_reset_cmd {
526 #define S_FW_RESET_CMD_HALT 31
527 #define M_FW_RESET_CMD_HALT 0x1
528 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
529 #define G_FW_RESET_CMD_HALT(x) \
530 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
531 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
534 FW_HELLO_CMD_STAGE_OS = 0,
537 struct fw_hello_cmd {
540 __be32 err_to_clearinit;
544 #define S_FW_HELLO_CMD_ERR 31
545 #define M_FW_HELLO_CMD_ERR 0x1
546 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
547 #define G_FW_HELLO_CMD_ERR(x) \
548 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
549 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
551 #define S_FW_HELLO_CMD_INIT 30
552 #define M_FW_HELLO_CMD_INIT 0x1
553 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
554 #define G_FW_HELLO_CMD_INIT(x) \
555 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
556 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
558 #define S_FW_HELLO_CMD_MASTERDIS 29
559 #define M_FW_HELLO_CMD_MASTERDIS 0x1
560 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
561 #define G_FW_HELLO_CMD_MASTERDIS(x) \
562 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
563 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
565 #define S_FW_HELLO_CMD_MASTERFORCE 28
566 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
567 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
568 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
569 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
570 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
572 #define S_FW_HELLO_CMD_MBMASTER 24
573 #define M_FW_HELLO_CMD_MBMASTER 0xf
574 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
575 #define G_FW_HELLO_CMD_MBMASTER(x) \
576 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
578 #define S_FW_HELLO_CMD_MBASYNCNOT 20
579 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
580 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
581 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
582 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
584 #define S_FW_HELLO_CMD_STAGE 17
585 #define M_FW_HELLO_CMD_STAGE 0x7
586 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
587 #define G_FW_HELLO_CMD_STAGE(x) \
588 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
590 #define S_FW_HELLO_CMD_CLEARINIT 16
591 #define M_FW_HELLO_CMD_CLEARINIT 0x1
592 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
593 #define G_FW_HELLO_CMD_CLEARINIT(x) \
594 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
595 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
603 struct fw_initialize_cmd {
609 enum fw_caps_config_nic {
610 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
611 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
615 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
618 struct fw_caps_config_cmd {
620 __be32 cfvalid_to_len16;
638 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
639 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
640 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
641 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
642 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
643 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
645 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
646 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
647 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
648 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
649 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
650 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
651 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
653 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
654 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
655 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
656 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
657 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
658 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
659 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
662 * params command mnemonics
664 enum fw_params_mnem {
665 FW_PARAMS_MNEM_DEV = 1, /* device params */
666 FW_PARAMS_MNEM_PFVF = 2, /* function params */
667 FW_PARAMS_MNEM_REG = 3, /* limited register access */
668 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
675 #define S_FW_PARAMS_PARAM_FILTER_MODE 16
676 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff
677 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \
678 (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \
679 M_FW_PARAMS_PARAM_FILTER_MODE)
681 #define S_FW_PARAMS_PARAM_FILTER_MASK 0
682 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff
683 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \
684 (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \
685 M_FW_PARAMS_PARAM_FILTER_MASK)
687 enum fw_params_param_dev {
688 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
689 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
690 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
691 * allocated by the device's
694 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
695 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
696 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
697 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
698 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
699 FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
703 * physical and virtual function parameters
705 enum fw_params_param_pfvf {
706 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
707 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
708 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
709 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
710 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
711 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
712 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
713 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
714 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
715 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
716 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
720 * dma queue parameters
722 enum fw_params_param_dmaq {
723 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
724 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
727 enum fw_params_param_dev_filter {
728 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01,
731 #define S_FW_PARAMS_MNEM 24
732 #define M_FW_PARAMS_MNEM 0xff
733 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
734 #define G_FW_PARAMS_MNEM(x) \
735 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
737 #define S_FW_PARAMS_PARAM_X 16
738 #define M_FW_PARAMS_PARAM_X 0xff
739 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
740 #define G_FW_PARAMS_PARAM_X(x) \
741 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
743 #define S_FW_PARAMS_PARAM_Y 8
744 #define M_FW_PARAMS_PARAM_Y 0xff
745 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
746 #define G_FW_PARAMS_PARAM_Y(x) \
747 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
749 #define S_FW_PARAMS_PARAM_Z 0
750 #define M_FW_PARAMS_PARAM_Z 0xff
751 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
752 #define G_FW_PARAMS_PARAM_Z(x) \
753 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
755 #define S_FW_PARAMS_PARAM_YZ 0
756 #define M_FW_PARAMS_PARAM_YZ 0xffff
757 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
758 #define G_FW_PARAMS_PARAM_YZ(x) \
759 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
761 #define S_FW_PARAMS_PARAM_XYZ 0
762 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
763 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
765 struct fw_params_cmd {
768 struct fw_params_param {
774 #define S_FW_PARAMS_CMD_PFN 8
775 #define M_FW_PARAMS_CMD_PFN 0x7
776 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
777 #define G_FW_PARAMS_CMD_PFN(x) \
778 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
780 #define S_FW_PARAMS_CMD_VFN 0
781 #define M_FW_PARAMS_CMD_VFN 0xff
782 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
783 #define G_FW_PARAMS_CMD_VFN(x) \
784 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
791 __be32 tc_to_nexactf;
792 __be32 r_caps_to_nethctrl;
798 #define S_FW_PFVF_CMD_PFN 8
799 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
801 #define S_FW_PFVF_CMD_VFN 0
802 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
804 #define S_FW_PFVF_CMD_NIQFLINT 20
805 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
806 #define G_FW_PFVF_CMD_NIQFLINT(x) \
807 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
809 #define S_FW_PFVF_CMD_NIQ 0
810 #define M_FW_PFVF_CMD_NIQ 0xfffff
811 #define G_FW_PFVF_CMD_NIQ(x) \
812 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
814 #define S_FW_PFVF_CMD_PMASK 20
815 #define M_FW_PFVF_CMD_PMASK 0xf
816 #define G_FW_PFVF_CMD_PMASK(x) \
817 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
819 #define S_FW_PFVF_CMD_NEQ 0
820 #define M_FW_PFVF_CMD_NEQ 0xfffff
821 #define G_FW_PFVF_CMD_NEQ(x) \
822 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
824 #define S_FW_PFVF_CMD_TC 24
825 #define M_FW_PFVF_CMD_TC 0xff
826 #define G_FW_PFVF_CMD_TC(x) \
827 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
829 #define S_FW_PFVF_CMD_NVI 16
830 #define M_FW_PFVF_CMD_NVI 0xff
831 #define G_FW_PFVF_CMD_NVI(x) \
832 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
834 #define S_FW_PFVF_CMD_NEXACTF 0
835 #define M_FW_PFVF_CMD_NEXACTF 0xffff
836 #define G_FW_PFVF_CMD_NEXACTF(x) \
837 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
839 #define S_FW_PFVF_CMD_R_CAPS 24
840 #define M_FW_PFVF_CMD_R_CAPS 0xff
841 #define G_FW_PFVF_CMD_R_CAPS(x) \
842 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
844 #define S_FW_PFVF_CMD_WX_CAPS 16
845 #define M_FW_PFVF_CMD_WX_CAPS 0xff
846 #define G_FW_PFVF_CMD_WX_CAPS(x) \
847 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
849 #define S_FW_PFVF_CMD_NETHCTRL 0
850 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
851 #define G_FW_PFVF_CMD_NETHCTRL(x) \
852 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
855 * ingress queue type; the first 1K ingress queues can have associated 0,
856 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
860 FW_IQ_TYPE_FL_INT_CAP,
864 FW_IQ_IQTYPE_NIC = 1,
870 __be32 alloc_to_len16;
875 __be32 type_to_iqandstindex;
876 __be16 iqdroprss_to_iqesize;
879 __be32 iqns_to_fl0congen;
880 __be16 fl0dcaen_to_fl0cidxfthresh;
883 __be32 fl1cngchmap_to_fl1congen;
884 __be16 fl1dcaen_to_fl1cidxfthresh;
889 #define S_FW_IQ_CMD_PFN 8
890 #define M_FW_IQ_CMD_PFN 0x7
891 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
892 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
894 #define S_FW_IQ_CMD_VFN 0
895 #define M_FW_IQ_CMD_VFN 0xff
896 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
897 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
899 #define S_FW_IQ_CMD_ALLOC 31
900 #define M_FW_IQ_CMD_ALLOC 0x1
901 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
902 #define G_FW_IQ_CMD_ALLOC(x) \
903 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
904 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
906 #define S_FW_IQ_CMD_FREE 30
907 #define M_FW_IQ_CMD_FREE 0x1
908 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
909 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
910 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
912 #define S_FW_IQ_CMD_IQSTART 28
913 #define M_FW_IQ_CMD_IQSTART 0x1
914 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
915 #define G_FW_IQ_CMD_IQSTART(x) \
916 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
917 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
919 #define S_FW_IQ_CMD_IQSTOP 27
920 #define M_FW_IQ_CMD_IQSTOP 0x1
921 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
922 #define G_FW_IQ_CMD_IQSTOP(x) \
923 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
924 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
926 #define S_FW_IQ_CMD_TYPE 29
927 #define M_FW_IQ_CMD_TYPE 0x7
928 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
929 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
931 #define S_FW_IQ_CMD_IQASYNCH 28
932 #define M_FW_IQ_CMD_IQASYNCH 0x1
933 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
934 #define G_FW_IQ_CMD_IQASYNCH(x) \
935 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
936 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
938 #define S_FW_IQ_CMD_VIID 16
939 #define M_FW_IQ_CMD_VIID 0xfff
940 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
941 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
943 #define S_FW_IQ_CMD_IQANDST 15
944 #define M_FW_IQ_CMD_IQANDST 0x1
945 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
946 #define G_FW_IQ_CMD_IQANDST(x) \
947 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
948 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
950 #define S_FW_IQ_CMD_IQANUD 12
951 #define M_FW_IQ_CMD_IQANUD 0x3
952 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
953 #define G_FW_IQ_CMD_IQANUD(x) \
954 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
956 #define S_FW_IQ_CMD_IQANDSTINDEX 0
957 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
958 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
959 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
960 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
962 #define S_FW_IQ_CMD_IQGTSMODE 14
963 #define M_FW_IQ_CMD_IQGTSMODE 0x1
964 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
965 #define G_FW_IQ_CMD_IQGTSMODE(x) \
966 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
967 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
969 #define S_FW_IQ_CMD_IQPCIECH 12
970 #define M_FW_IQ_CMD_IQPCIECH 0x3
971 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
972 #define G_FW_IQ_CMD_IQPCIECH(x) \
973 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
975 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
976 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
977 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
978 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
979 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
981 #define S_FW_IQ_CMD_IQESIZE 0
982 #define M_FW_IQ_CMD_IQESIZE 0x3
983 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
984 #define G_FW_IQ_CMD_IQESIZE(x) \
985 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
987 #define S_FW_IQ_CMD_IQRO 30
988 #define M_FW_IQ_CMD_IQRO 0x1
989 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
990 #define G_FW_IQ_CMD_IQRO(x) \
991 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
992 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
994 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
995 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
996 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
997 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
998 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
999 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
1001 #define S_FW_IQ_CMD_IQTYPE 24
1002 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
1004 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
1005 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
1006 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
1007 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
1008 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
1010 #define S_FW_IQ_CMD_FL0DATARO 12
1011 #define M_FW_IQ_CMD_FL0DATARO 0x1
1012 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
1013 #define G_FW_IQ_CMD_FL0DATARO(x) \
1014 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
1015 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
1017 #define S_FW_IQ_CMD_FL0CONGCIF 11
1018 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
1019 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
1020 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
1021 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
1022 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
1024 #define S_FW_IQ_CMD_FL0FETCHRO 6
1025 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
1026 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
1027 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
1028 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
1029 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
1031 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
1032 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
1033 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
1034 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
1035 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
1037 #define S_FW_IQ_CMD_FL0PADEN 2
1038 #define M_FW_IQ_CMD_FL0PADEN 0x1
1039 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
1040 #define G_FW_IQ_CMD_FL0PADEN(x) \
1041 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
1042 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
1044 #define S_FW_IQ_CMD_FL0PACKEN 1
1045 #define M_FW_IQ_CMD_FL0PACKEN 0x1
1046 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
1047 #define G_FW_IQ_CMD_FL0PACKEN(x) \
1048 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
1049 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
1051 #define S_FW_IQ_CMD_FL0CONGEN 0
1052 #define M_FW_IQ_CMD_FL0CONGEN 0x1
1053 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
1054 #define G_FW_IQ_CMD_FL0CONGEN(x) \
1055 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
1056 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
1058 #define S_FW_IQ_CMD_FL0FBMIN 7
1059 #define M_FW_IQ_CMD_FL0FBMIN 0x7
1060 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
1061 #define G_FW_IQ_CMD_FL0FBMIN(x) \
1062 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
1064 #define S_FW_IQ_CMD_FL0FBMAX 4
1065 #define M_FW_IQ_CMD_FL0FBMAX 0x7
1066 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
1067 #define G_FW_IQ_CMD_FL0FBMAX(x) \
1068 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
1070 struct fw_eq_eth_cmd {
1072 __be32 alloc_to_len16;
1074 __be32 physeqid_pkd;
1075 __be32 fetchszm_to_iqid;
1076 __be32 dcaen_to_eqsize;
1078 __be32 autoequiqe_to_viid;
1083 #define S_FW_EQ_ETH_CMD_PFN 8
1084 #define M_FW_EQ_ETH_CMD_PFN 0x7
1085 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
1086 #define G_FW_EQ_ETH_CMD_PFN(x) \
1087 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
1089 #define S_FW_EQ_ETH_CMD_VFN 0
1090 #define M_FW_EQ_ETH_CMD_VFN 0xff
1091 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
1092 #define G_FW_EQ_ETH_CMD_VFN(x) \
1093 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
1095 #define S_FW_EQ_ETH_CMD_ALLOC 31
1096 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
1097 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
1098 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
1099 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
1100 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
1102 #define S_FW_EQ_ETH_CMD_FREE 30
1103 #define M_FW_EQ_ETH_CMD_FREE 0x1
1104 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
1105 #define G_FW_EQ_ETH_CMD_FREE(x) \
1106 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
1107 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
1109 #define S_FW_EQ_ETH_CMD_EQSTART 28
1110 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
1111 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
1112 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
1113 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
1114 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
1116 #define S_FW_EQ_ETH_CMD_EQID 0
1117 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
1118 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
1119 #define G_FW_EQ_ETH_CMD_EQID(x) \
1120 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
1122 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
1123 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
1124 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
1125 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
1127 #define S_FW_EQ_ETH_CMD_FETCHRO 22
1128 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
1129 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
1130 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
1131 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
1132 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
1134 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
1135 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
1136 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
1137 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
1138 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
1140 #define S_FW_EQ_ETH_CMD_PCIECHN 16
1141 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
1142 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
1143 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
1144 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
1146 #define S_FW_EQ_ETH_CMD_IQID 0
1147 #define M_FW_EQ_ETH_CMD_IQID 0xffff
1148 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
1149 #define G_FW_EQ_ETH_CMD_IQID(x) \
1150 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
1152 #define S_FW_EQ_ETH_CMD_FBMIN 23
1153 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
1154 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
1155 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
1156 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
1158 #define S_FW_EQ_ETH_CMD_FBMAX 20
1159 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
1160 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
1161 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
1162 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
1164 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
1165 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
1166 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
1167 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
1168 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
1170 #define S_FW_EQ_ETH_CMD_EQSIZE 0
1171 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
1172 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
1173 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
1174 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
1176 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
1177 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
1178 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
1179 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
1180 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
1181 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
1183 #define S_FW_EQ_ETH_CMD_VIID 16
1184 #define M_FW_EQ_ETH_CMD_VIID 0xfff
1185 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
1186 #define G_FW_EQ_ETH_CMD_VIID(x) \
1187 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
1189 struct fw_eq_ctrl_cmd {
1191 __be32 alloc_to_len16;
1192 __be32 cmpliqid_eqid;
1193 __be32 physeqid_pkd;
1194 __be32 fetchszm_to_iqid;
1195 __be32 dcaen_to_eqsize;
1199 #define S_FW_EQ_CTRL_CMD_PFN 8
1200 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
1202 #define S_FW_EQ_CTRL_CMD_VFN 0
1203 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
1205 #define S_FW_EQ_CTRL_CMD_ALLOC 31
1206 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
1207 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
1209 #define S_FW_EQ_CTRL_CMD_FREE 30
1210 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
1211 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
1213 #define S_FW_EQ_CTRL_CMD_EQSTART 28
1214 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
1215 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
1217 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
1218 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
1220 #define S_FW_EQ_CTRL_CMD_EQID 0
1221 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
1222 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
1223 #define G_FW_EQ_CTRL_CMD_EQID(x) \
1224 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1226 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1227 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1228 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1229 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1230 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1232 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1233 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1234 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1236 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1237 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1238 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1240 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1241 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1243 #define S_FW_EQ_CTRL_CMD_IQID 0
1244 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1246 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1247 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1249 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1250 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1252 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1253 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1255 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1256 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1262 /* Macros for VIID parsing:
1263 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1266 #define S_FW_VIID_VIVLD 7
1267 #define M_FW_VIID_VIVLD 0x1
1268 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
1270 #define S_FW_VIID_VIN 0
1271 #define M_FW_VIID_VIN 0x7F
1272 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
1276 __be32 alloc_to_len16;
1277 __be16 type_to_viid;
1282 __be16 norss_rsssize;
1292 #define S_FW_VI_CMD_PFN 8
1293 #define M_FW_VI_CMD_PFN 0x7
1294 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1295 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1297 #define S_FW_VI_CMD_VFN 0
1298 #define M_FW_VI_CMD_VFN 0xff
1299 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1300 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1302 #define S_FW_VI_CMD_ALLOC 31
1303 #define M_FW_VI_CMD_ALLOC 0x1
1304 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1305 #define G_FW_VI_CMD_ALLOC(x) \
1306 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1307 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1309 #define S_FW_VI_CMD_FREE 30
1310 #define M_FW_VI_CMD_FREE 0x1
1311 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1312 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1313 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1315 #define S_FW_VI_CMD_VFVLD 24
1316 #define M_FW_VI_CMD_VFVLD 0x1
1317 #define G_FW_VI_CMD_VFVLD(x) \
1318 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
1320 #define S_FW_VI_CMD_VIN 16
1321 #define M_FW_VI_CMD_VIN 0xff
1322 #define G_FW_VI_CMD_VIN(x) \
1323 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
1325 #define S_FW_VI_CMD_TYPE 15
1326 #define M_FW_VI_CMD_TYPE 0x1
1327 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1328 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1329 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1331 #define S_FW_VI_CMD_FUNC 12
1332 #define M_FW_VI_CMD_FUNC 0x7
1333 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1334 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1336 #define S_FW_VI_CMD_VIID 0
1337 #define M_FW_VI_CMD_VIID 0xfff
1338 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1339 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1341 #define S_FW_VI_CMD_PORTID 4
1342 #define M_FW_VI_CMD_PORTID 0xf
1343 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1344 #define G_FW_VI_CMD_PORTID(x) \
1345 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1347 #define S_FW_VI_CMD_RSSSIZE 0
1348 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1349 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1350 #define G_FW_VI_CMD_RSSSIZE(x) \
1351 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1353 /* Special VI_MAC command index ids */
1354 #define FW_VI_MAC_ADD_MAC 0x3FF
1355 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1356 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
1358 enum fw_vi_mac_smac {
1359 FW_VI_MAC_MPS_TCAM_ENTRY = 0x0,
1360 FW_VI_MAC_SMT_AND_MPSTCAM = 0x3
1363 enum fw_vi_mac_entry_types {
1364 FW_VI_MAC_TYPE_RAW = 0x2,
1367 struct fw_vi_mac_cmd {
1369 __be32 freemacs_to_len16;
1371 struct fw_vi_mac_exact {
1372 __be16 valid_to_idx;
1375 struct fw_vi_mac_hash {
1378 struct fw_vi_mac_raw {
1388 #define S_FW_VI_MAC_CMD_VIID 0
1389 #define M_FW_VI_MAC_CMD_VIID 0xfff
1390 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1391 #define G_FW_VI_MAC_CMD_VIID(x) \
1392 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1394 #define S_FW_VI_MAC_CMD_FREEMACS 31
1395 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
1397 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
1398 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
1400 #define S_FW_VI_MAC_CMD_VALID 15
1401 #define M_FW_VI_MAC_CMD_VALID 0x1
1402 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1403 #define G_FW_VI_MAC_CMD_VALID(x) \
1404 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1405 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1407 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1408 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1409 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1410 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1411 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1413 #define S_FW_VI_MAC_CMD_IDX 0
1414 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1415 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1416 #define G_FW_VI_MAC_CMD_IDX(x) \
1417 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1419 #define S_FW_VI_MAC_CMD_RAW_IDX 16
1420 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
1421 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
1422 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
1423 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
1425 struct fw_vi_rxmode_cmd {
1427 __be32 retval_len16;
1428 __be32 mtu_to_vlanexen;
1432 #define S_FW_VI_RXMODE_CMD_VIID 0
1433 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1434 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1435 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1436 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1438 #define S_FW_VI_RXMODE_CMD_MTU 16
1439 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1440 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1441 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1442 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1444 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1445 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1446 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1447 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1448 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1450 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1451 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1452 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1453 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1454 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1455 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1457 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1458 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1459 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1460 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1461 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1462 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1463 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1465 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1466 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1467 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1468 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1469 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1471 struct fw_vi_enable_cmd {
1473 __be32 ien_to_len16;
1479 #define S_FW_VI_ENABLE_CMD_VIID 0
1480 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1481 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1482 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1483 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1485 #define S_FW_VI_ENABLE_CMD_IEN 31
1486 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1487 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1488 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1489 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1490 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1492 #define S_FW_VI_ENABLE_CMD_EEN 30
1493 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1494 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1495 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1496 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1497 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1499 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1500 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1501 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1502 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1503 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1504 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1506 /* VI VF stats offset definitions */
1507 #define VI_VF_NUM_STATS 16
1509 /* VI PF stats offset definitions */
1510 #define VI_PF_NUM_STATS 17
1511 enum fw_vi_stats_pf_index {
1512 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1513 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1514 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1515 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1516 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1517 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1518 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1519 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1520 FW_VI_PF_STAT_RX_BYTES_IX,
1521 FW_VI_PF_STAT_RX_FRAMES_IX,
1522 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1523 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1524 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1525 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1526 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1527 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1528 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1531 struct fw_vi_stats_cmd {
1533 __be32 retval_len16;
1535 struct fw_vi_stats_ctl {
1546 struct fw_vi_stats_pf {
1547 __be64 tx_bcast_bytes;
1548 __be64 tx_bcast_frames;
1549 __be64 tx_mcast_bytes;
1550 __be64 tx_mcast_frames;
1551 __be64 tx_ucast_bytes;
1552 __be64 tx_ucast_frames;
1553 __be64 tx_offload_bytes;
1554 __be64 tx_offload_frames;
1556 __be64 rx_pf_frames;
1557 __be64 rx_bcast_bytes;
1558 __be64 rx_bcast_frames;
1559 __be64 rx_mcast_bytes;
1560 __be64 rx_mcast_frames;
1561 __be64 rx_ucast_bytes;
1562 __be64 rx_ucast_frames;
1563 __be64 rx_err_frames;
1565 struct fw_vi_stats_vf {
1566 __be64 tx_bcast_bytes;
1567 __be64 tx_bcast_frames;
1568 __be64 tx_mcast_bytes;
1569 __be64 tx_mcast_frames;
1570 __be64 tx_ucast_bytes;
1571 __be64 tx_ucast_frames;
1572 __be64 tx_drop_frames;
1573 __be64 tx_offload_bytes;
1574 __be64 tx_offload_frames;
1575 __be64 rx_bcast_bytes;
1576 __be64 rx_bcast_frames;
1577 __be64 rx_mcast_bytes;
1578 __be64 rx_mcast_frames;
1579 __be64 rx_ucast_bytes;
1580 __be64 rx_ucast_frames;
1581 __be64 rx_err_frames;
1586 #define S_FW_VI_STATS_CMD_VIID 0
1587 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1589 #define S_FW_VI_STATS_CMD_NSTATS 12
1590 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1592 #define S_FW_VI_STATS_CMD_IX 0
1593 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1595 /* old 16-bit port capabilities bitmap */
1597 FW_PORT_CAP_SPEED_100M = 0x0001,
1598 FW_PORT_CAP_SPEED_1G = 0x0002,
1599 FW_PORT_CAP_SPEED_25G = 0x0004,
1600 FW_PORT_CAP_SPEED_10G = 0x0008,
1601 FW_PORT_CAP_SPEED_40G = 0x0010,
1602 FW_PORT_CAP_SPEED_100G = 0x0020,
1603 FW_PORT_CAP_FC_RX = 0x0040,
1604 FW_PORT_CAP_FC_TX = 0x0080,
1605 FW_PORT_CAP_ANEG = 0x0100,
1606 FW_PORT_CAP_MDIX = 0x0200,
1607 FW_PORT_CAP_MDIAUTO = 0x0400,
1608 FW_PORT_CAP_FEC_RS = 0x0800,
1609 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1610 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1611 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1612 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1615 #define S_FW_PORT_CAP_SPEED 0
1616 #define M_FW_PORT_CAP_SPEED 0x3f
1617 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1618 #define G_FW_PORT_CAP_SPEED(x) \
1619 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1622 FW_PORT_CAP_MDI_AUTO,
1625 #define S_FW_PORT_CAP_MDI 9
1626 #define M_FW_PORT_CAP_MDI 3
1627 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1628 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1630 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1631 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1632 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1633 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1634 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1635 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1636 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1637 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1638 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1639 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1640 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1641 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1642 #define FW_PORT_CAP32_ANEG 0x00100000UL
1643 #define FW_PORT_CAP32_MDIX 0x00200000UL
1644 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1645 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1646 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1648 #define S_FW_PORT_CAP32_SPEED 0
1649 #define M_FW_PORT_CAP32_SPEED 0xfff
1650 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1651 #define G_FW_PORT_CAP32_SPEED(x) \
1652 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1654 enum fw_port_mdi32 {
1655 FW_PORT_CAP32_MDI_AUTO,
1658 #define S_FW_PORT_CAP32_MDI 21
1659 #define M_FW_PORT_CAP32_MDI 3
1660 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1661 #define G_FW_PORT_CAP32_MDI(x) \
1662 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1664 enum fw_port_action {
1665 FW_PORT_ACTION_L1_CFG = 0x0001,
1666 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1667 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1668 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1671 struct fw_port_cmd {
1672 __be32 op_to_portid;
1673 __be32 action_to_len16;
1675 struct fw_port_l1cfg {
1679 struct fw_port_l2cfg {
1681 __u8 ovlan3_to_ivlan0;
1683 __be16 txipg_force_pinfo;
1694 struct fw_port_info {
1695 __be32 lstatus_to_modtype;
1706 struct fw_port_diags {
1712 struct fw_port_dcb_pgid {
1719 struct fw_port_dcb_pgrate {
1723 __u8 num_tcs_supported;
1727 struct fw_port_dcb_priorate {
1731 __u8 strict_priorate[8];
1733 struct fw_port_dcb_pfc {
1740 struct fw_port_app_priority {
1749 struct fw_port_dcb_control {
1752 __be16 dcb_version_to_app_state;
1757 struct fw_port_l1cfg32 {
1761 struct fw_port_info32 {
1762 __be32 lstatus32_to_cbllen32;
1763 __be32 auxlinfo32_mtu32;
1772 #define S_FW_PORT_CMD_PORTID 0
1773 #define M_FW_PORT_CMD_PORTID 0xf
1774 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1775 #define G_FW_PORT_CMD_PORTID(x) \
1776 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1778 #define S_FW_PORT_CMD_ACTION 16
1779 #define M_FW_PORT_CMD_ACTION 0xffff
1780 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1781 #define G_FW_PORT_CMD_ACTION(x) \
1782 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1784 #define S_FW_PORT_CMD_LSTATUS 31
1785 #define M_FW_PORT_CMD_LSTATUS 0x1
1786 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1787 #define G_FW_PORT_CMD_LSTATUS(x) \
1788 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1789 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1791 #define S_FW_PORT_CMD_LSPEED 24
1792 #define M_FW_PORT_CMD_LSPEED 0x3f
1793 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1794 #define G_FW_PORT_CMD_LSPEED(x) \
1795 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1797 #define S_FW_PORT_CMD_TXPAUSE 23
1798 #define M_FW_PORT_CMD_TXPAUSE 0x1
1799 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1800 #define G_FW_PORT_CMD_TXPAUSE(x) \
1801 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1802 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1804 #define S_FW_PORT_CMD_RXPAUSE 22
1805 #define M_FW_PORT_CMD_RXPAUSE 0x1
1806 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1807 #define G_FW_PORT_CMD_RXPAUSE(x) \
1808 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1809 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1811 #define S_FW_PORT_CMD_MDIOCAP 21
1812 #define M_FW_PORT_CMD_MDIOCAP 0x1
1813 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1814 #define G_FW_PORT_CMD_MDIOCAP(x) \
1815 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1816 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1818 #define S_FW_PORT_CMD_MDIOADDR 16
1819 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1820 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1821 #define G_FW_PORT_CMD_MDIOADDR(x) \
1822 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1824 #define S_FW_PORT_CMD_PTYPE 8
1825 #define M_FW_PORT_CMD_PTYPE 0x1f
1826 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1827 #define G_FW_PORT_CMD_PTYPE(x) \
1828 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1830 #define S_FW_PORT_CMD_LINKDNRC 5
1831 #define M_FW_PORT_CMD_LINKDNRC 0x7
1832 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1833 #define G_FW_PORT_CMD_LINKDNRC(x) \
1834 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1836 #define S_FW_PORT_CMD_MODTYPE 0
1837 #define M_FW_PORT_CMD_MODTYPE 0x1f
1838 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1839 #define G_FW_PORT_CMD_MODTYPE(x) \
1840 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1842 #define S_FW_PORT_CMD_LSTATUS32 31
1843 #define M_FW_PORT_CMD_LSTATUS32 0x1
1844 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1845 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1847 #define S_FW_PORT_CMD_LINKDNRC32 28
1848 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1849 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1850 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1852 #define S_FW_PORT_CMD_MDIOCAP32 26
1853 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1854 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1855 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1857 #define S_FW_PORT_CMD_MDIOADDR32 21
1858 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1859 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1860 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1862 #define S_FW_PORT_CMD_PORTTYPE32 13
1863 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1864 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1865 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1867 #define S_FW_PORT_CMD_MODTYPE32 8
1868 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1869 #define G_FW_PORT_CMD_MODTYPE32(x) \
1870 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1873 * These are configured into the VPD and hence tools that generate
1874 * VPD may use this enumeration.
1875 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1878 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1879 * with any new Firmware Port Technology Types!
1882 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1883 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1884 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1885 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1886 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1887 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1888 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1889 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1890 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1891 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1892 FW_PORT_TYPE_BP_AP = 10,
1893 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1894 FW_PORT_TYPE_BP4_AP = 11,
1895 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1896 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1897 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1898 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1899 FW_PORT_TYPE_BP40_BA = 15,
1900 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1901 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1902 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1903 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1904 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1905 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1906 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1907 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1910 /* These are read from module's EEPROM and determined once the
1911 * module is inserted.
1913 enum fw_port_module_type {
1914 FW_PORT_MOD_TYPE_NA = 0x0,
1915 FW_PORT_MOD_TYPE_LR = 0x1,
1916 FW_PORT_MOD_TYPE_SR = 0x2,
1917 FW_PORT_MOD_TYPE_ER = 0x3,
1918 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1919 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1920 FW_PORT_MOD_TYPE_LRM = 0x6,
1921 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1922 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1923 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1924 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1927 /* used by FW and tools may use this to generate VPD */
1928 enum fw_port_mod_sub_type {
1929 FW_PORT_MOD_SUB_TYPE_NA,
1930 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1931 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1932 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1933 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1934 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1935 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1936 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1937 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1940 * The following will never been in the VPD. They are TWINAX cable
1941 * lengths decoded from SFP+ module i2c PROMs. These should almost
1942 * certainly go somewhere else ...
1944 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1945 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1946 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1947 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1950 /* link down reason codes (3b) */
1951 enum fw_port_link_dn_rc {
1952 FW_PORT_LINK_DN_RC_NONE,
1953 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1954 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1955 FW_PORT_LINK_DN_RESERVED3,
1956 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1957 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1958 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1959 FW_PORT_LINK_DN_RESERVED7
1963 #define FW_NUM_PORT_STATS 50
1964 #define FW_NUM_PORT_TX_STATS 23
1965 #define FW_NUM_PORT_RX_STATS 27
1967 enum fw_port_stats_tx_index {
1968 FW_STAT_TX_PORT_BYTES_IX,
1969 FW_STAT_TX_PORT_FRAMES_IX,
1970 FW_STAT_TX_PORT_BCAST_IX,
1971 FW_STAT_TX_PORT_MCAST_IX,
1972 FW_STAT_TX_PORT_UCAST_IX,
1973 FW_STAT_TX_PORT_ERROR_IX,
1974 FW_STAT_TX_PORT_64B_IX,
1975 FW_STAT_TX_PORT_65B_127B_IX,
1976 FW_STAT_TX_PORT_128B_255B_IX,
1977 FW_STAT_TX_PORT_256B_511B_IX,
1978 FW_STAT_TX_PORT_512B_1023B_IX,
1979 FW_STAT_TX_PORT_1024B_1518B_IX,
1980 FW_STAT_TX_PORT_1519B_MAX_IX,
1981 FW_STAT_TX_PORT_DROP_IX,
1982 FW_STAT_TX_PORT_PAUSE_IX,
1983 FW_STAT_TX_PORT_PPP0_IX,
1984 FW_STAT_TX_PORT_PPP1_IX,
1985 FW_STAT_TX_PORT_PPP2_IX,
1986 FW_STAT_TX_PORT_PPP3_IX,
1987 FW_STAT_TX_PORT_PPP4_IX,
1988 FW_STAT_TX_PORT_PPP5_IX,
1989 FW_STAT_TX_PORT_PPP6_IX,
1990 FW_STAT_TX_PORT_PPP7_IX
1993 enum fw_port_stat_rx_index {
1994 FW_STAT_RX_PORT_BYTES_IX,
1995 FW_STAT_RX_PORT_FRAMES_IX,
1996 FW_STAT_RX_PORT_BCAST_IX,
1997 FW_STAT_RX_PORT_MCAST_IX,
1998 FW_STAT_RX_PORT_UCAST_IX,
1999 FW_STAT_RX_PORT_MTU_ERROR_IX,
2000 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2001 FW_STAT_RX_PORT_CRC_ERROR_IX,
2002 FW_STAT_RX_PORT_LEN_ERROR_IX,
2003 FW_STAT_RX_PORT_SYM_ERROR_IX,
2004 FW_STAT_RX_PORT_64B_IX,
2005 FW_STAT_RX_PORT_65B_127B_IX,
2006 FW_STAT_RX_PORT_128B_255B_IX,
2007 FW_STAT_RX_PORT_256B_511B_IX,
2008 FW_STAT_RX_PORT_512B_1023B_IX,
2009 FW_STAT_RX_PORT_1024B_1518B_IX,
2010 FW_STAT_RX_PORT_1519B_MAX_IX,
2011 FW_STAT_RX_PORT_PAUSE_IX,
2012 FW_STAT_RX_PORT_PPP0_IX,
2013 FW_STAT_RX_PORT_PPP1_IX,
2014 FW_STAT_RX_PORT_PPP2_IX,
2015 FW_STAT_RX_PORT_PPP3_IX,
2016 FW_STAT_RX_PORT_PPP4_IX,
2017 FW_STAT_RX_PORT_PPP5_IX,
2018 FW_STAT_RX_PORT_PPP6_IX,
2019 FW_STAT_RX_PORT_PPP7_IX,
2020 FW_STAT_RX_PORT_LESS_64B_IX
2023 struct fw_port_stats_cmd {
2024 __be32 op_to_portid;
2025 __be32 retval_len16;
2026 union fw_port_stats {
2027 struct fw_port_stats_ctl {
2039 struct fw_port_stats_all {
2048 __be64 tx_128b_255b;
2049 __be64 tx_256b_511b;
2050 __be64 tx_512b_1023b;
2051 __be64 tx_1024b_1518b;
2052 __be64 tx_1519b_max;
2068 __be64 rx_mtu_error;
2069 __be64 rx_mtu_crc_error;
2070 __be64 rx_crc_error;
2071 __be64 rx_len_error;
2072 __be64 rx_sym_error;
2075 __be64 rx_128b_255b;
2076 __be64 rx_256b_511b;
2077 __be64 rx_512b_1023b;
2078 __be64 rx_1024b_1518b;
2079 __be64 rx_1519b_max;
2096 struct fw_rss_ind_tbl_cmd {
2098 __be32 retval_len16;
2106 __be32 iq12_to_iq14;
2107 __be32 iq15_to_iq17;
2108 __be32 iq18_to_iq20;
2109 __be32 iq21_to_iq23;
2110 __be32 iq24_to_iq26;
2111 __be32 iq27_to_iq29;
2116 #define S_FW_RSS_IND_TBL_CMD_VIID 0
2117 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
2118 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
2119 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
2120 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
2122 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
2123 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
2124 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
2125 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
2126 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
2128 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
2129 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
2130 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
2131 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
2132 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
2134 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
2135 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
2136 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
2137 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
2138 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
2140 struct fw_rss_glb_config_cmd {
2142 __be32 retval_len16;
2143 union fw_rss_glb_config {
2144 struct fw_rss_glb_config_manual {
2150 struct fw_rss_glb_config_basicvirtual {
2151 __be32 mode_keymode;
2152 __be32 synmapen_to_hashtoeplitz;
2159 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
2160 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
2161 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
2162 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
2164 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2166 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
2167 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
2168 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
2169 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
2171 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
2172 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
2173 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
2174 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
2175 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
2177 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
2178 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
2179 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
2180 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
2181 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
2183 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
2184 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
2185 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
2186 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
2187 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
2189 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
2190 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
2191 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
2192 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
2193 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
2195 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
2196 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
2197 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
2198 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
2200 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
2201 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
2202 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
2203 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
2205 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
2206 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
2207 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
2208 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
2209 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
2211 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
2212 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
2213 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
2214 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
2215 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
2217 struct fw_rss_vi_config_cmd {
2219 __be32 retval_len16;
2220 union fw_rss_vi_config {
2221 struct fw_rss_vi_config_manual {
2226 struct fw_rss_vi_config_basicvirtual {
2228 __be32 defaultq_to_udpen;
2235 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
2236 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
2237 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
2238 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
2239 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
2241 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
2242 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
2243 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2244 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2245 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2246 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
2247 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2249 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
2250 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
2251 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2252 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2253 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2254 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
2255 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2256 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
2257 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
2259 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
2260 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
2261 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2262 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2263 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2264 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
2265 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2266 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
2267 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
2269 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
2270 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2271 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2272 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2273 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2274 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2275 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2276 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2277 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2279 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2280 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2281 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2282 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2283 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2284 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2285 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2286 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2287 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2289 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2290 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2291 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2292 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2293 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2294 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2296 struct fw_clip_cmd {
2298 __be32 alloc_to_len16;
2304 #define S_FW_CLIP_CMD_ALLOC 31
2305 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
2306 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
2308 #define S_FW_CLIP_CMD_FREE 30
2309 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
2310 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
2312 /******************************************************************************
2313 * D E B U G C O M M A N D s
2314 ******************************************************/
2316 struct fw_debug_cmd {
2320 struct fw_debug_assert {
2325 __u8 filename_0_7[8];
2326 __u8 filename_8_15[8];
2329 struct fw_debug_prt {
2332 __be32 dprtstrparam0;
2333 __be32 dprtstrparam1;
2334 __be32 dprtstrparam2;
2335 __be32 dprtstrparam3;
2340 #define S_FW_DEBUG_CMD_TYPE 0
2341 #define M_FW_DEBUG_CMD_TYPE 0xff
2342 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2343 #define G_FW_DEBUG_CMD_TYPE(x) \
2344 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2346 /******************************************************************************
2347 * P C I E F W R E G I S T E R
2348 **************************************/
2351 * Register definitions for the PCIE_FW register which the firmware uses
2352 * to retain status across RESETs. This register should be considered
2353 * as a READ-ONLY register for Host Software and only to be used to
2354 * track firmware initialization/error state, etc.
2356 #define S_PCIE_FW_ERR 31
2357 #define M_PCIE_FW_ERR 0x1
2358 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2359 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2360 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2362 #define S_PCIE_FW_INIT 30
2363 #define M_PCIE_FW_INIT 0x1
2364 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2365 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2366 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2368 #define S_PCIE_FW_HALT 29
2369 #define M_PCIE_FW_HALT 0x1
2370 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2371 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2372 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2374 #define S_PCIE_FW_EVAL 24
2375 #define M_PCIE_FW_EVAL 0x7
2376 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2377 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2379 #define S_PCIE_FW_MASTER_VLD 15
2380 #define M_PCIE_FW_MASTER_VLD 0x1
2381 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2382 #define G_PCIE_FW_MASTER_VLD(x) \
2383 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2384 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2386 #define S_PCIE_FW_MASTER 12
2387 #define M_PCIE_FW_MASTER 0x7
2388 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2389 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2391 /******************************************************************************
2392 * B I N A R Y H E A D E R F O R M A T
2393 **********************************************/
2396 * firmware binary header format
2400 __u8 chip; /* terminator chip family */
2401 __be16 len512; /* bin length in units of 512-bytes */
2402 __be32 fw_ver; /* firmware version */
2403 __be32 tp_microcode_ver; /* tcp processor microcode version */
2408 __u8 intfver_iscsipdu;
2410 __u8 intfver_fcoepdu;
2414 __u32 magic; /* runtime or bootstrap fw */
2416 __be32 reserved6[23];
2419 #define S_FW_HDR_FW_VER_MAJOR 24
2420 #define M_FW_HDR_FW_VER_MAJOR 0xff
2421 #define V_FW_HDR_FW_VER_MAJOR(x) \
2422 ((x) << S_FW_HDR_FW_VER_MAJOR)
2423 #define G_FW_HDR_FW_VER_MAJOR(x) \
2424 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2426 #define S_FW_HDR_FW_VER_MINOR 16
2427 #define M_FW_HDR_FW_VER_MINOR 0xff
2428 #define V_FW_HDR_FW_VER_MINOR(x) \
2429 ((x) << S_FW_HDR_FW_VER_MINOR)
2430 #define G_FW_HDR_FW_VER_MINOR(x) \
2431 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2433 #define S_FW_HDR_FW_VER_MICRO 8
2434 #define M_FW_HDR_FW_VER_MICRO 0xff
2435 #define V_FW_HDR_FW_VER_MICRO(x) \
2436 ((x) << S_FW_HDR_FW_VER_MICRO)
2437 #define G_FW_HDR_FW_VER_MICRO(x) \
2438 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2440 #define S_FW_HDR_FW_VER_BUILD 0
2441 #define M_FW_HDR_FW_VER_BUILD 0xff
2442 #define V_FW_HDR_FW_VER_BUILD(x) \
2443 ((x) << S_FW_HDR_FW_VER_BUILD)
2444 #define G_FW_HDR_FW_VER_BUILD(x) \
2445 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2447 #endif /* _T4FW_INTERFACE_H_ */