4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _T4FW_INTERFACE_H_
35 #define _T4FW_INTERFACE_H_
37 /******************************************************************************
38 * R E T U R N V A L U E S
39 ********************************/
42 FW_SUCCESS = 0, /* completed successfully */
43 FW_EPERM = 1, /* operation not permitted */
44 FW_ENOENT = 2, /* no such file or directory */
45 FW_EIO = 5, /* input/output error; hw bad */
46 FW_ENOEXEC = 8, /* exec format error; inv microcode */
47 FW_EAGAIN = 11, /* try again */
48 FW_ENOMEM = 12, /* out of memory */
49 FW_EFAULT = 14, /* bad address; fw bad */
50 FW_EBUSY = 16, /* resource busy */
51 FW_EEXIST = 17, /* file exists */
52 FW_ENODEV = 19, /* no such device */
53 FW_EINVAL = 22, /* invalid argument */
54 FW_ENOSPC = 28, /* no space left on device */
55 FW_ENOSYS = 38, /* functionality not implemented */
56 FW_ENODATA = 61, /* no data available */
57 FW_EPROTO = 71, /* protocol error */
58 FW_EADDRINUSE = 98, /* address already in use */
59 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
60 FW_ENETDOWN = 100, /* network is down */
61 FW_ENETUNREACH = 101, /* network is unreachable */
62 FW_ENOBUFS = 105, /* no buffer space available */
63 FW_ETIMEDOUT = 110, /* timeout */
64 FW_EINPROGRESS = 115, /* fw internal */
67 /******************************************************************************
68 * M E M O R Y T Y P E s
69 ******************************/
72 FW_MEMTYPE_EDC0 = 0x0,
73 FW_MEMTYPE_EDC1 = 0x1,
74 FW_MEMTYPE_EXTMEM = 0x2,
75 FW_MEMTYPE_FLASH = 0x4,
76 FW_MEMTYPE_INTERNAL = 0x5,
77 FW_MEMTYPE_EXTMEM1 = 0x6,
80 /******************************************************************************
81 * W O R K R E Q U E S T s
82 ********************************/
85 FW_ETH_TX_PKT_WR = 0x08,
86 FW_ETH_TX_PKTS_WR = 0x09,
87 FW_ETH_TX_PKT_VM_WR = 0x11,
88 FW_ETH_TX_PKTS_VM_WR = 0x12,
89 FW_ETH_TX_PKTS2_WR = 0x78,
93 * Generic work request header flit0
100 /* work request opcode (hi)
102 #define S_FW_WR_OP 24
103 #define M_FW_WR_OP 0xff
104 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
105 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
107 /* work request immediate data length (hi)
109 #define S_FW_WR_IMMDLEN 0
110 #define M_FW_WR_IMMDLEN 0xff
111 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
112 #define G_FW_WR_IMMDLEN(x) \
113 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
115 /* egress queue status update to egress queue status entry (lo)
117 #define S_FW_WR_EQUEQ 30
118 #define M_FW_WR_EQUEQ 0x1
119 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
120 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
121 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
123 /* length in units of 16-bytes (lo)
125 #define S_FW_WR_LEN16 0
126 #define M_FW_WR_LEN16 0xff
127 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
128 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
130 struct fw_eth_tx_pkt_wr {
132 __be32 equiq_to_len16;
136 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
137 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
138 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
139 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
140 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
142 struct fw_eth_tx_pkts_wr {
144 __be32 equiq_to_len16;
151 struct fw_eth_tx_pkt_vm_wr {
153 __be32 equiq_to_len16;
161 struct fw_eth_tx_pkts_vm_wr {
163 __be32 equiq_to_len16;
174 /******************************************************************************
176 *********************/
179 * The maximum length of time, in miliseconds, that we expect any firmware
180 * command to take to execute and return a reply to the host. The RESET
181 * and INITIALIZE commands can take a fair amount of time to execute but
182 * most execute in far less time than this maximum. This constant is used
183 * by host software to determine how long to wait for a firmware command
184 * reply before declaring the firmware as dead/unreachable ...
186 #define FW_CMD_MAX_TIMEOUT 10000
189 * If a host driver does a HELLO and discovers that there's already a MASTER
190 * selected, we may have to wait for that MASTER to finish issuing RESET,
191 * configuration and INITIALIZE commands. Also, there's a possibility that
192 * our own HELLO may get lost if it happens right as the MASTER is issuign a
193 * RESET command, so we need to be willing to make a few retries of our HELLO.
195 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
196 #define FW_CMD_HELLO_RETRIES 3
198 enum fw_cmd_opcodes {
203 FW_INITIALIZE_CMD = 0x06,
204 FW_CAPS_CONFIG_CMD = 0x07,
205 FW_PARAMS_CMD = 0x08,
208 FW_EQ_ETH_CMD = 0x12,
210 FW_VI_MAC_CMD = 0x15,
211 FW_VI_RXMODE_CMD = 0x16,
212 FW_VI_ENABLE_CMD = 0x17,
213 FW_VI_STATS_CMD = 0x1a,
215 FW_RSS_IND_TBL_CMD = 0x20,
216 FW_RSS_GLB_CONFIG_CMD = 0x22,
217 FW_RSS_VI_CONFIG_CMD = 0x23,
222 FW_CMD_CAP_PORT = 0x04,
226 * Generic command header flit0
233 #define S_FW_CMD_OP 24
234 #define M_FW_CMD_OP 0xff
235 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
236 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
238 #define S_FW_CMD_REQUEST 23
239 #define M_FW_CMD_REQUEST 0x1
240 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
241 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
242 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
244 #define S_FW_CMD_READ 22
245 #define M_FW_CMD_READ 0x1
246 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
247 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
248 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
250 #define S_FW_CMD_WRITE 21
251 #define M_FW_CMD_WRITE 0x1
252 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
253 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
254 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
256 #define S_FW_CMD_EXEC 20
257 #define M_FW_CMD_EXEC 0x1
258 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
259 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
260 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
262 #define S_FW_CMD_RETVAL 8
263 #define M_FW_CMD_RETVAL 0xff
264 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
265 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
267 #define S_FW_CMD_LEN16 0
268 #define M_FW_CMD_LEN16 0xff
269 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
270 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
272 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
276 enum fw_ldst_addrspc {
277 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
281 __be32 op_to_addrspace;
282 __be32 cycles_to_len16;
284 struct fw_ldst_addrval {
288 struct fw_ldst_idctxt {
290 __be32 msg_ctxtflush;
300 struct fw_ldst_mdio {
316 struct fw_ldst_func {
324 struct fw_ldst_pcie {
334 struct fw_ldst_i2c_deprecated {
358 #define S_FW_LDST_CMD_ADDRSPACE 0
359 #define M_FW_LDST_CMD_ADDRSPACE 0xff
360 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
362 struct fw_reset_cmd {
369 #define S_FW_RESET_CMD_HALT 31
370 #define M_FW_RESET_CMD_HALT 0x1
371 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
372 #define G_FW_RESET_CMD_HALT(x) \
373 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
374 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
377 FW_HELLO_CMD_STAGE_OS = 0,
380 struct fw_hello_cmd {
383 __be32 err_to_clearinit;
387 #define S_FW_HELLO_CMD_ERR 31
388 #define M_FW_HELLO_CMD_ERR 0x1
389 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
390 #define G_FW_HELLO_CMD_ERR(x) \
391 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
392 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
394 #define S_FW_HELLO_CMD_INIT 30
395 #define M_FW_HELLO_CMD_INIT 0x1
396 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
397 #define G_FW_HELLO_CMD_INIT(x) \
398 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
399 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
401 #define S_FW_HELLO_CMD_MASTERDIS 29
402 #define M_FW_HELLO_CMD_MASTERDIS 0x1
403 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
404 #define G_FW_HELLO_CMD_MASTERDIS(x) \
405 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
406 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
408 #define S_FW_HELLO_CMD_MASTERFORCE 28
409 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
410 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
411 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
412 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
413 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
415 #define S_FW_HELLO_CMD_MBMASTER 24
416 #define M_FW_HELLO_CMD_MBMASTER 0xf
417 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
418 #define G_FW_HELLO_CMD_MBMASTER(x) \
419 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
421 #define S_FW_HELLO_CMD_MBASYNCNOT 20
422 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
423 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
424 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
425 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
427 #define S_FW_HELLO_CMD_STAGE 17
428 #define M_FW_HELLO_CMD_STAGE 0x7
429 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
430 #define G_FW_HELLO_CMD_STAGE(x) \
431 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
433 #define S_FW_HELLO_CMD_CLEARINIT 16
434 #define M_FW_HELLO_CMD_CLEARINIT 0x1
435 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
436 #define G_FW_HELLO_CMD_CLEARINIT(x) \
437 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
438 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
446 struct fw_initialize_cmd {
452 enum fw_caps_config_nic {
453 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
454 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
458 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
461 struct fw_caps_config_cmd {
463 __be32 cfvalid_to_len16;
481 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
482 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
483 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
484 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
485 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
486 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
488 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
489 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
490 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
491 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
492 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
493 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
494 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
496 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
497 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
498 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
499 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
500 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
501 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
502 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
505 * params command mnemonics
507 enum fw_params_mnem {
508 FW_PARAMS_MNEM_DEV = 1, /* device params */
509 FW_PARAMS_MNEM_PFVF = 2, /* function params */
510 FW_PARAMS_MNEM_REG = 3, /* limited register access */
511 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
517 enum fw_params_param_dev {
518 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
519 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
520 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
521 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
522 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
526 * physical and virtual function parameters
528 enum fw_params_param_pfvf {
529 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
530 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
534 * dma queue parameters
536 enum fw_params_param_dmaq {
537 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
538 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
541 #define S_FW_PARAMS_MNEM 24
542 #define M_FW_PARAMS_MNEM 0xff
543 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
544 #define G_FW_PARAMS_MNEM(x) \
545 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
547 #define S_FW_PARAMS_PARAM_X 16
548 #define M_FW_PARAMS_PARAM_X 0xff
549 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
550 #define G_FW_PARAMS_PARAM_X(x) \
551 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
553 #define S_FW_PARAMS_PARAM_Y 8
554 #define M_FW_PARAMS_PARAM_Y 0xff
555 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
556 #define G_FW_PARAMS_PARAM_Y(x) \
557 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
559 #define S_FW_PARAMS_PARAM_Z 0
560 #define M_FW_PARAMS_PARAM_Z 0xff
561 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
562 #define G_FW_PARAMS_PARAM_Z(x) \
563 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
565 #define S_FW_PARAMS_PARAM_YZ 0
566 #define M_FW_PARAMS_PARAM_YZ 0xffff
567 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
568 #define G_FW_PARAMS_PARAM_YZ(x) \
569 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
571 #define S_FW_PARAMS_PARAM_XYZ 0
572 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
573 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
575 struct fw_params_cmd {
578 struct fw_params_param {
584 #define S_FW_PARAMS_CMD_PFN 8
585 #define M_FW_PARAMS_CMD_PFN 0x7
586 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
587 #define G_FW_PARAMS_CMD_PFN(x) \
588 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
590 #define S_FW_PARAMS_CMD_VFN 0
591 #define M_FW_PARAMS_CMD_VFN 0xff
592 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
593 #define G_FW_PARAMS_CMD_VFN(x) \
594 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
601 __be32 tc_to_nexactf;
602 __be32 r_caps_to_nethctrl;
608 #define S_FW_PFVF_CMD_NIQFLINT 20
609 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
610 #define G_FW_PFVF_CMD_NIQFLINT(x) \
611 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
613 #define S_FW_PFVF_CMD_NIQ 0
614 #define M_FW_PFVF_CMD_NIQ 0xfffff
615 #define G_FW_PFVF_CMD_NIQ(x) \
616 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
618 #define S_FW_PFVF_CMD_PMASK 20
619 #define M_FW_PFVF_CMD_PMASK 0xf
620 #define G_FW_PFVF_CMD_PMASK(x) \
621 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
623 #define S_FW_PFVF_CMD_NEQ 0
624 #define M_FW_PFVF_CMD_NEQ 0xfffff
625 #define G_FW_PFVF_CMD_NEQ(x) \
626 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
628 #define S_FW_PFVF_CMD_TC 24
629 #define M_FW_PFVF_CMD_TC 0xff
630 #define G_FW_PFVF_CMD_TC(x) \
631 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
633 #define S_FW_PFVF_CMD_NVI 16
634 #define M_FW_PFVF_CMD_NVI 0xff
635 #define G_FW_PFVF_CMD_NVI(x) \
636 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
638 #define S_FW_PFVF_CMD_NEXACTF 0
639 #define M_FW_PFVF_CMD_NEXACTF 0xffff
640 #define G_FW_PFVF_CMD_NEXACTF(x) \
641 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
643 #define S_FW_PFVF_CMD_R_CAPS 24
644 #define M_FW_PFVF_CMD_R_CAPS 0xff
645 #define G_FW_PFVF_CMD_R_CAPS(x) \
646 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
648 #define S_FW_PFVF_CMD_WX_CAPS 16
649 #define M_FW_PFVF_CMD_WX_CAPS 0xff
650 #define G_FW_PFVF_CMD_WX_CAPS(x) \
651 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
653 #define S_FW_PFVF_CMD_NETHCTRL 0
654 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
655 #define G_FW_PFVF_CMD_NETHCTRL(x) \
656 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
659 * ingress queue type; the first 1K ingress queues can have associated 0,
660 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
664 FW_IQ_TYPE_FL_INT_CAP,
669 __be32 alloc_to_len16;
674 __be32 type_to_iqandstindex;
675 __be16 iqdroprss_to_iqesize;
678 __be32 iqns_to_fl0congen;
679 __be16 fl0dcaen_to_fl0cidxfthresh;
682 __be32 fl1cngchmap_to_fl1congen;
683 __be16 fl1dcaen_to_fl1cidxfthresh;
688 #define S_FW_IQ_CMD_PFN 8
689 #define M_FW_IQ_CMD_PFN 0x7
690 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
691 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
693 #define S_FW_IQ_CMD_VFN 0
694 #define M_FW_IQ_CMD_VFN 0xff
695 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
696 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
698 #define S_FW_IQ_CMD_ALLOC 31
699 #define M_FW_IQ_CMD_ALLOC 0x1
700 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
701 #define G_FW_IQ_CMD_ALLOC(x) \
702 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
703 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
705 #define S_FW_IQ_CMD_FREE 30
706 #define M_FW_IQ_CMD_FREE 0x1
707 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
708 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
709 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
711 #define S_FW_IQ_CMD_IQSTART 28
712 #define M_FW_IQ_CMD_IQSTART 0x1
713 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
714 #define G_FW_IQ_CMD_IQSTART(x) \
715 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
716 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
718 #define S_FW_IQ_CMD_IQSTOP 27
719 #define M_FW_IQ_CMD_IQSTOP 0x1
720 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
721 #define G_FW_IQ_CMD_IQSTOP(x) \
722 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
723 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
725 #define S_FW_IQ_CMD_TYPE 29
726 #define M_FW_IQ_CMD_TYPE 0x7
727 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
728 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
730 #define S_FW_IQ_CMD_IQASYNCH 28
731 #define M_FW_IQ_CMD_IQASYNCH 0x1
732 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
733 #define G_FW_IQ_CMD_IQASYNCH(x) \
734 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
735 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
737 #define S_FW_IQ_CMD_VIID 16
738 #define M_FW_IQ_CMD_VIID 0xfff
739 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
740 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
742 #define S_FW_IQ_CMD_IQANDST 15
743 #define M_FW_IQ_CMD_IQANDST 0x1
744 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
745 #define G_FW_IQ_CMD_IQANDST(x) \
746 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
747 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
749 #define S_FW_IQ_CMD_IQANUD 12
750 #define M_FW_IQ_CMD_IQANUD 0x3
751 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
752 #define G_FW_IQ_CMD_IQANUD(x) \
753 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
755 #define S_FW_IQ_CMD_IQANDSTINDEX 0
756 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
757 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
758 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
759 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
761 #define S_FW_IQ_CMD_IQGTSMODE 14
762 #define M_FW_IQ_CMD_IQGTSMODE 0x1
763 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
764 #define G_FW_IQ_CMD_IQGTSMODE(x) \
765 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
766 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
768 #define S_FW_IQ_CMD_IQPCIECH 12
769 #define M_FW_IQ_CMD_IQPCIECH 0x3
770 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
771 #define G_FW_IQ_CMD_IQPCIECH(x) \
772 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
774 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
775 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
776 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
777 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
778 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
780 #define S_FW_IQ_CMD_IQESIZE 0
781 #define M_FW_IQ_CMD_IQESIZE 0x3
782 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
783 #define G_FW_IQ_CMD_IQESIZE(x) \
784 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
786 #define S_FW_IQ_CMD_IQRO 30
787 #define M_FW_IQ_CMD_IQRO 0x1
788 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
789 #define G_FW_IQ_CMD_IQRO(x) \
790 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
791 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
793 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
794 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
795 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
796 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
797 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
798 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
800 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
801 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
802 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
803 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
804 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
806 #define S_FW_IQ_CMD_FL0DATARO 12
807 #define M_FW_IQ_CMD_FL0DATARO 0x1
808 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
809 #define G_FW_IQ_CMD_FL0DATARO(x) \
810 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
811 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
813 #define S_FW_IQ_CMD_FL0CONGCIF 11
814 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
815 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
816 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
817 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
818 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
820 #define S_FW_IQ_CMD_FL0FETCHRO 6
821 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
822 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
823 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
824 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
825 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
827 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
828 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
829 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
830 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
831 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
833 #define S_FW_IQ_CMD_FL0PADEN 2
834 #define M_FW_IQ_CMD_FL0PADEN 0x1
835 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
836 #define G_FW_IQ_CMD_FL0PADEN(x) \
837 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
838 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
840 #define S_FW_IQ_CMD_FL0PACKEN 1
841 #define M_FW_IQ_CMD_FL0PACKEN 0x1
842 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
843 #define G_FW_IQ_CMD_FL0PACKEN(x) \
844 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
845 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
847 #define S_FW_IQ_CMD_FL0CONGEN 0
848 #define M_FW_IQ_CMD_FL0CONGEN 0x1
849 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
850 #define G_FW_IQ_CMD_FL0CONGEN(x) \
851 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
852 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
854 #define S_FW_IQ_CMD_FL0FBMIN 7
855 #define M_FW_IQ_CMD_FL0FBMIN 0x7
856 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
857 #define G_FW_IQ_CMD_FL0FBMIN(x) \
858 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
860 #define S_FW_IQ_CMD_FL0FBMAX 4
861 #define M_FW_IQ_CMD_FL0FBMAX 0x7
862 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
863 #define G_FW_IQ_CMD_FL0FBMAX(x) \
864 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
866 struct fw_eq_eth_cmd {
868 __be32 alloc_to_len16;
871 __be32 fetchszm_to_iqid;
872 __be32 dcaen_to_eqsize;
874 __be32 autoequiqe_to_viid;
879 #define S_FW_EQ_ETH_CMD_PFN 8
880 #define M_FW_EQ_ETH_CMD_PFN 0x7
881 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
882 #define G_FW_EQ_ETH_CMD_PFN(x) \
883 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
885 #define S_FW_EQ_ETH_CMD_VFN 0
886 #define M_FW_EQ_ETH_CMD_VFN 0xff
887 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
888 #define G_FW_EQ_ETH_CMD_VFN(x) \
889 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
891 #define S_FW_EQ_ETH_CMD_ALLOC 31
892 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
893 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
894 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
895 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
896 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
898 #define S_FW_EQ_ETH_CMD_FREE 30
899 #define M_FW_EQ_ETH_CMD_FREE 0x1
900 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
901 #define G_FW_EQ_ETH_CMD_FREE(x) \
902 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
903 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
905 #define S_FW_EQ_ETH_CMD_EQSTART 28
906 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
907 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
908 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
909 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
910 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
912 #define S_FW_EQ_ETH_CMD_EQID 0
913 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
914 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
915 #define G_FW_EQ_ETH_CMD_EQID(x) \
916 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
918 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
919 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
920 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
921 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
923 #define S_FW_EQ_ETH_CMD_FETCHRO 22
924 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
925 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
926 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
927 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
928 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
930 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
931 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
932 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
933 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
934 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
936 #define S_FW_EQ_ETH_CMD_PCIECHN 16
937 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
938 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
939 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
940 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
942 #define S_FW_EQ_ETH_CMD_IQID 0
943 #define M_FW_EQ_ETH_CMD_IQID 0xffff
944 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
945 #define G_FW_EQ_ETH_CMD_IQID(x) \
946 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
948 #define S_FW_EQ_ETH_CMD_FBMIN 23
949 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
950 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
951 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
952 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
954 #define S_FW_EQ_ETH_CMD_FBMAX 20
955 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
956 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
957 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
958 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
960 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
961 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
962 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
963 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
964 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
966 #define S_FW_EQ_ETH_CMD_EQSIZE 0
967 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
968 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
969 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
970 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
972 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
973 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
974 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
975 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
976 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
977 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
979 #define S_FW_EQ_ETH_CMD_VIID 16
980 #define M_FW_EQ_ETH_CMD_VIID 0xfff
981 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
982 #define G_FW_EQ_ETH_CMD_VIID(x) \
983 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
991 __be32 alloc_to_len16;
997 __be16 norss_rsssize;
1007 #define S_FW_VI_CMD_PFN 8
1008 #define M_FW_VI_CMD_PFN 0x7
1009 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1010 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1012 #define S_FW_VI_CMD_VFN 0
1013 #define M_FW_VI_CMD_VFN 0xff
1014 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1015 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1017 #define S_FW_VI_CMD_ALLOC 31
1018 #define M_FW_VI_CMD_ALLOC 0x1
1019 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1020 #define G_FW_VI_CMD_ALLOC(x) \
1021 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1022 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1024 #define S_FW_VI_CMD_FREE 30
1025 #define M_FW_VI_CMD_FREE 0x1
1026 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1027 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1028 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1030 #define S_FW_VI_CMD_TYPE 15
1031 #define M_FW_VI_CMD_TYPE 0x1
1032 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1033 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1034 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1036 #define S_FW_VI_CMD_FUNC 12
1037 #define M_FW_VI_CMD_FUNC 0x7
1038 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1039 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1041 #define S_FW_VI_CMD_VIID 0
1042 #define M_FW_VI_CMD_VIID 0xfff
1043 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1044 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1046 #define S_FW_VI_CMD_PORTID 4
1047 #define M_FW_VI_CMD_PORTID 0xf
1048 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1049 #define G_FW_VI_CMD_PORTID(x) \
1050 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1052 #define S_FW_VI_CMD_RSSSIZE 0
1053 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1054 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1055 #define G_FW_VI_CMD_RSSSIZE(x) \
1056 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1058 /* Special VI_MAC command index ids */
1059 #define FW_VI_MAC_ADD_MAC 0x3FF
1060 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1062 enum fw_vi_mac_smac {
1063 FW_VI_MAC_MPS_TCAM_ENTRY,
1064 FW_VI_MAC_SMT_AND_MPSTCAM
1067 struct fw_vi_mac_cmd {
1069 __be32 freemacs_to_len16;
1071 struct fw_vi_mac_exact {
1072 __be16 valid_to_idx;
1075 struct fw_vi_mac_hash {
1081 #define S_FW_VI_MAC_CMD_VIID 0
1082 #define M_FW_VI_MAC_CMD_VIID 0xfff
1083 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1084 #define G_FW_VI_MAC_CMD_VIID(x) \
1085 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1087 #define S_FW_VI_MAC_CMD_VALID 15
1088 #define M_FW_VI_MAC_CMD_VALID 0x1
1089 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1090 #define G_FW_VI_MAC_CMD_VALID(x) \
1091 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1092 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1094 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1095 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1096 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1097 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1098 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1100 #define S_FW_VI_MAC_CMD_IDX 0
1101 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1102 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1103 #define G_FW_VI_MAC_CMD_IDX(x) \
1104 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1106 struct fw_vi_rxmode_cmd {
1108 __be32 retval_len16;
1109 __be32 mtu_to_vlanexen;
1113 #define S_FW_VI_RXMODE_CMD_VIID 0
1114 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1115 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1116 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1117 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1119 #define S_FW_VI_RXMODE_CMD_MTU 16
1120 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1121 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1122 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1123 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1125 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1126 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1127 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1128 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1129 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1131 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1132 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1133 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1134 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1135 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1136 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1138 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1139 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1140 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1141 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1142 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1143 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1144 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1146 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1147 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1148 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1149 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1150 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1152 struct fw_vi_enable_cmd {
1154 __be32 ien_to_len16;
1160 #define S_FW_VI_ENABLE_CMD_VIID 0
1161 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1162 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1163 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1164 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1166 #define S_FW_VI_ENABLE_CMD_IEN 31
1167 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1168 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1169 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1170 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1171 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1173 #define S_FW_VI_ENABLE_CMD_EEN 30
1174 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1175 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1176 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1177 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1178 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1180 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1181 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1182 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1183 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1184 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1185 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1187 /* VI VF stats offset definitions */
1188 #define VI_VF_NUM_STATS 16
1190 /* VI PF stats offset definitions */
1191 #define VI_PF_NUM_STATS 17
1192 enum fw_vi_stats_pf_index {
1193 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1194 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1195 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1196 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1197 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1198 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1199 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1200 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1201 FW_VI_PF_STAT_RX_BYTES_IX,
1202 FW_VI_PF_STAT_RX_FRAMES_IX,
1203 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1204 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1205 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1206 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1207 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1208 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1209 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1212 struct fw_vi_stats_cmd {
1214 __be32 retval_len16;
1216 struct fw_vi_stats_ctl {
1227 struct fw_vi_stats_pf {
1228 __be64 tx_bcast_bytes;
1229 __be64 tx_bcast_frames;
1230 __be64 tx_mcast_bytes;
1231 __be64 tx_mcast_frames;
1232 __be64 tx_ucast_bytes;
1233 __be64 tx_ucast_frames;
1234 __be64 tx_offload_bytes;
1235 __be64 tx_offload_frames;
1237 __be64 rx_pf_frames;
1238 __be64 rx_bcast_bytes;
1239 __be64 rx_bcast_frames;
1240 __be64 rx_mcast_bytes;
1241 __be64 rx_mcast_frames;
1242 __be64 rx_ucast_bytes;
1243 __be64 rx_ucast_frames;
1244 __be64 rx_err_frames;
1246 struct fw_vi_stats_vf {
1247 __be64 tx_bcast_bytes;
1248 __be64 tx_bcast_frames;
1249 __be64 tx_mcast_bytes;
1250 __be64 tx_mcast_frames;
1251 __be64 tx_ucast_bytes;
1252 __be64 tx_ucast_frames;
1253 __be64 tx_drop_frames;
1254 __be64 tx_offload_bytes;
1255 __be64 tx_offload_frames;
1256 __be64 rx_bcast_bytes;
1257 __be64 rx_bcast_frames;
1258 __be64 rx_mcast_bytes;
1259 __be64 rx_mcast_frames;
1260 __be64 rx_ucast_bytes;
1261 __be64 rx_ucast_frames;
1262 __be64 rx_err_frames;
1267 #define S_FW_VI_STATS_CMD_VIID 0
1268 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1270 #define S_FW_VI_STATS_CMD_NSTATS 12
1271 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1273 #define S_FW_VI_STATS_CMD_IX 0
1274 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1276 /* old 16-bit port capabilities bitmap */
1278 FW_PORT_CAP_SPEED_100M = 0x0001,
1279 FW_PORT_CAP_SPEED_1G = 0x0002,
1280 FW_PORT_CAP_SPEED_25G = 0x0004,
1281 FW_PORT_CAP_SPEED_10G = 0x0008,
1282 FW_PORT_CAP_SPEED_40G = 0x0010,
1283 FW_PORT_CAP_SPEED_100G = 0x0020,
1284 FW_PORT_CAP_FC_RX = 0x0040,
1285 FW_PORT_CAP_FC_TX = 0x0080,
1286 FW_PORT_CAP_ANEG = 0x0100,
1287 FW_PORT_CAP_MDIX = 0x0200,
1288 FW_PORT_CAP_MDIAUTO = 0x0400,
1289 FW_PORT_CAP_FEC_RS = 0x0800,
1290 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1291 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1292 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1293 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1296 #define S_FW_PORT_CAP_SPEED 0
1297 #define M_FW_PORT_CAP_SPEED 0x3f
1298 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1299 #define G_FW_PORT_CAP_SPEED(x) \
1300 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1303 FW_PORT_CAP_MDI_AUTO,
1306 #define S_FW_PORT_CAP_MDI 9
1307 #define M_FW_PORT_CAP_MDI 3
1308 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1309 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1311 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1312 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1313 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1314 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1315 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1316 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1317 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1318 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1319 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1320 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1321 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1322 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1323 #define FW_PORT_CAP32_ANEG 0x00100000UL
1324 #define FW_PORT_CAP32_MDIX 0x00200000UL
1325 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1326 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1327 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1329 #define S_FW_PORT_CAP32_SPEED 0
1330 #define M_FW_PORT_CAP32_SPEED 0xfff
1331 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1332 #define G_FW_PORT_CAP32_SPEED(x) \
1333 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1335 enum fw_port_mdi32 {
1336 FW_PORT_CAP32_MDI_AUTO,
1339 #define S_FW_PORT_CAP32_MDI 21
1340 #define M_FW_PORT_CAP32_MDI 3
1341 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1342 #define G_FW_PORT_CAP32_MDI(x) \
1343 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1345 enum fw_port_action {
1346 FW_PORT_ACTION_L1_CFG = 0x0001,
1347 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1348 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1349 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1352 struct fw_port_cmd {
1353 __be32 op_to_portid;
1354 __be32 action_to_len16;
1356 struct fw_port_l1cfg {
1360 struct fw_port_l2cfg {
1362 __u8 ovlan3_to_ivlan0;
1364 __be16 txipg_force_pinfo;
1375 struct fw_port_info {
1376 __be32 lstatus_to_modtype;
1387 struct fw_port_diags {
1393 struct fw_port_dcb_pgid {
1400 struct fw_port_dcb_pgrate {
1404 __u8 num_tcs_supported;
1408 struct fw_port_dcb_priorate {
1412 __u8 strict_priorate[8];
1414 struct fw_port_dcb_pfc {
1421 struct fw_port_app_priority {
1430 struct fw_port_dcb_control {
1433 __be16 dcb_version_to_app_state;
1438 struct fw_port_l1cfg32 {
1442 struct fw_port_info32 {
1443 __be32 lstatus32_to_cbllen32;
1444 __be32 auxlinfo32_mtu32;
1453 #define S_FW_PORT_CMD_PORTID 0
1454 #define M_FW_PORT_CMD_PORTID 0xf
1455 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1456 #define G_FW_PORT_CMD_PORTID(x) \
1457 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1459 #define S_FW_PORT_CMD_ACTION 16
1460 #define M_FW_PORT_CMD_ACTION 0xffff
1461 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1462 #define G_FW_PORT_CMD_ACTION(x) \
1463 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1465 #define S_FW_PORT_CMD_LSTATUS 31
1466 #define M_FW_PORT_CMD_LSTATUS 0x1
1467 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1468 #define G_FW_PORT_CMD_LSTATUS(x) \
1469 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1470 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1472 #define S_FW_PORT_CMD_LSPEED 24
1473 #define M_FW_PORT_CMD_LSPEED 0x3f
1474 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1475 #define G_FW_PORT_CMD_LSPEED(x) \
1476 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1478 #define S_FW_PORT_CMD_TXPAUSE 23
1479 #define M_FW_PORT_CMD_TXPAUSE 0x1
1480 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1481 #define G_FW_PORT_CMD_TXPAUSE(x) \
1482 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1483 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1485 #define S_FW_PORT_CMD_RXPAUSE 22
1486 #define M_FW_PORT_CMD_RXPAUSE 0x1
1487 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1488 #define G_FW_PORT_CMD_RXPAUSE(x) \
1489 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1490 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1492 #define S_FW_PORT_CMD_MDIOCAP 21
1493 #define M_FW_PORT_CMD_MDIOCAP 0x1
1494 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1495 #define G_FW_PORT_CMD_MDIOCAP(x) \
1496 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1497 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1499 #define S_FW_PORT_CMD_MDIOADDR 16
1500 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1501 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1502 #define G_FW_PORT_CMD_MDIOADDR(x) \
1503 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1505 #define S_FW_PORT_CMD_PTYPE 8
1506 #define M_FW_PORT_CMD_PTYPE 0x1f
1507 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1508 #define G_FW_PORT_CMD_PTYPE(x) \
1509 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1511 #define S_FW_PORT_CMD_LINKDNRC 5
1512 #define M_FW_PORT_CMD_LINKDNRC 0x7
1513 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1514 #define G_FW_PORT_CMD_LINKDNRC(x) \
1515 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1517 #define S_FW_PORT_CMD_MODTYPE 0
1518 #define M_FW_PORT_CMD_MODTYPE 0x1f
1519 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1520 #define G_FW_PORT_CMD_MODTYPE(x) \
1521 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1523 #define S_FW_PORT_CMD_LSTATUS32 31
1524 #define M_FW_PORT_CMD_LSTATUS32 0x1
1525 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1526 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1528 #define S_FW_PORT_CMD_LINKDNRC32 28
1529 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1530 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1531 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1533 #define S_FW_PORT_CMD_MDIOCAP32 26
1534 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1535 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1536 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1538 #define S_FW_PORT_CMD_MDIOADDR32 21
1539 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1540 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1541 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1543 #define S_FW_PORT_CMD_PORTTYPE32 13
1544 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1545 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1546 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1548 #define S_FW_PORT_CMD_MODTYPE32 8
1549 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1550 #define G_FW_PORT_CMD_MODTYPE32(x) \
1551 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1554 * These are configured into the VPD and hence tools that generate
1555 * VPD may use this enumeration.
1556 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1559 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1560 * with any new Firmware Port Technology Types!
1563 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1564 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1565 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1566 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1567 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1568 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1569 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1570 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1571 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1572 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1573 FW_PORT_TYPE_BP_AP = 10,
1574 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1575 FW_PORT_TYPE_BP4_AP = 11,
1576 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1577 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1578 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1579 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1580 FW_PORT_TYPE_BP40_BA = 15,
1581 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1582 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1583 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1584 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1585 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1586 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1587 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1588 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1591 /* These are read from module's EEPROM and determined once the
1592 * module is inserted.
1594 enum fw_port_module_type {
1595 FW_PORT_MOD_TYPE_NA = 0x0,
1596 FW_PORT_MOD_TYPE_LR = 0x1,
1597 FW_PORT_MOD_TYPE_SR = 0x2,
1598 FW_PORT_MOD_TYPE_ER = 0x3,
1599 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1600 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1601 FW_PORT_MOD_TYPE_LRM = 0x6,
1602 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1603 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1604 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1605 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1608 /* used by FW and tools may use this to generate VPD */
1609 enum fw_port_mod_sub_type {
1610 FW_PORT_MOD_SUB_TYPE_NA,
1611 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1612 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1613 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1614 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1615 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1616 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1617 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1618 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1621 * The following will never been in the VPD. They are TWINAX cable
1622 * lengths decoded from SFP+ module i2c PROMs. These should almost
1623 * certainly go somewhere else ...
1625 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1626 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1627 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1628 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1631 /* link down reason codes (3b) */
1632 enum fw_port_link_dn_rc {
1633 FW_PORT_LINK_DN_RC_NONE,
1634 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1635 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1636 FW_PORT_LINK_DN_RESERVED3,
1637 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1638 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1639 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1640 FW_PORT_LINK_DN_RESERVED7
1644 #define FW_NUM_PORT_STATS 50
1645 #define FW_NUM_PORT_TX_STATS 23
1646 #define FW_NUM_PORT_RX_STATS 27
1648 enum fw_port_stats_tx_index {
1649 FW_STAT_TX_PORT_BYTES_IX,
1650 FW_STAT_TX_PORT_FRAMES_IX,
1651 FW_STAT_TX_PORT_BCAST_IX,
1652 FW_STAT_TX_PORT_MCAST_IX,
1653 FW_STAT_TX_PORT_UCAST_IX,
1654 FW_STAT_TX_PORT_ERROR_IX,
1655 FW_STAT_TX_PORT_64B_IX,
1656 FW_STAT_TX_PORT_65B_127B_IX,
1657 FW_STAT_TX_PORT_128B_255B_IX,
1658 FW_STAT_TX_PORT_256B_511B_IX,
1659 FW_STAT_TX_PORT_512B_1023B_IX,
1660 FW_STAT_TX_PORT_1024B_1518B_IX,
1661 FW_STAT_TX_PORT_1519B_MAX_IX,
1662 FW_STAT_TX_PORT_DROP_IX,
1663 FW_STAT_TX_PORT_PAUSE_IX,
1664 FW_STAT_TX_PORT_PPP0_IX,
1665 FW_STAT_TX_PORT_PPP1_IX,
1666 FW_STAT_TX_PORT_PPP2_IX,
1667 FW_STAT_TX_PORT_PPP3_IX,
1668 FW_STAT_TX_PORT_PPP4_IX,
1669 FW_STAT_TX_PORT_PPP5_IX,
1670 FW_STAT_TX_PORT_PPP6_IX,
1671 FW_STAT_TX_PORT_PPP7_IX
1674 enum fw_port_stat_rx_index {
1675 FW_STAT_RX_PORT_BYTES_IX,
1676 FW_STAT_RX_PORT_FRAMES_IX,
1677 FW_STAT_RX_PORT_BCAST_IX,
1678 FW_STAT_RX_PORT_MCAST_IX,
1679 FW_STAT_RX_PORT_UCAST_IX,
1680 FW_STAT_RX_PORT_MTU_ERROR_IX,
1681 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1682 FW_STAT_RX_PORT_CRC_ERROR_IX,
1683 FW_STAT_RX_PORT_LEN_ERROR_IX,
1684 FW_STAT_RX_PORT_SYM_ERROR_IX,
1685 FW_STAT_RX_PORT_64B_IX,
1686 FW_STAT_RX_PORT_65B_127B_IX,
1687 FW_STAT_RX_PORT_128B_255B_IX,
1688 FW_STAT_RX_PORT_256B_511B_IX,
1689 FW_STAT_RX_PORT_512B_1023B_IX,
1690 FW_STAT_RX_PORT_1024B_1518B_IX,
1691 FW_STAT_RX_PORT_1519B_MAX_IX,
1692 FW_STAT_RX_PORT_PAUSE_IX,
1693 FW_STAT_RX_PORT_PPP0_IX,
1694 FW_STAT_RX_PORT_PPP1_IX,
1695 FW_STAT_RX_PORT_PPP2_IX,
1696 FW_STAT_RX_PORT_PPP3_IX,
1697 FW_STAT_RX_PORT_PPP4_IX,
1698 FW_STAT_RX_PORT_PPP5_IX,
1699 FW_STAT_RX_PORT_PPP6_IX,
1700 FW_STAT_RX_PORT_PPP7_IX,
1701 FW_STAT_RX_PORT_LESS_64B_IX
1704 struct fw_port_stats_cmd {
1705 __be32 op_to_portid;
1706 __be32 retval_len16;
1707 union fw_port_stats {
1708 struct fw_port_stats_ctl {
1720 struct fw_port_stats_all {
1729 __be64 tx_128b_255b;
1730 __be64 tx_256b_511b;
1731 __be64 tx_512b_1023b;
1732 __be64 tx_1024b_1518b;
1733 __be64 tx_1519b_max;
1749 __be64 rx_mtu_error;
1750 __be64 rx_mtu_crc_error;
1751 __be64 rx_crc_error;
1752 __be64 rx_len_error;
1753 __be64 rx_sym_error;
1756 __be64 rx_128b_255b;
1757 __be64 rx_256b_511b;
1758 __be64 rx_512b_1023b;
1759 __be64 rx_1024b_1518b;
1760 __be64 rx_1519b_max;
1777 struct fw_rss_ind_tbl_cmd {
1779 __be32 retval_len16;
1787 __be32 iq12_to_iq14;
1788 __be32 iq15_to_iq17;
1789 __be32 iq18_to_iq20;
1790 __be32 iq21_to_iq23;
1791 __be32 iq24_to_iq26;
1792 __be32 iq27_to_iq29;
1797 #define S_FW_RSS_IND_TBL_CMD_VIID 0
1798 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
1799 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
1800 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
1801 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
1803 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
1804 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
1805 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
1806 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
1807 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
1809 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
1810 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
1811 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
1812 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
1813 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
1815 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
1816 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
1817 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
1818 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
1819 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
1821 struct fw_rss_glb_config_cmd {
1823 __be32 retval_len16;
1824 union fw_rss_glb_config {
1825 struct fw_rss_glb_config_manual {
1831 struct fw_rss_glb_config_basicvirtual {
1832 __be32 mode_keymode;
1833 __be32 synmapen_to_hashtoeplitz;
1840 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
1841 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
1842 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
1843 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
1845 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
1847 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
1848 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
1849 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
1850 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
1852 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
1853 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
1854 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
1855 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
1856 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
1858 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
1859 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
1860 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
1861 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
1862 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
1864 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
1865 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
1866 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
1867 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
1868 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
1870 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
1871 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
1872 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
1873 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
1874 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
1876 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
1877 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
1878 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
1879 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
1881 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
1882 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
1883 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
1884 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
1886 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
1887 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
1888 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
1889 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
1890 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
1892 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
1893 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
1894 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
1895 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
1896 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
1898 struct fw_rss_vi_config_cmd {
1900 __be32 retval_len16;
1901 union fw_rss_vi_config {
1902 struct fw_rss_vi_config_manual {
1907 struct fw_rss_vi_config_basicvirtual {
1909 __be32 defaultq_to_udpen;
1916 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
1917 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
1918 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
1919 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
1920 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
1922 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
1923 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
1924 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1925 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1926 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1927 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
1928 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1930 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
1931 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
1932 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1933 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1934 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1935 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
1936 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1937 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
1938 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
1940 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
1941 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
1942 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1943 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1944 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1945 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
1946 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1947 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
1948 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
1950 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
1951 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
1952 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
1953 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1954 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
1955 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
1956 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1957 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
1958 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
1960 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
1961 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
1962 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
1963 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1964 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
1965 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
1966 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1967 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
1968 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
1970 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
1971 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
1972 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
1973 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
1974 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
1975 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
1977 /******************************************************************************
1978 * D E B U G C O M M A N D s
1979 ******************************************************/
1981 struct fw_debug_cmd {
1985 struct fw_debug_assert {
1990 __u8 filename_0_7[8];
1991 __u8 filename_8_15[8];
1994 struct fw_debug_prt {
1997 __be32 dprtstrparam0;
1998 __be32 dprtstrparam1;
1999 __be32 dprtstrparam2;
2000 __be32 dprtstrparam3;
2005 #define S_FW_DEBUG_CMD_TYPE 0
2006 #define M_FW_DEBUG_CMD_TYPE 0xff
2007 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2008 #define G_FW_DEBUG_CMD_TYPE(x) \
2009 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2011 /******************************************************************************
2012 * P C I E F W R E G I S T E R
2013 **************************************/
2016 * Register definitions for the PCIE_FW register which the firmware uses
2017 * to retain status across RESETs. This register should be considered
2018 * as a READ-ONLY register for Host Software and only to be used to
2019 * track firmware initialization/error state, etc.
2021 #define S_PCIE_FW_ERR 31
2022 #define M_PCIE_FW_ERR 0x1
2023 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2024 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2025 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2027 #define S_PCIE_FW_INIT 30
2028 #define M_PCIE_FW_INIT 0x1
2029 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2030 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2031 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2033 #define S_PCIE_FW_HALT 29
2034 #define M_PCIE_FW_HALT 0x1
2035 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2036 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2037 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2039 #define S_PCIE_FW_EVAL 24
2040 #define M_PCIE_FW_EVAL 0x7
2041 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2042 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2044 #define S_PCIE_FW_MASTER_VLD 15
2045 #define M_PCIE_FW_MASTER_VLD 0x1
2046 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2047 #define G_PCIE_FW_MASTER_VLD(x) \
2048 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2049 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2051 #define S_PCIE_FW_MASTER 12
2052 #define M_PCIE_FW_MASTER 0x7
2053 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2054 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2056 /******************************************************************************
2057 * B I N A R Y H E A D E R F O R M A T
2058 **********************************************/
2061 * firmware binary header format
2065 __u8 chip; /* terminator chip family */
2066 __be16 len512; /* bin length in units of 512-bytes */
2067 __be32 fw_ver; /* firmware version */
2068 __be32 tp_microcode_ver; /* tcp processor microcode version */
2073 __u8 intfver_iscsipdu;
2075 __u8 intfver_fcoepdu;
2079 __u32 magic; /* runtime or bootstrap fw */
2081 __be32 reserved6[23];
2084 #define S_FW_HDR_FW_VER_MAJOR 24
2085 #define M_FW_HDR_FW_VER_MAJOR 0xff
2086 #define V_FW_HDR_FW_VER_MAJOR(x) \
2087 ((x) << S_FW_HDR_FW_VER_MAJOR)
2088 #define G_FW_HDR_FW_VER_MAJOR(x) \
2089 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2091 #define S_FW_HDR_FW_VER_MINOR 16
2092 #define M_FW_HDR_FW_VER_MINOR 0xff
2093 #define V_FW_HDR_FW_VER_MINOR(x) \
2094 ((x) << S_FW_HDR_FW_VER_MINOR)
2095 #define G_FW_HDR_FW_VER_MINOR(x) \
2096 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2098 #define S_FW_HDR_FW_VER_MICRO 8
2099 #define M_FW_HDR_FW_VER_MICRO 0xff
2100 #define V_FW_HDR_FW_VER_MICRO(x) \
2101 ((x) << S_FW_HDR_FW_VER_MICRO)
2102 #define G_FW_HDR_FW_VER_MICRO(x) \
2103 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2105 #define S_FW_HDR_FW_VER_BUILD 0
2106 #define M_FW_HDR_FW_VER_BUILD 0xff
2107 #define V_FW_HDR_FW_VER_BUILD(x) \
2108 ((x) << S_FW_HDR_FW_VER_BUILD)
2109 #define G_FW_HDR_FW_VER_BUILD(x) \
2110 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2112 #endif /* _T4FW_INTERFACE_H_ */