1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
58 FW_ETH_TX_PKT_WR = 0x08,
59 FW_ETH_TX_PKTS_WR = 0x09,
60 FW_ETH_TX_PKT_VM_WR = 0x11,
61 FW_ETH_TX_PKTS_VM_WR = 0x12,
62 FW_ETH_TX_PKTS2_WR = 0x78,
66 * Generic work request header flit0
73 /* work request opcode (hi)
76 #define M_FW_WR_OP 0xff
77 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
78 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
80 /* work request immediate data length (hi)
82 #define S_FW_WR_IMMDLEN 0
83 #define M_FW_WR_IMMDLEN 0xff
84 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
85 #define G_FW_WR_IMMDLEN(x) \
86 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
88 /* egress queue status update to egress queue status entry (lo)
90 #define S_FW_WR_EQUEQ 30
91 #define M_FW_WR_EQUEQ 0x1
92 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
93 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
94 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
96 /* length in units of 16-bytes (lo)
98 #define S_FW_WR_LEN16 0
99 #define M_FW_WR_LEN16 0xff
100 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
101 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
103 struct fw_eth_tx_pkt_wr {
105 __be32 equiq_to_len16;
109 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
110 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
111 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
112 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
113 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
115 struct fw_eth_tx_pkts_wr {
117 __be32 equiq_to_len16;
124 struct fw_eth_tx_pkt_vm_wr {
126 __be32 equiq_to_len16;
134 struct fw_eth_tx_pkts_vm_wr {
136 __be32 equiq_to_len16;
147 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
148 enum fw_filter_wr_cookie {
149 FW_FILTER_WR_SUCCESS,
150 FW_FILTER_WR_FLT_ADDED,
151 FW_FILTER_WR_FLT_DELETED,
152 FW_FILTER_WR_SMT_TBL_FULL,
156 struct fw_filter_wr {
161 __be32 del_filter_to_l2tix;
164 __u8 frag_to_ovlan_vldm;
166 __be16 rx_chan_rx_rpl_iq;
167 __be32 maci_to_matchtypem;
188 #define S_FW_FILTER_WR_TID 12
189 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
191 #define S_FW_FILTER_WR_RQTYPE 11
192 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
194 #define S_FW_FILTER_WR_NOREPLY 10
195 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
197 #define S_FW_FILTER_WR_IQ 0
198 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
200 #define S_FW_FILTER_WR_DEL_FILTER 31
201 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
202 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
204 #define S_FW_FILTER_WR_RPTTID 25
205 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
207 #define S_FW_FILTER_WR_DROP 24
208 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
210 #define S_FW_FILTER_WR_DIRSTEER 23
211 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
213 #define S_FW_FILTER_WR_MASKHASH 22
214 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
216 #define S_FW_FILTER_WR_DIRSTEERHASH 21
217 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
219 #define S_FW_FILTER_WR_LPBK 20
220 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
222 #define S_FW_FILTER_WR_DMAC 19
223 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
225 #define S_FW_FILTER_WR_INSVLAN 17
226 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
228 #define S_FW_FILTER_WR_RMVLAN 16
229 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
231 #define S_FW_FILTER_WR_HITCNTS 15
232 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
234 #define S_FW_FILTER_WR_TXCHAN 13
235 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
237 #define S_FW_FILTER_WR_PRIO 12
238 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
240 #define S_FW_FILTER_WR_L2TIX 0
241 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
243 #define S_FW_FILTER_WR_FRAG 7
244 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
246 #define S_FW_FILTER_WR_FRAGM 6
247 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
249 #define S_FW_FILTER_WR_IVLAN_VLD 5
250 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
252 #define S_FW_FILTER_WR_OVLAN_VLD 4
253 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
255 #define S_FW_FILTER_WR_IVLAN_VLDM 3
256 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
258 #define S_FW_FILTER_WR_OVLAN_VLDM 2
259 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
261 #define S_FW_FILTER_WR_RX_CHAN 15
262 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
264 #define S_FW_FILTER_WR_RX_RPL_IQ 0
265 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
267 #define S_FW_FILTER_WR_MACI 23
268 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
270 #define S_FW_FILTER_WR_MACIM 14
271 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
273 #define S_FW_FILTER_WR_FCOE 13
274 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
276 #define S_FW_FILTER_WR_FCOEM 12
277 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
279 #define S_FW_FILTER_WR_PORT 9
280 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
282 #define S_FW_FILTER_WR_PORTM 6
283 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
285 #define S_FW_FILTER_WR_MATCHTYPE 3
286 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
288 #define S_FW_FILTER_WR_MATCHTYPEM 0
289 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
291 /******************************************************************************
293 *********************/
296 * The maximum length of time, in miliseconds, that we expect any firmware
297 * command to take to execute and return a reply to the host. The RESET
298 * and INITIALIZE commands can take a fair amount of time to execute but
299 * most execute in far less time than this maximum. This constant is used
300 * by host software to determine how long to wait for a firmware command
301 * reply before declaring the firmware as dead/unreachable ...
303 #define FW_CMD_MAX_TIMEOUT 10000
306 * If a host driver does a HELLO and discovers that there's already a MASTER
307 * selected, we may have to wait for that MASTER to finish issuing RESET,
308 * configuration and INITIALIZE commands. Also, there's a possibility that
309 * our own HELLO may get lost if it happens right as the MASTER is issuign a
310 * RESET command, so we need to be willing to make a few retries of our HELLO.
312 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
313 #define FW_CMD_HELLO_RETRIES 3
315 enum fw_cmd_opcodes {
320 FW_INITIALIZE_CMD = 0x06,
321 FW_CAPS_CONFIG_CMD = 0x07,
322 FW_PARAMS_CMD = 0x08,
325 FW_EQ_ETH_CMD = 0x12,
326 FW_EQ_CTRL_CMD = 0x13,
328 FW_VI_MAC_CMD = 0x15,
329 FW_VI_RXMODE_CMD = 0x16,
330 FW_VI_ENABLE_CMD = 0x17,
331 FW_VI_STATS_CMD = 0x1a,
333 FW_RSS_IND_TBL_CMD = 0x20,
334 FW_RSS_GLB_CONFIG_CMD = 0x22,
335 FW_RSS_VI_CONFIG_CMD = 0x23,
340 FW_CMD_CAP_PORT = 0x04,
344 * Generic command header flit0
351 #define S_FW_CMD_OP 24
352 #define M_FW_CMD_OP 0xff
353 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
354 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
356 #define S_FW_CMD_REQUEST 23
357 #define M_FW_CMD_REQUEST 0x1
358 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
359 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
360 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
362 #define S_FW_CMD_READ 22
363 #define M_FW_CMD_READ 0x1
364 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
365 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
366 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
368 #define S_FW_CMD_WRITE 21
369 #define M_FW_CMD_WRITE 0x1
370 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
371 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
372 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
374 #define S_FW_CMD_EXEC 20
375 #define M_FW_CMD_EXEC 0x1
376 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
377 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
378 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
380 #define S_FW_CMD_RETVAL 8
381 #define M_FW_CMD_RETVAL 0xff
382 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
383 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
385 #define S_FW_CMD_LEN16 0
386 #define M_FW_CMD_LEN16 0xff
387 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
388 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
390 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
394 enum fw_ldst_addrspc {
395 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
399 __be32 op_to_addrspace;
400 __be32 cycles_to_len16;
402 struct fw_ldst_addrval {
406 struct fw_ldst_idctxt {
408 __be32 msg_ctxtflush;
418 struct fw_ldst_mdio {
434 struct fw_ldst_func {
442 struct fw_ldst_pcie {
452 struct fw_ldst_i2c_deprecated {
476 #define S_FW_LDST_CMD_ADDRSPACE 0
477 #define M_FW_LDST_CMD_ADDRSPACE 0xff
478 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
480 struct fw_reset_cmd {
487 #define S_FW_RESET_CMD_HALT 31
488 #define M_FW_RESET_CMD_HALT 0x1
489 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
490 #define G_FW_RESET_CMD_HALT(x) \
491 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
492 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
495 FW_HELLO_CMD_STAGE_OS = 0,
498 struct fw_hello_cmd {
501 __be32 err_to_clearinit;
505 #define S_FW_HELLO_CMD_ERR 31
506 #define M_FW_HELLO_CMD_ERR 0x1
507 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
508 #define G_FW_HELLO_CMD_ERR(x) \
509 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
510 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
512 #define S_FW_HELLO_CMD_INIT 30
513 #define M_FW_HELLO_CMD_INIT 0x1
514 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
515 #define G_FW_HELLO_CMD_INIT(x) \
516 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
517 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
519 #define S_FW_HELLO_CMD_MASTERDIS 29
520 #define M_FW_HELLO_CMD_MASTERDIS 0x1
521 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
522 #define G_FW_HELLO_CMD_MASTERDIS(x) \
523 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
524 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
526 #define S_FW_HELLO_CMD_MASTERFORCE 28
527 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
528 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
529 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
530 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
531 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
533 #define S_FW_HELLO_CMD_MBMASTER 24
534 #define M_FW_HELLO_CMD_MBMASTER 0xf
535 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
536 #define G_FW_HELLO_CMD_MBMASTER(x) \
537 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
539 #define S_FW_HELLO_CMD_MBASYNCNOT 20
540 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
541 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
542 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
543 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
545 #define S_FW_HELLO_CMD_STAGE 17
546 #define M_FW_HELLO_CMD_STAGE 0x7
547 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
548 #define G_FW_HELLO_CMD_STAGE(x) \
549 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
551 #define S_FW_HELLO_CMD_CLEARINIT 16
552 #define M_FW_HELLO_CMD_CLEARINIT 0x1
553 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
554 #define G_FW_HELLO_CMD_CLEARINIT(x) \
555 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
556 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
564 struct fw_initialize_cmd {
570 enum fw_caps_config_nic {
571 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
572 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
576 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
579 struct fw_caps_config_cmd {
581 __be32 cfvalid_to_len16;
599 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
600 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
601 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
602 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
603 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
604 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
606 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
607 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
608 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
609 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
610 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
611 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
612 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
614 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
615 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
616 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
617 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
618 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
619 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
620 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
623 * params command mnemonics
625 enum fw_params_mnem {
626 FW_PARAMS_MNEM_DEV = 1, /* device params */
627 FW_PARAMS_MNEM_PFVF = 2, /* function params */
628 FW_PARAMS_MNEM_REG = 3, /* limited register access */
629 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
635 enum fw_params_param_dev {
636 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
637 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
638 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
639 * allocated by the device's
642 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
643 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
644 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
648 * physical and virtual function parameters
650 enum fw_params_param_pfvf {
651 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
652 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
653 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
654 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
658 * dma queue parameters
660 enum fw_params_param_dmaq {
661 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
662 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
665 #define S_FW_PARAMS_MNEM 24
666 #define M_FW_PARAMS_MNEM 0xff
667 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
668 #define G_FW_PARAMS_MNEM(x) \
669 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
671 #define S_FW_PARAMS_PARAM_X 16
672 #define M_FW_PARAMS_PARAM_X 0xff
673 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
674 #define G_FW_PARAMS_PARAM_X(x) \
675 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
677 #define S_FW_PARAMS_PARAM_Y 8
678 #define M_FW_PARAMS_PARAM_Y 0xff
679 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
680 #define G_FW_PARAMS_PARAM_Y(x) \
681 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
683 #define S_FW_PARAMS_PARAM_Z 0
684 #define M_FW_PARAMS_PARAM_Z 0xff
685 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
686 #define G_FW_PARAMS_PARAM_Z(x) \
687 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
689 #define S_FW_PARAMS_PARAM_YZ 0
690 #define M_FW_PARAMS_PARAM_YZ 0xffff
691 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
692 #define G_FW_PARAMS_PARAM_YZ(x) \
693 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
695 #define S_FW_PARAMS_PARAM_XYZ 0
696 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
697 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
699 struct fw_params_cmd {
702 struct fw_params_param {
708 #define S_FW_PARAMS_CMD_PFN 8
709 #define M_FW_PARAMS_CMD_PFN 0x7
710 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
711 #define G_FW_PARAMS_CMD_PFN(x) \
712 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
714 #define S_FW_PARAMS_CMD_VFN 0
715 #define M_FW_PARAMS_CMD_VFN 0xff
716 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
717 #define G_FW_PARAMS_CMD_VFN(x) \
718 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
725 __be32 tc_to_nexactf;
726 __be32 r_caps_to_nethctrl;
732 #define S_FW_PFVF_CMD_NIQFLINT 20
733 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
734 #define G_FW_PFVF_CMD_NIQFLINT(x) \
735 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
737 #define S_FW_PFVF_CMD_NIQ 0
738 #define M_FW_PFVF_CMD_NIQ 0xfffff
739 #define G_FW_PFVF_CMD_NIQ(x) \
740 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
742 #define S_FW_PFVF_CMD_PMASK 20
743 #define M_FW_PFVF_CMD_PMASK 0xf
744 #define G_FW_PFVF_CMD_PMASK(x) \
745 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
747 #define S_FW_PFVF_CMD_NEQ 0
748 #define M_FW_PFVF_CMD_NEQ 0xfffff
749 #define G_FW_PFVF_CMD_NEQ(x) \
750 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
752 #define S_FW_PFVF_CMD_TC 24
753 #define M_FW_PFVF_CMD_TC 0xff
754 #define G_FW_PFVF_CMD_TC(x) \
755 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
757 #define S_FW_PFVF_CMD_NVI 16
758 #define M_FW_PFVF_CMD_NVI 0xff
759 #define G_FW_PFVF_CMD_NVI(x) \
760 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
762 #define S_FW_PFVF_CMD_NEXACTF 0
763 #define M_FW_PFVF_CMD_NEXACTF 0xffff
764 #define G_FW_PFVF_CMD_NEXACTF(x) \
765 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
767 #define S_FW_PFVF_CMD_R_CAPS 24
768 #define M_FW_PFVF_CMD_R_CAPS 0xff
769 #define G_FW_PFVF_CMD_R_CAPS(x) \
770 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
772 #define S_FW_PFVF_CMD_WX_CAPS 16
773 #define M_FW_PFVF_CMD_WX_CAPS 0xff
774 #define G_FW_PFVF_CMD_WX_CAPS(x) \
775 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
777 #define S_FW_PFVF_CMD_NETHCTRL 0
778 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
779 #define G_FW_PFVF_CMD_NETHCTRL(x) \
780 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
783 * ingress queue type; the first 1K ingress queues can have associated 0,
784 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
788 FW_IQ_TYPE_FL_INT_CAP,
793 __be32 alloc_to_len16;
798 __be32 type_to_iqandstindex;
799 __be16 iqdroprss_to_iqesize;
802 __be32 iqns_to_fl0congen;
803 __be16 fl0dcaen_to_fl0cidxfthresh;
806 __be32 fl1cngchmap_to_fl1congen;
807 __be16 fl1dcaen_to_fl1cidxfthresh;
812 #define S_FW_IQ_CMD_PFN 8
813 #define M_FW_IQ_CMD_PFN 0x7
814 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
815 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
817 #define S_FW_IQ_CMD_VFN 0
818 #define M_FW_IQ_CMD_VFN 0xff
819 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
820 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
822 #define S_FW_IQ_CMD_ALLOC 31
823 #define M_FW_IQ_CMD_ALLOC 0x1
824 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
825 #define G_FW_IQ_CMD_ALLOC(x) \
826 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
827 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
829 #define S_FW_IQ_CMD_FREE 30
830 #define M_FW_IQ_CMD_FREE 0x1
831 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
832 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
833 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
835 #define S_FW_IQ_CMD_IQSTART 28
836 #define M_FW_IQ_CMD_IQSTART 0x1
837 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
838 #define G_FW_IQ_CMD_IQSTART(x) \
839 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
840 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
842 #define S_FW_IQ_CMD_IQSTOP 27
843 #define M_FW_IQ_CMD_IQSTOP 0x1
844 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
845 #define G_FW_IQ_CMD_IQSTOP(x) \
846 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
847 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
849 #define S_FW_IQ_CMD_TYPE 29
850 #define M_FW_IQ_CMD_TYPE 0x7
851 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
852 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
854 #define S_FW_IQ_CMD_IQASYNCH 28
855 #define M_FW_IQ_CMD_IQASYNCH 0x1
856 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
857 #define G_FW_IQ_CMD_IQASYNCH(x) \
858 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
859 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
861 #define S_FW_IQ_CMD_VIID 16
862 #define M_FW_IQ_CMD_VIID 0xfff
863 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
864 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
866 #define S_FW_IQ_CMD_IQANDST 15
867 #define M_FW_IQ_CMD_IQANDST 0x1
868 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
869 #define G_FW_IQ_CMD_IQANDST(x) \
870 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
871 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
873 #define S_FW_IQ_CMD_IQANUD 12
874 #define M_FW_IQ_CMD_IQANUD 0x3
875 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
876 #define G_FW_IQ_CMD_IQANUD(x) \
877 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
879 #define S_FW_IQ_CMD_IQANDSTINDEX 0
880 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
881 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
882 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
883 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
885 #define S_FW_IQ_CMD_IQGTSMODE 14
886 #define M_FW_IQ_CMD_IQGTSMODE 0x1
887 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
888 #define G_FW_IQ_CMD_IQGTSMODE(x) \
889 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
890 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
892 #define S_FW_IQ_CMD_IQPCIECH 12
893 #define M_FW_IQ_CMD_IQPCIECH 0x3
894 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
895 #define G_FW_IQ_CMD_IQPCIECH(x) \
896 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
898 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
899 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
900 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
901 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
902 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
904 #define S_FW_IQ_CMD_IQESIZE 0
905 #define M_FW_IQ_CMD_IQESIZE 0x3
906 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
907 #define G_FW_IQ_CMD_IQESIZE(x) \
908 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
910 #define S_FW_IQ_CMD_IQRO 30
911 #define M_FW_IQ_CMD_IQRO 0x1
912 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
913 #define G_FW_IQ_CMD_IQRO(x) \
914 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
915 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
917 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
918 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
919 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
920 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
921 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
922 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
924 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
925 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
926 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
927 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
928 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
930 #define S_FW_IQ_CMD_FL0DATARO 12
931 #define M_FW_IQ_CMD_FL0DATARO 0x1
932 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
933 #define G_FW_IQ_CMD_FL0DATARO(x) \
934 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
935 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
937 #define S_FW_IQ_CMD_FL0CONGCIF 11
938 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
939 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
940 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
941 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
942 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
944 #define S_FW_IQ_CMD_FL0FETCHRO 6
945 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
946 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
947 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
948 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
949 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
951 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
952 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
953 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
954 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
955 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
957 #define S_FW_IQ_CMD_FL0PADEN 2
958 #define M_FW_IQ_CMD_FL0PADEN 0x1
959 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
960 #define G_FW_IQ_CMD_FL0PADEN(x) \
961 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
962 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
964 #define S_FW_IQ_CMD_FL0PACKEN 1
965 #define M_FW_IQ_CMD_FL0PACKEN 0x1
966 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
967 #define G_FW_IQ_CMD_FL0PACKEN(x) \
968 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
969 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
971 #define S_FW_IQ_CMD_FL0CONGEN 0
972 #define M_FW_IQ_CMD_FL0CONGEN 0x1
973 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
974 #define G_FW_IQ_CMD_FL0CONGEN(x) \
975 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
976 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
978 #define S_FW_IQ_CMD_FL0FBMIN 7
979 #define M_FW_IQ_CMD_FL0FBMIN 0x7
980 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
981 #define G_FW_IQ_CMD_FL0FBMIN(x) \
982 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
984 #define S_FW_IQ_CMD_FL0FBMAX 4
985 #define M_FW_IQ_CMD_FL0FBMAX 0x7
986 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
987 #define G_FW_IQ_CMD_FL0FBMAX(x) \
988 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
990 struct fw_eq_eth_cmd {
992 __be32 alloc_to_len16;
995 __be32 fetchszm_to_iqid;
996 __be32 dcaen_to_eqsize;
998 __be32 autoequiqe_to_viid;
1003 #define S_FW_EQ_ETH_CMD_PFN 8
1004 #define M_FW_EQ_ETH_CMD_PFN 0x7
1005 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
1006 #define G_FW_EQ_ETH_CMD_PFN(x) \
1007 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
1009 #define S_FW_EQ_ETH_CMD_VFN 0
1010 #define M_FW_EQ_ETH_CMD_VFN 0xff
1011 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
1012 #define G_FW_EQ_ETH_CMD_VFN(x) \
1013 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
1015 #define S_FW_EQ_ETH_CMD_ALLOC 31
1016 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
1017 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
1018 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
1019 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
1020 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
1022 #define S_FW_EQ_ETH_CMD_FREE 30
1023 #define M_FW_EQ_ETH_CMD_FREE 0x1
1024 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
1025 #define G_FW_EQ_ETH_CMD_FREE(x) \
1026 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
1027 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
1029 #define S_FW_EQ_ETH_CMD_EQSTART 28
1030 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
1031 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
1032 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
1033 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
1034 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
1036 #define S_FW_EQ_ETH_CMD_EQID 0
1037 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
1038 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
1039 #define G_FW_EQ_ETH_CMD_EQID(x) \
1040 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
1042 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
1043 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
1044 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
1045 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
1047 #define S_FW_EQ_ETH_CMD_FETCHRO 22
1048 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
1049 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
1050 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
1051 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
1052 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
1054 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
1055 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
1056 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
1057 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
1058 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
1060 #define S_FW_EQ_ETH_CMD_PCIECHN 16
1061 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
1062 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
1063 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
1064 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
1066 #define S_FW_EQ_ETH_CMD_IQID 0
1067 #define M_FW_EQ_ETH_CMD_IQID 0xffff
1068 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
1069 #define G_FW_EQ_ETH_CMD_IQID(x) \
1070 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
1072 #define S_FW_EQ_ETH_CMD_FBMIN 23
1073 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
1074 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
1075 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
1076 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
1078 #define S_FW_EQ_ETH_CMD_FBMAX 20
1079 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
1080 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
1081 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
1082 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
1084 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
1085 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
1086 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
1087 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
1088 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
1090 #define S_FW_EQ_ETH_CMD_EQSIZE 0
1091 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
1092 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
1093 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
1094 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
1096 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
1097 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
1098 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
1099 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
1100 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
1101 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
1103 #define S_FW_EQ_ETH_CMD_VIID 16
1104 #define M_FW_EQ_ETH_CMD_VIID 0xfff
1105 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
1106 #define G_FW_EQ_ETH_CMD_VIID(x) \
1107 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
1109 struct fw_eq_ctrl_cmd {
1111 __be32 alloc_to_len16;
1112 __be32 cmpliqid_eqid;
1113 __be32 physeqid_pkd;
1114 __be32 fetchszm_to_iqid;
1115 __be32 dcaen_to_eqsize;
1119 #define S_FW_EQ_CTRL_CMD_PFN 8
1120 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
1122 #define S_FW_EQ_CTRL_CMD_VFN 0
1123 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
1125 #define S_FW_EQ_CTRL_CMD_ALLOC 31
1126 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
1127 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
1129 #define S_FW_EQ_CTRL_CMD_FREE 30
1130 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
1131 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
1133 #define S_FW_EQ_CTRL_CMD_EQSTART 28
1134 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
1135 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
1137 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
1138 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
1140 #define S_FW_EQ_CTRL_CMD_EQID 0
1141 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
1142 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
1143 #define G_FW_EQ_CTRL_CMD_EQID(x) \
1144 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1146 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1147 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1148 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1149 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1150 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1152 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1153 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1154 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1156 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1157 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1158 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1160 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1161 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1163 #define S_FW_EQ_CTRL_CMD_IQID 0
1164 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1166 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1167 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1169 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1170 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1172 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1173 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1175 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1176 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1184 __be32 alloc_to_len16;
1185 __be16 type_to_viid;
1190 __be16 norss_rsssize;
1200 #define S_FW_VI_CMD_PFN 8
1201 #define M_FW_VI_CMD_PFN 0x7
1202 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1203 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1205 #define S_FW_VI_CMD_VFN 0
1206 #define M_FW_VI_CMD_VFN 0xff
1207 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1208 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1210 #define S_FW_VI_CMD_ALLOC 31
1211 #define M_FW_VI_CMD_ALLOC 0x1
1212 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1213 #define G_FW_VI_CMD_ALLOC(x) \
1214 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1215 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1217 #define S_FW_VI_CMD_FREE 30
1218 #define M_FW_VI_CMD_FREE 0x1
1219 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1220 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1221 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1223 #define S_FW_VI_CMD_TYPE 15
1224 #define M_FW_VI_CMD_TYPE 0x1
1225 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1226 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1227 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1229 #define S_FW_VI_CMD_FUNC 12
1230 #define M_FW_VI_CMD_FUNC 0x7
1231 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1232 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1234 #define S_FW_VI_CMD_VIID 0
1235 #define M_FW_VI_CMD_VIID 0xfff
1236 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1237 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1239 #define S_FW_VI_CMD_PORTID 4
1240 #define M_FW_VI_CMD_PORTID 0xf
1241 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1242 #define G_FW_VI_CMD_PORTID(x) \
1243 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1245 #define S_FW_VI_CMD_RSSSIZE 0
1246 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1247 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1248 #define G_FW_VI_CMD_RSSSIZE(x) \
1249 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1251 /* Special VI_MAC command index ids */
1252 #define FW_VI_MAC_ADD_MAC 0x3FF
1253 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1255 enum fw_vi_mac_smac {
1256 FW_VI_MAC_MPS_TCAM_ENTRY,
1257 FW_VI_MAC_SMT_AND_MPSTCAM
1260 struct fw_vi_mac_cmd {
1262 __be32 freemacs_to_len16;
1264 struct fw_vi_mac_exact {
1265 __be16 valid_to_idx;
1268 struct fw_vi_mac_hash {
1274 #define S_FW_VI_MAC_CMD_VIID 0
1275 #define M_FW_VI_MAC_CMD_VIID 0xfff
1276 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1277 #define G_FW_VI_MAC_CMD_VIID(x) \
1278 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1280 #define S_FW_VI_MAC_CMD_VALID 15
1281 #define M_FW_VI_MAC_CMD_VALID 0x1
1282 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1283 #define G_FW_VI_MAC_CMD_VALID(x) \
1284 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1285 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1287 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1288 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1289 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1290 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1291 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1293 #define S_FW_VI_MAC_CMD_IDX 0
1294 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1295 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1296 #define G_FW_VI_MAC_CMD_IDX(x) \
1297 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1299 struct fw_vi_rxmode_cmd {
1301 __be32 retval_len16;
1302 __be32 mtu_to_vlanexen;
1306 #define S_FW_VI_RXMODE_CMD_VIID 0
1307 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1308 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1309 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1310 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1312 #define S_FW_VI_RXMODE_CMD_MTU 16
1313 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1314 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1315 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1316 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1318 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1319 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1320 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1321 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1322 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1324 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1325 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1326 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1327 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1328 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1329 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1331 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1332 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1333 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1334 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1335 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1336 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1337 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1339 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1340 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1341 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1342 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1343 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1345 struct fw_vi_enable_cmd {
1347 __be32 ien_to_len16;
1353 #define S_FW_VI_ENABLE_CMD_VIID 0
1354 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1355 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1356 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1357 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1359 #define S_FW_VI_ENABLE_CMD_IEN 31
1360 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1361 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1362 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1363 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1364 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1366 #define S_FW_VI_ENABLE_CMD_EEN 30
1367 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1368 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1369 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1370 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1371 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1373 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1374 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1375 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1376 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1377 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1378 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1380 /* VI VF stats offset definitions */
1381 #define VI_VF_NUM_STATS 16
1383 /* VI PF stats offset definitions */
1384 #define VI_PF_NUM_STATS 17
1385 enum fw_vi_stats_pf_index {
1386 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1387 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1388 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1389 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1390 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1391 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1392 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1393 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1394 FW_VI_PF_STAT_RX_BYTES_IX,
1395 FW_VI_PF_STAT_RX_FRAMES_IX,
1396 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1397 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1398 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1399 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1400 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1401 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1402 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1405 struct fw_vi_stats_cmd {
1407 __be32 retval_len16;
1409 struct fw_vi_stats_ctl {
1420 struct fw_vi_stats_pf {
1421 __be64 tx_bcast_bytes;
1422 __be64 tx_bcast_frames;
1423 __be64 tx_mcast_bytes;
1424 __be64 tx_mcast_frames;
1425 __be64 tx_ucast_bytes;
1426 __be64 tx_ucast_frames;
1427 __be64 tx_offload_bytes;
1428 __be64 tx_offload_frames;
1430 __be64 rx_pf_frames;
1431 __be64 rx_bcast_bytes;
1432 __be64 rx_bcast_frames;
1433 __be64 rx_mcast_bytes;
1434 __be64 rx_mcast_frames;
1435 __be64 rx_ucast_bytes;
1436 __be64 rx_ucast_frames;
1437 __be64 rx_err_frames;
1439 struct fw_vi_stats_vf {
1440 __be64 tx_bcast_bytes;
1441 __be64 tx_bcast_frames;
1442 __be64 tx_mcast_bytes;
1443 __be64 tx_mcast_frames;
1444 __be64 tx_ucast_bytes;
1445 __be64 tx_ucast_frames;
1446 __be64 tx_drop_frames;
1447 __be64 tx_offload_bytes;
1448 __be64 tx_offload_frames;
1449 __be64 rx_bcast_bytes;
1450 __be64 rx_bcast_frames;
1451 __be64 rx_mcast_bytes;
1452 __be64 rx_mcast_frames;
1453 __be64 rx_ucast_bytes;
1454 __be64 rx_ucast_frames;
1455 __be64 rx_err_frames;
1460 #define S_FW_VI_STATS_CMD_VIID 0
1461 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1463 #define S_FW_VI_STATS_CMD_NSTATS 12
1464 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1466 #define S_FW_VI_STATS_CMD_IX 0
1467 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1469 /* old 16-bit port capabilities bitmap */
1471 FW_PORT_CAP_SPEED_100M = 0x0001,
1472 FW_PORT_CAP_SPEED_1G = 0x0002,
1473 FW_PORT_CAP_SPEED_25G = 0x0004,
1474 FW_PORT_CAP_SPEED_10G = 0x0008,
1475 FW_PORT_CAP_SPEED_40G = 0x0010,
1476 FW_PORT_CAP_SPEED_100G = 0x0020,
1477 FW_PORT_CAP_FC_RX = 0x0040,
1478 FW_PORT_CAP_FC_TX = 0x0080,
1479 FW_PORT_CAP_ANEG = 0x0100,
1480 FW_PORT_CAP_MDIX = 0x0200,
1481 FW_PORT_CAP_MDIAUTO = 0x0400,
1482 FW_PORT_CAP_FEC_RS = 0x0800,
1483 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1484 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1485 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1486 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1489 #define S_FW_PORT_CAP_SPEED 0
1490 #define M_FW_PORT_CAP_SPEED 0x3f
1491 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1492 #define G_FW_PORT_CAP_SPEED(x) \
1493 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1496 FW_PORT_CAP_MDI_AUTO,
1499 #define S_FW_PORT_CAP_MDI 9
1500 #define M_FW_PORT_CAP_MDI 3
1501 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1502 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1504 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1505 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1506 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1507 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1508 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1509 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1510 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1511 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1512 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1513 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1514 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1515 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1516 #define FW_PORT_CAP32_ANEG 0x00100000UL
1517 #define FW_PORT_CAP32_MDIX 0x00200000UL
1518 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1519 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1520 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1522 #define S_FW_PORT_CAP32_SPEED 0
1523 #define M_FW_PORT_CAP32_SPEED 0xfff
1524 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1525 #define G_FW_PORT_CAP32_SPEED(x) \
1526 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1528 enum fw_port_mdi32 {
1529 FW_PORT_CAP32_MDI_AUTO,
1532 #define S_FW_PORT_CAP32_MDI 21
1533 #define M_FW_PORT_CAP32_MDI 3
1534 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1535 #define G_FW_PORT_CAP32_MDI(x) \
1536 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1538 enum fw_port_action {
1539 FW_PORT_ACTION_L1_CFG = 0x0001,
1540 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1541 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1542 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1545 struct fw_port_cmd {
1546 __be32 op_to_portid;
1547 __be32 action_to_len16;
1549 struct fw_port_l1cfg {
1553 struct fw_port_l2cfg {
1555 __u8 ovlan3_to_ivlan0;
1557 __be16 txipg_force_pinfo;
1568 struct fw_port_info {
1569 __be32 lstatus_to_modtype;
1580 struct fw_port_diags {
1586 struct fw_port_dcb_pgid {
1593 struct fw_port_dcb_pgrate {
1597 __u8 num_tcs_supported;
1601 struct fw_port_dcb_priorate {
1605 __u8 strict_priorate[8];
1607 struct fw_port_dcb_pfc {
1614 struct fw_port_app_priority {
1623 struct fw_port_dcb_control {
1626 __be16 dcb_version_to_app_state;
1631 struct fw_port_l1cfg32 {
1635 struct fw_port_info32 {
1636 __be32 lstatus32_to_cbllen32;
1637 __be32 auxlinfo32_mtu32;
1646 #define S_FW_PORT_CMD_PORTID 0
1647 #define M_FW_PORT_CMD_PORTID 0xf
1648 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1649 #define G_FW_PORT_CMD_PORTID(x) \
1650 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1652 #define S_FW_PORT_CMD_ACTION 16
1653 #define M_FW_PORT_CMD_ACTION 0xffff
1654 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1655 #define G_FW_PORT_CMD_ACTION(x) \
1656 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1658 #define S_FW_PORT_CMD_LSTATUS 31
1659 #define M_FW_PORT_CMD_LSTATUS 0x1
1660 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1661 #define G_FW_PORT_CMD_LSTATUS(x) \
1662 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1663 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1665 #define S_FW_PORT_CMD_LSPEED 24
1666 #define M_FW_PORT_CMD_LSPEED 0x3f
1667 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1668 #define G_FW_PORT_CMD_LSPEED(x) \
1669 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1671 #define S_FW_PORT_CMD_TXPAUSE 23
1672 #define M_FW_PORT_CMD_TXPAUSE 0x1
1673 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1674 #define G_FW_PORT_CMD_TXPAUSE(x) \
1675 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1676 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1678 #define S_FW_PORT_CMD_RXPAUSE 22
1679 #define M_FW_PORT_CMD_RXPAUSE 0x1
1680 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1681 #define G_FW_PORT_CMD_RXPAUSE(x) \
1682 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1683 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1685 #define S_FW_PORT_CMD_MDIOCAP 21
1686 #define M_FW_PORT_CMD_MDIOCAP 0x1
1687 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1688 #define G_FW_PORT_CMD_MDIOCAP(x) \
1689 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1690 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1692 #define S_FW_PORT_CMD_MDIOADDR 16
1693 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1694 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1695 #define G_FW_PORT_CMD_MDIOADDR(x) \
1696 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1698 #define S_FW_PORT_CMD_PTYPE 8
1699 #define M_FW_PORT_CMD_PTYPE 0x1f
1700 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1701 #define G_FW_PORT_CMD_PTYPE(x) \
1702 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1704 #define S_FW_PORT_CMD_LINKDNRC 5
1705 #define M_FW_PORT_CMD_LINKDNRC 0x7
1706 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1707 #define G_FW_PORT_CMD_LINKDNRC(x) \
1708 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1710 #define S_FW_PORT_CMD_MODTYPE 0
1711 #define M_FW_PORT_CMD_MODTYPE 0x1f
1712 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1713 #define G_FW_PORT_CMD_MODTYPE(x) \
1714 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1716 #define S_FW_PORT_CMD_LSTATUS32 31
1717 #define M_FW_PORT_CMD_LSTATUS32 0x1
1718 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1719 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1721 #define S_FW_PORT_CMD_LINKDNRC32 28
1722 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1723 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1724 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1726 #define S_FW_PORT_CMD_MDIOCAP32 26
1727 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1728 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1729 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1731 #define S_FW_PORT_CMD_MDIOADDR32 21
1732 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1733 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1734 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1736 #define S_FW_PORT_CMD_PORTTYPE32 13
1737 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1738 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1739 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1741 #define S_FW_PORT_CMD_MODTYPE32 8
1742 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1743 #define G_FW_PORT_CMD_MODTYPE32(x) \
1744 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1747 * These are configured into the VPD and hence tools that generate
1748 * VPD may use this enumeration.
1749 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1752 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1753 * with any new Firmware Port Technology Types!
1756 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1757 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1758 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1759 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1760 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1761 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1762 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1763 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1764 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1765 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1766 FW_PORT_TYPE_BP_AP = 10,
1767 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1768 FW_PORT_TYPE_BP4_AP = 11,
1769 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1770 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1771 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1772 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1773 FW_PORT_TYPE_BP40_BA = 15,
1774 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1775 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1776 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1777 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1778 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1779 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1780 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1781 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1784 /* These are read from module's EEPROM and determined once the
1785 * module is inserted.
1787 enum fw_port_module_type {
1788 FW_PORT_MOD_TYPE_NA = 0x0,
1789 FW_PORT_MOD_TYPE_LR = 0x1,
1790 FW_PORT_MOD_TYPE_SR = 0x2,
1791 FW_PORT_MOD_TYPE_ER = 0x3,
1792 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1793 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1794 FW_PORT_MOD_TYPE_LRM = 0x6,
1795 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1796 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1797 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1798 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1801 /* used by FW and tools may use this to generate VPD */
1802 enum fw_port_mod_sub_type {
1803 FW_PORT_MOD_SUB_TYPE_NA,
1804 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1805 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1806 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1807 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1808 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1809 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1810 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1811 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1814 * The following will never been in the VPD. They are TWINAX cable
1815 * lengths decoded from SFP+ module i2c PROMs. These should almost
1816 * certainly go somewhere else ...
1818 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1819 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1820 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1821 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1824 /* link down reason codes (3b) */
1825 enum fw_port_link_dn_rc {
1826 FW_PORT_LINK_DN_RC_NONE,
1827 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1828 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1829 FW_PORT_LINK_DN_RESERVED3,
1830 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1831 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1832 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1833 FW_PORT_LINK_DN_RESERVED7
1837 #define FW_NUM_PORT_STATS 50
1838 #define FW_NUM_PORT_TX_STATS 23
1839 #define FW_NUM_PORT_RX_STATS 27
1841 enum fw_port_stats_tx_index {
1842 FW_STAT_TX_PORT_BYTES_IX,
1843 FW_STAT_TX_PORT_FRAMES_IX,
1844 FW_STAT_TX_PORT_BCAST_IX,
1845 FW_STAT_TX_PORT_MCAST_IX,
1846 FW_STAT_TX_PORT_UCAST_IX,
1847 FW_STAT_TX_PORT_ERROR_IX,
1848 FW_STAT_TX_PORT_64B_IX,
1849 FW_STAT_TX_PORT_65B_127B_IX,
1850 FW_STAT_TX_PORT_128B_255B_IX,
1851 FW_STAT_TX_PORT_256B_511B_IX,
1852 FW_STAT_TX_PORT_512B_1023B_IX,
1853 FW_STAT_TX_PORT_1024B_1518B_IX,
1854 FW_STAT_TX_PORT_1519B_MAX_IX,
1855 FW_STAT_TX_PORT_DROP_IX,
1856 FW_STAT_TX_PORT_PAUSE_IX,
1857 FW_STAT_TX_PORT_PPP0_IX,
1858 FW_STAT_TX_PORT_PPP1_IX,
1859 FW_STAT_TX_PORT_PPP2_IX,
1860 FW_STAT_TX_PORT_PPP3_IX,
1861 FW_STAT_TX_PORT_PPP4_IX,
1862 FW_STAT_TX_PORT_PPP5_IX,
1863 FW_STAT_TX_PORT_PPP6_IX,
1864 FW_STAT_TX_PORT_PPP7_IX
1867 enum fw_port_stat_rx_index {
1868 FW_STAT_RX_PORT_BYTES_IX,
1869 FW_STAT_RX_PORT_FRAMES_IX,
1870 FW_STAT_RX_PORT_BCAST_IX,
1871 FW_STAT_RX_PORT_MCAST_IX,
1872 FW_STAT_RX_PORT_UCAST_IX,
1873 FW_STAT_RX_PORT_MTU_ERROR_IX,
1874 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1875 FW_STAT_RX_PORT_CRC_ERROR_IX,
1876 FW_STAT_RX_PORT_LEN_ERROR_IX,
1877 FW_STAT_RX_PORT_SYM_ERROR_IX,
1878 FW_STAT_RX_PORT_64B_IX,
1879 FW_STAT_RX_PORT_65B_127B_IX,
1880 FW_STAT_RX_PORT_128B_255B_IX,
1881 FW_STAT_RX_PORT_256B_511B_IX,
1882 FW_STAT_RX_PORT_512B_1023B_IX,
1883 FW_STAT_RX_PORT_1024B_1518B_IX,
1884 FW_STAT_RX_PORT_1519B_MAX_IX,
1885 FW_STAT_RX_PORT_PAUSE_IX,
1886 FW_STAT_RX_PORT_PPP0_IX,
1887 FW_STAT_RX_PORT_PPP1_IX,
1888 FW_STAT_RX_PORT_PPP2_IX,
1889 FW_STAT_RX_PORT_PPP3_IX,
1890 FW_STAT_RX_PORT_PPP4_IX,
1891 FW_STAT_RX_PORT_PPP5_IX,
1892 FW_STAT_RX_PORT_PPP6_IX,
1893 FW_STAT_RX_PORT_PPP7_IX,
1894 FW_STAT_RX_PORT_LESS_64B_IX
1897 struct fw_port_stats_cmd {
1898 __be32 op_to_portid;
1899 __be32 retval_len16;
1900 union fw_port_stats {
1901 struct fw_port_stats_ctl {
1913 struct fw_port_stats_all {
1922 __be64 tx_128b_255b;
1923 __be64 tx_256b_511b;
1924 __be64 tx_512b_1023b;
1925 __be64 tx_1024b_1518b;
1926 __be64 tx_1519b_max;
1942 __be64 rx_mtu_error;
1943 __be64 rx_mtu_crc_error;
1944 __be64 rx_crc_error;
1945 __be64 rx_len_error;
1946 __be64 rx_sym_error;
1949 __be64 rx_128b_255b;
1950 __be64 rx_256b_511b;
1951 __be64 rx_512b_1023b;
1952 __be64 rx_1024b_1518b;
1953 __be64 rx_1519b_max;
1970 struct fw_rss_ind_tbl_cmd {
1972 __be32 retval_len16;
1980 __be32 iq12_to_iq14;
1981 __be32 iq15_to_iq17;
1982 __be32 iq18_to_iq20;
1983 __be32 iq21_to_iq23;
1984 __be32 iq24_to_iq26;
1985 __be32 iq27_to_iq29;
1990 #define S_FW_RSS_IND_TBL_CMD_VIID 0
1991 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
1992 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
1993 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
1994 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
1996 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
1997 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
1998 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
1999 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
2000 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
2002 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
2003 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
2004 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
2005 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
2006 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
2008 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
2009 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
2010 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
2011 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
2012 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
2014 struct fw_rss_glb_config_cmd {
2016 __be32 retval_len16;
2017 union fw_rss_glb_config {
2018 struct fw_rss_glb_config_manual {
2024 struct fw_rss_glb_config_basicvirtual {
2025 __be32 mode_keymode;
2026 __be32 synmapen_to_hashtoeplitz;
2033 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
2034 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
2035 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
2036 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
2038 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2040 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
2041 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
2042 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
2043 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
2045 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
2046 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
2047 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
2048 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
2049 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
2051 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
2052 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
2053 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
2054 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
2055 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
2057 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
2058 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
2059 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
2060 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
2061 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
2063 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
2064 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
2065 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
2066 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
2067 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
2069 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
2070 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
2071 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
2072 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
2074 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
2075 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
2076 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
2077 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
2079 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
2080 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
2081 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
2082 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
2083 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
2085 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
2086 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
2087 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
2088 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
2089 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
2091 struct fw_rss_vi_config_cmd {
2093 __be32 retval_len16;
2094 union fw_rss_vi_config {
2095 struct fw_rss_vi_config_manual {
2100 struct fw_rss_vi_config_basicvirtual {
2102 __be32 defaultq_to_udpen;
2109 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
2110 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
2111 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
2112 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
2113 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
2115 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
2116 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
2117 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2118 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2119 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2120 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
2121 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2123 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
2124 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
2125 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2126 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2127 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2128 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
2129 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2130 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
2131 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
2133 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
2134 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
2135 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2136 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2137 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2138 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
2139 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2140 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
2141 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
2143 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
2144 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2145 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2146 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2147 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2148 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2149 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2150 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2151 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2153 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2154 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2155 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2156 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2157 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2158 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2159 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2160 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2161 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2163 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2164 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2165 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2166 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2167 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2168 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2170 /******************************************************************************
2171 * D E B U G C O M M A N D s
2172 ******************************************************/
2174 struct fw_debug_cmd {
2178 struct fw_debug_assert {
2183 __u8 filename_0_7[8];
2184 __u8 filename_8_15[8];
2187 struct fw_debug_prt {
2190 __be32 dprtstrparam0;
2191 __be32 dprtstrparam1;
2192 __be32 dprtstrparam2;
2193 __be32 dprtstrparam3;
2198 #define S_FW_DEBUG_CMD_TYPE 0
2199 #define M_FW_DEBUG_CMD_TYPE 0xff
2200 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2201 #define G_FW_DEBUG_CMD_TYPE(x) \
2202 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2204 /******************************************************************************
2205 * P C I E F W R E G I S T E R
2206 **************************************/
2209 * Register definitions for the PCIE_FW register which the firmware uses
2210 * to retain status across RESETs. This register should be considered
2211 * as a READ-ONLY register for Host Software and only to be used to
2212 * track firmware initialization/error state, etc.
2214 #define S_PCIE_FW_ERR 31
2215 #define M_PCIE_FW_ERR 0x1
2216 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2217 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2218 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2220 #define S_PCIE_FW_INIT 30
2221 #define M_PCIE_FW_INIT 0x1
2222 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2223 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2224 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2226 #define S_PCIE_FW_HALT 29
2227 #define M_PCIE_FW_HALT 0x1
2228 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2229 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2230 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2232 #define S_PCIE_FW_EVAL 24
2233 #define M_PCIE_FW_EVAL 0x7
2234 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2235 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2237 #define S_PCIE_FW_MASTER_VLD 15
2238 #define M_PCIE_FW_MASTER_VLD 0x1
2239 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2240 #define G_PCIE_FW_MASTER_VLD(x) \
2241 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2242 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2244 #define S_PCIE_FW_MASTER 12
2245 #define M_PCIE_FW_MASTER 0x7
2246 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2247 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2249 /******************************************************************************
2250 * B I N A R Y H E A D E R F O R M A T
2251 **********************************************/
2254 * firmware binary header format
2258 __u8 chip; /* terminator chip family */
2259 __be16 len512; /* bin length in units of 512-bytes */
2260 __be32 fw_ver; /* firmware version */
2261 __be32 tp_microcode_ver; /* tcp processor microcode version */
2266 __u8 intfver_iscsipdu;
2268 __u8 intfver_fcoepdu;
2272 __u32 magic; /* runtime or bootstrap fw */
2274 __be32 reserved6[23];
2277 #define S_FW_HDR_FW_VER_MAJOR 24
2278 #define M_FW_HDR_FW_VER_MAJOR 0xff
2279 #define V_FW_HDR_FW_VER_MAJOR(x) \
2280 ((x) << S_FW_HDR_FW_VER_MAJOR)
2281 #define G_FW_HDR_FW_VER_MAJOR(x) \
2282 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2284 #define S_FW_HDR_FW_VER_MINOR 16
2285 #define M_FW_HDR_FW_VER_MINOR 0xff
2286 #define V_FW_HDR_FW_VER_MINOR(x) \
2287 ((x) << S_FW_HDR_FW_VER_MINOR)
2288 #define G_FW_HDR_FW_VER_MINOR(x) \
2289 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2291 #define S_FW_HDR_FW_VER_MICRO 8
2292 #define M_FW_HDR_FW_VER_MICRO 0xff
2293 #define V_FW_HDR_FW_VER_MICRO(x) \
2294 ((x) << S_FW_HDR_FW_VER_MICRO)
2295 #define G_FW_HDR_FW_VER_MICRO(x) \
2296 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2298 #define S_FW_HDR_FW_VER_BUILD 0
2299 #define M_FW_HDR_FW_VER_BUILD 0xff
2300 #define V_FW_HDR_FW_VER_BUILD(x) \
2301 ((x) << S_FW_HDR_FW_VER_BUILD)
2302 #define G_FW_HDR_FW_VER_BUILD(x) \
2303 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2305 #endif /* _T4FW_INTERFACE_H_ */