4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _T4FW_INTERFACE_H_
35 #define _T4FW_INTERFACE_H_
37 /******************************************************************************
38 * R E T U R N V A L U E S
39 ********************************/
42 FW_SUCCESS = 0, /* completed successfully */
43 FW_EPERM = 1, /* operation not permitted */
44 FW_ENOENT = 2, /* no such file or directory */
45 FW_EIO = 5, /* input/output error; hw bad */
46 FW_ENOEXEC = 8, /* exec format error; inv microcode */
47 FW_EAGAIN = 11, /* try again */
48 FW_ENOMEM = 12, /* out of memory */
49 FW_EFAULT = 14, /* bad address; fw bad */
50 FW_EBUSY = 16, /* resource busy */
51 FW_EEXIST = 17, /* file exists */
52 FW_ENODEV = 19, /* no such device */
53 FW_EINVAL = 22, /* invalid argument */
54 FW_ENOSPC = 28, /* no space left on device */
55 FW_ENOSYS = 38, /* functionality not implemented */
56 FW_ENODATA = 61, /* no data available */
57 FW_EPROTO = 71, /* protocol error */
58 FW_EADDRINUSE = 98, /* address already in use */
59 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
60 FW_ENETDOWN = 100, /* network is down */
61 FW_ENETUNREACH = 101, /* network is unreachable */
62 FW_ENOBUFS = 105, /* no buffer space available */
63 FW_ETIMEDOUT = 110, /* timeout */
64 FW_EINPROGRESS = 115, /* fw internal */
67 /******************************************************************************
68 * M E M O R Y T Y P E s
69 ******************************/
72 FW_MEMTYPE_EDC0 = 0x0,
73 FW_MEMTYPE_EDC1 = 0x1,
74 FW_MEMTYPE_EXTMEM = 0x2,
75 FW_MEMTYPE_FLASH = 0x4,
76 FW_MEMTYPE_INTERNAL = 0x5,
77 FW_MEMTYPE_EXTMEM1 = 0x6,
80 /******************************************************************************
81 * W O R K R E Q U E S T s
82 ********************************/
85 FW_ETH_TX_PKT_WR = 0x08,
86 FW_ETH_TX_PKTS_WR = 0x09,
87 FW_ETH_TX_PKTS2_WR = 0x78,
91 * Generic work request header flit0
98 /* work request opcode (hi)
100 #define S_FW_WR_OP 24
101 #define M_FW_WR_OP 0xff
102 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
103 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
105 /* work request immediate data length (hi)
107 #define S_FW_WR_IMMDLEN 0
108 #define M_FW_WR_IMMDLEN 0xff
109 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
110 #define G_FW_WR_IMMDLEN(x) \
111 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
113 /* egress queue status update to egress queue status entry (lo)
115 #define S_FW_WR_EQUEQ 30
116 #define M_FW_WR_EQUEQ 0x1
117 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
118 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
119 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
121 /* length in units of 16-bytes (lo)
123 #define S_FW_WR_LEN16 0
124 #define M_FW_WR_LEN16 0xff
125 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
126 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
128 struct fw_eth_tx_pkt_wr {
130 __be32 equiq_to_len16;
134 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
135 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
136 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
137 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
138 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
140 struct fw_eth_tx_pkts_wr {
142 __be32 equiq_to_len16;
149 /******************************************************************************
151 *********************/
154 * The maximum length of time, in miliseconds, that we expect any firmware
155 * command to take to execute and return a reply to the host. The RESET
156 * and INITIALIZE commands can take a fair amount of time to execute but
157 * most execute in far less time than this maximum. This constant is used
158 * by host software to determine how long to wait for a firmware command
159 * reply before declaring the firmware as dead/unreachable ...
161 #define FW_CMD_MAX_TIMEOUT 10000
164 * If a host driver does a HELLO and discovers that there's already a MASTER
165 * selected, we may have to wait for that MASTER to finish issuing RESET,
166 * configuration and INITIALIZE commands. Also, there's a possibility that
167 * our own HELLO may get lost if it happens right as the MASTER is issuign a
168 * RESET command, so we need to be willing to make a few retries of our HELLO.
170 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
171 #define FW_CMD_HELLO_RETRIES 3
173 enum fw_cmd_opcodes {
178 FW_INITIALIZE_CMD = 0x06,
179 FW_CAPS_CONFIG_CMD = 0x07,
180 FW_PARAMS_CMD = 0x08,
183 FW_EQ_ETH_CMD = 0x12,
185 FW_VI_MAC_CMD = 0x15,
186 FW_VI_RXMODE_CMD = 0x16,
187 FW_VI_ENABLE_CMD = 0x17,
189 FW_RSS_IND_TBL_CMD = 0x20,
190 FW_RSS_VI_CONFIG_CMD = 0x23,
195 FW_CMD_CAP_PORT = 0x04,
199 * Generic command header flit0
206 #define S_FW_CMD_OP 24
207 #define M_FW_CMD_OP 0xff
208 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
209 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
211 #define S_FW_CMD_REQUEST 23
212 #define M_FW_CMD_REQUEST 0x1
213 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
214 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
215 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
217 #define S_FW_CMD_READ 22
218 #define M_FW_CMD_READ 0x1
219 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
220 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
221 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
223 #define S_FW_CMD_WRITE 21
224 #define M_FW_CMD_WRITE 0x1
225 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
226 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
227 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
229 #define S_FW_CMD_EXEC 20
230 #define M_FW_CMD_EXEC 0x1
231 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
232 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
233 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
235 #define S_FW_CMD_RETVAL 8
236 #define M_FW_CMD_RETVAL 0xff
237 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
238 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
240 #define S_FW_CMD_LEN16 0
241 #define M_FW_CMD_LEN16 0xff
242 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
243 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
245 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
249 enum fw_ldst_addrspc {
250 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
254 __be32 op_to_addrspace;
255 __be32 cycles_to_len16;
257 struct fw_ldst_addrval {
261 struct fw_ldst_idctxt {
263 __be32 msg_ctxtflush;
273 struct fw_ldst_mdio {
289 struct fw_ldst_func {
297 struct fw_ldst_pcie {
307 struct fw_ldst_i2c_deprecated {
331 #define S_FW_LDST_CMD_ADDRSPACE 0
332 #define M_FW_LDST_CMD_ADDRSPACE 0xff
333 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
335 struct fw_reset_cmd {
342 #define S_FW_RESET_CMD_HALT 31
343 #define M_FW_RESET_CMD_HALT 0x1
344 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
345 #define G_FW_RESET_CMD_HALT(x) \
346 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
347 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
350 FW_HELLO_CMD_STAGE_OS = 0,
353 struct fw_hello_cmd {
356 __be32 err_to_clearinit;
360 #define S_FW_HELLO_CMD_ERR 31
361 #define M_FW_HELLO_CMD_ERR 0x1
362 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
363 #define G_FW_HELLO_CMD_ERR(x) \
364 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
365 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
367 #define S_FW_HELLO_CMD_INIT 30
368 #define M_FW_HELLO_CMD_INIT 0x1
369 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
370 #define G_FW_HELLO_CMD_INIT(x) \
371 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
372 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
374 #define S_FW_HELLO_CMD_MASTERDIS 29
375 #define M_FW_HELLO_CMD_MASTERDIS 0x1
376 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
377 #define G_FW_HELLO_CMD_MASTERDIS(x) \
378 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
379 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
381 #define S_FW_HELLO_CMD_MASTERFORCE 28
382 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
383 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
384 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
385 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
386 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
388 #define S_FW_HELLO_CMD_MBMASTER 24
389 #define M_FW_HELLO_CMD_MBMASTER 0xf
390 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
391 #define G_FW_HELLO_CMD_MBMASTER(x) \
392 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
394 #define S_FW_HELLO_CMD_MBASYNCNOT 20
395 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
396 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
397 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
398 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
400 #define S_FW_HELLO_CMD_STAGE 17
401 #define M_FW_HELLO_CMD_STAGE 0x7
402 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
403 #define G_FW_HELLO_CMD_STAGE(x) \
404 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
406 #define S_FW_HELLO_CMD_CLEARINIT 16
407 #define M_FW_HELLO_CMD_CLEARINIT 0x1
408 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
409 #define G_FW_HELLO_CMD_CLEARINIT(x) \
410 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
411 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
419 struct fw_initialize_cmd {
425 enum fw_caps_config_nic {
426 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
427 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
431 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
434 struct fw_caps_config_cmd {
436 __be32 cfvalid_to_len16;
454 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
455 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
456 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
457 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
458 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
459 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
461 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
462 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
463 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
464 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
465 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
466 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
467 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
469 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
470 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
471 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
472 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
473 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
474 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
475 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
478 * params command mnemonics
480 enum fw_params_mnem {
481 FW_PARAMS_MNEM_DEV = 1, /* device params */
482 FW_PARAMS_MNEM_PFVF = 2, /* function params */
483 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
489 enum fw_params_param_dev {
490 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
491 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
492 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
493 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
494 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
498 * physical and virtual function parameters
500 enum fw_params_param_pfvf {
501 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
502 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
506 * dma queue parameters
508 enum fw_params_param_dmaq {
509 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
510 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
513 #define S_FW_PARAMS_MNEM 24
514 #define M_FW_PARAMS_MNEM 0xff
515 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
516 #define G_FW_PARAMS_MNEM(x) \
517 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
519 #define S_FW_PARAMS_PARAM_X 16
520 #define M_FW_PARAMS_PARAM_X 0xff
521 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
522 #define G_FW_PARAMS_PARAM_X(x) \
523 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
525 #define S_FW_PARAMS_PARAM_Y 8
526 #define M_FW_PARAMS_PARAM_Y 0xff
527 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
528 #define G_FW_PARAMS_PARAM_Y(x) \
529 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
531 #define S_FW_PARAMS_PARAM_Z 0
532 #define M_FW_PARAMS_PARAM_Z 0xff
533 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
534 #define G_FW_PARAMS_PARAM_Z(x) \
535 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
537 #define S_FW_PARAMS_PARAM_YZ 0
538 #define M_FW_PARAMS_PARAM_YZ 0xffff
539 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
540 #define G_FW_PARAMS_PARAM_YZ(x) \
541 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
543 #define S_FW_PARAMS_PARAM_XYZ 0
544 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
545 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
547 struct fw_params_cmd {
550 struct fw_params_param {
556 #define S_FW_PARAMS_CMD_PFN 8
557 #define M_FW_PARAMS_CMD_PFN 0x7
558 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
559 #define G_FW_PARAMS_CMD_PFN(x) \
560 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
562 #define S_FW_PARAMS_CMD_VFN 0
563 #define M_FW_PARAMS_CMD_VFN 0xff
564 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
565 #define G_FW_PARAMS_CMD_VFN(x) \
566 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
573 __be32 tc_to_nexactf;
574 __be32 r_caps_to_nethctrl;
580 #define S_FW_PFVF_CMD_NIQFLINT 20
581 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
582 #define G_FW_PFVF_CMD_NIQFLINT(x) \
583 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
585 #define S_FW_PFVF_CMD_NIQ 0
586 #define M_FW_PFVF_CMD_NIQ 0xfffff
587 #define G_FW_PFVF_CMD_NIQ(x) \
588 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
590 #define S_FW_PFVF_CMD_PMASK 20
591 #define M_FW_PFVF_CMD_PMASK 0xf
592 #define G_FW_PFVF_CMD_PMASK(x) \
593 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
595 #define S_FW_PFVF_CMD_NEQ 0
596 #define M_FW_PFVF_CMD_NEQ 0xfffff
597 #define G_FW_PFVF_CMD_NEQ(x) \
598 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
600 #define S_FW_PFVF_CMD_TC 24
601 #define M_FW_PFVF_CMD_TC 0xff
602 #define G_FW_PFVF_CMD_TC(x) \
603 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
605 #define S_FW_PFVF_CMD_NVI 16
606 #define M_FW_PFVF_CMD_NVI 0xff
607 #define G_FW_PFVF_CMD_NVI(x) \
608 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
610 #define S_FW_PFVF_CMD_NEXACTF 0
611 #define M_FW_PFVF_CMD_NEXACTF 0xffff
612 #define G_FW_PFVF_CMD_NEXACTF(x) \
613 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
615 #define S_FW_PFVF_CMD_R_CAPS 24
616 #define M_FW_PFVF_CMD_R_CAPS 0xff
617 #define G_FW_PFVF_CMD_R_CAPS(x) \
618 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
620 #define S_FW_PFVF_CMD_WX_CAPS 16
621 #define M_FW_PFVF_CMD_WX_CAPS 0xff
622 #define G_FW_PFVF_CMD_WX_CAPS(x) \
623 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
625 #define S_FW_PFVF_CMD_NETHCTRL 0
626 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
627 #define G_FW_PFVF_CMD_NETHCTRL(x) \
628 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
631 * ingress queue type; the first 1K ingress queues can have associated 0,
632 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
636 FW_IQ_TYPE_FL_INT_CAP,
641 __be32 alloc_to_len16;
646 __be32 type_to_iqandstindex;
647 __be16 iqdroprss_to_iqesize;
650 __be32 iqns_to_fl0congen;
651 __be16 fl0dcaen_to_fl0cidxfthresh;
654 __be32 fl1cngchmap_to_fl1congen;
655 __be16 fl1dcaen_to_fl1cidxfthresh;
660 #define S_FW_IQ_CMD_PFN 8
661 #define M_FW_IQ_CMD_PFN 0x7
662 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
663 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
665 #define S_FW_IQ_CMD_VFN 0
666 #define M_FW_IQ_CMD_VFN 0xff
667 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
668 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
670 #define S_FW_IQ_CMD_ALLOC 31
671 #define M_FW_IQ_CMD_ALLOC 0x1
672 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
673 #define G_FW_IQ_CMD_ALLOC(x) \
674 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
675 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
677 #define S_FW_IQ_CMD_FREE 30
678 #define M_FW_IQ_CMD_FREE 0x1
679 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
680 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
681 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
683 #define S_FW_IQ_CMD_IQSTART 28
684 #define M_FW_IQ_CMD_IQSTART 0x1
685 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
686 #define G_FW_IQ_CMD_IQSTART(x) \
687 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
688 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
690 #define S_FW_IQ_CMD_IQSTOP 27
691 #define M_FW_IQ_CMD_IQSTOP 0x1
692 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
693 #define G_FW_IQ_CMD_IQSTOP(x) \
694 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
695 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
697 #define S_FW_IQ_CMD_TYPE 29
698 #define M_FW_IQ_CMD_TYPE 0x7
699 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
700 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
702 #define S_FW_IQ_CMD_IQASYNCH 28
703 #define M_FW_IQ_CMD_IQASYNCH 0x1
704 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
705 #define G_FW_IQ_CMD_IQASYNCH(x) \
706 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
707 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
709 #define S_FW_IQ_CMD_VIID 16
710 #define M_FW_IQ_CMD_VIID 0xfff
711 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
712 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
714 #define S_FW_IQ_CMD_IQANDST 15
715 #define M_FW_IQ_CMD_IQANDST 0x1
716 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
717 #define G_FW_IQ_CMD_IQANDST(x) \
718 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
719 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
721 #define S_FW_IQ_CMD_IQANUD 12
722 #define M_FW_IQ_CMD_IQANUD 0x3
723 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
724 #define G_FW_IQ_CMD_IQANUD(x) \
725 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
727 #define S_FW_IQ_CMD_IQANDSTINDEX 0
728 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
729 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
730 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
731 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
733 #define S_FW_IQ_CMD_IQGTSMODE 14
734 #define M_FW_IQ_CMD_IQGTSMODE 0x1
735 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
736 #define G_FW_IQ_CMD_IQGTSMODE(x) \
737 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
738 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
740 #define S_FW_IQ_CMD_IQPCIECH 12
741 #define M_FW_IQ_CMD_IQPCIECH 0x3
742 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
743 #define G_FW_IQ_CMD_IQPCIECH(x) \
744 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
746 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
747 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
748 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
749 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
750 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
752 #define S_FW_IQ_CMD_IQESIZE 0
753 #define M_FW_IQ_CMD_IQESIZE 0x3
754 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
755 #define G_FW_IQ_CMD_IQESIZE(x) \
756 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
758 #define S_FW_IQ_CMD_IQRO 30
759 #define M_FW_IQ_CMD_IQRO 0x1
760 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
761 #define G_FW_IQ_CMD_IQRO(x) \
762 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
763 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
765 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
766 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
767 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
768 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
769 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
770 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
772 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
773 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
774 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
775 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
776 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
778 #define S_FW_IQ_CMD_FL0DATARO 12
779 #define M_FW_IQ_CMD_FL0DATARO 0x1
780 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
781 #define G_FW_IQ_CMD_FL0DATARO(x) \
782 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
783 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
785 #define S_FW_IQ_CMD_FL0CONGCIF 11
786 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
787 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
788 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
789 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
790 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
792 #define S_FW_IQ_CMD_FL0FETCHRO 6
793 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
794 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
795 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
796 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
797 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
799 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
800 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
801 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
802 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
803 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
805 #define S_FW_IQ_CMD_FL0PADEN 2
806 #define M_FW_IQ_CMD_FL0PADEN 0x1
807 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
808 #define G_FW_IQ_CMD_FL0PADEN(x) \
809 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
810 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
812 #define S_FW_IQ_CMD_FL0PACKEN 1
813 #define M_FW_IQ_CMD_FL0PACKEN 0x1
814 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
815 #define G_FW_IQ_CMD_FL0PACKEN(x) \
816 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
817 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
819 #define S_FW_IQ_CMD_FL0CONGEN 0
820 #define M_FW_IQ_CMD_FL0CONGEN 0x1
821 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
822 #define G_FW_IQ_CMD_FL0CONGEN(x) \
823 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
824 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
826 #define S_FW_IQ_CMD_FL0FBMIN 7
827 #define M_FW_IQ_CMD_FL0FBMIN 0x7
828 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
829 #define G_FW_IQ_CMD_FL0FBMIN(x) \
830 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
832 #define S_FW_IQ_CMD_FL0FBMAX 4
833 #define M_FW_IQ_CMD_FL0FBMAX 0x7
834 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
835 #define G_FW_IQ_CMD_FL0FBMAX(x) \
836 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
838 struct fw_eq_eth_cmd {
840 __be32 alloc_to_len16;
843 __be32 fetchszm_to_iqid;
844 __be32 dcaen_to_eqsize;
846 __be32 autoequiqe_to_viid;
851 #define S_FW_EQ_ETH_CMD_PFN 8
852 #define M_FW_EQ_ETH_CMD_PFN 0x7
853 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
854 #define G_FW_EQ_ETH_CMD_PFN(x) \
855 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
857 #define S_FW_EQ_ETH_CMD_VFN 0
858 #define M_FW_EQ_ETH_CMD_VFN 0xff
859 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
860 #define G_FW_EQ_ETH_CMD_VFN(x) \
861 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
863 #define S_FW_EQ_ETH_CMD_ALLOC 31
864 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
865 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
866 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
867 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
868 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
870 #define S_FW_EQ_ETH_CMD_FREE 30
871 #define M_FW_EQ_ETH_CMD_FREE 0x1
872 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
873 #define G_FW_EQ_ETH_CMD_FREE(x) \
874 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
875 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
877 #define S_FW_EQ_ETH_CMD_EQSTART 28
878 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
879 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
880 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
881 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
882 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
884 #define S_FW_EQ_ETH_CMD_EQID 0
885 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
886 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
887 #define G_FW_EQ_ETH_CMD_EQID(x) \
888 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
890 #define S_FW_EQ_ETH_CMD_FETCHRO 22
891 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
892 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
893 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
894 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
895 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
897 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
898 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
899 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
900 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
901 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
903 #define S_FW_EQ_ETH_CMD_PCIECHN 16
904 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
905 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
906 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
907 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
909 #define S_FW_EQ_ETH_CMD_IQID 0
910 #define M_FW_EQ_ETH_CMD_IQID 0xffff
911 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
912 #define G_FW_EQ_ETH_CMD_IQID(x) \
913 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
915 #define S_FW_EQ_ETH_CMD_FBMIN 23
916 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
917 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
918 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
919 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
921 #define S_FW_EQ_ETH_CMD_FBMAX 20
922 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
923 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
924 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
925 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
927 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
928 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
929 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
930 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
931 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
933 #define S_FW_EQ_ETH_CMD_EQSIZE 0
934 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
935 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
936 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
937 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
939 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
940 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
941 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
942 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
943 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
944 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
946 #define S_FW_EQ_ETH_CMD_VIID 16
947 #define M_FW_EQ_ETH_CMD_VIID 0xfff
948 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
949 #define G_FW_EQ_ETH_CMD_VIID(x) \
950 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
958 __be32 alloc_to_len16;
964 __be16 norss_rsssize;
974 #define S_FW_VI_CMD_PFN 8
975 #define M_FW_VI_CMD_PFN 0x7
976 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
977 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
979 #define S_FW_VI_CMD_VFN 0
980 #define M_FW_VI_CMD_VFN 0xff
981 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
982 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
984 #define S_FW_VI_CMD_ALLOC 31
985 #define M_FW_VI_CMD_ALLOC 0x1
986 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
987 #define G_FW_VI_CMD_ALLOC(x) \
988 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
989 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
991 #define S_FW_VI_CMD_FREE 30
992 #define M_FW_VI_CMD_FREE 0x1
993 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
994 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
995 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
997 #define S_FW_VI_CMD_TYPE 15
998 #define M_FW_VI_CMD_TYPE 0x1
999 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1000 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1001 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1003 #define S_FW_VI_CMD_FUNC 12
1004 #define M_FW_VI_CMD_FUNC 0x7
1005 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1006 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1008 #define S_FW_VI_CMD_VIID 0
1009 #define M_FW_VI_CMD_VIID 0xfff
1010 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1011 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1013 #define S_FW_VI_CMD_PORTID 4
1014 #define M_FW_VI_CMD_PORTID 0xf
1015 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1016 #define G_FW_VI_CMD_PORTID(x) \
1017 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1019 #define S_FW_VI_CMD_RSSSIZE 0
1020 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1021 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1022 #define G_FW_VI_CMD_RSSSIZE(x) \
1023 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1025 /* Special VI_MAC command index ids */
1026 #define FW_VI_MAC_ADD_MAC 0x3FF
1027 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1029 enum fw_vi_mac_smac {
1030 FW_VI_MAC_MPS_TCAM_ENTRY,
1031 FW_VI_MAC_SMT_AND_MPSTCAM
1034 struct fw_vi_mac_cmd {
1036 __be32 freemacs_to_len16;
1038 struct fw_vi_mac_exact {
1039 __be16 valid_to_idx;
1042 struct fw_vi_mac_hash {
1048 #define S_FW_VI_MAC_CMD_VIID 0
1049 #define M_FW_VI_MAC_CMD_VIID 0xfff
1050 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1051 #define G_FW_VI_MAC_CMD_VIID(x) \
1052 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1054 #define S_FW_VI_MAC_CMD_VALID 15
1055 #define M_FW_VI_MAC_CMD_VALID 0x1
1056 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1057 #define G_FW_VI_MAC_CMD_VALID(x) \
1058 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1059 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1061 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1062 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1063 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1064 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1065 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1067 #define S_FW_VI_MAC_CMD_IDX 0
1068 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1069 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1070 #define G_FW_VI_MAC_CMD_IDX(x) \
1071 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1073 struct fw_vi_rxmode_cmd {
1075 __be32 retval_len16;
1076 __be32 mtu_to_vlanexen;
1080 #define S_FW_VI_RXMODE_CMD_VIID 0
1081 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1082 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1083 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1084 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1086 #define S_FW_VI_RXMODE_CMD_MTU 16
1087 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1088 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1089 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1090 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1092 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1093 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1094 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1095 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1096 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1098 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1099 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1100 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1101 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1102 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1103 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1105 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1106 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1107 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1108 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1109 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1110 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1111 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1113 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1114 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1115 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1116 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1117 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1119 struct fw_vi_enable_cmd {
1121 __be32 ien_to_len16;
1127 #define S_FW_VI_ENABLE_CMD_VIID 0
1128 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1129 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1130 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1131 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1133 #define S_FW_VI_ENABLE_CMD_IEN 31
1134 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1135 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1136 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1137 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1138 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1140 #define S_FW_VI_ENABLE_CMD_EEN 30
1141 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1142 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1143 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1144 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1145 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1147 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1148 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1149 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1150 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1151 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1152 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1154 /* VI PF stats offset definitions */
1155 #define VI_PF_NUM_STATS 17
1156 enum fw_vi_stats_pf_index {
1157 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1158 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1159 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1160 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1161 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1162 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1163 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1164 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1165 FW_VI_PF_STAT_RX_BYTES_IX,
1166 FW_VI_PF_STAT_RX_FRAMES_IX,
1167 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1168 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1169 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1170 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1171 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1172 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1173 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1176 struct fw_vi_stats_cmd {
1178 __be32 retval_len16;
1180 struct fw_vi_stats_ctl {
1191 struct fw_vi_stats_pf {
1192 __be64 tx_bcast_bytes;
1193 __be64 tx_bcast_frames;
1194 __be64 tx_mcast_bytes;
1195 __be64 tx_mcast_frames;
1196 __be64 tx_ucast_bytes;
1197 __be64 tx_ucast_frames;
1198 __be64 tx_offload_bytes;
1199 __be64 tx_offload_frames;
1201 __be64 rx_pf_frames;
1202 __be64 rx_bcast_bytes;
1203 __be64 rx_bcast_frames;
1204 __be64 rx_mcast_bytes;
1205 __be64 rx_mcast_frames;
1206 __be64 rx_ucast_bytes;
1207 __be64 rx_ucast_frames;
1208 __be64 rx_err_frames;
1210 struct fw_vi_stats_vf {
1211 __be64 tx_bcast_bytes;
1212 __be64 tx_bcast_frames;
1213 __be64 tx_mcast_bytes;
1214 __be64 tx_mcast_frames;
1215 __be64 tx_ucast_bytes;
1216 __be64 tx_ucast_frames;
1217 __be64 tx_drop_frames;
1218 __be64 tx_offload_bytes;
1219 __be64 tx_offload_frames;
1220 __be64 rx_bcast_bytes;
1221 __be64 rx_bcast_frames;
1222 __be64 rx_mcast_bytes;
1223 __be64 rx_mcast_frames;
1224 __be64 rx_ucast_bytes;
1225 __be64 rx_ucast_frames;
1226 __be64 rx_err_frames;
1231 /* old 16-bit port capabilities bitmap */
1233 FW_PORT_CAP_SPEED_100M = 0x0001,
1234 FW_PORT_CAP_SPEED_1G = 0x0002,
1235 FW_PORT_CAP_SPEED_25G = 0x0004,
1236 FW_PORT_CAP_SPEED_10G = 0x0008,
1237 FW_PORT_CAP_SPEED_40G = 0x0010,
1238 FW_PORT_CAP_SPEED_100G = 0x0020,
1239 FW_PORT_CAP_FC_RX = 0x0040,
1240 FW_PORT_CAP_FC_TX = 0x0080,
1241 FW_PORT_CAP_ANEG = 0x0100,
1242 FW_PORT_CAP_MDIX = 0x0200,
1243 FW_PORT_CAP_MDIAUTO = 0x0400,
1244 FW_PORT_CAP_FEC_RS = 0x0800,
1245 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1246 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1247 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1248 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1251 #define S_FW_PORT_CAP_SPEED 0
1252 #define M_FW_PORT_CAP_SPEED 0x3f
1253 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1254 #define G_FW_PORT_CAP_SPEED(x) \
1255 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1258 FW_PORT_CAP_MDI_AUTO,
1261 #define S_FW_PORT_CAP_MDI 9
1262 #define M_FW_PORT_CAP_MDI 3
1263 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1264 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1266 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1267 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1268 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1269 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1270 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1271 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1272 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1273 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1274 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1275 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1276 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1277 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1278 #define FW_PORT_CAP32_ANEG 0x00100000UL
1279 #define FW_PORT_CAP32_MDIX 0x00200000UL
1280 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1281 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1282 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1284 #define S_FW_PORT_CAP32_SPEED 0
1285 #define M_FW_PORT_CAP32_SPEED 0xfff
1286 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1287 #define G_FW_PORT_CAP32_SPEED(x) \
1288 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1290 enum fw_port_mdi32 {
1291 FW_PORT_CAP32_MDI_AUTO,
1294 #define S_FW_PORT_CAP32_MDI 21
1295 #define M_FW_PORT_CAP32_MDI 3
1296 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1297 #define G_FW_PORT_CAP32_MDI(x) \
1298 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1300 enum fw_port_action {
1301 FW_PORT_ACTION_L1_CFG = 0x0001,
1302 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1303 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1304 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1307 struct fw_port_cmd {
1308 __be32 op_to_portid;
1309 __be32 action_to_len16;
1311 struct fw_port_l1cfg {
1315 struct fw_port_l2cfg {
1317 __u8 ovlan3_to_ivlan0;
1319 __be16 txipg_force_pinfo;
1330 struct fw_port_info {
1331 __be32 lstatus_to_modtype;
1342 struct fw_port_diags {
1348 struct fw_port_dcb_pgid {
1355 struct fw_port_dcb_pgrate {
1359 __u8 num_tcs_supported;
1363 struct fw_port_dcb_priorate {
1367 __u8 strict_priorate[8];
1369 struct fw_port_dcb_pfc {
1376 struct fw_port_app_priority {
1385 struct fw_port_dcb_control {
1388 __be16 dcb_version_to_app_state;
1393 struct fw_port_l1cfg32 {
1397 struct fw_port_info32 {
1398 __be32 lstatus32_to_cbllen32;
1399 __be32 auxlinfo32_mtu32;
1408 #define S_FW_PORT_CMD_PORTID 0
1409 #define M_FW_PORT_CMD_PORTID 0xf
1410 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1411 #define G_FW_PORT_CMD_PORTID(x) \
1412 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1414 #define S_FW_PORT_CMD_ACTION 16
1415 #define M_FW_PORT_CMD_ACTION 0xffff
1416 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1417 #define G_FW_PORT_CMD_ACTION(x) \
1418 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1420 #define S_FW_PORT_CMD_LSTATUS 31
1421 #define M_FW_PORT_CMD_LSTATUS 0x1
1422 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1423 #define G_FW_PORT_CMD_LSTATUS(x) \
1424 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1425 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1427 #define S_FW_PORT_CMD_LSPEED 24
1428 #define M_FW_PORT_CMD_LSPEED 0x3f
1429 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1430 #define G_FW_PORT_CMD_LSPEED(x) \
1431 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1433 #define S_FW_PORT_CMD_TXPAUSE 23
1434 #define M_FW_PORT_CMD_TXPAUSE 0x1
1435 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1436 #define G_FW_PORT_CMD_TXPAUSE(x) \
1437 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1438 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1440 #define S_FW_PORT_CMD_RXPAUSE 22
1441 #define M_FW_PORT_CMD_RXPAUSE 0x1
1442 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1443 #define G_FW_PORT_CMD_RXPAUSE(x) \
1444 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1445 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1447 #define S_FW_PORT_CMD_MDIOCAP 21
1448 #define M_FW_PORT_CMD_MDIOCAP 0x1
1449 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1450 #define G_FW_PORT_CMD_MDIOCAP(x) \
1451 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1452 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1454 #define S_FW_PORT_CMD_MDIOADDR 16
1455 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1456 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1457 #define G_FW_PORT_CMD_MDIOADDR(x) \
1458 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1460 #define S_FW_PORT_CMD_PTYPE 8
1461 #define M_FW_PORT_CMD_PTYPE 0x1f
1462 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1463 #define G_FW_PORT_CMD_PTYPE(x) \
1464 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1466 #define S_FW_PORT_CMD_LINKDNRC 5
1467 #define M_FW_PORT_CMD_LINKDNRC 0x7
1468 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1469 #define G_FW_PORT_CMD_LINKDNRC(x) \
1470 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1472 #define S_FW_PORT_CMD_MODTYPE 0
1473 #define M_FW_PORT_CMD_MODTYPE 0x1f
1474 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1475 #define G_FW_PORT_CMD_MODTYPE(x) \
1476 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1478 #define S_FW_PORT_CMD_LSTATUS32 31
1479 #define M_FW_PORT_CMD_LSTATUS32 0x1
1480 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1481 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1483 #define S_FW_PORT_CMD_LINKDNRC32 28
1484 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1485 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1486 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1488 #define S_FW_PORT_CMD_MDIOCAP32 26
1489 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1490 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1491 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1493 #define S_FW_PORT_CMD_MDIOADDR32 21
1494 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1495 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1496 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1498 #define S_FW_PORT_CMD_PORTTYPE32 13
1499 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1500 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1501 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1503 #define S_FW_PORT_CMD_MODTYPE32 8
1504 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1505 #define G_FW_PORT_CMD_MODTYPE32(x) \
1506 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1509 * These are configured into the VPD and hence tools that generate
1510 * VPD may use this enumeration.
1511 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1514 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1515 * with any new Firmware Port Technology Types!
1518 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1519 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1520 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1521 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1522 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1523 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1524 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1525 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1526 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1527 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1528 FW_PORT_TYPE_BP_AP = 10,
1529 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1530 FW_PORT_TYPE_BP4_AP = 11,
1531 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1532 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1533 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1534 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1535 FW_PORT_TYPE_BP40_BA = 15,
1536 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1537 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1538 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1539 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1540 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1541 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1542 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1543 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1546 /* These are read from module's EEPROM and determined once the
1547 * module is inserted.
1549 enum fw_port_module_type {
1550 FW_PORT_MOD_TYPE_NA = 0x0,
1551 FW_PORT_MOD_TYPE_LR = 0x1,
1552 FW_PORT_MOD_TYPE_SR = 0x2,
1553 FW_PORT_MOD_TYPE_ER = 0x3,
1554 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1555 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1556 FW_PORT_MOD_TYPE_LRM = 0x6,
1557 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1558 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1559 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1560 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1563 /* used by FW and tools may use this to generate VPD */
1564 enum fw_port_mod_sub_type {
1565 FW_PORT_MOD_SUB_TYPE_NA,
1566 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1567 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1568 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1569 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1570 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1571 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1572 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1573 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1576 * The following will never been in the VPD. They are TWINAX cable
1577 * lengths decoded from SFP+ module i2c PROMs. These should almost
1578 * certainly go somewhere else ...
1580 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1581 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1582 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1583 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1586 /* link down reason codes (3b) */
1587 enum fw_port_link_dn_rc {
1588 FW_PORT_LINK_DN_RC_NONE,
1589 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1590 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1591 FW_PORT_LINK_DN_RESERVED3,
1592 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1593 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1594 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1595 FW_PORT_LINK_DN_RESERVED7
1599 #define FW_NUM_PORT_STATS 50
1600 #define FW_NUM_PORT_TX_STATS 23
1601 #define FW_NUM_PORT_RX_STATS 27
1603 enum fw_port_stats_tx_index {
1604 FW_STAT_TX_PORT_BYTES_IX,
1605 FW_STAT_TX_PORT_FRAMES_IX,
1606 FW_STAT_TX_PORT_BCAST_IX,
1607 FW_STAT_TX_PORT_MCAST_IX,
1608 FW_STAT_TX_PORT_UCAST_IX,
1609 FW_STAT_TX_PORT_ERROR_IX,
1610 FW_STAT_TX_PORT_64B_IX,
1611 FW_STAT_TX_PORT_65B_127B_IX,
1612 FW_STAT_TX_PORT_128B_255B_IX,
1613 FW_STAT_TX_PORT_256B_511B_IX,
1614 FW_STAT_TX_PORT_512B_1023B_IX,
1615 FW_STAT_TX_PORT_1024B_1518B_IX,
1616 FW_STAT_TX_PORT_1519B_MAX_IX,
1617 FW_STAT_TX_PORT_DROP_IX,
1618 FW_STAT_TX_PORT_PAUSE_IX,
1619 FW_STAT_TX_PORT_PPP0_IX,
1620 FW_STAT_TX_PORT_PPP1_IX,
1621 FW_STAT_TX_PORT_PPP2_IX,
1622 FW_STAT_TX_PORT_PPP3_IX,
1623 FW_STAT_TX_PORT_PPP4_IX,
1624 FW_STAT_TX_PORT_PPP5_IX,
1625 FW_STAT_TX_PORT_PPP6_IX,
1626 FW_STAT_TX_PORT_PPP7_IX
1629 enum fw_port_stat_rx_index {
1630 FW_STAT_RX_PORT_BYTES_IX,
1631 FW_STAT_RX_PORT_FRAMES_IX,
1632 FW_STAT_RX_PORT_BCAST_IX,
1633 FW_STAT_RX_PORT_MCAST_IX,
1634 FW_STAT_RX_PORT_UCAST_IX,
1635 FW_STAT_RX_PORT_MTU_ERROR_IX,
1636 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1637 FW_STAT_RX_PORT_CRC_ERROR_IX,
1638 FW_STAT_RX_PORT_LEN_ERROR_IX,
1639 FW_STAT_RX_PORT_SYM_ERROR_IX,
1640 FW_STAT_RX_PORT_64B_IX,
1641 FW_STAT_RX_PORT_65B_127B_IX,
1642 FW_STAT_RX_PORT_128B_255B_IX,
1643 FW_STAT_RX_PORT_256B_511B_IX,
1644 FW_STAT_RX_PORT_512B_1023B_IX,
1645 FW_STAT_RX_PORT_1024B_1518B_IX,
1646 FW_STAT_RX_PORT_1519B_MAX_IX,
1647 FW_STAT_RX_PORT_PAUSE_IX,
1648 FW_STAT_RX_PORT_PPP0_IX,
1649 FW_STAT_RX_PORT_PPP1_IX,
1650 FW_STAT_RX_PORT_PPP2_IX,
1651 FW_STAT_RX_PORT_PPP3_IX,
1652 FW_STAT_RX_PORT_PPP4_IX,
1653 FW_STAT_RX_PORT_PPP5_IX,
1654 FW_STAT_RX_PORT_PPP6_IX,
1655 FW_STAT_RX_PORT_PPP7_IX,
1656 FW_STAT_RX_PORT_LESS_64B_IX
1659 struct fw_port_stats_cmd {
1660 __be32 op_to_portid;
1661 __be32 retval_len16;
1662 union fw_port_stats {
1663 struct fw_port_stats_ctl {
1675 struct fw_port_stats_all {
1684 __be64 tx_128b_255b;
1685 __be64 tx_256b_511b;
1686 __be64 tx_512b_1023b;
1687 __be64 tx_1024b_1518b;
1688 __be64 tx_1519b_max;
1704 __be64 rx_mtu_error;
1705 __be64 rx_mtu_crc_error;
1706 __be64 rx_crc_error;
1707 __be64 rx_len_error;
1708 __be64 rx_sym_error;
1711 __be64 rx_128b_255b;
1712 __be64 rx_256b_511b;
1713 __be64 rx_512b_1023b;
1714 __be64 rx_1024b_1518b;
1715 __be64 rx_1519b_max;
1732 struct fw_rss_ind_tbl_cmd {
1734 __be32 retval_len16;
1742 __be32 iq12_to_iq14;
1743 __be32 iq15_to_iq17;
1744 __be32 iq18_to_iq20;
1745 __be32 iq21_to_iq23;
1746 __be32 iq24_to_iq26;
1747 __be32 iq27_to_iq29;
1752 #define S_FW_RSS_IND_TBL_CMD_VIID 0
1753 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
1754 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
1755 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
1756 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
1758 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
1759 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
1760 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
1761 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
1762 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
1764 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
1765 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
1766 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
1767 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
1768 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
1770 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
1771 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
1772 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
1773 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
1774 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
1776 struct fw_rss_vi_config_cmd {
1778 __be32 retval_len16;
1779 union fw_rss_vi_config {
1780 struct fw_rss_vi_config_manual {
1785 struct fw_rss_vi_config_basicvirtual {
1787 __be32 defaultq_to_udpen;
1794 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
1795 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
1796 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
1797 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
1798 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
1800 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
1801 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
1802 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1803 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1804 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1805 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
1806 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1808 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
1809 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
1810 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1811 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1812 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1813 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
1814 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1815 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
1816 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
1818 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
1819 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
1820 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1821 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1822 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1823 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
1824 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1825 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
1826 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
1828 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
1829 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
1830 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
1831 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1832 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
1833 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
1834 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1835 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
1836 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
1838 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
1839 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
1840 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
1841 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1842 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
1843 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
1844 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1845 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
1846 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
1848 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
1849 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
1850 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
1851 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
1852 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
1853 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
1855 /******************************************************************************
1856 * D E B U G C O M M A N D s
1857 ******************************************************/
1859 struct fw_debug_cmd {
1863 struct fw_debug_assert {
1868 __u8 filename_0_7[8];
1869 __u8 filename_8_15[8];
1872 struct fw_debug_prt {
1875 __be32 dprtstrparam0;
1876 __be32 dprtstrparam1;
1877 __be32 dprtstrparam2;
1878 __be32 dprtstrparam3;
1883 #define S_FW_DEBUG_CMD_TYPE 0
1884 #define M_FW_DEBUG_CMD_TYPE 0xff
1885 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
1886 #define G_FW_DEBUG_CMD_TYPE(x) \
1887 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
1889 /******************************************************************************
1890 * P C I E F W R E G I S T E R
1891 **************************************/
1894 * Register definitions for the PCIE_FW register which the firmware uses
1895 * to retain status across RESETs. This register should be considered
1896 * as a READ-ONLY register for Host Software and only to be used to
1897 * track firmware initialization/error state, etc.
1899 #define S_PCIE_FW_ERR 31
1900 #define M_PCIE_FW_ERR 0x1
1901 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
1902 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
1903 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
1905 #define S_PCIE_FW_INIT 30
1906 #define M_PCIE_FW_INIT 0x1
1907 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
1908 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
1909 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
1911 #define S_PCIE_FW_HALT 29
1912 #define M_PCIE_FW_HALT 0x1
1913 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
1914 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
1915 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
1917 #define S_PCIE_FW_EVAL 24
1918 #define M_PCIE_FW_EVAL 0x7
1919 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
1920 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
1922 #define S_PCIE_FW_MASTER_VLD 15
1923 #define M_PCIE_FW_MASTER_VLD 0x1
1924 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
1925 #define G_PCIE_FW_MASTER_VLD(x) \
1926 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
1927 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
1929 #define S_PCIE_FW_MASTER 12
1930 #define M_PCIE_FW_MASTER 0x7
1931 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
1932 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
1934 /******************************************************************************
1935 * B I N A R Y H E A D E R F O R M A T
1936 **********************************************/
1939 * firmware binary header format
1943 __u8 chip; /* terminator chip family */
1944 __be16 len512; /* bin length in units of 512-bytes */
1945 __be32 fw_ver; /* firmware version */
1946 __be32 tp_microcode_ver; /* tcp processor microcode version */
1951 __u8 intfver_iscsipdu;
1953 __u8 intfver_fcoepdu;
1957 __u32 magic; /* runtime or bootstrap fw */
1959 __be32 reserved6[23];
1962 #define S_FW_HDR_FW_VER_MAJOR 24
1963 #define M_FW_HDR_FW_VER_MAJOR 0xff
1964 #define V_FW_HDR_FW_VER_MAJOR(x) \
1965 ((x) << S_FW_HDR_FW_VER_MAJOR)
1966 #define G_FW_HDR_FW_VER_MAJOR(x) \
1967 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
1969 #define S_FW_HDR_FW_VER_MINOR 16
1970 #define M_FW_HDR_FW_VER_MINOR 0xff
1971 #define V_FW_HDR_FW_VER_MINOR(x) \
1972 ((x) << S_FW_HDR_FW_VER_MINOR)
1973 #define G_FW_HDR_FW_VER_MINOR(x) \
1974 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
1976 #define S_FW_HDR_FW_VER_MICRO 8
1977 #define M_FW_HDR_FW_VER_MICRO 0xff
1978 #define V_FW_HDR_FW_VER_MICRO(x) \
1979 ((x) << S_FW_HDR_FW_VER_MICRO)
1980 #define G_FW_HDR_FW_VER_MICRO(x) \
1981 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
1983 #define S_FW_HDR_FW_VER_BUILD 0
1984 #define M_FW_HDR_FW_VER_BUILD 0xff
1985 #define V_FW_HDR_FW_VER_BUILD(x) \
1986 ((x) << S_FW_HDR_FW_VER_BUILD)
1987 #define G_FW_HDR_FW_VER_BUILD(x) \
1988 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
1990 #endif /* _T4FW_INTERFACE_H_ */