1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
60 FW_ETH_TX_PKT_WR = 0x08,
61 FW_ETH_TX_PKTS_WR = 0x09,
62 FW_ETH_TX_PKT_VM_WR = 0x11,
63 FW_ETH_TX_PKTS_VM_WR = 0x12,
64 FW_ETH_TX_PKTS2_WR = 0x78,
68 * Generic work request header flit0
75 /* work request opcode (hi)
78 #define M_FW_WR_OP 0xff
79 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
80 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
82 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
84 #define S_FW_WR_ATOMIC 23
85 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
87 /* work request immediate data length (hi)
89 #define S_FW_WR_IMMDLEN 0
90 #define M_FW_WR_IMMDLEN 0xff
91 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
92 #define G_FW_WR_IMMDLEN(x) \
93 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
95 /* egress queue status update to egress queue status entry (lo)
97 #define S_FW_WR_EQUEQ 30
98 #define M_FW_WR_EQUEQ 0x1
99 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
100 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
101 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
103 /* flow context identifier (lo)
105 #define S_FW_WR_FLOWID 8
106 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
108 /* length in units of 16-bytes (lo)
110 #define S_FW_WR_LEN16 0
111 #define M_FW_WR_LEN16 0xff
112 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
113 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
115 struct fw_eth_tx_pkt_wr {
117 __be32 equiq_to_len16;
121 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
122 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
123 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
124 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
125 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
127 struct fw_eth_tx_pkts_wr {
129 __be32 equiq_to_len16;
136 struct fw_eth_tx_pkt_vm_wr {
138 __be32 equiq_to_len16;
146 struct fw_eth_tx_pkts_vm_wr {
148 __be32 equiq_to_len16;
159 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
160 enum fw_filter_wr_cookie {
161 FW_FILTER_WR_SUCCESS,
162 FW_FILTER_WR_FLT_ADDED,
163 FW_FILTER_WR_FLT_DELETED,
164 FW_FILTER_WR_SMT_TBL_FULL,
168 struct fw_filter_wr {
173 __be32 del_filter_to_l2tix;
176 __u8 frag_to_ovlan_vldm;
178 __be16 rx_chan_rx_rpl_iq;
179 __be32 maci_to_matchtypem;
200 #define S_FW_FILTER_WR_TID 12
201 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
203 #define S_FW_FILTER_WR_RQTYPE 11
204 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
206 #define S_FW_FILTER_WR_NOREPLY 10
207 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
209 #define S_FW_FILTER_WR_IQ 0
210 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
212 #define S_FW_FILTER_WR_DEL_FILTER 31
213 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
214 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
216 #define S_FW_FILTER_WR_RPTTID 25
217 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
219 #define S_FW_FILTER_WR_DROP 24
220 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
222 #define S_FW_FILTER_WR_DIRSTEER 23
223 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
225 #define S_FW_FILTER_WR_MASKHASH 22
226 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
228 #define S_FW_FILTER_WR_DIRSTEERHASH 21
229 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
231 #define S_FW_FILTER_WR_LPBK 20
232 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
234 #define S_FW_FILTER_WR_DMAC 19
235 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
237 #define S_FW_FILTER_WR_INSVLAN 17
238 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
240 #define S_FW_FILTER_WR_RMVLAN 16
241 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
243 #define S_FW_FILTER_WR_HITCNTS 15
244 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
246 #define S_FW_FILTER_WR_TXCHAN 13
247 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
249 #define S_FW_FILTER_WR_PRIO 12
250 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
252 #define S_FW_FILTER_WR_L2TIX 0
253 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
255 #define S_FW_FILTER_WR_FRAG 7
256 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
258 #define S_FW_FILTER_WR_FRAGM 6
259 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
261 #define S_FW_FILTER_WR_IVLAN_VLD 5
262 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
264 #define S_FW_FILTER_WR_OVLAN_VLD 4
265 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
267 #define S_FW_FILTER_WR_IVLAN_VLDM 3
268 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
270 #define S_FW_FILTER_WR_OVLAN_VLDM 2
271 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
273 #define S_FW_FILTER_WR_RX_CHAN 15
274 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
276 #define S_FW_FILTER_WR_RX_RPL_IQ 0
277 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
279 #define S_FW_FILTER_WR_MACI 23
280 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
282 #define S_FW_FILTER_WR_MACIM 14
283 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
285 #define S_FW_FILTER_WR_FCOE 13
286 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
288 #define S_FW_FILTER_WR_FCOEM 12
289 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
291 #define S_FW_FILTER_WR_PORT 9
292 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
294 #define S_FW_FILTER_WR_PORTM 6
295 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
297 #define S_FW_FILTER_WR_MATCHTYPE 3
298 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
300 #define S_FW_FILTER_WR_MATCHTYPEM 0
301 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
303 /******************************************************************************
305 *********************/
308 * The maximum length of time, in miliseconds, that we expect any firmware
309 * command to take to execute and return a reply to the host. The RESET
310 * and INITIALIZE commands can take a fair amount of time to execute but
311 * most execute in far less time than this maximum. This constant is used
312 * by host software to determine how long to wait for a firmware command
313 * reply before declaring the firmware as dead/unreachable ...
315 #define FW_CMD_MAX_TIMEOUT 10000
318 * If a host driver does a HELLO and discovers that there's already a MASTER
319 * selected, we may have to wait for that MASTER to finish issuing RESET,
320 * configuration and INITIALIZE commands. Also, there's a possibility that
321 * our own HELLO may get lost if it happens right as the MASTER is issuign a
322 * RESET command, so we need to be willing to make a few retries of our HELLO.
324 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
325 #define FW_CMD_HELLO_RETRIES 3
327 enum fw_cmd_opcodes {
332 FW_INITIALIZE_CMD = 0x06,
333 FW_CAPS_CONFIG_CMD = 0x07,
334 FW_PARAMS_CMD = 0x08,
337 FW_EQ_ETH_CMD = 0x12,
338 FW_EQ_CTRL_CMD = 0x13,
340 FW_VI_MAC_CMD = 0x15,
341 FW_VI_RXMODE_CMD = 0x16,
342 FW_VI_ENABLE_CMD = 0x17,
343 FW_VI_STATS_CMD = 0x1a,
345 FW_RSS_IND_TBL_CMD = 0x20,
346 FW_RSS_GLB_CONFIG_CMD = 0x22,
347 FW_RSS_VI_CONFIG_CMD = 0x23,
353 FW_CMD_CAP_PORT = 0x04,
357 * Generic command header flit0
364 #define S_FW_CMD_OP 24
365 #define M_FW_CMD_OP 0xff
366 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
367 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
369 #define S_FW_CMD_REQUEST 23
370 #define M_FW_CMD_REQUEST 0x1
371 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
372 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
373 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
375 #define S_FW_CMD_READ 22
376 #define M_FW_CMD_READ 0x1
377 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
378 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
379 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
381 #define S_FW_CMD_WRITE 21
382 #define M_FW_CMD_WRITE 0x1
383 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
384 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
385 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
387 #define S_FW_CMD_EXEC 20
388 #define M_FW_CMD_EXEC 0x1
389 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
390 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
391 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
393 #define S_FW_CMD_RETVAL 8
394 #define M_FW_CMD_RETVAL 0xff
395 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
396 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
398 #define S_FW_CMD_LEN16 0
399 #define M_FW_CMD_LEN16 0xff
400 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
401 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
403 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
407 enum fw_ldst_addrspc {
408 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
412 __be32 op_to_addrspace;
413 __be32 cycles_to_len16;
415 struct fw_ldst_addrval {
419 struct fw_ldst_idctxt {
421 __be32 msg_ctxtflush;
431 struct fw_ldst_mdio {
447 struct fw_ldst_func {
455 struct fw_ldst_pcie {
465 struct fw_ldst_i2c_deprecated {
489 #define S_FW_LDST_CMD_ADDRSPACE 0
490 #define M_FW_LDST_CMD_ADDRSPACE 0xff
491 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
493 struct fw_reset_cmd {
500 #define S_FW_RESET_CMD_HALT 31
501 #define M_FW_RESET_CMD_HALT 0x1
502 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
503 #define G_FW_RESET_CMD_HALT(x) \
504 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
505 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
508 FW_HELLO_CMD_STAGE_OS = 0,
511 struct fw_hello_cmd {
514 __be32 err_to_clearinit;
518 #define S_FW_HELLO_CMD_ERR 31
519 #define M_FW_HELLO_CMD_ERR 0x1
520 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
521 #define G_FW_HELLO_CMD_ERR(x) \
522 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
523 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
525 #define S_FW_HELLO_CMD_INIT 30
526 #define M_FW_HELLO_CMD_INIT 0x1
527 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
528 #define G_FW_HELLO_CMD_INIT(x) \
529 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
530 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
532 #define S_FW_HELLO_CMD_MASTERDIS 29
533 #define M_FW_HELLO_CMD_MASTERDIS 0x1
534 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
535 #define G_FW_HELLO_CMD_MASTERDIS(x) \
536 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
537 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
539 #define S_FW_HELLO_CMD_MASTERFORCE 28
540 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
541 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
542 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
543 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
544 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
546 #define S_FW_HELLO_CMD_MBMASTER 24
547 #define M_FW_HELLO_CMD_MBMASTER 0xf
548 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
549 #define G_FW_HELLO_CMD_MBMASTER(x) \
550 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
552 #define S_FW_HELLO_CMD_MBASYNCNOT 20
553 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
554 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
555 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
556 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
558 #define S_FW_HELLO_CMD_STAGE 17
559 #define M_FW_HELLO_CMD_STAGE 0x7
560 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
561 #define G_FW_HELLO_CMD_STAGE(x) \
562 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
564 #define S_FW_HELLO_CMD_CLEARINIT 16
565 #define M_FW_HELLO_CMD_CLEARINIT 0x1
566 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
567 #define G_FW_HELLO_CMD_CLEARINIT(x) \
568 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
569 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
577 struct fw_initialize_cmd {
583 enum fw_caps_config_nic {
584 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
585 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
589 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
592 struct fw_caps_config_cmd {
594 __be32 cfvalid_to_len16;
612 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
613 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
614 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
615 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
616 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
617 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
619 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
620 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
621 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
622 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
623 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
624 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
625 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
627 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
628 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
629 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
630 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
631 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
632 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
633 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
636 * params command mnemonics
638 enum fw_params_mnem {
639 FW_PARAMS_MNEM_DEV = 1, /* device params */
640 FW_PARAMS_MNEM_PFVF = 2, /* function params */
641 FW_PARAMS_MNEM_REG = 3, /* limited register access */
642 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
648 enum fw_params_param_dev {
649 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
650 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
651 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
652 * allocated by the device's
655 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
656 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
657 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
661 * physical and virtual function parameters
663 enum fw_params_param_pfvf {
664 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
665 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
666 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
667 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
668 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
669 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
673 * dma queue parameters
675 enum fw_params_param_dmaq {
676 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
677 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
680 #define S_FW_PARAMS_MNEM 24
681 #define M_FW_PARAMS_MNEM 0xff
682 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
683 #define G_FW_PARAMS_MNEM(x) \
684 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
686 #define S_FW_PARAMS_PARAM_X 16
687 #define M_FW_PARAMS_PARAM_X 0xff
688 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
689 #define G_FW_PARAMS_PARAM_X(x) \
690 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
692 #define S_FW_PARAMS_PARAM_Y 8
693 #define M_FW_PARAMS_PARAM_Y 0xff
694 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
695 #define G_FW_PARAMS_PARAM_Y(x) \
696 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
698 #define S_FW_PARAMS_PARAM_Z 0
699 #define M_FW_PARAMS_PARAM_Z 0xff
700 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
701 #define G_FW_PARAMS_PARAM_Z(x) \
702 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
704 #define S_FW_PARAMS_PARAM_YZ 0
705 #define M_FW_PARAMS_PARAM_YZ 0xffff
706 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
707 #define G_FW_PARAMS_PARAM_YZ(x) \
708 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
710 #define S_FW_PARAMS_PARAM_XYZ 0
711 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
712 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
714 struct fw_params_cmd {
717 struct fw_params_param {
723 #define S_FW_PARAMS_CMD_PFN 8
724 #define M_FW_PARAMS_CMD_PFN 0x7
725 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
726 #define G_FW_PARAMS_CMD_PFN(x) \
727 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
729 #define S_FW_PARAMS_CMD_VFN 0
730 #define M_FW_PARAMS_CMD_VFN 0xff
731 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
732 #define G_FW_PARAMS_CMD_VFN(x) \
733 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
740 __be32 tc_to_nexactf;
741 __be32 r_caps_to_nethctrl;
747 #define S_FW_PFVF_CMD_PFN 8
748 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
750 #define S_FW_PFVF_CMD_VFN 0
751 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
753 #define S_FW_PFVF_CMD_NIQFLINT 20
754 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
755 #define G_FW_PFVF_CMD_NIQFLINT(x) \
756 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
758 #define S_FW_PFVF_CMD_NIQ 0
759 #define M_FW_PFVF_CMD_NIQ 0xfffff
760 #define G_FW_PFVF_CMD_NIQ(x) \
761 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
763 #define S_FW_PFVF_CMD_PMASK 20
764 #define M_FW_PFVF_CMD_PMASK 0xf
765 #define G_FW_PFVF_CMD_PMASK(x) \
766 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
768 #define S_FW_PFVF_CMD_NEQ 0
769 #define M_FW_PFVF_CMD_NEQ 0xfffff
770 #define G_FW_PFVF_CMD_NEQ(x) \
771 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
773 #define S_FW_PFVF_CMD_TC 24
774 #define M_FW_PFVF_CMD_TC 0xff
775 #define G_FW_PFVF_CMD_TC(x) \
776 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
778 #define S_FW_PFVF_CMD_NVI 16
779 #define M_FW_PFVF_CMD_NVI 0xff
780 #define G_FW_PFVF_CMD_NVI(x) \
781 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
783 #define S_FW_PFVF_CMD_NEXACTF 0
784 #define M_FW_PFVF_CMD_NEXACTF 0xffff
785 #define G_FW_PFVF_CMD_NEXACTF(x) \
786 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
788 #define S_FW_PFVF_CMD_R_CAPS 24
789 #define M_FW_PFVF_CMD_R_CAPS 0xff
790 #define G_FW_PFVF_CMD_R_CAPS(x) \
791 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
793 #define S_FW_PFVF_CMD_WX_CAPS 16
794 #define M_FW_PFVF_CMD_WX_CAPS 0xff
795 #define G_FW_PFVF_CMD_WX_CAPS(x) \
796 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
798 #define S_FW_PFVF_CMD_NETHCTRL 0
799 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
800 #define G_FW_PFVF_CMD_NETHCTRL(x) \
801 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
804 * ingress queue type; the first 1K ingress queues can have associated 0,
805 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
809 FW_IQ_TYPE_FL_INT_CAP,
813 FW_IQ_IQTYPE_NIC = 1,
819 __be32 alloc_to_len16;
824 __be32 type_to_iqandstindex;
825 __be16 iqdroprss_to_iqesize;
828 __be32 iqns_to_fl0congen;
829 __be16 fl0dcaen_to_fl0cidxfthresh;
832 __be32 fl1cngchmap_to_fl1congen;
833 __be16 fl1dcaen_to_fl1cidxfthresh;
838 #define S_FW_IQ_CMD_PFN 8
839 #define M_FW_IQ_CMD_PFN 0x7
840 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
841 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
843 #define S_FW_IQ_CMD_VFN 0
844 #define M_FW_IQ_CMD_VFN 0xff
845 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
846 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
848 #define S_FW_IQ_CMD_ALLOC 31
849 #define M_FW_IQ_CMD_ALLOC 0x1
850 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
851 #define G_FW_IQ_CMD_ALLOC(x) \
852 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
853 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
855 #define S_FW_IQ_CMD_FREE 30
856 #define M_FW_IQ_CMD_FREE 0x1
857 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
858 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
859 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
861 #define S_FW_IQ_CMD_IQSTART 28
862 #define M_FW_IQ_CMD_IQSTART 0x1
863 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
864 #define G_FW_IQ_CMD_IQSTART(x) \
865 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
866 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
868 #define S_FW_IQ_CMD_IQSTOP 27
869 #define M_FW_IQ_CMD_IQSTOP 0x1
870 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
871 #define G_FW_IQ_CMD_IQSTOP(x) \
872 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
873 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
875 #define S_FW_IQ_CMD_TYPE 29
876 #define M_FW_IQ_CMD_TYPE 0x7
877 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
878 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
880 #define S_FW_IQ_CMD_IQASYNCH 28
881 #define M_FW_IQ_CMD_IQASYNCH 0x1
882 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
883 #define G_FW_IQ_CMD_IQASYNCH(x) \
884 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
885 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
887 #define S_FW_IQ_CMD_VIID 16
888 #define M_FW_IQ_CMD_VIID 0xfff
889 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
890 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
892 #define S_FW_IQ_CMD_IQANDST 15
893 #define M_FW_IQ_CMD_IQANDST 0x1
894 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
895 #define G_FW_IQ_CMD_IQANDST(x) \
896 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
897 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
899 #define S_FW_IQ_CMD_IQANUD 12
900 #define M_FW_IQ_CMD_IQANUD 0x3
901 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
902 #define G_FW_IQ_CMD_IQANUD(x) \
903 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
905 #define S_FW_IQ_CMD_IQANDSTINDEX 0
906 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
907 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
908 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
909 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
911 #define S_FW_IQ_CMD_IQGTSMODE 14
912 #define M_FW_IQ_CMD_IQGTSMODE 0x1
913 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
914 #define G_FW_IQ_CMD_IQGTSMODE(x) \
915 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
916 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
918 #define S_FW_IQ_CMD_IQPCIECH 12
919 #define M_FW_IQ_CMD_IQPCIECH 0x3
920 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
921 #define G_FW_IQ_CMD_IQPCIECH(x) \
922 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
924 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
925 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
926 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
927 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
928 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
930 #define S_FW_IQ_CMD_IQESIZE 0
931 #define M_FW_IQ_CMD_IQESIZE 0x3
932 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
933 #define G_FW_IQ_CMD_IQESIZE(x) \
934 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
936 #define S_FW_IQ_CMD_IQRO 30
937 #define M_FW_IQ_CMD_IQRO 0x1
938 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
939 #define G_FW_IQ_CMD_IQRO(x) \
940 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
941 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
943 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
944 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
945 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
946 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
947 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
948 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
950 #define S_FW_IQ_CMD_IQTYPE 24
951 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
953 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
954 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
955 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
956 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
957 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
959 #define S_FW_IQ_CMD_FL0DATARO 12
960 #define M_FW_IQ_CMD_FL0DATARO 0x1
961 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
962 #define G_FW_IQ_CMD_FL0DATARO(x) \
963 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
964 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
966 #define S_FW_IQ_CMD_FL0CONGCIF 11
967 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
968 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
969 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
970 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
971 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
973 #define S_FW_IQ_CMD_FL0FETCHRO 6
974 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
975 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
976 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
977 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
978 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
980 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
981 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
982 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
983 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
984 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
986 #define S_FW_IQ_CMD_FL0PADEN 2
987 #define M_FW_IQ_CMD_FL0PADEN 0x1
988 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
989 #define G_FW_IQ_CMD_FL0PADEN(x) \
990 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
991 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
993 #define S_FW_IQ_CMD_FL0PACKEN 1
994 #define M_FW_IQ_CMD_FL0PACKEN 0x1
995 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
996 #define G_FW_IQ_CMD_FL0PACKEN(x) \
997 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
998 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
1000 #define S_FW_IQ_CMD_FL0CONGEN 0
1001 #define M_FW_IQ_CMD_FL0CONGEN 0x1
1002 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
1003 #define G_FW_IQ_CMD_FL0CONGEN(x) \
1004 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
1005 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
1007 #define S_FW_IQ_CMD_FL0FBMIN 7
1008 #define M_FW_IQ_CMD_FL0FBMIN 0x7
1009 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
1010 #define G_FW_IQ_CMD_FL0FBMIN(x) \
1011 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
1013 #define S_FW_IQ_CMD_FL0FBMAX 4
1014 #define M_FW_IQ_CMD_FL0FBMAX 0x7
1015 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
1016 #define G_FW_IQ_CMD_FL0FBMAX(x) \
1017 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
1019 struct fw_eq_eth_cmd {
1021 __be32 alloc_to_len16;
1023 __be32 physeqid_pkd;
1024 __be32 fetchszm_to_iqid;
1025 __be32 dcaen_to_eqsize;
1027 __be32 autoequiqe_to_viid;
1032 #define S_FW_EQ_ETH_CMD_PFN 8
1033 #define M_FW_EQ_ETH_CMD_PFN 0x7
1034 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
1035 #define G_FW_EQ_ETH_CMD_PFN(x) \
1036 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
1038 #define S_FW_EQ_ETH_CMD_VFN 0
1039 #define M_FW_EQ_ETH_CMD_VFN 0xff
1040 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
1041 #define G_FW_EQ_ETH_CMD_VFN(x) \
1042 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
1044 #define S_FW_EQ_ETH_CMD_ALLOC 31
1045 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
1046 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
1047 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
1048 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
1049 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
1051 #define S_FW_EQ_ETH_CMD_FREE 30
1052 #define M_FW_EQ_ETH_CMD_FREE 0x1
1053 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
1054 #define G_FW_EQ_ETH_CMD_FREE(x) \
1055 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
1056 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
1058 #define S_FW_EQ_ETH_CMD_EQSTART 28
1059 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
1060 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
1061 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
1062 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
1063 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
1065 #define S_FW_EQ_ETH_CMD_EQID 0
1066 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
1067 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
1068 #define G_FW_EQ_ETH_CMD_EQID(x) \
1069 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
1071 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
1072 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
1073 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
1074 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
1076 #define S_FW_EQ_ETH_CMD_FETCHRO 22
1077 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
1078 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
1079 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
1080 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
1081 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
1083 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
1084 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
1085 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
1086 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
1087 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
1089 #define S_FW_EQ_ETH_CMD_PCIECHN 16
1090 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
1091 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
1092 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
1093 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
1095 #define S_FW_EQ_ETH_CMD_IQID 0
1096 #define M_FW_EQ_ETH_CMD_IQID 0xffff
1097 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
1098 #define G_FW_EQ_ETH_CMD_IQID(x) \
1099 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
1101 #define S_FW_EQ_ETH_CMD_FBMIN 23
1102 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
1103 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
1104 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
1105 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
1107 #define S_FW_EQ_ETH_CMD_FBMAX 20
1108 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
1109 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
1110 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
1111 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
1113 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
1114 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
1115 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
1116 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
1117 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
1119 #define S_FW_EQ_ETH_CMD_EQSIZE 0
1120 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
1121 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
1122 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
1123 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
1125 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
1126 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
1127 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
1128 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
1129 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
1130 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
1132 #define S_FW_EQ_ETH_CMD_VIID 16
1133 #define M_FW_EQ_ETH_CMD_VIID 0xfff
1134 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
1135 #define G_FW_EQ_ETH_CMD_VIID(x) \
1136 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
1138 struct fw_eq_ctrl_cmd {
1140 __be32 alloc_to_len16;
1141 __be32 cmpliqid_eqid;
1142 __be32 physeqid_pkd;
1143 __be32 fetchszm_to_iqid;
1144 __be32 dcaen_to_eqsize;
1148 #define S_FW_EQ_CTRL_CMD_PFN 8
1149 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
1151 #define S_FW_EQ_CTRL_CMD_VFN 0
1152 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
1154 #define S_FW_EQ_CTRL_CMD_ALLOC 31
1155 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
1156 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
1158 #define S_FW_EQ_CTRL_CMD_FREE 30
1159 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
1160 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
1162 #define S_FW_EQ_CTRL_CMD_EQSTART 28
1163 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
1164 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
1166 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
1167 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
1169 #define S_FW_EQ_CTRL_CMD_EQID 0
1170 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
1171 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
1172 #define G_FW_EQ_CTRL_CMD_EQID(x) \
1173 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1175 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1176 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1177 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1178 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1179 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1181 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1182 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1183 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1185 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1186 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1187 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1189 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1190 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1192 #define S_FW_EQ_CTRL_CMD_IQID 0
1193 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1195 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1196 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1198 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1199 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1201 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1202 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1204 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1205 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1213 __be32 alloc_to_len16;
1214 __be16 type_to_viid;
1219 __be16 norss_rsssize;
1229 #define S_FW_VI_CMD_PFN 8
1230 #define M_FW_VI_CMD_PFN 0x7
1231 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1232 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1234 #define S_FW_VI_CMD_VFN 0
1235 #define M_FW_VI_CMD_VFN 0xff
1236 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1237 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1239 #define S_FW_VI_CMD_ALLOC 31
1240 #define M_FW_VI_CMD_ALLOC 0x1
1241 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1242 #define G_FW_VI_CMD_ALLOC(x) \
1243 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1244 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1246 #define S_FW_VI_CMD_FREE 30
1247 #define M_FW_VI_CMD_FREE 0x1
1248 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1249 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1250 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1252 #define S_FW_VI_CMD_TYPE 15
1253 #define M_FW_VI_CMD_TYPE 0x1
1254 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1255 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1256 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1258 #define S_FW_VI_CMD_FUNC 12
1259 #define M_FW_VI_CMD_FUNC 0x7
1260 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1261 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1263 #define S_FW_VI_CMD_VIID 0
1264 #define M_FW_VI_CMD_VIID 0xfff
1265 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1266 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1268 #define S_FW_VI_CMD_PORTID 4
1269 #define M_FW_VI_CMD_PORTID 0xf
1270 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1271 #define G_FW_VI_CMD_PORTID(x) \
1272 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1274 #define S_FW_VI_CMD_RSSSIZE 0
1275 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1276 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1277 #define G_FW_VI_CMD_RSSSIZE(x) \
1278 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1280 /* Special VI_MAC command index ids */
1281 #define FW_VI_MAC_ADD_MAC 0x3FF
1282 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1284 enum fw_vi_mac_smac {
1285 FW_VI_MAC_MPS_TCAM_ENTRY,
1286 FW_VI_MAC_SMT_AND_MPSTCAM
1289 struct fw_vi_mac_cmd {
1291 __be32 freemacs_to_len16;
1293 struct fw_vi_mac_exact {
1294 __be16 valid_to_idx;
1297 struct fw_vi_mac_hash {
1303 #define S_FW_VI_MAC_CMD_VIID 0
1304 #define M_FW_VI_MAC_CMD_VIID 0xfff
1305 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1306 #define G_FW_VI_MAC_CMD_VIID(x) \
1307 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1309 #define S_FW_VI_MAC_CMD_VALID 15
1310 #define M_FW_VI_MAC_CMD_VALID 0x1
1311 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1312 #define G_FW_VI_MAC_CMD_VALID(x) \
1313 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1314 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1316 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1317 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1318 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1319 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1320 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1322 #define S_FW_VI_MAC_CMD_IDX 0
1323 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1324 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1325 #define G_FW_VI_MAC_CMD_IDX(x) \
1326 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1328 struct fw_vi_rxmode_cmd {
1330 __be32 retval_len16;
1331 __be32 mtu_to_vlanexen;
1335 #define S_FW_VI_RXMODE_CMD_VIID 0
1336 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1337 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1338 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1339 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1341 #define S_FW_VI_RXMODE_CMD_MTU 16
1342 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1343 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1344 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1345 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1347 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1348 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1349 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1350 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1351 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1353 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1354 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1355 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1356 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1357 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1358 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1360 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1361 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1362 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1363 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1364 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1365 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1366 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1368 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1369 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1370 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1371 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1372 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1374 struct fw_vi_enable_cmd {
1376 __be32 ien_to_len16;
1382 #define S_FW_VI_ENABLE_CMD_VIID 0
1383 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1384 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1385 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1386 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1388 #define S_FW_VI_ENABLE_CMD_IEN 31
1389 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1390 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1391 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1392 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1393 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1395 #define S_FW_VI_ENABLE_CMD_EEN 30
1396 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1397 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1398 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1399 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1400 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1402 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1403 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1404 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1405 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1406 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1407 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1409 /* VI VF stats offset definitions */
1410 #define VI_VF_NUM_STATS 16
1412 /* VI PF stats offset definitions */
1413 #define VI_PF_NUM_STATS 17
1414 enum fw_vi_stats_pf_index {
1415 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1416 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1417 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1418 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1419 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1420 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1421 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1422 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1423 FW_VI_PF_STAT_RX_BYTES_IX,
1424 FW_VI_PF_STAT_RX_FRAMES_IX,
1425 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1426 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1427 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1428 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1429 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1430 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1431 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1434 struct fw_vi_stats_cmd {
1436 __be32 retval_len16;
1438 struct fw_vi_stats_ctl {
1449 struct fw_vi_stats_pf {
1450 __be64 tx_bcast_bytes;
1451 __be64 tx_bcast_frames;
1452 __be64 tx_mcast_bytes;
1453 __be64 tx_mcast_frames;
1454 __be64 tx_ucast_bytes;
1455 __be64 tx_ucast_frames;
1456 __be64 tx_offload_bytes;
1457 __be64 tx_offload_frames;
1459 __be64 rx_pf_frames;
1460 __be64 rx_bcast_bytes;
1461 __be64 rx_bcast_frames;
1462 __be64 rx_mcast_bytes;
1463 __be64 rx_mcast_frames;
1464 __be64 rx_ucast_bytes;
1465 __be64 rx_ucast_frames;
1466 __be64 rx_err_frames;
1468 struct fw_vi_stats_vf {
1469 __be64 tx_bcast_bytes;
1470 __be64 tx_bcast_frames;
1471 __be64 tx_mcast_bytes;
1472 __be64 tx_mcast_frames;
1473 __be64 tx_ucast_bytes;
1474 __be64 tx_ucast_frames;
1475 __be64 tx_drop_frames;
1476 __be64 tx_offload_bytes;
1477 __be64 tx_offload_frames;
1478 __be64 rx_bcast_bytes;
1479 __be64 rx_bcast_frames;
1480 __be64 rx_mcast_bytes;
1481 __be64 rx_mcast_frames;
1482 __be64 rx_ucast_bytes;
1483 __be64 rx_ucast_frames;
1484 __be64 rx_err_frames;
1489 #define S_FW_VI_STATS_CMD_VIID 0
1490 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1492 #define S_FW_VI_STATS_CMD_NSTATS 12
1493 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1495 #define S_FW_VI_STATS_CMD_IX 0
1496 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1498 /* old 16-bit port capabilities bitmap */
1500 FW_PORT_CAP_SPEED_100M = 0x0001,
1501 FW_PORT_CAP_SPEED_1G = 0x0002,
1502 FW_PORT_CAP_SPEED_25G = 0x0004,
1503 FW_PORT_CAP_SPEED_10G = 0x0008,
1504 FW_PORT_CAP_SPEED_40G = 0x0010,
1505 FW_PORT_CAP_SPEED_100G = 0x0020,
1506 FW_PORT_CAP_FC_RX = 0x0040,
1507 FW_PORT_CAP_FC_TX = 0x0080,
1508 FW_PORT_CAP_ANEG = 0x0100,
1509 FW_PORT_CAP_MDIX = 0x0200,
1510 FW_PORT_CAP_MDIAUTO = 0x0400,
1511 FW_PORT_CAP_FEC_RS = 0x0800,
1512 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1513 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1514 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1515 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1518 #define S_FW_PORT_CAP_SPEED 0
1519 #define M_FW_PORT_CAP_SPEED 0x3f
1520 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1521 #define G_FW_PORT_CAP_SPEED(x) \
1522 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1525 FW_PORT_CAP_MDI_AUTO,
1528 #define S_FW_PORT_CAP_MDI 9
1529 #define M_FW_PORT_CAP_MDI 3
1530 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1531 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1533 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1534 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1535 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1536 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1537 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1538 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1539 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1540 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1541 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1542 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1543 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1544 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1545 #define FW_PORT_CAP32_ANEG 0x00100000UL
1546 #define FW_PORT_CAP32_MDIX 0x00200000UL
1547 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1548 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1549 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1551 #define S_FW_PORT_CAP32_SPEED 0
1552 #define M_FW_PORT_CAP32_SPEED 0xfff
1553 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1554 #define G_FW_PORT_CAP32_SPEED(x) \
1555 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1557 enum fw_port_mdi32 {
1558 FW_PORT_CAP32_MDI_AUTO,
1561 #define S_FW_PORT_CAP32_MDI 21
1562 #define M_FW_PORT_CAP32_MDI 3
1563 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1564 #define G_FW_PORT_CAP32_MDI(x) \
1565 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1567 enum fw_port_action {
1568 FW_PORT_ACTION_L1_CFG = 0x0001,
1569 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1570 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1571 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1574 struct fw_port_cmd {
1575 __be32 op_to_portid;
1576 __be32 action_to_len16;
1578 struct fw_port_l1cfg {
1582 struct fw_port_l2cfg {
1584 __u8 ovlan3_to_ivlan0;
1586 __be16 txipg_force_pinfo;
1597 struct fw_port_info {
1598 __be32 lstatus_to_modtype;
1609 struct fw_port_diags {
1615 struct fw_port_dcb_pgid {
1622 struct fw_port_dcb_pgrate {
1626 __u8 num_tcs_supported;
1630 struct fw_port_dcb_priorate {
1634 __u8 strict_priorate[8];
1636 struct fw_port_dcb_pfc {
1643 struct fw_port_app_priority {
1652 struct fw_port_dcb_control {
1655 __be16 dcb_version_to_app_state;
1660 struct fw_port_l1cfg32 {
1664 struct fw_port_info32 {
1665 __be32 lstatus32_to_cbllen32;
1666 __be32 auxlinfo32_mtu32;
1675 #define S_FW_PORT_CMD_PORTID 0
1676 #define M_FW_PORT_CMD_PORTID 0xf
1677 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1678 #define G_FW_PORT_CMD_PORTID(x) \
1679 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1681 #define S_FW_PORT_CMD_ACTION 16
1682 #define M_FW_PORT_CMD_ACTION 0xffff
1683 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1684 #define G_FW_PORT_CMD_ACTION(x) \
1685 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1687 #define S_FW_PORT_CMD_LSTATUS 31
1688 #define M_FW_PORT_CMD_LSTATUS 0x1
1689 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1690 #define G_FW_PORT_CMD_LSTATUS(x) \
1691 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1692 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1694 #define S_FW_PORT_CMD_LSPEED 24
1695 #define M_FW_PORT_CMD_LSPEED 0x3f
1696 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1697 #define G_FW_PORT_CMD_LSPEED(x) \
1698 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1700 #define S_FW_PORT_CMD_TXPAUSE 23
1701 #define M_FW_PORT_CMD_TXPAUSE 0x1
1702 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1703 #define G_FW_PORT_CMD_TXPAUSE(x) \
1704 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1705 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1707 #define S_FW_PORT_CMD_RXPAUSE 22
1708 #define M_FW_PORT_CMD_RXPAUSE 0x1
1709 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1710 #define G_FW_PORT_CMD_RXPAUSE(x) \
1711 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1712 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1714 #define S_FW_PORT_CMD_MDIOCAP 21
1715 #define M_FW_PORT_CMD_MDIOCAP 0x1
1716 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1717 #define G_FW_PORT_CMD_MDIOCAP(x) \
1718 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1719 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1721 #define S_FW_PORT_CMD_MDIOADDR 16
1722 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1723 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1724 #define G_FW_PORT_CMD_MDIOADDR(x) \
1725 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1727 #define S_FW_PORT_CMD_PTYPE 8
1728 #define M_FW_PORT_CMD_PTYPE 0x1f
1729 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1730 #define G_FW_PORT_CMD_PTYPE(x) \
1731 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1733 #define S_FW_PORT_CMD_LINKDNRC 5
1734 #define M_FW_PORT_CMD_LINKDNRC 0x7
1735 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1736 #define G_FW_PORT_CMD_LINKDNRC(x) \
1737 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1739 #define S_FW_PORT_CMD_MODTYPE 0
1740 #define M_FW_PORT_CMD_MODTYPE 0x1f
1741 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1742 #define G_FW_PORT_CMD_MODTYPE(x) \
1743 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1745 #define S_FW_PORT_CMD_LSTATUS32 31
1746 #define M_FW_PORT_CMD_LSTATUS32 0x1
1747 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1748 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1750 #define S_FW_PORT_CMD_LINKDNRC32 28
1751 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1752 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1753 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1755 #define S_FW_PORT_CMD_MDIOCAP32 26
1756 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1757 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1758 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1760 #define S_FW_PORT_CMD_MDIOADDR32 21
1761 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1762 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1763 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1765 #define S_FW_PORT_CMD_PORTTYPE32 13
1766 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1767 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1768 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1770 #define S_FW_PORT_CMD_MODTYPE32 8
1771 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1772 #define G_FW_PORT_CMD_MODTYPE32(x) \
1773 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1776 * These are configured into the VPD and hence tools that generate
1777 * VPD may use this enumeration.
1778 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1781 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1782 * with any new Firmware Port Technology Types!
1785 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1786 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1787 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1788 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1789 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1790 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1791 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1792 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1793 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1794 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1795 FW_PORT_TYPE_BP_AP = 10,
1796 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1797 FW_PORT_TYPE_BP4_AP = 11,
1798 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1799 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1800 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1801 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1802 FW_PORT_TYPE_BP40_BA = 15,
1803 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1804 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1805 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1806 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1807 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1808 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1809 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1810 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1813 /* These are read from module's EEPROM and determined once the
1814 * module is inserted.
1816 enum fw_port_module_type {
1817 FW_PORT_MOD_TYPE_NA = 0x0,
1818 FW_PORT_MOD_TYPE_LR = 0x1,
1819 FW_PORT_MOD_TYPE_SR = 0x2,
1820 FW_PORT_MOD_TYPE_ER = 0x3,
1821 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1822 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1823 FW_PORT_MOD_TYPE_LRM = 0x6,
1824 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1825 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1826 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1827 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1830 /* used by FW and tools may use this to generate VPD */
1831 enum fw_port_mod_sub_type {
1832 FW_PORT_MOD_SUB_TYPE_NA,
1833 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1834 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1835 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1836 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1837 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1838 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1839 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1840 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1843 * The following will never been in the VPD. They are TWINAX cable
1844 * lengths decoded from SFP+ module i2c PROMs. These should almost
1845 * certainly go somewhere else ...
1847 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1848 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1849 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1850 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1853 /* link down reason codes (3b) */
1854 enum fw_port_link_dn_rc {
1855 FW_PORT_LINK_DN_RC_NONE,
1856 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1857 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1858 FW_PORT_LINK_DN_RESERVED3,
1859 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1860 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1861 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1862 FW_PORT_LINK_DN_RESERVED7
1866 #define FW_NUM_PORT_STATS 50
1867 #define FW_NUM_PORT_TX_STATS 23
1868 #define FW_NUM_PORT_RX_STATS 27
1870 enum fw_port_stats_tx_index {
1871 FW_STAT_TX_PORT_BYTES_IX,
1872 FW_STAT_TX_PORT_FRAMES_IX,
1873 FW_STAT_TX_PORT_BCAST_IX,
1874 FW_STAT_TX_PORT_MCAST_IX,
1875 FW_STAT_TX_PORT_UCAST_IX,
1876 FW_STAT_TX_PORT_ERROR_IX,
1877 FW_STAT_TX_PORT_64B_IX,
1878 FW_STAT_TX_PORT_65B_127B_IX,
1879 FW_STAT_TX_PORT_128B_255B_IX,
1880 FW_STAT_TX_PORT_256B_511B_IX,
1881 FW_STAT_TX_PORT_512B_1023B_IX,
1882 FW_STAT_TX_PORT_1024B_1518B_IX,
1883 FW_STAT_TX_PORT_1519B_MAX_IX,
1884 FW_STAT_TX_PORT_DROP_IX,
1885 FW_STAT_TX_PORT_PAUSE_IX,
1886 FW_STAT_TX_PORT_PPP0_IX,
1887 FW_STAT_TX_PORT_PPP1_IX,
1888 FW_STAT_TX_PORT_PPP2_IX,
1889 FW_STAT_TX_PORT_PPP3_IX,
1890 FW_STAT_TX_PORT_PPP4_IX,
1891 FW_STAT_TX_PORT_PPP5_IX,
1892 FW_STAT_TX_PORT_PPP6_IX,
1893 FW_STAT_TX_PORT_PPP7_IX
1896 enum fw_port_stat_rx_index {
1897 FW_STAT_RX_PORT_BYTES_IX,
1898 FW_STAT_RX_PORT_FRAMES_IX,
1899 FW_STAT_RX_PORT_BCAST_IX,
1900 FW_STAT_RX_PORT_MCAST_IX,
1901 FW_STAT_RX_PORT_UCAST_IX,
1902 FW_STAT_RX_PORT_MTU_ERROR_IX,
1903 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1904 FW_STAT_RX_PORT_CRC_ERROR_IX,
1905 FW_STAT_RX_PORT_LEN_ERROR_IX,
1906 FW_STAT_RX_PORT_SYM_ERROR_IX,
1907 FW_STAT_RX_PORT_64B_IX,
1908 FW_STAT_RX_PORT_65B_127B_IX,
1909 FW_STAT_RX_PORT_128B_255B_IX,
1910 FW_STAT_RX_PORT_256B_511B_IX,
1911 FW_STAT_RX_PORT_512B_1023B_IX,
1912 FW_STAT_RX_PORT_1024B_1518B_IX,
1913 FW_STAT_RX_PORT_1519B_MAX_IX,
1914 FW_STAT_RX_PORT_PAUSE_IX,
1915 FW_STAT_RX_PORT_PPP0_IX,
1916 FW_STAT_RX_PORT_PPP1_IX,
1917 FW_STAT_RX_PORT_PPP2_IX,
1918 FW_STAT_RX_PORT_PPP3_IX,
1919 FW_STAT_RX_PORT_PPP4_IX,
1920 FW_STAT_RX_PORT_PPP5_IX,
1921 FW_STAT_RX_PORT_PPP6_IX,
1922 FW_STAT_RX_PORT_PPP7_IX,
1923 FW_STAT_RX_PORT_LESS_64B_IX
1926 struct fw_port_stats_cmd {
1927 __be32 op_to_portid;
1928 __be32 retval_len16;
1929 union fw_port_stats {
1930 struct fw_port_stats_ctl {
1942 struct fw_port_stats_all {
1951 __be64 tx_128b_255b;
1952 __be64 tx_256b_511b;
1953 __be64 tx_512b_1023b;
1954 __be64 tx_1024b_1518b;
1955 __be64 tx_1519b_max;
1971 __be64 rx_mtu_error;
1972 __be64 rx_mtu_crc_error;
1973 __be64 rx_crc_error;
1974 __be64 rx_len_error;
1975 __be64 rx_sym_error;
1978 __be64 rx_128b_255b;
1979 __be64 rx_256b_511b;
1980 __be64 rx_512b_1023b;
1981 __be64 rx_1024b_1518b;
1982 __be64 rx_1519b_max;
1999 struct fw_rss_ind_tbl_cmd {
2001 __be32 retval_len16;
2009 __be32 iq12_to_iq14;
2010 __be32 iq15_to_iq17;
2011 __be32 iq18_to_iq20;
2012 __be32 iq21_to_iq23;
2013 __be32 iq24_to_iq26;
2014 __be32 iq27_to_iq29;
2019 #define S_FW_RSS_IND_TBL_CMD_VIID 0
2020 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
2021 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
2022 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
2023 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
2025 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
2026 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
2027 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
2028 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
2029 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
2031 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
2032 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
2033 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
2034 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
2035 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
2037 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
2038 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
2039 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
2040 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
2041 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
2043 struct fw_rss_glb_config_cmd {
2045 __be32 retval_len16;
2046 union fw_rss_glb_config {
2047 struct fw_rss_glb_config_manual {
2053 struct fw_rss_glb_config_basicvirtual {
2054 __be32 mode_keymode;
2055 __be32 synmapen_to_hashtoeplitz;
2062 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
2063 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
2064 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
2065 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
2067 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2069 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
2070 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
2071 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
2072 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
2074 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
2075 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
2076 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
2077 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
2078 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
2080 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
2081 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
2082 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
2083 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
2084 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
2086 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
2087 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
2088 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
2089 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
2090 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
2092 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
2093 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
2094 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
2095 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
2096 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
2098 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
2099 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
2100 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
2101 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
2103 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
2104 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
2105 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
2106 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
2108 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
2109 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
2110 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
2111 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
2112 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
2114 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
2115 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
2116 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
2117 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
2118 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
2120 struct fw_rss_vi_config_cmd {
2122 __be32 retval_len16;
2123 union fw_rss_vi_config {
2124 struct fw_rss_vi_config_manual {
2129 struct fw_rss_vi_config_basicvirtual {
2131 __be32 defaultq_to_udpen;
2138 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
2139 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
2140 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
2141 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
2142 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
2144 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
2145 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
2146 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2147 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2148 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2149 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
2150 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2152 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
2153 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
2154 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2155 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2156 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2157 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
2158 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2159 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
2160 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
2162 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
2163 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
2164 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2165 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2166 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2167 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
2168 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2169 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
2170 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
2172 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
2173 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2174 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2175 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2176 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2177 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2178 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2179 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2180 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2182 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2183 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2184 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2185 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2186 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2187 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2188 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2189 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2190 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2192 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2193 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2194 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2195 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2196 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2197 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2199 struct fw_clip_cmd {
2201 __be32 alloc_to_len16;
2207 #define S_FW_CLIP_CMD_ALLOC 31
2208 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
2209 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
2211 #define S_FW_CLIP_CMD_FREE 30
2212 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
2213 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
2215 /******************************************************************************
2216 * D E B U G C O M M A N D s
2217 ******************************************************/
2219 struct fw_debug_cmd {
2223 struct fw_debug_assert {
2228 __u8 filename_0_7[8];
2229 __u8 filename_8_15[8];
2232 struct fw_debug_prt {
2235 __be32 dprtstrparam0;
2236 __be32 dprtstrparam1;
2237 __be32 dprtstrparam2;
2238 __be32 dprtstrparam3;
2243 #define S_FW_DEBUG_CMD_TYPE 0
2244 #define M_FW_DEBUG_CMD_TYPE 0xff
2245 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2246 #define G_FW_DEBUG_CMD_TYPE(x) \
2247 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2249 /******************************************************************************
2250 * P C I E F W R E G I S T E R
2251 **************************************/
2254 * Register definitions for the PCIE_FW register which the firmware uses
2255 * to retain status across RESETs. This register should be considered
2256 * as a READ-ONLY register for Host Software and only to be used to
2257 * track firmware initialization/error state, etc.
2259 #define S_PCIE_FW_ERR 31
2260 #define M_PCIE_FW_ERR 0x1
2261 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2262 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2263 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2265 #define S_PCIE_FW_INIT 30
2266 #define M_PCIE_FW_INIT 0x1
2267 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2268 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2269 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2271 #define S_PCIE_FW_HALT 29
2272 #define M_PCIE_FW_HALT 0x1
2273 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2274 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2275 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2277 #define S_PCIE_FW_EVAL 24
2278 #define M_PCIE_FW_EVAL 0x7
2279 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2280 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2282 #define S_PCIE_FW_MASTER_VLD 15
2283 #define M_PCIE_FW_MASTER_VLD 0x1
2284 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2285 #define G_PCIE_FW_MASTER_VLD(x) \
2286 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2287 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2289 #define S_PCIE_FW_MASTER 12
2290 #define M_PCIE_FW_MASTER 0x7
2291 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2292 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2294 /******************************************************************************
2295 * B I N A R Y H E A D E R F O R M A T
2296 **********************************************/
2299 * firmware binary header format
2303 __u8 chip; /* terminator chip family */
2304 __be16 len512; /* bin length in units of 512-bytes */
2305 __be32 fw_ver; /* firmware version */
2306 __be32 tp_microcode_ver; /* tcp processor microcode version */
2311 __u8 intfver_iscsipdu;
2313 __u8 intfver_fcoepdu;
2317 __u32 magic; /* runtime or bootstrap fw */
2319 __be32 reserved6[23];
2322 #define S_FW_HDR_FW_VER_MAJOR 24
2323 #define M_FW_HDR_FW_VER_MAJOR 0xff
2324 #define V_FW_HDR_FW_VER_MAJOR(x) \
2325 ((x) << S_FW_HDR_FW_VER_MAJOR)
2326 #define G_FW_HDR_FW_VER_MAJOR(x) \
2327 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2329 #define S_FW_HDR_FW_VER_MINOR 16
2330 #define M_FW_HDR_FW_VER_MINOR 0xff
2331 #define V_FW_HDR_FW_VER_MINOR(x) \
2332 ((x) << S_FW_HDR_FW_VER_MINOR)
2333 #define G_FW_HDR_FW_VER_MINOR(x) \
2334 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2336 #define S_FW_HDR_FW_VER_MICRO 8
2337 #define M_FW_HDR_FW_VER_MICRO 0xff
2338 #define V_FW_HDR_FW_VER_MICRO(x) \
2339 ((x) << S_FW_HDR_FW_VER_MICRO)
2340 #define G_FW_HDR_FW_VER_MICRO(x) \
2341 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2343 #define S_FW_HDR_FW_VER_BUILD 0
2344 #define M_FW_HDR_FW_VER_BUILD 0xff
2345 #define V_FW_HDR_FW_VER_BUILD(x) \
2346 ((x) << S_FW_HDR_FW_VER_BUILD)
2347 #define G_FW_HDR_FW_VER_BUILD(x) \
2348 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2350 #endif /* _T4FW_INTERFACE_H_ */