1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
60 FW_ETH_TX_PKT_WR = 0x08,
61 FW_ETH_TX_PKTS_WR = 0x09,
62 FW_ETH_TX_PKT_VM_WR = 0x11,
63 FW_ETH_TX_PKTS_VM_WR = 0x12,
65 FW_ETH_TX_PKTS2_WR = 0x78,
69 * Generic work request header flit0
76 /* work request opcode (hi)
79 #define M_FW_WR_OP 0xff
80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
81 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
83 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
85 #define S_FW_WR_ATOMIC 23
86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
88 /* work request immediate data length (hi)
90 #define S_FW_WR_IMMDLEN 0
91 #define M_FW_WR_IMMDLEN 0xff
92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
93 #define G_FW_WR_IMMDLEN(x) \
94 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
96 /* egress queue status update to egress queue status entry (lo)
98 #define S_FW_WR_EQUEQ 30
99 #define M_FW_WR_EQUEQ 0x1
100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
101 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
102 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
104 /* flow context identifier (lo)
106 #define S_FW_WR_FLOWID 8
107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
109 /* length in units of 16-bytes (lo)
111 #define S_FW_WR_LEN16 0
112 #define M_FW_WR_LEN16 0xff
113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
114 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
116 struct fw_eth_tx_pkt_wr {
118 __be32 equiq_to_len16;
122 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
123 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
124 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
125 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
126 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
128 struct fw_eth_tx_pkts_wr {
130 __be32 equiq_to_len16;
137 struct fw_eth_tx_pkt_vm_wr {
139 __be32 equiq_to_len16;
147 struct fw_eth_tx_pkts_vm_wr {
149 __be32 equiq_to_len16;
160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
161 enum fw_filter_wr_cookie {
162 FW_FILTER_WR_SUCCESS,
163 FW_FILTER_WR_FLT_ADDED,
164 FW_FILTER_WR_FLT_DELETED,
165 FW_FILTER_WR_SMT_TBL_FULL,
169 struct fw_filter2_wr {
174 __be32 del_filter_to_l2tix;
177 __u8 frag_to_ovlan_vldm;
179 __be16 rx_chan_rx_rpl_iq;
180 __be32 maci_to_matchtypem;
200 __u8 filter_type_swapmac;
201 __u8 natmode_to_ulp_type;
214 #define S_FW_FILTER_WR_TID 12
215 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
217 #define S_FW_FILTER_WR_RQTYPE 11
218 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
220 #define S_FW_FILTER_WR_NOREPLY 10
221 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
223 #define S_FW_FILTER_WR_IQ 0
224 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
226 #define S_FW_FILTER_WR_DEL_FILTER 31
227 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
228 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
230 #define S_FW_FILTER_WR_RPTTID 25
231 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
233 #define S_FW_FILTER_WR_DROP 24
234 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
236 #define S_FW_FILTER_WR_DIRSTEER 23
237 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
239 #define S_FW_FILTER_WR_MASKHASH 22
240 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
242 #define S_FW_FILTER_WR_DIRSTEERHASH 21
243 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
245 #define S_FW_FILTER_WR_LPBK 20
246 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
248 #define S_FW_FILTER_WR_DMAC 19
249 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
251 #define S_FW_FILTER_WR_INSVLAN 17
252 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
254 #define S_FW_FILTER_WR_RMVLAN 16
255 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
257 #define S_FW_FILTER_WR_HITCNTS 15
258 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
260 #define S_FW_FILTER_WR_TXCHAN 13
261 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
263 #define S_FW_FILTER_WR_PRIO 12
264 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
266 #define S_FW_FILTER_WR_L2TIX 0
267 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
269 #define S_FW_FILTER_WR_FRAG 7
270 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
272 #define S_FW_FILTER_WR_FRAGM 6
273 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
275 #define S_FW_FILTER_WR_IVLAN_VLD 5
276 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
278 #define S_FW_FILTER_WR_OVLAN_VLD 4
279 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
281 #define S_FW_FILTER_WR_IVLAN_VLDM 3
282 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
284 #define S_FW_FILTER_WR_OVLAN_VLDM 2
285 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
287 #define S_FW_FILTER_WR_RX_CHAN 15
288 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
290 #define S_FW_FILTER_WR_RX_RPL_IQ 0
291 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
293 #define S_FW_FILTER_WR_MACI 23
294 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
296 #define S_FW_FILTER_WR_MACIM 14
297 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
299 #define S_FW_FILTER_WR_FCOE 13
300 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
302 #define S_FW_FILTER_WR_FCOEM 12
303 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
305 #define S_FW_FILTER_WR_PORT 9
306 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
308 #define S_FW_FILTER_WR_PORTM 6
309 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
311 #define S_FW_FILTER_WR_MATCHTYPE 3
312 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
314 #define S_FW_FILTER_WR_MATCHTYPEM 0
315 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
317 #define S_FW_FILTER2_WR_SWAPMAC 0
318 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
320 #define S_FW_FILTER2_WR_NATMODE 5
321 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
323 #define S_FW_FILTER2_WR_ULP_TYPE 0
324 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
326 /******************************************************************************
328 *********************/
331 * The maximum length of time, in miliseconds, that we expect any firmware
332 * command to take to execute and return a reply to the host. The RESET
333 * and INITIALIZE commands can take a fair amount of time to execute but
334 * most execute in far less time than this maximum. This constant is used
335 * by host software to determine how long to wait for a firmware command
336 * reply before declaring the firmware as dead/unreachable ...
338 #define FW_CMD_MAX_TIMEOUT 10000
341 * If a host driver does a HELLO and discovers that there's already a MASTER
342 * selected, we may have to wait for that MASTER to finish issuing RESET,
343 * configuration and INITIALIZE commands. Also, there's a possibility that
344 * our own HELLO may get lost if it happens right as the MASTER is issuign a
345 * RESET command, so we need to be willing to make a few retries of our HELLO.
347 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
348 #define FW_CMD_HELLO_RETRIES 3
350 enum fw_cmd_opcodes {
355 FW_INITIALIZE_CMD = 0x06,
356 FW_CAPS_CONFIG_CMD = 0x07,
357 FW_PARAMS_CMD = 0x08,
360 FW_EQ_ETH_CMD = 0x12,
361 FW_EQ_CTRL_CMD = 0x13,
363 FW_VI_MAC_CMD = 0x15,
364 FW_VI_RXMODE_CMD = 0x16,
365 FW_VI_ENABLE_CMD = 0x17,
366 FW_VI_STATS_CMD = 0x1a,
368 FW_RSS_IND_TBL_CMD = 0x20,
369 FW_RSS_GLB_CONFIG_CMD = 0x22,
370 FW_RSS_VI_CONFIG_CMD = 0x23,
376 FW_CMD_CAP_PORT = 0x04,
380 * Generic command header flit0
387 #define S_FW_CMD_OP 24
388 #define M_FW_CMD_OP 0xff
389 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
390 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
392 #define S_FW_CMD_REQUEST 23
393 #define M_FW_CMD_REQUEST 0x1
394 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
395 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
396 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
398 #define S_FW_CMD_READ 22
399 #define M_FW_CMD_READ 0x1
400 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
401 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
402 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
404 #define S_FW_CMD_WRITE 21
405 #define M_FW_CMD_WRITE 0x1
406 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
407 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
408 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
410 #define S_FW_CMD_EXEC 20
411 #define M_FW_CMD_EXEC 0x1
412 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
413 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
414 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
416 #define S_FW_CMD_RETVAL 8
417 #define M_FW_CMD_RETVAL 0xff
418 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
419 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
421 #define S_FW_CMD_LEN16 0
422 #define M_FW_CMD_LEN16 0xff
423 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
424 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
426 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
430 enum fw_ldst_addrspc {
431 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
435 __be32 op_to_addrspace;
436 __be32 cycles_to_len16;
438 struct fw_ldst_addrval {
442 struct fw_ldst_idctxt {
444 __be32 msg_ctxtflush;
454 struct fw_ldst_mdio {
470 struct fw_ldst_func {
478 struct fw_ldst_pcie {
488 struct fw_ldst_i2c_deprecated {
512 #define S_FW_LDST_CMD_ADDRSPACE 0
513 #define M_FW_LDST_CMD_ADDRSPACE 0xff
514 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
516 struct fw_reset_cmd {
523 #define S_FW_RESET_CMD_HALT 31
524 #define M_FW_RESET_CMD_HALT 0x1
525 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
526 #define G_FW_RESET_CMD_HALT(x) \
527 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
528 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
531 FW_HELLO_CMD_STAGE_OS = 0,
534 struct fw_hello_cmd {
537 __be32 err_to_clearinit;
541 #define S_FW_HELLO_CMD_ERR 31
542 #define M_FW_HELLO_CMD_ERR 0x1
543 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
544 #define G_FW_HELLO_CMD_ERR(x) \
545 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
546 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
548 #define S_FW_HELLO_CMD_INIT 30
549 #define M_FW_HELLO_CMD_INIT 0x1
550 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
551 #define G_FW_HELLO_CMD_INIT(x) \
552 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
553 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
555 #define S_FW_HELLO_CMD_MASTERDIS 29
556 #define M_FW_HELLO_CMD_MASTERDIS 0x1
557 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
558 #define G_FW_HELLO_CMD_MASTERDIS(x) \
559 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
560 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
562 #define S_FW_HELLO_CMD_MASTERFORCE 28
563 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
564 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
565 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
566 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
567 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
569 #define S_FW_HELLO_CMD_MBMASTER 24
570 #define M_FW_HELLO_CMD_MBMASTER 0xf
571 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
572 #define G_FW_HELLO_CMD_MBMASTER(x) \
573 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
575 #define S_FW_HELLO_CMD_MBASYNCNOT 20
576 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
577 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
578 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
579 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
581 #define S_FW_HELLO_CMD_STAGE 17
582 #define M_FW_HELLO_CMD_STAGE 0x7
583 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
584 #define G_FW_HELLO_CMD_STAGE(x) \
585 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
587 #define S_FW_HELLO_CMD_CLEARINIT 16
588 #define M_FW_HELLO_CMD_CLEARINIT 0x1
589 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
590 #define G_FW_HELLO_CMD_CLEARINIT(x) \
591 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
592 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
600 struct fw_initialize_cmd {
606 enum fw_caps_config_nic {
607 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
608 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
612 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
615 struct fw_caps_config_cmd {
617 __be32 cfvalid_to_len16;
635 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
636 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
637 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
638 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
639 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
640 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
642 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
643 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
644 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
645 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
646 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
647 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
648 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
650 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
651 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
652 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
653 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
654 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
655 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
656 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
659 * params command mnemonics
661 enum fw_params_mnem {
662 FW_PARAMS_MNEM_DEV = 1, /* device params */
663 FW_PARAMS_MNEM_PFVF = 2, /* function params */
664 FW_PARAMS_MNEM_REG = 3, /* limited register access */
665 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
671 enum fw_params_param_dev {
672 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
673 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
674 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
675 * allocated by the device's
678 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
679 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
680 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
681 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
685 * physical and virtual function parameters
687 enum fw_params_param_pfvf {
688 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
689 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
690 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
691 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
692 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
693 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
694 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
695 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
696 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
700 * dma queue parameters
702 enum fw_params_param_dmaq {
703 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
704 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
707 #define S_FW_PARAMS_MNEM 24
708 #define M_FW_PARAMS_MNEM 0xff
709 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
710 #define G_FW_PARAMS_MNEM(x) \
711 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
713 #define S_FW_PARAMS_PARAM_X 16
714 #define M_FW_PARAMS_PARAM_X 0xff
715 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
716 #define G_FW_PARAMS_PARAM_X(x) \
717 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
719 #define S_FW_PARAMS_PARAM_Y 8
720 #define M_FW_PARAMS_PARAM_Y 0xff
721 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
722 #define G_FW_PARAMS_PARAM_Y(x) \
723 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
725 #define S_FW_PARAMS_PARAM_Z 0
726 #define M_FW_PARAMS_PARAM_Z 0xff
727 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
728 #define G_FW_PARAMS_PARAM_Z(x) \
729 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
731 #define S_FW_PARAMS_PARAM_YZ 0
732 #define M_FW_PARAMS_PARAM_YZ 0xffff
733 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
734 #define G_FW_PARAMS_PARAM_YZ(x) \
735 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
737 #define S_FW_PARAMS_PARAM_XYZ 0
738 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
739 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
741 struct fw_params_cmd {
744 struct fw_params_param {
750 #define S_FW_PARAMS_CMD_PFN 8
751 #define M_FW_PARAMS_CMD_PFN 0x7
752 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
753 #define G_FW_PARAMS_CMD_PFN(x) \
754 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
756 #define S_FW_PARAMS_CMD_VFN 0
757 #define M_FW_PARAMS_CMD_VFN 0xff
758 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
759 #define G_FW_PARAMS_CMD_VFN(x) \
760 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
767 __be32 tc_to_nexactf;
768 __be32 r_caps_to_nethctrl;
774 #define S_FW_PFVF_CMD_PFN 8
775 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
777 #define S_FW_PFVF_CMD_VFN 0
778 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
780 #define S_FW_PFVF_CMD_NIQFLINT 20
781 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
782 #define G_FW_PFVF_CMD_NIQFLINT(x) \
783 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
785 #define S_FW_PFVF_CMD_NIQ 0
786 #define M_FW_PFVF_CMD_NIQ 0xfffff
787 #define G_FW_PFVF_CMD_NIQ(x) \
788 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
790 #define S_FW_PFVF_CMD_PMASK 20
791 #define M_FW_PFVF_CMD_PMASK 0xf
792 #define G_FW_PFVF_CMD_PMASK(x) \
793 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
795 #define S_FW_PFVF_CMD_NEQ 0
796 #define M_FW_PFVF_CMD_NEQ 0xfffff
797 #define G_FW_PFVF_CMD_NEQ(x) \
798 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
800 #define S_FW_PFVF_CMD_TC 24
801 #define M_FW_PFVF_CMD_TC 0xff
802 #define G_FW_PFVF_CMD_TC(x) \
803 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
805 #define S_FW_PFVF_CMD_NVI 16
806 #define M_FW_PFVF_CMD_NVI 0xff
807 #define G_FW_PFVF_CMD_NVI(x) \
808 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
810 #define S_FW_PFVF_CMD_NEXACTF 0
811 #define M_FW_PFVF_CMD_NEXACTF 0xffff
812 #define G_FW_PFVF_CMD_NEXACTF(x) \
813 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
815 #define S_FW_PFVF_CMD_R_CAPS 24
816 #define M_FW_PFVF_CMD_R_CAPS 0xff
817 #define G_FW_PFVF_CMD_R_CAPS(x) \
818 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
820 #define S_FW_PFVF_CMD_WX_CAPS 16
821 #define M_FW_PFVF_CMD_WX_CAPS 0xff
822 #define G_FW_PFVF_CMD_WX_CAPS(x) \
823 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
825 #define S_FW_PFVF_CMD_NETHCTRL 0
826 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
827 #define G_FW_PFVF_CMD_NETHCTRL(x) \
828 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
831 * ingress queue type; the first 1K ingress queues can have associated 0,
832 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
836 FW_IQ_TYPE_FL_INT_CAP,
840 FW_IQ_IQTYPE_NIC = 1,
846 __be32 alloc_to_len16;
851 __be32 type_to_iqandstindex;
852 __be16 iqdroprss_to_iqesize;
855 __be32 iqns_to_fl0congen;
856 __be16 fl0dcaen_to_fl0cidxfthresh;
859 __be32 fl1cngchmap_to_fl1congen;
860 __be16 fl1dcaen_to_fl1cidxfthresh;
865 #define S_FW_IQ_CMD_PFN 8
866 #define M_FW_IQ_CMD_PFN 0x7
867 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
868 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
870 #define S_FW_IQ_CMD_VFN 0
871 #define M_FW_IQ_CMD_VFN 0xff
872 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
873 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
875 #define S_FW_IQ_CMD_ALLOC 31
876 #define M_FW_IQ_CMD_ALLOC 0x1
877 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
878 #define G_FW_IQ_CMD_ALLOC(x) \
879 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
880 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
882 #define S_FW_IQ_CMD_FREE 30
883 #define M_FW_IQ_CMD_FREE 0x1
884 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
885 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
886 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
888 #define S_FW_IQ_CMD_IQSTART 28
889 #define M_FW_IQ_CMD_IQSTART 0x1
890 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
891 #define G_FW_IQ_CMD_IQSTART(x) \
892 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
893 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
895 #define S_FW_IQ_CMD_IQSTOP 27
896 #define M_FW_IQ_CMD_IQSTOP 0x1
897 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
898 #define G_FW_IQ_CMD_IQSTOP(x) \
899 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
900 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
902 #define S_FW_IQ_CMD_TYPE 29
903 #define M_FW_IQ_CMD_TYPE 0x7
904 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
905 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
907 #define S_FW_IQ_CMD_IQASYNCH 28
908 #define M_FW_IQ_CMD_IQASYNCH 0x1
909 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
910 #define G_FW_IQ_CMD_IQASYNCH(x) \
911 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
912 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
914 #define S_FW_IQ_CMD_VIID 16
915 #define M_FW_IQ_CMD_VIID 0xfff
916 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
917 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
919 #define S_FW_IQ_CMD_IQANDST 15
920 #define M_FW_IQ_CMD_IQANDST 0x1
921 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
922 #define G_FW_IQ_CMD_IQANDST(x) \
923 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
924 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
926 #define S_FW_IQ_CMD_IQANUD 12
927 #define M_FW_IQ_CMD_IQANUD 0x3
928 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
929 #define G_FW_IQ_CMD_IQANUD(x) \
930 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
932 #define S_FW_IQ_CMD_IQANDSTINDEX 0
933 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
934 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
935 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
936 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
938 #define S_FW_IQ_CMD_IQGTSMODE 14
939 #define M_FW_IQ_CMD_IQGTSMODE 0x1
940 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
941 #define G_FW_IQ_CMD_IQGTSMODE(x) \
942 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
943 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
945 #define S_FW_IQ_CMD_IQPCIECH 12
946 #define M_FW_IQ_CMD_IQPCIECH 0x3
947 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
948 #define G_FW_IQ_CMD_IQPCIECH(x) \
949 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
951 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
952 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
953 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
954 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
955 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
957 #define S_FW_IQ_CMD_IQESIZE 0
958 #define M_FW_IQ_CMD_IQESIZE 0x3
959 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
960 #define G_FW_IQ_CMD_IQESIZE(x) \
961 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
963 #define S_FW_IQ_CMD_IQRO 30
964 #define M_FW_IQ_CMD_IQRO 0x1
965 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
966 #define G_FW_IQ_CMD_IQRO(x) \
967 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
968 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
970 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
971 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
972 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
973 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
974 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
975 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
977 #define S_FW_IQ_CMD_IQTYPE 24
978 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
980 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
981 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
982 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
983 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
984 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
986 #define S_FW_IQ_CMD_FL0DATARO 12
987 #define M_FW_IQ_CMD_FL0DATARO 0x1
988 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
989 #define G_FW_IQ_CMD_FL0DATARO(x) \
990 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
991 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
993 #define S_FW_IQ_CMD_FL0CONGCIF 11
994 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
995 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
996 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
997 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
998 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
1000 #define S_FW_IQ_CMD_FL0FETCHRO 6
1001 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
1002 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
1003 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
1004 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
1005 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
1007 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
1008 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
1009 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
1010 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
1011 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
1013 #define S_FW_IQ_CMD_FL0PADEN 2
1014 #define M_FW_IQ_CMD_FL0PADEN 0x1
1015 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
1016 #define G_FW_IQ_CMD_FL0PADEN(x) \
1017 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
1018 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
1020 #define S_FW_IQ_CMD_FL0PACKEN 1
1021 #define M_FW_IQ_CMD_FL0PACKEN 0x1
1022 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
1023 #define G_FW_IQ_CMD_FL0PACKEN(x) \
1024 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
1025 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
1027 #define S_FW_IQ_CMD_FL0CONGEN 0
1028 #define M_FW_IQ_CMD_FL0CONGEN 0x1
1029 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
1030 #define G_FW_IQ_CMD_FL0CONGEN(x) \
1031 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
1032 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
1034 #define S_FW_IQ_CMD_FL0FBMIN 7
1035 #define M_FW_IQ_CMD_FL0FBMIN 0x7
1036 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
1037 #define G_FW_IQ_CMD_FL0FBMIN(x) \
1038 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
1040 #define S_FW_IQ_CMD_FL0FBMAX 4
1041 #define M_FW_IQ_CMD_FL0FBMAX 0x7
1042 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
1043 #define G_FW_IQ_CMD_FL0FBMAX(x) \
1044 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
1046 struct fw_eq_eth_cmd {
1048 __be32 alloc_to_len16;
1050 __be32 physeqid_pkd;
1051 __be32 fetchszm_to_iqid;
1052 __be32 dcaen_to_eqsize;
1054 __be32 autoequiqe_to_viid;
1059 #define S_FW_EQ_ETH_CMD_PFN 8
1060 #define M_FW_EQ_ETH_CMD_PFN 0x7
1061 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
1062 #define G_FW_EQ_ETH_CMD_PFN(x) \
1063 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
1065 #define S_FW_EQ_ETH_CMD_VFN 0
1066 #define M_FW_EQ_ETH_CMD_VFN 0xff
1067 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
1068 #define G_FW_EQ_ETH_CMD_VFN(x) \
1069 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
1071 #define S_FW_EQ_ETH_CMD_ALLOC 31
1072 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
1073 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
1074 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
1075 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
1076 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
1078 #define S_FW_EQ_ETH_CMD_FREE 30
1079 #define M_FW_EQ_ETH_CMD_FREE 0x1
1080 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
1081 #define G_FW_EQ_ETH_CMD_FREE(x) \
1082 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
1083 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
1085 #define S_FW_EQ_ETH_CMD_EQSTART 28
1086 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
1087 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
1088 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
1089 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
1090 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
1092 #define S_FW_EQ_ETH_CMD_EQID 0
1093 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
1094 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
1095 #define G_FW_EQ_ETH_CMD_EQID(x) \
1096 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
1098 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
1099 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
1100 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
1101 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
1103 #define S_FW_EQ_ETH_CMD_FETCHRO 22
1104 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
1105 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
1106 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
1107 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
1108 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
1110 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
1111 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
1112 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
1113 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
1114 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
1116 #define S_FW_EQ_ETH_CMD_PCIECHN 16
1117 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
1118 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
1119 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
1120 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
1122 #define S_FW_EQ_ETH_CMD_IQID 0
1123 #define M_FW_EQ_ETH_CMD_IQID 0xffff
1124 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
1125 #define G_FW_EQ_ETH_CMD_IQID(x) \
1126 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
1128 #define S_FW_EQ_ETH_CMD_FBMIN 23
1129 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
1130 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
1131 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
1132 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
1134 #define S_FW_EQ_ETH_CMD_FBMAX 20
1135 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
1136 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
1137 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
1138 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
1140 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
1141 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
1142 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
1143 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
1144 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
1146 #define S_FW_EQ_ETH_CMD_EQSIZE 0
1147 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
1148 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
1149 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
1150 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
1152 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
1153 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
1154 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
1155 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
1156 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
1157 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
1159 #define S_FW_EQ_ETH_CMD_VIID 16
1160 #define M_FW_EQ_ETH_CMD_VIID 0xfff
1161 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
1162 #define G_FW_EQ_ETH_CMD_VIID(x) \
1163 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
1165 struct fw_eq_ctrl_cmd {
1167 __be32 alloc_to_len16;
1168 __be32 cmpliqid_eqid;
1169 __be32 physeqid_pkd;
1170 __be32 fetchszm_to_iqid;
1171 __be32 dcaen_to_eqsize;
1175 #define S_FW_EQ_CTRL_CMD_PFN 8
1176 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
1178 #define S_FW_EQ_CTRL_CMD_VFN 0
1179 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
1181 #define S_FW_EQ_CTRL_CMD_ALLOC 31
1182 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
1183 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
1185 #define S_FW_EQ_CTRL_CMD_FREE 30
1186 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
1187 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
1189 #define S_FW_EQ_CTRL_CMD_EQSTART 28
1190 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
1191 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
1193 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
1194 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
1196 #define S_FW_EQ_CTRL_CMD_EQID 0
1197 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
1198 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
1199 #define G_FW_EQ_CTRL_CMD_EQID(x) \
1200 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1202 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1203 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1204 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1205 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1206 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1208 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1209 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1210 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1212 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1213 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1214 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1216 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1217 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1219 #define S_FW_EQ_CTRL_CMD_IQID 0
1220 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1222 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1223 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1225 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1226 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1228 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1229 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1231 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1232 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1240 __be32 alloc_to_len16;
1241 __be16 type_to_viid;
1246 __be16 norss_rsssize;
1256 #define S_FW_VI_CMD_PFN 8
1257 #define M_FW_VI_CMD_PFN 0x7
1258 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1259 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1261 #define S_FW_VI_CMD_VFN 0
1262 #define M_FW_VI_CMD_VFN 0xff
1263 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1264 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1266 #define S_FW_VI_CMD_ALLOC 31
1267 #define M_FW_VI_CMD_ALLOC 0x1
1268 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1269 #define G_FW_VI_CMD_ALLOC(x) \
1270 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1271 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1273 #define S_FW_VI_CMD_FREE 30
1274 #define M_FW_VI_CMD_FREE 0x1
1275 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1276 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1277 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1279 #define S_FW_VI_CMD_TYPE 15
1280 #define M_FW_VI_CMD_TYPE 0x1
1281 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1282 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1283 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1285 #define S_FW_VI_CMD_FUNC 12
1286 #define M_FW_VI_CMD_FUNC 0x7
1287 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1288 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1290 #define S_FW_VI_CMD_VIID 0
1291 #define M_FW_VI_CMD_VIID 0xfff
1292 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1293 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1295 #define S_FW_VI_CMD_PORTID 4
1296 #define M_FW_VI_CMD_PORTID 0xf
1297 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1298 #define G_FW_VI_CMD_PORTID(x) \
1299 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1301 #define S_FW_VI_CMD_RSSSIZE 0
1302 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1303 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1304 #define G_FW_VI_CMD_RSSSIZE(x) \
1305 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1307 /* Special VI_MAC command index ids */
1308 #define FW_VI_MAC_ADD_MAC 0x3FF
1309 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1310 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
1312 enum fw_vi_mac_smac {
1313 FW_VI_MAC_MPS_TCAM_ENTRY,
1314 FW_VI_MAC_SMT_AND_MPSTCAM
1317 enum fw_vi_mac_entry_types {
1318 FW_VI_MAC_TYPE_RAW = 0x2,
1321 struct fw_vi_mac_cmd {
1323 __be32 freemacs_to_len16;
1325 struct fw_vi_mac_exact {
1326 __be16 valid_to_idx;
1329 struct fw_vi_mac_hash {
1332 struct fw_vi_mac_raw {
1342 #define S_FW_VI_MAC_CMD_VIID 0
1343 #define M_FW_VI_MAC_CMD_VIID 0xfff
1344 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1345 #define G_FW_VI_MAC_CMD_VIID(x) \
1346 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1348 #define S_FW_VI_MAC_CMD_FREEMACS 31
1349 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
1351 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
1352 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
1354 #define S_FW_VI_MAC_CMD_VALID 15
1355 #define M_FW_VI_MAC_CMD_VALID 0x1
1356 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1357 #define G_FW_VI_MAC_CMD_VALID(x) \
1358 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1359 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1361 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1362 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1363 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1364 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1365 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1367 #define S_FW_VI_MAC_CMD_IDX 0
1368 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1369 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1370 #define G_FW_VI_MAC_CMD_IDX(x) \
1371 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1373 #define S_FW_VI_MAC_CMD_RAW_IDX 16
1374 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
1375 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
1376 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
1377 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
1379 struct fw_vi_rxmode_cmd {
1381 __be32 retval_len16;
1382 __be32 mtu_to_vlanexen;
1386 #define S_FW_VI_RXMODE_CMD_VIID 0
1387 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1388 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1389 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1390 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1392 #define S_FW_VI_RXMODE_CMD_MTU 16
1393 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1394 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1395 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1396 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1398 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1399 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1400 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1401 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1402 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1404 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1405 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1406 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1407 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1408 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1409 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1411 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1412 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1413 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1414 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1415 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1416 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1417 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1419 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1420 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1421 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1422 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1423 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1425 struct fw_vi_enable_cmd {
1427 __be32 ien_to_len16;
1433 #define S_FW_VI_ENABLE_CMD_VIID 0
1434 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1435 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1436 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1437 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1439 #define S_FW_VI_ENABLE_CMD_IEN 31
1440 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1441 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1442 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1443 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1444 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1446 #define S_FW_VI_ENABLE_CMD_EEN 30
1447 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1448 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1449 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1450 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1451 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1453 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1454 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1455 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1456 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1457 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1458 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1460 /* VI VF stats offset definitions */
1461 #define VI_VF_NUM_STATS 16
1463 /* VI PF stats offset definitions */
1464 #define VI_PF_NUM_STATS 17
1465 enum fw_vi_stats_pf_index {
1466 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1467 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1468 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1469 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1470 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1471 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1472 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1473 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1474 FW_VI_PF_STAT_RX_BYTES_IX,
1475 FW_VI_PF_STAT_RX_FRAMES_IX,
1476 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1477 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1478 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1479 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1480 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1481 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1482 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1485 struct fw_vi_stats_cmd {
1487 __be32 retval_len16;
1489 struct fw_vi_stats_ctl {
1500 struct fw_vi_stats_pf {
1501 __be64 tx_bcast_bytes;
1502 __be64 tx_bcast_frames;
1503 __be64 tx_mcast_bytes;
1504 __be64 tx_mcast_frames;
1505 __be64 tx_ucast_bytes;
1506 __be64 tx_ucast_frames;
1507 __be64 tx_offload_bytes;
1508 __be64 tx_offload_frames;
1510 __be64 rx_pf_frames;
1511 __be64 rx_bcast_bytes;
1512 __be64 rx_bcast_frames;
1513 __be64 rx_mcast_bytes;
1514 __be64 rx_mcast_frames;
1515 __be64 rx_ucast_bytes;
1516 __be64 rx_ucast_frames;
1517 __be64 rx_err_frames;
1519 struct fw_vi_stats_vf {
1520 __be64 tx_bcast_bytes;
1521 __be64 tx_bcast_frames;
1522 __be64 tx_mcast_bytes;
1523 __be64 tx_mcast_frames;
1524 __be64 tx_ucast_bytes;
1525 __be64 tx_ucast_frames;
1526 __be64 tx_drop_frames;
1527 __be64 tx_offload_bytes;
1528 __be64 tx_offload_frames;
1529 __be64 rx_bcast_bytes;
1530 __be64 rx_bcast_frames;
1531 __be64 rx_mcast_bytes;
1532 __be64 rx_mcast_frames;
1533 __be64 rx_ucast_bytes;
1534 __be64 rx_ucast_frames;
1535 __be64 rx_err_frames;
1540 #define S_FW_VI_STATS_CMD_VIID 0
1541 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1543 #define S_FW_VI_STATS_CMD_NSTATS 12
1544 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1546 #define S_FW_VI_STATS_CMD_IX 0
1547 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1549 /* old 16-bit port capabilities bitmap */
1551 FW_PORT_CAP_SPEED_100M = 0x0001,
1552 FW_PORT_CAP_SPEED_1G = 0x0002,
1553 FW_PORT_CAP_SPEED_25G = 0x0004,
1554 FW_PORT_CAP_SPEED_10G = 0x0008,
1555 FW_PORT_CAP_SPEED_40G = 0x0010,
1556 FW_PORT_CAP_SPEED_100G = 0x0020,
1557 FW_PORT_CAP_FC_RX = 0x0040,
1558 FW_PORT_CAP_FC_TX = 0x0080,
1559 FW_PORT_CAP_ANEG = 0x0100,
1560 FW_PORT_CAP_MDIX = 0x0200,
1561 FW_PORT_CAP_MDIAUTO = 0x0400,
1562 FW_PORT_CAP_FEC_RS = 0x0800,
1563 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1564 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1565 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1566 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1569 #define S_FW_PORT_CAP_SPEED 0
1570 #define M_FW_PORT_CAP_SPEED 0x3f
1571 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1572 #define G_FW_PORT_CAP_SPEED(x) \
1573 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1576 FW_PORT_CAP_MDI_AUTO,
1579 #define S_FW_PORT_CAP_MDI 9
1580 #define M_FW_PORT_CAP_MDI 3
1581 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1582 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1584 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1585 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1586 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1587 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1588 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1589 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1590 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1591 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1592 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1593 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1594 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1595 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1596 #define FW_PORT_CAP32_ANEG 0x00100000UL
1597 #define FW_PORT_CAP32_MDIX 0x00200000UL
1598 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1599 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1600 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1602 #define S_FW_PORT_CAP32_SPEED 0
1603 #define M_FW_PORT_CAP32_SPEED 0xfff
1604 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1605 #define G_FW_PORT_CAP32_SPEED(x) \
1606 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1608 enum fw_port_mdi32 {
1609 FW_PORT_CAP32_MDI_AUTO,
1612 #define S_FW_PORT_CAP32_MDI 21
1613 #define M_FW_PORT_CAP32_MDI 3
1614 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1615 #define G_FW_PORT_CAP32_MDI(x) \
1616 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1618 enum fw_port_action {
1619 FW_PORT_ACTION_L1_CFG = 0x0001,
1620 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1621 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1622 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1625 struct fw_port_cmd {
1626 __be32 op_to_portid;
1627 __be32 action_to_len16;
1629 struct fw_port_l1cfg {
1633 struct fw_port_l2cfg {
1635 __u8 ovlan3_to_ivlan0;
1637 __be16 txipg_force_pinfo;
1648 struct fw_port_info {
1649 __be32 lstatus_to_modtype;
1660 struct fw_port_diags {
1666 struct fw_port_dcb_pgid {
1673 struct fw_port_dcb_pgrate {
1677 __u8 num_tcs_supported;
1681 struct fw_port_dcb_priorate {
1685 __u8 strict_priorate[8];
1687 struct fw_port_dcb_pfc {
1694 struct fw_port_app_priority {
1703 struct fw_port_dcb_control {
1706 __be16 dcb_version_to_app_state;
1711 struct fw_port_l1cfg32 {
1715 struct fw_port_info32 {
1716 __be32 lstatus32_to_cbllen32;
1717 __be32 auxlinfo32_mtu32;
1726 #define S_FW_PORT_CMD_PORTID 0
1727 #define M_FW_PORT_CMD_PORTID 0xf
1728 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1729 #define G_FW_PORT_CMD_PORTID(x) \
1730 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1732 #define S_FW_PORT_CMD_ACTION 16
1733 #define M_FW_PORT_CMD_ACTION 0xffff
1734 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1735 #define G_FW_PORT_CMD_ACTION(x) \
1736 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1738 #define S_FW_PORT_CMD_LSTATUS 31
1739 #define M_FW_PORT_CMD_LSTATUS 0x1
1740 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1741 #define G_FW_PORT_CMD_LSTATUS(x) \
1742 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1743 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1745 #define S_FW_PORT_CMD_LSPEED 24
1746 #define M_FW_PORT_CMD_LSPEED 0x3f
1747 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1748 #define G_FW_PORT_CMD_LSPEED(x) \
1749 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1751 #define S_FW_PORT_CMD_TXPAUSE 23
1752 #define M_FW_PORT_CMD_TXPAUSE 0x1
1753 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1754 #define G_FW_PORT_CMD_TXPAUSE(x) \
1755 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1756 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1758 #define S_FW_PORT_CMD_RXPAUSE 22
1759 #define M_FW_PORT_CMD_RXPAUSE 0x1
1760 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1761 #define G_FW_PORT_CMD_RXPAUSE(x) \
1762 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1763 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1765 #define S_FW_PORT_CMD_MDIOCAP 21
1766 #define M_FW_PORT_CMD_MDIOCAP 0x1
1767 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1768 #define G_FW_PORT_CMD_MDIOCAP(x) \
1769 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1770 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1772 #define S_FW_PORT_CMD_MDIOADDR 16
1773 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1774 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1775 #define G_FW_PORT_CMD_MDIOADDR(x) \
1776 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1778 #define S_FW_PORT_CMD_PTYPE 8
1779 #define M_FW_PORT_CMD_PTYPE 0x1f
1780 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1781 #define G_FW_PORT_CMD_PTYPE(x) \
1782 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1784 #define S_FW_PORT_CMD_LINKDNRC 5
1785 #define M_FW_PORT_CMD_LINKDNRC 0x7
1786 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1787 #define G_FW_PORT_CMD_LINKDNRC(x) \
1788 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1790 #define S_FW_PORT_CMD_MODTYPE 0
1791 #define M_FW_PORT_CMD_MODTYPE 0x1f
1792 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1793 #define G_FW_PORT_CMD_MODTYPE(x) \
1794 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1796 #define S_FW_PORT_CMD_LSTATUS32 31
1797 #define M_FW_PORT_CMD_LSTATUS32 0x1
1798 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1799 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1801 #define S_FW_PORT_CMD_LINKDNRC32 28
1802 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1803 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1804 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1806 #define S_FW_PORT_CMD_MDIOCAP32 26
1807 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1808 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1809 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1811 #define S_FW_PORT_CMD_MDIOADDR32 21
1812 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1813 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1814 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1816 #define S_FW_PORT_CMD_PORTTYPE32 13
1817 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1818 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1819 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1821 #define S_FW_PORT_CMD_MODTYPE32 8
1822 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1823 #define G_FW_PORT_CMD_MODTYPE32(x) \
1824 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1827 * These are configured into the VPD and hence tools that generate
1828 * VPD may use this enumeration.
1829 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1832 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1833 * with any new Firmware Port Technology Types!
1836 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1837 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1838 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1839 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1840 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1841 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1842 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1843 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1844 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1845 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1846 FW_PORT_TYPE_BP_AP = 10,
1847 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1848 FW_PORT_TYPE_BP4_AP = 11,
1849 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1850 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1851 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1852 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1853 FW_PORT_TYPE_BP40_BA = 15,
1854 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1855 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1856 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1857 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1858 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1859 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1860 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1861 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1864 /* These are read from module's EEPROM and determined once the
1865 * module is inserted.
1867 enum fw_port_module_type {
1868 FW_PORT_MOD_TYPE_NA = 0x0,
1869 FW_PORT_MOD_TYPE_LR = 0x1,
1870 FW_PORT_MOD_TYPE_SR = 0x2,
1871 FW_PORT_MOD_TYPE_ER = 0x3,
1872 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1873 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1874 FW_PORT_MOD_TYPE_LRM = 0x6,
1875 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1876 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1877 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1878 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1881 /* used by FW and tools may use this to generate VPD */
1882 enum fw_port_mod_sub_type {
1883 FW_PORT_MOD_SUB_TYPE_NA,
1884 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1885 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1886 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1887 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1888 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1889 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1890 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1891 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1894 * The following will never been in the VPD. They are TWINAX cable
1895 * lengths decoded from SFP+ module i2c PROMs. These should almost
1896 * certainly go somewhere else ...
1898 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1899 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1900 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1901 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1904 /* link down reason codes (3b) */
1905 enum fw_port_link_dn_rc {
1906 FW_PORT_LINK_DN_RC_NONE,
1907 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1908 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1909 FW_PORT_LINK_DN_RESERVED3,
1910 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1911 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1912 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1913 FW_PORT_LINK_DN_RESERVED7
1917 #define FW_NUM_PORT_STATS 50
1918 #define FW_NUM_PORT_TX_STATS 23
1919 #define FW_NUM_PORT_RX_STATS 27
1921 enum fw_port_stats_tx_index {
1922 FW_STAT_TX_PORT_BYTES_IX,
1923 FW_STAT_TX_PORT_FRAMES_IX,
1924 FW_STAT_TX_PORT_BCAST_IX,
1925 FW_STAT_TX_PORT_MCAST_IX,
1926 FW_STAT_TX_PORT_UCAST_IX,
1927 FW_STAT_TX_PORT_ERROR_IX,
1928 FW_STAT_TX_PORT_64B_IX,
1929 FW_STAT_TX_PORT_65B_127B_IX,
1930 FW_STAT_TX_PORT_128B_255B_IX,
1931 FW_STAT_TX_PORT_256B_511B_IX,
1932 FW_STAT_TX_PORT_512B_1023B_IX,
1933 FW_STAT_TX_PORT_1024B_1518B_IX,
1934 FW_STAT_TX_PORT_1519B_MAX_IX,
1935 FW_STAT_TX_PORT_DROP_IX,
1936 FW_STAT_TX_PORT_PAUSE_IX,
1937 FW_STAT_TX_PORT_PPP0_IX,
1938 FW_STAT_TX_PORT_PPP1_IX,
1939 FW_STAT_TX_PORT_PPP2_IX,
1940 FW_STAT_TX_PORT_PPP3_IX,
1941 FW_STAT_TX_PORT_PPP4_IX,
1942 FW_STAT_TX_PORT_PPP5_IX,
1943 FW_STAT_TX_PORT_PPP6_IX,
1944 FW_STAT_TX_PORT_PPP7_IX
1947 enum fw_port_stat_rx_index {
1948 FW_STAT_RX_PORT_BYTES_IX,
1949 FW_STAT_RX_PORT_FRAMES_IX,
1950 FW_STAT_RX_PORT_BCAST_IX,
1951 FW_STAT_RX_PORT_MCAST_IX,
1952 FW_STAT_RX_PORT_UCAST_IX,
1953 FW_STAT_RX_PORT_MTU_ERROR_IX,
1954 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1955 FW_STAT_RX_PORT_CRC_ERROR_IX,
1956 FW_STAT_RX_PORT_LEN_ERROR_IX,
1957 FW_STAT_RX_PORT_SYM_ERROR_IX,
1958 FW_STAT_RX_PORT_64B_IX,
1959 FW_STAT_RX_PORT_65B_127B_IX,
1960 FW_STAT_RX_PORT_128B_255B_IX,
1961 FW_STAT_RX_PORT_256B_511B_IX,
1962 FW_STAT_RX_PORT_512B_1023B_IX,
1963 FW_STAT_RX_PORT_1024B_1518B_IX,
1964 FW_STAT_RX_PORT_1519B_MAX_IX,
1965 FW_STAT_RX_PORT_PAUSE_IX,
1966 FW_STAT_RX_PORT_PPP0_IX,
1967 FW_STAT_RX_PORT_PPP1_IX,
1968 FW_STAT_RX_PORT_PPP2_IX,
1969 FW_STAT_RX_PORT_PPP3_IX,
1970 FW_STAT_RX_PORT_PPP4_IX,
1971 FW_STAT_RX_PORT_PPP5_IX,
1972 FW_STAT_RX_PORT_PPP6_IX,
1973 FW_STAT_RX_PORT_PPP7_IX,
1974 FW_STAT_RX_PORT_LESS_64B_IX
1977 struct fw_port_stats_cmd {
1978 __be32 op_to_portid;
1979 __be32 retval_len16;
1980 union fw_port_stats {
1981 struct fw_port_stats_ctl {
1993 struct fw_port_stats_all {
2002 __be64 tx_128b_255b;
2003 __be64 tx_256b_511b;
2004 __be64 tx_512b_1023b;
2005 __be64 tx_1024b_1518b;
2006 __be64 tx_1519b_max;
2022 __be64 rx_mtu_error;
2023 __be64 rx_mtu_crc_error;
2024 __be64 rx_crc_error;
2025 __be64 rx_len_error;
2026 __be64 rx_sym_error;
2029 __be64 rx_128b_255b;
2030 __be64 rx_256b_511b;
2031 __be64 rx_512b_1023b;
2032 __be64 rx_1024b_1518b;
2033 __be64 rx_1519b_max;
2050 struct fw_rss_ind_tbl_cmd {
2052 __be32 retval_len16;
2060 __be32 iq12_to_iq14;
2061 __be32 iq15_to_iq17;
2062 __be32 iq18_to_iq20;
2063 __be32 iq21_to_iq23;
2064 __be32 iq24_to_iq26;
2065 __be32 iq27_to_iq29;
2070 #define S_FW_RSS_IND_TBL_CMD_VIID 0
2071 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
2072 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
2073 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
2074 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
2076 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
2077 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
2078 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
2079 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
2080 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
2082 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
2083 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
2084 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
2085 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
2086 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
2088 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
2089 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
2090 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
2091 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
2092 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
2094 struct fw_rss_glb_config_cmd {
2096 __be32 retval_len16;
2097 union fw_rss_glb_config {
2098 struct fw_rss_glb_config_manual {
2104 struct fw_rss_glb_config_basicvirtual {
2105 __be32 mode_keymode;
2106 __be32 synmapen_to_hashtoeplitz;
2113 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
2114 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
2115 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
2116 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
2118 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2120 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
2121 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
2122 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
2123 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
2125 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
2126 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
2127 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
2128 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
2129 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
2131 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
2132 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
2133 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
2134 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
2135 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
2137 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
2138 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
2139 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
2140 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
2141 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
2143 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
2144 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
2145 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
2146 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
2147 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
2149 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
2150 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
2151 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
2152 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
2154 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
2155 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
2156 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
2157 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
2159 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
2160 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
2161 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
2162 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
2163 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
2165 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
2166 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
2167 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
2168 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
2169 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
2171 struct fw_rss_vi_config_cmd {
2173 __be32 retval_len16;
2174 union fw_rss_vi_config {
2175 struct fw_rss_vi_config_manual {
2180 struct fw_rss_vi_config_basicvirtual {
2182 __be32 defaultq_to_udpen;
2189 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
2190 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
2191 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
2192 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
2193 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
2195 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
2196 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
2197 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2198 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2199 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2200 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
2201 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2203 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
2204 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
2205 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2206 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2207 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2208 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
2209 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2210 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
2211 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
2213 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
2214 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
2215 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2216 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2217 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2218 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
2219 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2220 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
2221 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
2223 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
2224 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2225 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2226 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2227 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2228 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2229 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2230 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2231 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2233 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2234 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2235 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2236 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2237 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2238 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2239 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2240 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2241 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2243 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2244 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2245 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2246 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2247 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2248 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2250 struct fw_clip_cmd {
2252 __be32 alloc_to_len16;
2258 #define S_FW_CLIP_CMD_ALLOC 31
2259 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
2260 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
2262 #define S_FW_CLIP_CMD_FREE 30
2263 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
2264 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
2266 /******************************************************************************
2267 * D E B U G C O M M A N D s
2268 ******************************************************/
2270 struct fw_debug_cmd {
2274 struct fw_debug_assert {
2279 __u8 filename_0_7[8];
2280 __u8 filename_8_15[8];
2283 struct fw_debug_prt {
2286 __be32 dprtstrparam0;
2287 __be32 dprtstrparam1;
2288 __be32 dprtstrparam2;
2289 __be32 dprtstrparam3;
2294 #define S_FW_DEBUG_CMD_TYPE 0
2295 #define M_FW_DEBUG_CMD_TYPE 0xff
2296 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2297 #define G_FW_DEBUG_CMD_TYPE(x) \
2298 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2300 /******************************************************************************
2301 * P C I E F W R E G I S T E R
2302 **************************************/
2305 * Register definitions for the PCIE_FW register which the firmware uses
2306 * to retain status across RESETs. This register should be considered
2307 * as a READ-ONLY register for Host Software and only to be used to
2308 * track firmware initialization/error state, etc.
2310 #define S_PCIE_FW_ERR 31
2311 #define M_PCIE_FW_ERR 0x1
2312 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2313 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2314 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2316 #define S_PCIE_FW_INIT 30
2317 #define M_PCIE_FW_INIT 0x1
2318 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2319 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2320 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2322 #define S_PCIE_FW_HALT 29
2323 #define M_PCIE_FW_HALT 0x1
2324 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2325 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2326 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2328 #define S_PCIE_FW_EVAL 24
2329 #define M_PCIE_FW_EVAL 0x7
2330 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2331 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2333 #define S_PCIE_FW_MASTER_VLD 15
2334 #define M_PCIE_FW_MASTER_VLD 0x1
2335 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2336 #define G_PCIE_FW_MASTER_VLD(x) \
2337 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2338 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2340 #define S_PCIE_FW_MASTER 12
2341 #define M_PCIE_FW_MASTER 0x7
2342 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2343 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2345 /******************************************************************************
2346 * B I N A R Y H E A D E R F O R M A T
2347 **********************************************/
2350 * firmware binary header format
2354 __u8 chip; /* terminator chip family */
2355 __be16 len512; /* bin length in units of 512-bytes */
2356 __be32 fw_ver; /* firmware version */
2357 __be32 tp_microcode_ver; /* tcp processor microcode version */
2362 __u8 intfver_iscsipdu;
2364 __u8 intfver_fcoepdu;
2368 __u32 magic; /* runtime or bootstrap fw */
2370 __be32 reserved6[23];
2373 #define S_FW_HDR_FW_VER_MAJOR 24
2374 #define M_FW_HDR_FW_VER_MAJOR 0xff
2375 #define V_FW_HDR_FW_VER_MAJOR(x) \
2376 ((x) << S_FW_HDR_FW_VER_MAJOR)
2377 #define G_FW_HDR_FW_VER_MAJOR(x) \
2378 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2380 #define S_FW_HDR_FW_VER_MINOR 16
2381 #define M_FW_HDR_FW_VER_MINOR 0xff
2382 #define V_FW_HDR_FW_VER_MINOR(x) \
2383 ((x) << S_FW_HDR_FW_VER_MINOR)
2384 #define G_FW_HDR_FW_VER_MINOR(x) \
2385 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2387 #define S_FW_HDR_FW_VER_MICRO 8
2388 #define M_FW_HDR_FW_VER_MICRO 0xff
2389 #define V_FW_HDR_FW_VER_MICRO(x) \
2390 ((x) << S_FW_HDR_FW_VER_MICRO)
2391 #define G_FW_HDR_FW_VER_MICRO(x) \
2392 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2394 #define S_FW_HDR_FW_VER_BUILD 0
2395 #define M_FW_HDR_FW_VER_BUILD 0xff
2396 #define V_FW_HDR_FW_VER_BUILD(x) \
2397 ((x) << S_FW_HDR_FW_VER_BUILD)
2398 #define G_FW_HDR_FW_VER_BUILD(x) \
2399 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2401 #endif /* _T4FW_INTERFACE_H_ */