1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
60 FW_ETH_TX_PKT_WR = 0x08,
61 FW_ETH_TX_PKTS_WR = 0x09,
62 FW_ETH_TX_PKT_VM_WR = 0x11,
63 FW_ETH_TX_PKTS_VM_WR = 0x12,
65 FW_ETH_TX_PKTS2_WR = 0x78,
69 * Generic work request header flit0
76 /* work request opcode (hi)
79 #define M_FW_WR_OP 0xff
80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
81 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
83 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
85 #define S_FW_WR_ATOMIC 23
86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
88 /* work request immediate data length (hi)
90 #define S_FW_WR_IMMDLEN 0
91 #define M_FW_WR_IMMDLEN 0xff
92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
93 #define G_FW_WR_IMMDLEN(x) \
94 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
96 /* egress queue status update to egress queue status entry (lo)
98 #define S_FW_WR_EQUEQ 30
99 #define M_FW_WR_EQUEQ 0x1
100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
101 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
102 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
104 /* flow context identifier (lo)
106 #define S_FW_WR_FLOWID 8
107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
109 /* length in units of 16-bytes (lo)
111 #define S_FW_WR_LEN16 0
112 #define M_FW_WR_LEN16 0xff
113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
114 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
116 struct fw_eth_tx_pkt_wr {
118 __be32 equiq_to_len16;
122 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
123 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
124 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
125 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
126 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
128 struct fw_eth_tx_pkts_wr {
130 __be32 equiq_to_len16;
137 struct fw_eth_tx_pkt_vm_wr {
139 __be32 equiq_to_len16;
147 struct fw_eth_tx_pkts_vm_wr {
149 __be32 equiq_to_len16;
160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
161 enum fw_filter_wr_cookie {
162 FW_FILTER_WR_SUCCESS,
163 FW_FILTER_WR_FLT_ADDED,
164 FW_FILTER_WR_FLT_DELETED,
165 FW_FILTER_WR_SMT_TBL_FULL,
169 struct fw_filter2_wr {
174 __be32 del_filter_to_l2tix;
177 __u8 frag_to_ovlan_vldm;
179 __be16 rx_chan_rx_rpl_iq;
180 __be32 maci_to_matchtypem;
200 __u8 filter_type_swapmac;
201 __u8 natmode_to_ulp_type;
214 #define S_FW_FILTER_WR_TID 12
215 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
217 #define S_FW_FILTER_WR_RQTYPE 11
218 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
220 #define S_FW_FILTER_WR_NOREPLY 10
221 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
223 #define S_FW_FILTER_WR_IQ 0
224 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
226 #define S_FW_FILTER_WR_DEL_FILTER 31
227 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
228 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
230 #define S_FW_FILTER_WR_RPTTID 25
231 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
233 #define S_FW_FILTER_WR_DROP 24
234 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
236 #define S_FW_FILTER_WR_DIRSTEER 23
237 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
239 #define S_FW_FILTER_WR_MASKHASH 22
240 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
242 #define S_FW_FILTER_WR_DIRSTEERHASH 21
243 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
245 #define S_FW_FILTER_WR_LPBK 20
246 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
248 #define S_FW_FILTER_WR_DMAC 19
249 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
251 #define S_FW_FILTER_WR_INSVLAN 17
252 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
254 #define S_FW_FILTER_WR_RMVLAN 16
255 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
257 #define S_FW_FILTER_WR_HITCNTS 15
258 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
260 #define S_FW_FILTER_WR_TXCHAN 13
261 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
263 #define S_FW_FILTER_WR_PRIO 12
264 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
266 #define S_FW_FILTER_WR_L2TIX 0
267 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
269 #define S_FW_FILTER_WR_FRAG 7
270 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
272 #define S_FW_FILTER_WR_FRAGM 6
273 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
275 #define S_FW_FILTER_WR_IVLAN_VLD 5
276 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
278 #define S_FW_FILTER_WR_OVLAN_VLD 4
279 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
281 #define S_FW_FILTER_WR_IVLAN_VLDM 3
282 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
284 #define S_FW_FILTER_WR_OVLAN_VLDM 2
285 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
287 #define S_FW_FILTER_WR_RX_CHAN 15
288 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
290 #define S_FW_FILTER_WR_RX_RPL_IQ 0
291 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
293 #define S_FW_FILTER_WR_MACI 23
294 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
296 #define S_FW_FILTER_WR_MACIM 14
297 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
299 #define S_FW_FILTER_WR_FCOE 13
300 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
302 #define S_FW_FILTER_WR_FCOEM 12
303 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
305 #define S_FW_FILTER_WR_PORT 9
306 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
308 #define S_FW_FILTER_WR_PORTM 6
309 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
311 #define S_FW_FILTER_WR_MATCHTYPE 3
312 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
314 #define S_FW_FILTER_WR_MATCHTYPEM 0
315 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
317 #define S_FW_FILTER2_WR_SWAPMAC 0
318 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
320 #define S_FW_FILTER2_WR_NATMODE 5
321 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
323 #define S_FW_FILTER2_WR_ULP_TYPE 0
324 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
326 /******************************************************************************
328 *********************/
331 * The maximum length of time, in miliseconds, that we expect any firmware
332 * command to take to execute and return a reply to the host. The RESET
333 * and INITIALIZE commands can take a fair amount of time to execute but
334 * most execute in far less time than this maximum. This constant is used
335 * by host software to determine how long to wait for a firmware command
336 * reply before declaring the firmware as dead/unreachable ...
338 #define FW_CMD_MAX_TIMEOUT 10000
341 * If a host driver does a HELLO and discovers that there's already a MASTER
342 * selected, we may have to wait for that MASTER to finish issuing RESET,
343 * configuration and INITIALIZE commands. Also, there's a possibility that
344 * our own HELLO may get lost if it happens right as the MASTER is issuign a
345 * RESET command, so we need to be willing to make a few retries of our HELLO.
347 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
348 #define FW_CMD_HELLO_RETRIES 3
350 enum fw_cmd_opcodes {
355 FW_INITIALIZE_CMD = 0x06,
356 FW_CAPS_CONFIG_CMD = 0x07,
357 FW_PARAMS_CMD = 0x08,
360 FW_EQ_ETH_CMD = 0x12,
361 FW_EQ_CTRL_CMD = 0x13,
363 FW_VI_MAC_CMD = 0x15,
364 FW_VI_RXMODE_CMD = 0x16,
365 FW_VI_ENABLE_CMD = 0x17,
366 FW_VI_STATS_CMD = 0x1a,
368 FW_RSS_IND_TBL_CMD = 0x20,
369 FW_RSS_GLB_CONFIG_CMD = 0x22,
370 FW_RSS_VI_CONFIG_CMD = 0x23,
376 FW_CMD_CAP_PORT = 0x04,
380 * Generic command header flit0
387 #define S_FW_CMD_OP 24
388 #define M_FW_CMD_OP 0xff
389 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
390 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
392 #define S_FW_CMD_REQUEST 23
393 #define M_FW_CMD_REQUEST 0x1
394 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
395 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
396 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
398 #define S_FW_CMD_READ 22
399 #define M_FW_CMD_READ 0x1
400 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
401 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
402 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
404 #define S_FW_CMD_WRITE 21
405 #define M_FW_CMD_WRITE 0x1
406 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
407 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
408 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
410 #define S_FW_CMD_EXEC 20
411 #define M_FW_CMD_EXEC 0x1
412 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
413 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
414 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
416 #define S_FW_CMD_RETVAL 8
417 #define M_FW_CMD_RETVAL 0xff
418 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
419 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
421 #define S_FW_CMD_LEN16 0
422 #define M_FW_CMD_LEN16 0xff
423 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
424 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
426 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
430 enum fw_ldst_addrspc {
431 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
435 __be32 op_to_addrspace;
436 __be32 cycles_to_len16;
438 struct fw_ldst_addrval {
442 struct fw_ldst_idctxt {
444 __be32 msg_ctxtflush;
454 struct fw_ldst_mdio {
470 struct fw_ldst_func {
478 struct fw_ldst_pcie {
488 struct fw_ldst_i2c_deprecated {
512 #define S_FW_LDST_CMD_ADDRSPACE 0
513 #define M_FW_LDST_CMD_ADDRSPACE 0xff
514 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
516 struct fw_reset_cmd {
523 #define S_FW_RESET_CMD_HALT 31
524 #define M_FW_RESET_CMD_HALT 0x1
525 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
526 #define G_FW_RESET_CMD_HALT(x) \
527 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
528 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
531 FW_HELLO_CMD_STAGE_OS = 0,
534 struct fw_hello_cmd {
537 __be32 err_to_clearinit;
541 #define S_FW_HELLO_CMD_ERR 31
542 #define M_FW_HELLO_CMD_ERR 0x1
543 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
544 #define G_FW_HELLO_CMD_ERR(x) \
545 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
546 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
548 #define S_FW_HELLO_CMD_INIT 30
549 #define M_FW_HELLO_CMD_INIT 0x1
550 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
551 #define G_FW_HELLO_CMD_INIT(x) \
552 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
553 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
555 #define S_FW_HELLO_CMD_MASTERDIS 29
556 #define M_FW_HELLO_CMD_MASTERDIS 0x1
557 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
558 #define G_FW_HELLO_CMD_MASTERDIS(x) \
559 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
560 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
562 #define S_FW_HELLO_CMD_MASTERFORCE 28
563 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
564 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
565 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
566 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
567 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
569 #define S_FW_HELLO_CMD_MBMASTER 24
570 #define M_FW_HELLO_CMD_MBMASTER 0xf
571 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
572 #define G_FW_HELLO_CMD_MBMASTER(x) \
573 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
575 #define S_FW_HELLO_CMD_MBASYNCNOT 20
576 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
577 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
578 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
579 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
581 #define S_FW_HELLO_CMD_STAGE 17
582 #define M_FW_HELLO_CMD_STAGE 0x7
583 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
584 #define G_FW_HELLO_CMD_STAGE(x) \
585 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
587 #define S_FW_HELLO_CMD_CLEARINIT 16
588 #define M_FW_HELLO_CMD_CLEARINIT 0x1
589 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
590 #define G_FW_HELLO_CMD_CLEARINIT(x) \
591 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
592 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
600 struct fw_initialize_cmd {
606 enum fw_caps_config_nic {
607 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
608 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
612 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
615 struct fw_caps_config_cmd {
617 __be32 cfvalid_to_len16;
635 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
636 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
637 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
638 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
639 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
640 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
642 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
643 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
644 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
645 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
646 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
647 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
648 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
650 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
651 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
652 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
653 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
654 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
655 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
656 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
659 * params command mnemonics
661 enum fw_params_mnem {
662 FW_PARAMS_MNEM_DEV = 1, /* device params */
663 FW_PARAMS_MNEM_PFVF = 2, /* function params */
664 FW_PARAMS_MNEM_REG = 3, /* limited register access */
665 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
671 enum fw_params_param_dev {
672 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
673 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
674 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
675 * allocated by the device's
678 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
679 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
680 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
681 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
682 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
686 * physical and virtual function parameters
688 enum fw_params_param_pfvf {
689 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
690 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
691 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
692 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
693 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
694 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
695 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
696 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
697 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
701 * dma queue parameters
703 enum fw_params_param_dmaq {
704 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
705 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
708 #define S_FW_PARAMS_MNEM 24
709 #define M_FW_PARAMS_MNEM 0xff
710 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
711 #define G_FW_PARAMS_MNEM(x) \
712 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
714 #define S_FW_PARAMS_PARAM_X 16
715 #define M_FW_PARAMS_PARAM_X 0xff
716 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
717 #define G_FW_PARAMS_PARAM_X(x) \
718 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
720 #define S_FW_PARAMS_PARAM_Y 8
721 #define M_FW_PARAMS_PARAM_Y 0xff
722 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
723 #define G_FW_PARAMS_PARAM_Y(x) \
724 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
726 #define S_FW_PARAMS_PARAM_Z 0
727 #define M_FW_PARAMS_PARAM_Z 0xff
728 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
729 #define G_FW_PARAMS_PARAM_Z(x) \
730 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
732 #define S_FW_PARAMS_PARAM_YZ 0
733 #define M_FW_PARAMS_PARAM_YZ 0xffff
734 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
735 #define G_FW_PARAMS_PARAM_YZ(x) \
736 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
738 #define S_FW_PARAMS_PARAM_XYZ 0
739 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
740 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
742 struct fw_params_cmd {
745 struct fw_params_param {
751 #define S_FW_PARAMS_CMD_PFN 8
752 #define M_FW_PARAMS_CMD_PFN 0x7
753 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
754 #define G_FW_PARAMS_CMD_PFN(x) \
755 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
757 #define S_FW_PARAMS_CMD_VFN 0
758 #define M_FW_PARAMS_CMD_VFN 0xff
759 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
760 #define G_FW_PARAMS_CMD_VFN(x) \
761 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
768 __be32 tc_to_nexactf;
769 __be32 r_caps_to_nethctrl;
775 #define S_FW_PFVF_CMD_PFN 8
776 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
778 #define S_FW_PFVF_CMD_VFN 0
779 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
781 #define S_FW_PFVF_CMD_NIQFLINT 20
782 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
783 #define G_FW_PFVF_CMD_NIQFLINT(x) \
784 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
786 #define S_FW_PFVF_CMD_NIQ 0
787 #define M_FW_PFVF_CMD_NIQ 0xfffff
788 #define G_FW_PFVF_CMD_NIQ(x) \
789 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
791 #define S_FW_PFVF_CMD_PMASK 20
792 #define M_FW_PFVF_CMD_PMASK 0xf
793 #define G_FW_PFVF_CMD_PMASK(x) \
794 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
796 #define S_FW_PFVF_CMD_NEQ 0
797 #define M_FW_PFVF_CMD_NEQ 0xfffff
798 #define G_FW_PFVF_CMD_NEQ(x) \
799 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
801 #define S_FW_PFVF_CMD_TC 24
802 #define M_FW_PFVF_CMD_TC 0xff
803 #define G_FW_PFVF_CMD_TC(x) \
804 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
806 #define S_FW_PFVF_CMD_NVI 16
807 #define M_FW_PFVF_CMD_NVI 0xff
808 #define G_FW_PFVF_CMD_NVI(x) \
809 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
811 #define S_FW_PFVF_CMD_NEXACTF 0
812 #define M_FW_PFVF_CMD_NEXACTF 0xffff
813 #define G_FW_PFVF_CMD_NEXACTF(x) \
814 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
816 #define S_FW_PFVF_CMD_R_CAPS 24
817 #define M_FW_PFVF_CMD_R_CAPS 0xff
818 #define G_FW_PFVF_CMD_R_CAPS(x) \
819 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
821 #define S_FW_PFVF_CMD_WX_CAPS 16
822 #define M_FW_PFVF_CMD_WX_CAPS 0xff
823 #define G_FW_PFVF_CMD_WX_CAPS(x) \
824 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
826 #define S_FW_PFVF_CMD_NETHCTRL 0
827 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
828 #define G_FW_PFVF_CMD_NETHCTRL(x) \
829 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
832 * ingress queue type; the first 1K ingress queues can have associated 0,
833 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
837 FW_IQ_TYPE_FL_INT_CAP,
841 FW_IQ_IQTYPE_NIC = 1,
847 __be32 alloc_to_len16;
852 __be32 type_to_iqandstindex;
853 __be16 iqdroprss_to_iqesize;
856 __be32 iqns_to_fl0congen;
857 __be16 fl0dcaen_to_fl0cidxfthresh;
860 __be32 fl1cngchmap_to_fl1congen;
861 __be16 fl1dcaen_to_fl1cidxfthresh;
866 #define S_FW_IQ_CMD_PFN 8
867 #define M_FW_IQ_CMD_PFN 0x7
868 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
869 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
871 #define S_FW_IQ_CMD_VFN 0
872 #define M_FW_IQ_CMD_VFN 0xff
873 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
874 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
876 #define S_FW_IQ_CMD_ALLOC 31
877 #define M_FW_IQ_CMD_ALLOC 0x1
878 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
879 #define G_FW_IQ_CMD_ALLOC(x) \
880 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
881 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
883 #define S_FW_IQ_CMD_FREE 30
884 #define M_FW_IQ_CMD_FREE 0x1
885 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
886 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
887 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
889 #define S_FW_IQ_CMD_IQSTART 28
890 #define M_FW_IQ_CMD_IQSTART 0x1
891 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
892 #define G_FW_IQ_CMD_IQSTART(x) \
893 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
894 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
896 #define S_FW_IQ_CMD_IQSTOP 27
897 #define M_FW_IQ_CMD_IQSTOP 0x1
898 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
899 #define G_FW_IQ_CMD_IQSTOP(x) \
900 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
901 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
903 #define S_FW_IQ_CMD_TYPE 29
904 #define M_FW_IQ_CMD_TYPE 0x7
905 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
906 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
908 #define S_FW_IQ_CMD_IQASYNCH 28
909 #define M_FW_IQ_CMD_IQASYNCH 0x1
910 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
911 #define G_FW_IQ_CMD_IQASYNCH(x) \
912 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
913 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
915 #define S_FW_IQ_CMD_VIID 16
916 #define M_FW_IQ_CMD_VIID 0xfff
917 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
918 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
920 #define S_FW_IQ_CMD_IQANDST 15
921 #define M_FW_IQ_CMD_IQANDST 0x1
922 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
923 #define G_FW_IQ_CMD_IQANDST(x) \
924 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
925 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
927 #define S_FW_IQ_CMD_IQANUD 12
928 #define M_FW_IQ_CMD_IQANUD 0x3
929 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
930 #define G_FW_IQ_CMD_IQANUD(x) \
931 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
933 #define S_FW_IQ_CMD_IQANDSTINDEX 0
934 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
935 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
936 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
937 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
939 #define S_FW_IQ_CMD_IQGTSMODE 14
940 #define M_FW_IQ_CMD_IQGTSMODE 0x1
941 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
942 #define G_FW_IQ_CMD_IQGTSMODE(x) \
943 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
944 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
946 #define S_FW_IQ_CMD_IQPCIECH 12
947 #define M_FW_IQ_CMD_IQPCIECH 0x3
948 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
949 #define G_FW_IQ_CMD_IQPCIECH(x) \
950 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
952 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
953 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
954 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
955 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
956 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
958 #define S_FW_IQ_CMD_IQESIZE 0
959 #define M_FW_IQ_CMD_IQESIZE 0x3
960 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
961 #define G_FW_IQ_CMD_IQESIZE(x) \
962 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
964 #define S_FW_IQ_CMD_IQRO 30
965 #define M_FW_IQ_CMD_IQRO 0x1
966 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
967 #define G_FW_IQ_CMD_IQRO(x) \
968 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
969 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
971 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
972 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
973 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
974 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
975 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
976 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
978 #define S_FW_IQ_CMD_IQTYPE 24
979 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
981 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
982 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
983 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
984 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
985 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
987 #define S_FW_IQ_CMD_FL0DATARO 12
988 #define M_FW_IQ_CMD_FL0DATARO 0x1
989 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
990 #define G_FW_IQ_CMD_FL0DATARO(x) \
991 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
992 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
994 #define S_FW_IQ_CMD_FL0CONGCIF 11
995 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
996 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
997 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
998 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
999 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
1001 #define S_FW_IQ_CMD_FL0FETCHRO 6
1002 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
1003 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
1004 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
1005 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
1006 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
1008 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
1009 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
1010 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
1011 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
1012 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
1014 #define S_FW_IQ_CMD_FL0PADEN 2
1015 #define M_FW_IQ_CMD_FL0PADEN 0x1
1016 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
1017 #define G_FW_IQ_CMD_FL0PADEN(x) \
1018 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
1019 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
1021 #define S_FW_IQ_CMD_FL0PACKEN 1
1022 #define M_FW_IQ_CMD_FL0PACKEN 0x1
1023 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
1024 #define G_FW_IQ_CMD_FL0PACKEN(x) \
1025 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
1026 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
1028 #define S_FW_IQ_CMD_FL0CONGEN 0
1029 #define M_FW_IQ_CMD_FL0CONGEN 0x1
1030 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
1031 #define G_FW_IQ_CMD_FL0CONGEN(x) \
1032 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
1033 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
1035 #define S_FW_IQ_CMD_FL0FBMIN 7
1036 #define M_FW_IQ_CMD_FL0FBMIN 0x7
1037 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
1038 #define G_FW_IQ_CMD_FL0FBMIN(x) \
1039 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
1041 #define S_FW_IQ_CMD_FL0FBMAX 4
1042 #define M_FW_IQ_CMD_FL0FBMAX 0x7
1043 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
1044 #define G_FW_IQ_CMD_FL0FBMAX(x) \
1045 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
1047 struct fw_eq_eth_cmd {
1049 __be32 alloc_to_len16;
1051 __be32 physeqid_pkd;
1052 __be32 fetchszm_to_iqid;
1053 __be32 dcaen_to_eqsize;
1055 __be32 autoequiqe_to_viid;
1060 #define S_FW_EQ_ETH_CMD_PFN 8
1061 #define M_FW_EQ_ETH_CMD_PFN 0x7
1062 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
1063 #define G_FW_EQ_ETH_CMD_PFN(x) \
1064 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
1066 #define S_FW_EQ_ETH_CMD_VFN 0
1067 #define M_FW_EQ_ETH_CMD_VFN 0xff
1068 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
1069 #define G_FW_EQ_ETH_CMD_VFN(x) \
1070 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
1072 #define S_FW_EQ_ETH_CMD_ALLOC 31
1073 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
1074 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
1075 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
1076 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
1077 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
1079 #define S_FW_EQ_ETH_CMD_FREE 30
1080 #define M_FW_EQ_ETH_CMD_FREE 0x1
1081 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
1082 #define G_FW_EQ_ETH_CMD_FREE(x) \
1083 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
1084 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
1086 #define S_FW_EQ_ETH_CMD_EQSTART 28
1087 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
1088 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
1089 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
1090 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
1091 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
1093 #define S_FW_EQ_ETH_CMD_EQID 0
1094 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
1095 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
1096 #define G_FW_EQ_ETH_CMD_EQID(x) \
1097 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
1099 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
1100 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
1101 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
1102 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
1104 #define S_FW_EQ_ETH_CMD_FETCHRO 22
1105 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
1106 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
1107 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
1108 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
1109 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
1111 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
1112 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
1113 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
1114 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
1115 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
1117 #define S_FW_EQ_ETH_CMD_PCIECHN 16
1118 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
1119 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
1120 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
1121 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
1123 #define S_FW_EQ_ETH_CMD_IQID 0
1124 #define M_FW_EQ_ETH_CMD_IQID 0xffff
1125 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
1126 #define G_FW_EQ_ETH_CMD_IQID(x) \
1127 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
1129 #define S_FW_EQ_ETH_CMD_FBMIN 23
1130 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
1131 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
1132 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
1133 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
1135 #define S_FW_EQ_ETH_CMD_FBMAX 20
1136 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
1137 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
1138 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
1139 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
1141 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
1142 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
1143 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
1144 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
1145 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
1147 #define S_FW_EQ_ETH_CMD_EQSIZE 0
1148 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
1149 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
1150 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
1151 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
1153 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
1154 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
1155 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
1156 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
1157 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
1158 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
1160 #define S_FW_EQ_ETH_CMD_VIID 16
1161 #define M_FW_EQ_ETH_CMD_VIID 0xfff
1162 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
1163 #define G_FW_EQ_ETH_CMD_VIID(x) \
1164 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
1166 struct fw_eq_ctrl_cmd {
1168 __be32 alloc_to_len16;
1169 __be32 cmpliqid_eqid;
1170 __be32 physeqid_pkd;
1171 __be32 fetchszm_to_iqid;
1172 __be32 dcaen_to_eqsize;
1176 #define S_FW_EQ_CTRL_CMD_PFN 8
1177 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
1179 #define S_FW_EQ_CTRL_CMD_VFN 0
1180 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
1182 #define S_FW_EQ_CTRL_CMD_ALLOC 31
1183 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
1184 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
1186 #define S_FW_EQ_CTRL_CMD_FREE 30
1187 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
1188 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
1190 #define S_FW_EQ_CTRL_CMD_EQSTART 28
1191 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
1192 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
1194 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
1195 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
1197 #define S_FW_EQ_CTRL_CMD_EQID 0
1198 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
1199 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
1200 #define G_FW_EQ_CTRL_CMD_EQID(x) \
1201 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1203 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1204 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1205 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1206 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1207 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1209 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1210 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1211 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1213 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1214 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1215 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1217 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1218 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1220 #define S_FW_EQ_CTRL_CMD_IQID 0
1221 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1223 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1224 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1226 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1227 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1229 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1230 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1232 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1233 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1239 /* Macros for VIID parsing:
1240 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1243 #define S_FW_VIID_VIVLD 7
1244 #define M_FW_VIID_VIVLD 0x1
1245 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
1247 #define S_FW_VIID_VIN 0
1248 #define M_FW_VIID_VIN 0x7F
1249 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
1253 __be32 alloc_to_len16;
1254 __be16 type_to_viid;
1259 __be16 norss_rsssize;
1269 #define S_FW_VI_CMD_PFN 8
1270 #define M_FW_VI_CMD_PFN 0x7
1271 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1272 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1274 #define S_FW_VI_CMD_VFN 0
1275 #define M_FW_VI_CMD_VFN 0xff
1276 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1277 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1279 #define S_FW_VI_CMD_ALLOC 31
1280 #define M_FW_VI_CMD_ALLOC 0x1
1281 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1282 #define G_FW_VI_CMD_ALLOC(x) \
1283 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1284 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1286 #define S_FW_VI_CMD_FREE 30
1287 #define M_FW_VI_CMD_FREE 0x1
1288 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1289 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1290 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1292 #define S_FW_VI_CMD_VFVLD 24
1293 #define M_FW_VI_CMD_VFVLD 0x1
1294 #define G_FW_VI_CMD_VFVLD(x) \
1295 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
1297 #define S_FW_VI_CMD_VIN 16
1298 #define M_FW_VI_CMD_VIN 0xff
1299 #define G_FW_VI_CMD_VIN(x) \
1300 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
1302 #define S_FW_VI_CMD_TYPE 15
1303 #define M_FW_VI_CMD_TYPE 0x1
1304 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1305 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1306 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1308 #define S_FW_VI_CMD_FUNC 12
1309 #define M_FW_VI_CMD_FUNC 0x7
1310 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1311 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1313 #define S_FW_VI_CMD_VIID 0
1314 #define M_FW_VI_CMD_VIID 0xfff
1315 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1316 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1318 #define S_FW_VI_CMD_PORTID 4
1319 #define M_FW_VI_CMD_PORTID 0xf
1320 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1321 #define G_FW_VI_CMD_PORTID(x) \
1322 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1324 #define S_FW_VI_CMD_RSSSIZE 0
1325 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1326 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1327 #define G_FW_VI_CMD_RSSSIZE(x) \
1328 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1330 /* Special VI_MAC command index ids */
1331 #define FW_VI_MAC_ADD_MAC 0x3FF
1332 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1333 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
1335 enum fw_vi_mac_smac {
1336 FW_VI_MAC_MPS_TCAM_ENTRY,
1337 FW_VI_MAC_SMT_AND_MPSTCAM
1340 enum fw_vi_mac_entry_types {
1341 FW_VI_MAC_TYPE_RAW = 0x2,
1344 struct fw_vi_mac_cmd {
1346 __be32 freemacs_to_len16;
1348 struct fw_vi_mac_exact {
1349 __be16 valid_to_idx;
1352 struct fw_vi_mac_hash {
1355 struct fw_vi_mac_raw {
1365 #define S_FW_VI_MAC_CMD_VIID 0
1366 #define M_FW_VI_MAC_CMD_VIID 0xfff
1367 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1368 #define G_FW_VI_MAC_CMD_VIID(x) \
1369 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1371 #define S_FW_VI_MAC_CMD_FREEMACS 31
1372 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
1374 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
1375 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
1377 #define S_FW_VI_MAC_CMD_VALID 15
1378 #define M_FW_VI_MAC_CMD_VALID 0x1
1379 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1380 #define G_FW_VI_MAC_CMD_VALID(x) \
1381 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1382 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1384 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1385 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1386 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1387 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1388 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1390 #define S_FW_VI_MAC_CMD_IDX 0
1391 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1392 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1393 #define G_FW_VI_MAC_CMD_IDX(x) \
1394 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1396 #define S_FW_VI_MAC_CMD_RAW_IDX 16
1397 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
1398 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
1399 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
1400 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
1402 struct fw_vi_rxmode_cmd {
1404 __be32 retval_len16;
1405 __be32 mtu_to_vlanexen;
1409 #define S_FW_VI_RXMODE_CMD_VIID 0
1410 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1411 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1412 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1413 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1415 #define S_FW_VI_RXMODE_CMD_MTU 16
1416 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1417 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1418 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1419 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1421 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1422 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1423 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1424 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1425 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1427 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1428 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1429 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1430 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1431 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1432 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1434 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1435 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1436 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1437 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1438 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1439 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1440 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1442 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1443 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1444 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1445 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1446 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1448 struct fw_vi_enable_cmd {
1450 __be32 ien_to_len16;
1456 #define S_FW_VI_ENABLE_CMD_VIID 0
1457 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1458 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1459 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1460 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1462 #define S_FW_VI_ENABLE_CMD_IEN 31
1463 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1464 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1465 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1466 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1467 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1469 #define S_FW_VI_ENABLE_CMD_EEN 30
1470 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1471 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1472 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1473 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1474 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1476 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1477 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1478 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1479 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1480 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1481 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1483 /* VI VF stats offset definitions */
1484 #define VI_VF_NUM_STATS 16
1486 /* VI PF stats offset definitions */
1487 #define VI_PF_NUM_STATS 17
1488 enum fw_vi_stats_pf_index {
1489 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1490 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1491 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1492 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1493 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1494 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1495 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1496 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1497 FW_VI_PF_STAT_RX_BYTES_IX,
1498 FW_VI_PF_STAT_RX_FRAMES_IX,
1499 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1500 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1501 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1502 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1503 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1504 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1505 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1508 struct fw_vi_stats_cmd {
1510 __be32 retval_len16;
1512 struct fw_vi_stats_ctl {
1523 struct fw_vi_stats_pf {
1524 __be64 tx_bcast_bytes;
1525 __be64 tx_bcast_frames;
1526 __be64 tx_mcast_bytes;
1527 __be64 tx_mcast_frames;
1528 __be64 tx_ucast_bytes;
1529 __be64 tx_ucast_frames;
1530 __be64 tx_offload_bytes;
1531 __be64 tx_offload_frames;
1533 __be64 rx_pf_frames;
1534 __be64 rx_bcast_bytes;
1535 __be64 rx_bcast_frames;
1536 __be64 rx_mcast_bytes;
1537 __be64 rx_mcast_frames;
1538 __be64 rx_ucast_bytes;
1539 __be64 rx_ucast_frames;
1540 __be64 rx_err_frames;
1542 struct fw_vi_stats_vf {
1543 __be64 tx_bcast_bytes;
1544 __be64 tx_bcast_frames;
1545 __be64 tx_mcast_bytes;
1546 __be64 tx_mcast_frames;
1547 __be64 tx_ucast_bytes;
1548 __be64 tx_ucast_frames;
1549 __be64 tx_drop_frames;
1550 __be64 tx_offload_bytes;
1551 __be64 tx_offload_frames;
1552 __be64 rx_bcast_bytes;
1553 __be64 rx_bcast_frames;
1554 __be64 rx_mcast_bytes;
1555 __be64 rx_mcast_frames;
1556 __be64 rx_ucast_bytes;
1557 __be64 rx_ucast_frames;
1558 __be64 rx_err_frames;
1563 #define S_FW_VI_STATS_CMD_VIID 0
1564 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1566 #define S_FW_VI_STATS_CMD_NSTATS 12
1567 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1569 #define S_FW_VI_STATS_CMD_IX 0
1570 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1572 /* old 16-bit port capabilities bitmap */
1574 FW_PORT_CAP_SPEED_100M = 0x0001,
1575 FW_PORT_CAP_SPEED_1G = 0x0002,
1576 FW_PORT_CAP_SPEED_25G = 0x0004,
1577 FW_PORT_CAP_SPEED_10G = 0x0008,
1578 FW_PORT_CAP_SPEED_40G = 0x0010,
1579 FW_PORT_CAP_SPEED_100G = 0x0020,
1580 FW_PORT_CAP_FC_RX = 0x0040,
1581 FW_PORT_CAP_FC_TX = 0x0080,
1582 FW_PORT_CAP_ANEG = 0x0100,
1583 FW_PORT_CAP_MDIX = 0x0200,
1584 FW_PORT_CAP_MDIAUTO = 0x0400,
1585 FW_PORT_CAP_FEC_RS = 0x0800,
1586 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1587 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1588 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1589 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1592 #define S_FW_PORT_CAP_SPEED 0
1593 #define M_FW_PORT_CAP_SPEED 0x3f
1594 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1595 #define G_FW_PORT_CAP_SPEED(x) \
1596 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1599 FW_PORT_CAP_MDI_AUTO,
1602 #define S_FW_PORT_CAP_MDI 9
1603 #define M_FW_PORT_CAP_MDI 3
1604 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1605 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1607 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1608 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1609 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1610 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1611 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1612 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1613 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1614 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1615 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1616 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1617 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1618 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1619 #define FW_PORT_CAP32_ANEG 0x00100000UL
1620 #define FW_PORT_CAP32_MDIX 0x00200000UL
1621 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1622 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1623 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1625 #define S_FW_PORT_CAP32_SPEED 0
1626 #define M_FW_PORT_CAP32_SPEED 0xfff
1627 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1628 #define G_FW_PORT_CAP32_SPEED(x) \
1629 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1631 enum fw_port_mdi32 {
1632 FW_PORT_CAP32_MDI_AUTO,
1635 #define S_FW_PORT_CAP32_MDI 21
1636 #define M_FW_PORT_CAP32_MDI 3
1637 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1638 #define G_FW_PORT_CAP32_MDI(x) \
1639 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1641 enum fw_port_action {
1642 FW_PORT_ACTION_L1_CFG = 0x0001,
1643 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1644 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1645 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1648 struct fw_port_cmd {
1649 __be32 op_to_portid;
1650 __be32 action_to_len16;
1652 struct fw_port_l1cfg {
1656 struct fw_port_l2cfg {
1658 __u8 ovlan3_to_ivlan0;
1660 __be16 txipg_force_pinfo;
1671 struct fw_port_info {
1672 __be32 lstatus_to_modtype;
1683 struct fw_port_diags {
1689 struct fw_port_dcb_pgid {
1696 struct fw_port_dcb_pgrate {
1700 __u8 num_tcs_supported;
1704 struct fw_port_dcb_priorate {
1708 __u8 strict_priorate[8];
1710 struct fw_port_dcb_pfc {
1717 struct fw_port_app_priority {
1726 struct fw_port_dcb_control {
1729 __be16 dcb_version_to_app_state;
1734 struct fw_port_l1cfg32 {
1738 struct fw_port_info32 {
1739 __be32 lstatus32_to_cbllen32;
1740 __be32 auxlinfo32_mtu32;
1749 #define S_FW_PORT_CMD_PORTID 0
1750 #define M_FW_PORT_CMD_PORTID 0xf
1751 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1752 #define G_FW_PORT_CMD_PORTID(x) \
1753 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1755 #define S_FW_PORT_CMD_ACTION 16
1756 #define M_FW_PORT_CMD_ACTION 0xffff
1757 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1758 #define G_FW_PORT_CMD_ACTION(x) \
1759 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1761 #define S_FW_PORT_CMD_LSTATUS 31
1762 #define M_FW_PORT_CMD_LSTATUS 0x1
1763 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1764 #define G_FW_PORT_CMD_LSTATUS(x) \
1765 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1766 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1768 #define S_FW_PORT_CMD_LSPEED 24
1769 #define M_FW_PORT_CMD_LSPEED 0x3f
1770 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1771 #define G_FW_PORT_CMD_LSPEED(x) \
1772 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1774 #define S_FW_PORT_CMD_TXPAUSE 23
1775 #define M_FW_PORT_CMD_TXPAUSE 0x1
1776 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1777 #define G_FW_PORT_CMD_TXPAUSE(x) \
1778 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1779 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1781 #define S_FW_PORT_CMD_RXPAUSE 22
1782 #define M_FW_PORT_CMD_RXPAUSE 0x1
1783 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1784 #define G_FW_PORT_CMD_RXPAUSE(x) \
1785 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1786 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1788 #define S_FW_PORT_CMD_MDIOCAP 21
1789 #define M_FW_PORT_CMD_MDIOCAP 0x1
1790 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1791 #define G_FW_PORT_CMD_MDIOCAP(x) \
1792 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1793 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1795 #define S_FW_PORT_CMD_MDIOADDR 16
1796 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1797 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1798 #define G_FW_PORT_CMD_MDIOADDR(x) \
1799 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1801 #define S_FW_PORT_CMD_PTYPE 8
1802 #define M_FW_PORT_CMD_PTYPE 0x1f
1803 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1804 #define G_FW_PORT_CMD_PTYPE(x) \
1805 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1807 #define S_FW_PORT_CMD_LINKDNRC 5
1808 #define M_FW_PORT_CMD_LINKDNRC 0x7
1809 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1810 #define G_FW_PORT_CMD_LINKDNRC(x) \
1811 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1813 #define S_FW_PORT_CMD_MODTYPE 0
1814 #define M_FW_PORT_CMD_MODTYPE 0x1f
1815 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1816 #define G_FW_PORT_CMD_MODTYPE(x) \
1817 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1819 #define S_FW_PORT_CMD_LSTATUS32 31
1820 #define M_FW_PORT_CMD_LSTATUS32 0x1
1821 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1822 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1824 #define S_FW_PORT_CMD_LINKDNRC32 28
1825 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1826 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1827 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1829 #define S_FW_PORT_CMD_MDIOCAP32 26
1830 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1831 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1832 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1834 #define S_FW_PORT_CMD_MDIOADDR32 21
1835 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1836 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1837 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1839 #define S_FW_PORT_CMD_PORTTYPE32 13
1840 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1841 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1842 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1844 #define S_FW_PORT_CMD_MODTYPE32 8
1845 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1846 #define G_FW_PORT_CMD_MODTYPE32(x) \
1847 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1850 * These are configured into the VPD and hence tools that generate
1851 * VPD may use this enumeration.
1852 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1855 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1856 * with any new Firmware Port Technology Types!
1859 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1860 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1861 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1862 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1863 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1864 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1865 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1866 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1867 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1868 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1869 FW_PORT_TYPE_BP_AP = 10,
1870 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1871 FW_PORT_TYPE_BP4_AP = 11,
1872 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1873 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1874 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1875 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1876 FW_PORT_TYPE_BP40_BA = 15,
1877 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1878 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1879 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1880 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1881 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1882 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1883 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1884 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1887 /* These are read from module's EEPROM and determined once the
1888 * module is inserted.
1890 enum fw_port_module_type {
1891 FW_PORT_MOD_TYPE_NA = 0x0,
1892 FW_PORT_MOD_TYPE_LR = 0x1,
1893 FW_PORT_MOD_TYPE_SR = 0x2,
1894 FW_PORT_MOD_TYPE_ER = 0x3,
1895 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1896 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1897 FW_PORT_MOD_TYPE_LRM = 0x6,
1898 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1899 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1900 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1901 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1904 /* used by FW and tools may use this to generate VPD */
1905 enum fw_port_mod_sub_type {
1906 FW_PORT_MOD_SUB_TYPE_NA,
1907 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1908 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1909 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1910 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1911 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1912 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1913 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1914 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1917 * The following will never been in the VPD. They are TWINAX cable
1918 * lengths decoded from SFP+ module i2c PROMs. These should almost
1919 * certainly go somewhere else ...
1921 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1922 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1923 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1924 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1927 /* link down reason codes (3b) */
1928 enum fw_port_link_dn_rc {
1929 FW_PORT_LINK_DN_RC_NONE,
1930 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1931 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1932 FW_PORT_LINK_DN_RESERVED3,
1933 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1934 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1935 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1936 FW_PORT_LINK_DN_RESERVED7
1940 #define FW_NUM_PORT_STATS 50
1941 #define FW_NUM_PORT_TX_STATS 23
1942 #define FW_NUM_PORT_RX_STATS 27
1944 enum fw_port_stats_tx_index {
1945 FW_STAT_TX_PORT_BYTES_IX,
1946 FW_STAT_TX_PORT_FRAMES_IX,
1947 FW_STAT_TX_PORT_BCAST_IX,
1948 FW_STAT_TX_PORT_MCAST_IX,
1949 FW_STAT_TX_PORT_UCAST_IX,
1950 FW_STAT_TX_PORT_ERROR_IX,
1951 FW_STAT_TX_PORT_64B_IX,
1952 FW_STAT_TX_PORT_65B_127B_IX,
1953 FW_STAT_TX_PORT_128B_255B_IX,
1954 FW_STAT_TX_PORT_256B_511B_IX,
1955 FW_STAT_TX_PORT_512B_1023B_IX,
1956 FW_STAT_TX_PORT_1024B_1518B_IX,
1957 FW_STAT_TX_PORT_1519B_MAX_IX,
1958 FW_STAT_TX_PORT_DROP_IX,
1959 FW_STAT_TX_PORT_PAUSE_IX,
1960 FW_STAT_TX_PORT_PPP0_IX,
1961 FW_STAT_TX_PORT_PPP1_IX,
1962 FW_STAT_TX_PORT_PPP2_IX,
1963 FW_STAT_TX_PORT_PPP3_IX,
1964 FW_STAT_TX_PORT_PPP4_IX,
1965 FW_STAT_TX_PORT_PPP5_IX,
1966 FW_STAT_TX_PORT_PPP6_IX,
1967 FW_STAT_TX_PORT_PPP7_IX
1970 enum fw_port_stat_rx_index {
1971 FW_STAT_RX_PORT_BYTES_IX,
1972 FW_STAT_RX_PORT_FRAMES_IX,
1973 FW_STAT_RX_PORT_BCAST_IX,
1974 FW_STAT_RX_PORT_MCAST_IX,
1975 FW_STAT_RX_PORT_UCAST_IX,
1976 FW_STAT_RX_PORT_MTU_ERROR_IX,
1977 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1978 FW_STAT_RX_PORT_CRC_ERROR_IX,
1979 FW_STAT_RX_PORT_LEN_ERROR_IX,
1980 FW_STAT_RX_PORT_SYM_ERROR_IX,
1981 FW_STAT_RX_PORT_64B_IX,
1982 FW_STAT_RX_PORT_65B_127B_IX,
1983 FW_STAT_RX_PORT_128B_255B_IX,
1984 FW_STAT_RX_PORT_256B_511B_IX,
1985 FW_STAT_RX_PORT_512B_1023B_IX,
1986 FW_STAT_RX_PORT_1024B_1518B_IX,
1987 FW_STAT_RX_PORT_1519B_MAX_IX,
1988 FW_STAT_RX_PORT_PAUSE_IX,
1989 FW_STAT_RX_PORT_PPP0_IX,
1990 FW_STAT_RX_PORT_PPP1_IX,
1991 FW_STAT_RX_PORT_PPP2_IX,
1992 FW_STAT_RX_PORT_PPP3_IX,
1993 FW_STAT_RX_PORT_PPP4_IX,
1994 FW_STAT_RX_PORT_PPP5_IX,
1995 FW_STAT_RX_PORT_PPP6_IX,
1996 FW_STAT_RX_PORT_PPP7_IX,
1997 FW_STAT_RX_PORT_LESS_64B_IX
2000 struct fw_port_stats_cmd {
2001 __be32 op_to_portid;
2002 __be32 retval_len16;
2003 union fw_port_stats {
2004 struct fw_port_stats_ctl {
2016 struct fw_port_stats_all {
2025 __be64 tx_128b_255b;
2026 __be64 tx_256b_511b;
2027 __be64 tx_512b_1023b;
2028 __be64 tx_1024b_1518b;
2029 __be64 tx_1519b_max;
2045 __be64 rx_mtu_error;
2046 __be64 rx_mtu_crc_error;
2047 __be64 rx_crc_error;
2048 __be64 rx_len_error;
2049 __be64 rx_sym_error;
2052 __be64 rx_128b_255b;
2053 __be64 rx_256b_511b;
2054 __be64 rx_512b_1023b;
2055 __be64 rx_1024b_1518b;
2056 __be64 rx_1519b_max;
2073 struct fw_rss_ind_tbl_cmd {
2075 __be32 retval_len16;
2083 __be32 iq12_to_iq14;
2084 __be32 iq15_to_iq17;
2085 __be32 iq18_to_iq20;
2086 __be32 iq21_to_iq23;
2087 __be32 iq24_to_iq26;
2088 __be32 iq27_to_iq29;
2093 #define S_FW_RSS_IND_TBL_CMD_VIID 0
2094 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
2095 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
2096 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
2097 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
2099 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
2100 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
2101 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
2102 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
2103 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
2105 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
2106 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
2107 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
2108 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
2109 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
2111 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
2112 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
2113 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
2114 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
2115 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
2117 struct fw_rss_glb_config_cmd {
2119 __be32 retval_len16;
2120 union fw_rss_glb_config {
2121 struct fw_rss_glb_config_manual {
2127 struct fw_rss_glb_config_basicvirtual {
2128 __be32 mode_keymode;
2129 __be32 synmapen_to_hashtoeplitz;
2136 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
2137 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
2138 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
2139 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
2141 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2143 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
2144 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
2145 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
2146 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
2148 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
2149 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
2150 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
2151 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
2152 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
2154 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
2155 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
2156 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
2157 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
2158 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
2160 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
2161 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
2162 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
2163 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
2164 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
2166 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
2167 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
2168 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
2169 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
2170 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
2172 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
2173 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
2174 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
2175 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
2177 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
2178 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
2179 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
2180 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
2182 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
2183 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
2184 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
2185 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
2186 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
2188 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
2189 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
2190 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
2191 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
2192 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
2194 struct fw_rss_vi_config_cmd {
2196 __be32 retval_len16;
2197 union fw_rss_vi_config {
2198 struct fw_rss_vi_config_manual {
2203 struct fw_rss_vi_config_basicvirtual {
2205 __be32 defaultq_to_udpen;
2212 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
2213 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
2214 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
2215 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
2216 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
2218 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
2219 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
2220 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2221 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2222 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2223 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
2224 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2226 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
2227 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
2228 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2229 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2230 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2231 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
2232 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2233 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
2234 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
2236 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
2237 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
2238 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2239 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2240 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2241 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
2242 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2243 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
2244 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
2246 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
2247 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2248 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2249 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2250 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2251 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2252 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2253 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2254 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2256 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2257 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2258 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2259 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2260 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2261 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2262 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2263 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2264 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2266 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2267 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2268 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2269 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2270 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2271 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2273 struct fw_clip_cmd {
2275 __be32 alloc_to_len16;
2281 #define S_FW_CLIP_CMD_ALLOC 31
2282 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
2283 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
2285 #define S_FW_CLIP_CMD_FREE 30
2286 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
2287 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
2289 /******************************************************************************
2290 * D E B U G C O M M A N D s
2291 ******************************************************/
2293 struct fw_debug_cmd {
2297 struct fw_debug_assert {
2302 __u8 filename_0_7[8];
2303 __u8 filename_8_15[8];
2306 struct fw_debug_prt {
2309 __be32 dprtstrparam0;
2310 __be32 dprtstrparam1;
2311 __be32 dprtstrparam2;
2312 __be32 dprtstrparam3;
2317 #define S_FW_DEBUG_CMD_TYPE 0
2318 #define M_FW_DEBUG_CMD_TYPE 0xff
2319 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2320 #define G_FW_DEBUG_CMD_TYPE(x) \
2321 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2323 /******************************************************************************
2324 * P C I E F W R E G I S T E R
2325 **************************************/
2328 * Register definitions for the PCIE_FW register which the firmware uses
2329 * to retain status across RESETs. This register should be considered
2330 * as a READ-ONLY register for Host Software and only to be used to
2331 * track firmware initialization/error state, etc.
2333 #define S_PCIE_FW_ERR 31
2334 #define M_PCIE_FW_ERR 0x1
2335 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2336 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2337 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2339 #define S_PCIE_FW_INIT 30
2340 #define M_PCIE_FW_INIT 0x1
2341 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2342 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2343 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2345 #define S_PCIE_FW_HALT 29
2346 #define M_PCIE_FW_HALT 0x1
2347 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2348 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2349 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2351 #define S_PCIE_FW_EVAL 24
2352 #define M_PCIE_FW_EVAL 0x7
2353 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2354 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2356 #define S_PCIE_FW_MASTER_VLD 15
2357 #define M_PCIE_FW_MASTER_VLD 0x1
2358 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2359 #define G_PCIE_FW_MASTER_VLD(x) \
2360 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2361 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2363 #define S_PCIE_FW_MASTER 12
2364 #define M_PCIE_FW_MASTER 0x7
2365 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2366 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2368 /******************************************************************************
2369 * B I N A R Y H E A D E R F O R M A T
2370 **********************************************/
2373 * firmware binary header format
2377 __u8 chip; /* terminator chip family */
2378 __be16 len512; /* bin length in units of 512-bytes */
2379 __be32 fw_ver; /* firmware version */
2380 __be32 tp_microcode_ver; /* tcp processor microcode version */
2385 __u8 intfver_iscsipdu;
2387 __u8 intfver_fcoepdu;
2391 __u32 magic; /* runtime or bootstrap fw */
2393 __be32 reserved6[23];
2396 #define S_FW_HDR_FW_VER_MAJOR 24
2397 #define M_FW_HDR_FW_VER_MAJOR 0xff
2398 #define V_FW_HDR_FW_VER_MAJOR(x) \
2399 ((x) << S_FW_HDR_FW_VER_MAJOR)
2400 #define G_FW_HDR_FW_VER_MAJOR(x) \
2401 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2403 #define S_FW_HDR_FW_VER_MINOR 16
2404 #define M_FW_HDR_FW_VER_MINOR 0xff
2405 #define V_FW_HDR_FW_VER_MINOR(x) \
2406 ((x) << S_FW_HDR_FW_VER_MINOR)
2407 #define G_FW_HDR_FW_VER_MINOR(x) \
2408 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2410 #define S_FW_HDR_FW_VER_MICRO 8
2411 #define M_FW_HDR_FW_VER_MICRO 0xff
2412 #define V_FW_HDR_FW_VER_MICRO(x) \
2413 ((x) << S_FW_HDR_FW_VER_MICRO)
2414 #define G_FW_HDR_FW_VER_MICRO(x) \
2415 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2417 #define S_FW_HDR_FW_VER_BUILD 0
2418 #define M_FW_HDR_FW_VER_BUILD 0xff
2419 #define V_FW_HDR_FW_VER_BUILD(x) \
2420 ((x) << S_FW_HDR_FW_VER_BUILD)
2421 #define G_FW_HDR_FW_VER_BUILD(x) \
2422 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2424 #endif /* _T4FW_INTERFACE_H_ */