1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
57 FW_ETH_TX_PKT_WR = 0x08,
58 FW_ETH_TX_PKTS_WR = 0x09,
59 FW_ETH_TX_PKT_VM_WR = 0x11,
60 FW_ETH_TX_PKTS_VM_WR = 0x12,
61 FW_ETH_TX_PKTS2_WR = 0x78,
65 * Generic work request header flit0
72 /* work request opcode (hi)
75 #define M_FW_WR_OP 0xff
76 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
77 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
79 /* work request immediate data length (hi)
81 #define S_FW_WR_IMMDLEN 0
82 #define M_FW_WR_IMMDLEN 0xff
83 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
84 #define G_FW_WR_IMMDLEN(x) \
85 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
87 /* egress queue status update to egress queue status entry (lo)
89 #define S_FW_WR_EQUEQ 30
90 #define M_FW_WR_EQUEQ 0x1
91 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
92 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
93 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
95 /* length in units of 16-bytes (lo)
97 #define S_FW_WR_LEN16 0
98 #define M_FW_WR_LEN16 0xff
99 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
100 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
102 struct fw_eth_tx_pkt_wr {
104 __be32 equiq_to_len16;
108 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
109 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
110 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
111 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
112 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
114 struct fw_eth_tx_pkts_wr {
116 __be32 equiq_to_len16;
123 struct fw_eth_tx_pkt_vm_wr {
125 __be32 equiq_to_len16;
133 struct fw_eth_tx_pkts_vm_wr {
135 __be32 equiq_to_len16;
146 /******************************************************************************
148 *********************/
151 * The maximum length of time, in miliseconds, that we expect any firmware
152 * command to take to execute and return a reply to the host. The RESET
153 * and INITIALIZE commands can take a fair amount of time to execute but
154 * most execute in far less time than this maximum. This constant is used
155 * by host software to determine how long to wait for a firmware command
156 * reply before declaring the firmware as dead/unreachable ...
158 #define FW_CMD_MAX_TIMEOUT 10000
161 * If a host driver does a HELLO and discovers that there's already a MASTER
162 * selected, we may have to wait for that MASTER to finish issuing RESET,
163 * configuration and INITIALIZE commands. Also, there's a possibility that
164 * our own HELLO may get lost if it happens right as the MASTER is issuign a
165 * RESET command, so we need to be willing to make a few retries of our HELLO.
167 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
168 #define FW_CMD_HELLO_RETRIES 3
170 enum fw_cmd_opcodes {
175 FW_INITIALIZE_CMD = 0x06,
176 FW_CAPS_CONFIG_CMD = 0x07,
177 FW_PARAMS_CMD = 0x08,
180 FW_EQ_ETH_CMD = 0x12,
182 FW_VI_MAC_CMD = 0x15,
183 FW_VI_RXMODE_CMD = 0x16,
184 FW_VI_ENABLE_CMD = 0x17,
185 FW_VI_STATS_CMD = 0x1a,
187 FW_RSS_IND_TBL_CMD = 0x20,
188 FW_RSS_GLB_CONFIG_CMD = 0x22,
189 FW_RSS_VI_CONFIG_CMD = 0x23,
194 FW_CMD_CAP_PORT = 0x04,
198 * Generic command header flit0
205 #define S_FW_CMD_OP 24
206 #define M_FW_CMD_OP 0xff
207 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
208 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
210 #define S_FW_CMD_REQUEST 23
211 #define M_FW_CMD_REQUEST 0x1
212 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
213 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
214 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
216 #define S_FW_CMD_READ 22
217 #define M_FW_CMD_READ 0x1
218 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
219 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
220 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
222 #define S_FW_CMD_WRITE 21
223 #define M_FW_CMD_WRITE 0x1
224 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
225 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
226 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
228 #define S_FW_CMD_EXEC 20
229 #define M_FW_CMD_EXEC 0x1
230 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
231 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
232 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
234 #define S_FW_CMD_RETVAL 8
235 #define M_FW_CMD_RETVAL 0xff
236 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
237 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
239 #define S_FW_CMD_LEN16 0
240 #define M_FW_CMD_LEN16 0xff
241 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
242 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
244 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
248 enum fw_ldst_addrspc {
249 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
253 __be32 op_to_addrspace;
254 __be32 cycles_to_len16;
256 struct fw_ldst_addrval {
260 struct fw_ldst_idctxt {
262 __be32 msg_ctxtflush;
272 struct fw_ldst_mdio {
288 struct fw_ldst_func {
296 struct fw_ldst_pcie {
306 struct fw_ldst_i2c_deprecated {
330 #define S_FW_LDST_CMD_ADDRSPACE 0
331 #define M_FW_LDST_CMD_ADDRSPACE 0xff
332 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
334 struct fw_reset_cmd {
341 #define S_FW_RESET_CMD_HALT 31
342 #define M_FW_RESET_CMD_HALT 0x1
343 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
344 #define G_FW_RESET_CMD_HALT(x) \
345 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
346 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
349 FW_HELLO_CMD_STAGE_OS = 0,
352 struct fw_hello_cmd {
355 __be32 err_to_clearinit;
359 #define S_FW_HELLO_CMD_ERR 31
360 #define M_FW_HELLO_CMD_ERR 0x1
361 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
362 #define G_FW_HELLO_CMD_ERR(x) \
363 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
364 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
366 #define S_FW_HELLO_CMD_INIT 30
367 #define M_FW_HELLO_CMD_INIT 0x1
368 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
369 #define G_FW_HELLO_CMD_INIT(x) \
370 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
371 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
373 #define S_FW_HELLO_CMD_MASTERDIS 29
374 #define M_FW_HELLO_CMD_MASTERDIS 0x1
375 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
376 #define G_FW_HELLO_CMD_MASTERDIS(x) \
377 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
378 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
380 #define S_FW_HELLO_CMD_MASTERFORCE 28
381 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
382 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
383 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
384 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
385 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
387 #define S_FW_HELLO_CMD_MBMASTER 24
388 #define M_FW_HELLO_CMD_MBMASTER 0xf
389 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
390 #define G_FW_HELLO_CMD_MBMASTER(x) \
391 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
393 #define S_FW_HELLO_CMD_MBASYNCNOT 20
394 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
395 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
396 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
397 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
399 #define S_FW_HELLO_CMD_STAGE 17
400 #define M_FW_HELLO_CMD_STAGE 0x7
401 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
402 #define G_FW_HELLO_CMD_STAGE(x) \
403 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
405 #define S_FW_HELLO_CMD_CLEARINIT 16
406 #define M_FW_HELLO_CMD_CLEARINIT 0x1
407 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
408 #define G_FW_HELLO_CMD_CLEARINIT(x) \
409 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
410 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
418 struct fw_initialize_cmd {
424 enum fw_caps_config_nic {
425 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
426 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
430 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
433 struct fw_caps_config_cmd {
435 __be32 cfvalid_to_len16;
453 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
454 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
455 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
456 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
457 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
458 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
460 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
461 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
462 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
463 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
464 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
465 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
466 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
468 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
469 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
470 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
471 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
472 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
473 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
474 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
477 * params command mnemonics
479 enum fw_params_mnem {
480 FW_PARAMS_MNEM_DEV = 1, /* device params */
481 FW_PARAMS_MNEM_PFVF = 2, /* function params */
482 FW_PARAMS_MNEM_REG = 3, /* limited register access */
483 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
489 enum fw_params_param_dev {
490 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
491 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
492 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
493 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
494 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
498 * physical and virtual function parameters
500 enum fw_params_param_pfvf {
501 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
502 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
506 * dma queue parameters
508 enum fw_params_param_dmaq {
509 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
510 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
513 #define S_FW_PARAMS_MNEM 24
514 #define M_FW_PARAMS_MNEM 0xff
515 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
516 #define G_FW_PARAMS_MNEM(x) \
517 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
519 #define S_FW_PARAMS_PARAM_X 16
520 #define M_FW_PARAMS_PARAM_X 0xff
521 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
522 #define G_FW_PARAMS_PARAM_X(x) \
523 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
525 #define S_FW_PARAMS_PARAM_Y 8
526 #define M_FW_PARAMS_PARAM_Y 0xff
527 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
528 #define G_FW_PARAMS_PARAM_Y(x) \
529 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
531 #define S_FW_PARAMS_PARAM_Z 0
532 #define M_FW_PARAMS_PARAM_Z 0xff
533 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
534 #define G_FW_PARAMS_PARAM_Z(x) \
535 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
537 #define S_FW_PARAMS_PARAM_YZ 0
538 #define M_FW_PARAMS_PARAM_YZ 0xffff
539 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
540 #define G_FW_PARAMS_PARAM_YZ(x) \
541 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
543 #define S_FW_PARAMS_PARAM_XYZ 0
544 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
545 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
547 struct fw_params_cmd {
550 struct fw_params_param {
556 #define S_FW_PARAMS_CMD_PFN 8
557 #define M_FW_PARAMS_CMD_PFN 0x7
558 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
559 #define G_FW_PARAMS_CMD_PFN(x) \
560 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
562 #define S_FW_PARAMS_CMD_VFN 0
563 #define M_FW_PARAMS_CMD_VFN 0xff
564 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
565 #define G_FW_PARAMS_CMD_VFN(x) \
566 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
573 __be32 tc_to_nexactf;
574 __be32 r_caps_to_nethctrl;
580 #define S_FW_PFVF_CMD_NIQFLINT 20
581 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
582 #define G_FW_PFVF_CMD_NIQFLINT(x) \
583 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
585 #define S_FW_PFVF_CMD_NIQ 0
586 #define M_FW_PFVF_CMD_NIQ 0xfffff
587 #define G_FW_PFVF_CMD_NIQ(x) \
588 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
590 #define S_FW_PFVF_CMD_PMASK 20
591 #define M_FW_PFVF_CMD_PMASK 0xf
592 #define G_FW_PFVF_CMD_PMASK(x) \
593 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
595 #define S_FW_PFVF_CMD_NEQ 0
596 #define M_FW_PFVF_CMD_NEQ 0xfffff
597 #define G_FW_PFVF_CMD_NEQ(x) \
598 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
600 #define S_FW_PFVF_CMD_TC 24
601 #define M_FW_PFVF_CMD_TC 0xff
602 #define G_FW_PFVF_CMD_TC(x) \
603 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
605 #define S_FW_PFVF_CMD_NVI 16
606 #define M_FW_PFVF_CMD_NVI 0xff
607 #define G_FW_PFVF_CMD_NVI(x) \
608 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
610 #define S_FW_PFVF_CMD_NEXACTF 0
611 #define M_FW_PFVF_CMD_NEXACTF 0xffff
612 #define G_FW_PFVF_CMD_NEXACTF(x) \
613 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
615 #define S_FW_PFVF_CMD_R_CAPS 24
616 #define M_FW_PFVF_CMD_R_CAPS 0xff
617 #define G_FW_PFVF_CMD_R_CAPS(x) \
618 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
620 #define S_FW_PFVF_CMD_WX_CAPS 16
621 #define M_FW_PFVF_CMD_WX_CAPS 0xff
622 #define G_FW_PFVF_CMD_WX_CAPS(x) \
623 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
625 #define S_FW_PFVF_CMD_NETHCTRL 0
626 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
627 #define G_FW_PFVF_CMD_NETHCTRL(x) \
628 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
631 * ingress queue type; the first 1K ingress queues can have associated 0,
632 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
636 FW_IQ_TYPE_FL_INT_CAP,
641 __be32 alloc_to_len16;
646 __be32 type_to_iqandstindex;
647 __be16 iqdroprss_to_iqesize;
650 __be32 iqns_to_fl0congen;
651 __be16 fl0dcaen_to_fl0cidxfthresh;
654 __be32 fl1cngchmap_to_fl1congen;
655 __be16 fl1dcaen_to_fl1cidxfthresh;
660 #define S_FW_IQ_CMD_PFN 8
661 #define M_FW_IQ_CMD_PFN 0x7
662 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
663 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
665 #define S_FW_IQ_CMD_VFN 0
666 #define M_FW_IQ_CMD_VFN 0xff
667 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
668 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
670 #define S_FW_IQ_CMD_ALLOC 31
671 #define M_FW_IQ_CMD_ALLOC 0x1
672 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
673 #define G_FW_IQ_CMD_ALLOC(x) \
674 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
675 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
677 #define S_FW_IQ_CMD_FREE 30
678 #define M_FW_IQ_CMD_FREE 0x1
679 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
680 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
681 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
683 #define S_FW_IQ_CMD_IQSTART 28
684 #define M_FW_IQ_CMD_IQSTART 0x1
685 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
686 #define G_FW_IQ_CMD_IQSTART(x) \
687 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
688 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
690 #define S_FW_IQ_CMD_IQSTOP 27
691 #define M_FW_IQ_CMD_IQSTOP 0x1
692 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
693 #define G_FW_IQ_CMD_IQSTOP(x) \
694 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
695 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
697 #define S_FW_IQ_CMD_TYPE 29
698 #define M_FW_IQ_CMD_TYPE 0x7
699 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
700 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
702 #define S_FW_IQ_CMD_IQASYNCH 28
703 #define M_FW_IQ_CMD_IQASYNCH 0x1
704 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
705 #define G_FW_IQ_CMD_IQASYNCH(x) \
706 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
707 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
709 #define S_FW_IQ_CMD_VIID 16
710 #define M_FW_IQ_CMD_VIID 0xfff
711 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
712 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
714 #define S_FW_IQ_CMD_IQANDST 15
715 #define M_FW_IQ_CMD_IQANDST 0x1
716 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
717 #define G_FW_IQ_CMD_IQANDST(x) \
718 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
719 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
721 #define S_FW_IQ_CMD_IQANUD 12
722 #define M_FW_IQ_CMD_IQANUD 0x3
723 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
724 #define G_FW_IQ_CMD_IQANUD(x) \
725 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
727 #define S_FW_IQ_CMD_IQANDSTINDEX 0
728 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
729 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
730 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
731 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
733 #define S_FW_IQ_CMD_IQGTSMODE 14
734 #define M_FW_IQ_CMD_IQGTSMODE 0x1
735 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
736 #define G_FW_IQ_CMD_IQGTSMODE(x) \
737 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
738 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
740 #define S_FW_IQ_CMD_IQPCIECH 12
741 #define M_FW_IQ_CMD_IQPCIECH 0x3
742 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
743 #define G_FW_IQ_CMD_IQPCIECH(x) \
744 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
746 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
747 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
748 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
749 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
750 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
752 #define S_FW_IQ_CMD_IQESIZE 0
753 #define M_FW_IQ_CMD_IQESIZE 0x3
754 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
755 #define G_FW_IQ_CMD_IQESIZE(x) \
756 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
758 #define S_FW_IQ_CMD_IQRO 30
759 #define M_FW_IQ_CMD_IQRO 0x1
760 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
761 #define G_FW_IQ_CMD_IQRO(x) \
762 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
763 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
765 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
766 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
767 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
768 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
769 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
770 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
772 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
773 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
774 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
775 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
776 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
778 #define S_FW_IQ_CMD_FL0DATARO 12
779 #define M_FW_IQ_CMD_FL0DATARO 0x1
780 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
781 #define G_FW_IQ_CMD_FL0DATARO(x) \
782 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
783 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
785 #define S_FW_IQ_CMD_FL0CONGCIF 11
786 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
787 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
788 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
789 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
790 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
792 #define S_FW_IQ_CMD_FL0FETCHRO 6
793 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
794 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
795 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
796 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
797 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
799 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
800 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
801 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
802 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
803 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
805 #define S_FW_IQ_CMD_FL0PADEN 2
806 #define M_FW_IQ_CMD_FL0PADEN 0x1
807 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
808 #define G_FW_IQ_CMD_FL0PADEN(x) \
809 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
810 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
812 #define S_FW_IQ_CMD_FL0PACKEN 1
813 #define M_FW_IQ_CMD_FL0PACKEN 0x1
814 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
815 #define G_FW_IQ_CMD_FL0PACKEN(x) \
816 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
817 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
819 #define S_FW_IQ_CMD_FL0CONGEN 0
820 #define M_FW_IQ_CMD_FL0CONGEN 0x1
821 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
822 #define G_FW_IQ_CMD_FL0CONGEN(x) \
823 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
824 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
826 #define S_FW_IQ_CMD_FL0FBMIN 7
827 #define M_FW_IQ_CMD_FL0FBMIN 0x7
828 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
829 #define G_FW_IQ_CMD_FL0FBMIN(x) \
830 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
832 #define S_FW_IQ_CMD_FL0FBMAX 4
833 #define M_FW_IQ_CMD_FL0FBMAX 0x7
834 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
835 #define G_FW_IQ_CMD_FL0FBMAX(x) \
836 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
838 struct fw_eq_eth_cmd {
840 __be32 alloc_to_len16;
843 __be32 fetchszm_to_iqid;
844 __be32 dcaen_to_eqsize;
846 __be32 autoequiqe_to_viid;
851 #define S_FW_EQ_ETH_CMD_PFN 8
852 #define M_FW_EQ_ETH_CMD_PFN 0x7
853 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
854 #define G_FW_EQ_ETH_CMD_PFN(x) \
855 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
857 #define S_FW_EQ_ETH_CMD_VFN 0
858 #define M_FW_EQ_ETH_CMD_VFN 0xff
859 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
860 #define G_FW_EQ_ETH_CMD_VFN(x) \
861 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
863 #define S_FW_EQ_ETH_CMD_ALLOC 31
864 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
865 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
866 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
867 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
868 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
870 #define S_FW_EQ_ETH_CMD_FREE 30
871 #define M_FW_EQ_ETH_CMD_FREE 0x1
872 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
873 #define G_FW_EQ_ETH_CMD_FREE(x) \
874 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
875 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
877 #define S_FW_EQ_ETH_CMD_EQSTART 28
878 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
879 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
880 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
881 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
882 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
884 #define S_FW_EQ_ETH_CMD_EQID 0
885 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
886 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
887 #define G_FW_EQ_ETH_CMD_EQID(x) \
888 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
890 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
891 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
892 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
893 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
895 #define S_FW_EQ_ETH_CMD_FETCHRO 22
896 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
897 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
898 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
899 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
900 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
902 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
903 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
904 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
905 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
906 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
908 #define S_FW_EQ_ETH_CMD_PCIECHN 16
909 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
910 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
911 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
912 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
914 #define S_FW_EQ_ETH_CMD_IQID 0
915 #define M_FW_EQ_ETH_CMD_IQID 0xffff
916 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
917 #define G_FW_EQ_ETH_CMD_IQID(x) \
918 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
920 #define S_FW_EQ_ETH_CMD_FBMIN 23
921 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
922 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
923 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
924 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
926 #define S_FW_EQ_ETH_CMD_FBMAX 20
927 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
928 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
929 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
930 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
932 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
933 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
934 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
935 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
936 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
938 #define S_FW_EQ_ETH_CMD_EQSIZE 0
939 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
940 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
941 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
942 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
944 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
945 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
946 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
947 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
948 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
949 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
951 #define S_FW_EQ_ETH_CMD_VIID 16
952 #define M_FW_EQ_ETH_CMD_VIID 0xfff
953 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
954 #define G_FW_EQ_ETH_CMD_VIID(x) \
955 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
963 __be32 alloc_to_len16;
969 __be16 norss_rsssize;
979 #define S_FW_VI_CMD_PFN 8
980 #define M_FW_VI_CMD_PFN 0x7
981 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
982 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
984 #define S_FW_VI_CMD_VFN 0
985 #define M_FW_VI_CMD_VFN 0xff
986 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
987 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
989 #define S_FW_VI_CMD_ALLOC 31
990 #define M_FW_VI_CMD_ALLOC 0x1
991 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
992 #define G_FW_VI_CMD_ALLOC(x) \
993 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
994 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
996 #define S_FW_VI_CMD_FREE 30
997 #define M_FW_VI_CMD_FREE 0x1
998 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
999 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1000 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1002 #define S_FW_VI_CMD_TYPE 15
1003 #define M_FW_VI_CMD_TYPE 0x1
1004 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1005 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1006 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1008 #define S_FW_VI_CMD_FUNC 12
1009 #define M_FW_VI_CMD_FUNC 0x7
1010 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1011 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1013 #define S_FW_VI_CMD_VIID 0
1014 #define M_FW_VI_CMD_VIID 0xfff
1015 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1016 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1018 #define S_FW_VI_CMD_PORTID 4
1019 #define M_FW_VI_CMD_PORTID 0xf
1020 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1021 #define G_FW_VI_CMD_PORTID(x) \
1022 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1024 #define S_FW_VI_CMD_RSSSIZE 0
1025 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1026 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1027 #define G_FW_VI_CMD_RSSSIZE(x) \
1028 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1030 /* Special VI_MAC command index ids */
1031 #define FW_VI_MAC_ADD_MAC 0x3FF
1032 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1034 enum fw_vi_mac_smac {
1035 FW_VI_MAC_MPS_TCAM_ENTRY,
1036 FW_VI_MAC_SMT_AND_MPSTCAM
1039 struct fw_vi_mac_cmd {
1041 __be32 freemacs_to_len16;
1043 struct fw_vi_mac_exact {
1044 __be16 valid_to_idx;
1047 struct fw_vi_mac_hash {
1053 #define S_FW_VI_MAC_CMD_VIID 0
1054 #define M_FW_VI_MAC_CMD_VIID 0xfff
1055 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1056 #define G_FW_VI_MAC_CMD_VIID(x) \
1057 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1059 #define S_FW_VI_MAC_CMD_VALID 15
1060 #define M_FW_VI_MAC_CMD_VALID 0x1
1061 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1062 #define G_FW_VI_MAC_CMD_VALID(x) \
1063 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1064 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1066 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1067 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1068 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1069 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1070 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1072 #define S_FW_VI_MAC_CMD_IDX 0
1073 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1074 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1075 #define G_FW_VI_MAC_CMD_IDX(x) \
1076 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1078 struct fw_vi_rxmode_cmd {
1080 __be32 retval_len16;
1081 __be32 mtu_to_vlanexen;
1085 #define S_FW_VI_RXMODE_CMD_VIID 0
1086 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1087 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1088 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1089 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1091 #define S_FW_VI_RXMODE_CMD_MTU 16
1092 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1093 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1094 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1095 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1097 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1098 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1099 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1100 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1101 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1103 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1104 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1105 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1106 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1107 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1108 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1110 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1111 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1112 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1113 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1114 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1115 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1116 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1118 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1119 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1120 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1121 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1122 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1124 struct fw_vi_enable_cmd {
1126 __be32 ien_to_len16;
1132 #define S_FW_VI_ENABLE_CMD_VIID 0
1133 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1134 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1135 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1136 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1138 #define S_FW_VI_ENABLE_CMD_IEN 31
1139 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1140 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1141 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1142 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1143 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1145 #define S_FW_VI_ENABLE_CMD_EEN 30
1146 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1147 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1148 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1149 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1150 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1152 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1153 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1154 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1155 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1156 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1157 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1159 /* VI VF stats offset definitions */
1160 #define VI_VF_NUM_STATS 16
1162 /* VI PF stats offset definitions */
1163 #define VI_PF_NUM_STATS 17
1164 enum fw_vi_stats_pf_index {
1165 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1166 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1167 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1168 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1169 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1170 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1171 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1172 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1173 FW_VI_PF_STAT_RX_BYTES_IX,
1174 FW_VI_PF_STAT_RX_FRAMES_IX,
1175 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1176 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1177 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1178 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1179 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1180 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1181 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1184 struct fw_vi_stats_cmd {
1186 __be32 retval_len16;
1188 struct fw_vi_stats_ctl {
1199 struct fw_vi_stats_pf {
1200 __be64 tx_bcast_bytes;
1201 __be64 tx_bcast_frames;
1202 __be64 tx_mcast_bytes;
1203 __be64 tx_mcast_frames;
1204 __be64 tx_ucast_bytes;
1205 __be64 tx_ucast_frames;
1206 __be64 tx_offload_bytes;
1207 __be64 tx_offload_frames;
1209 __be64 rx_pf_frames;
1210 __be64 rx_bcast_bytes;
1211 __be64 rx_bcast_frames;
1212 __be64 rx_mcast_bytes;
1213 __be64 rx_mcast_frames;
1214 __be64 rx_ucast_bytes;
1215 __be64 rx_ucast_frames;
1216 __be64 rx_err_frames;
1218 struct fw_vi_stats_vf {
1219 __be64 tx_bcast_bytes;
1220 __be64 tx_bcast_frames;
1221 __be64 tx_mcast_bytes;
1222 __be64 tx_mcast_frames;
1223 __be64 tx_ucast_bytes;
1224 __be64 tx_ucast_frames;
1225 __be64 tx_drop_frames;
1226 __be64 tx_offload_bytes;
1227 __be64 tx_offload_frames;
1228 __be64 rx_bcast_bytes;
1229 __be64 rx_bcast_frames;
1230 __be64 rx_mcast_bytes;
1231 __be64 rx_mcast_frames;
1232 __be64 rx_ucast_bytes;
1233 __be64 rx_ucast_frames;
1234 __be64 rx_err_frames;
1239 #define S_FW_VI_STATS_CMD_VIID 0
1240 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1242 #define S_FW_VI_STATS_CMD_NSTATS 12
1243 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1245 #define S_FW_VI_STATS_CMD_IX 0
1246 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1248 /* old 16-bit port capabilities bitmap */
1250 FW_PORT_CAP_SPEED_100M = 0x0001,
1251 FW_PORT_CAP_SPEED_1G = 0x0002,
1252 FW_PORT_CAP_SPEED_25G = 0x0004,
1253 FW_PORT_CAP_SPEED_10G = 0x0008,
1254 FW_PORT_CAP_SPEED_40G = 0x0010,
1255 FW_PORT_CAP_SPEED_100G = 0x0020,
1256 FW_PORT_CAP_FC_RX = 0x0040,
1257 FW_PORT_CAP_FC_TX = 0x0080,
1258 FW_PORT_CAP_ANEG = 0x0100,
1259 FW_PORT_CAP_MDIX = 0x0200,
1260 FW_PORT_CAP_MDIAUTO = 0x0400,
1261 FW_PORT_CAP_FEC_RS = 0x0800,
1262 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1263 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1264 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1265 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1268 #define S_FW_PORT_CAP_SPEED 0
1269 #define M_FW_PORT_CAP_SPEED 0x3f
1270 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1271 #define G_FW_PORT_CAP_SPEED(x) \
1272 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1275 FW_PORT_CAP_MDI_AUTO,
1278 #define S_FW_PORT_CAP_MDI 9
1279 #define M_FW_PORT_CAP_MDI 3
1280 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1281 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1283 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1284 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1285 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1286 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1287 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1288 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1289 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1290 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1291 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1292 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1293 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1294 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1295 #define FW_PORT_CAP32_ANEG 0x00100000UL
1296 #define FW_PORT_CAP32_MDIX 0x00200000UL
1297 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1298 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1299 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1301 #define S_FW_PORT_CAP32_SPEED 0
1302 #define M_FW_PORT_CAP32_SPEED 0xfff
1303 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1304 #define G_FW_PORT_CAP32_SPEED(x) \
1305 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1307 enum fw_port_mdi32 {
1308 FW_PORT_CAP32_MDI_AUTO,
1311 #define S_FW_PORT_CAP32_MDI 21
1312 #define M_FW_PORT_CAP32_MDI 3
1313 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1314 #define G_FW_PORT_CAP32_MDI(x) \
1315 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1317 enum fw_port_action {
1318 FW_PORT_ACTION_L1_CFG = 0x0001,
1319 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1320 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1321 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1324 struct fw_port_cmd {
1325 __be32 op_to_portid;
1326 __be32 action_to_len16;
1328 struct fw_port_l1cfg {
1332 struct fw_port_l2cfg {
1334 __u8 ovlan3_to_ivlan0;
1336 __be16 txipg_force_pinfo;
1347 struct fw_port_info {
1348 __be32 lstatus_to_modtype;
1359 struct fw_port_diags {
1365 struct fw_port_dcb_pgid {
1372 struct fw_port_dcb_pgrate {
1376 __u8 num_tcs_supported;
1380 struct fw_port_dcb_priorate {
1384 __u8 strict_priorate[8];
1386 struct fw_port_dcb_pfc {
1393 struct fw_port_app_priority {
1402 struct fw_port_dcb_control {
1405 __be16 dcb_version_to_app_state;
1410 struct fw_port_l1cfg32 {
1414 struct fw_port_info32 {
1415 __be32 lstatus32_to_cbllen32;
1416 __be32 auxlinfo32_mtu32;
1425 #define S_FW_PORT_CMD_PORTID 0
1426 #define M_FW_PORT_CMD_PORTID 0xf
1427 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1428 #define G_FW_PORT_CMD_PORTID(x) \
1429 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1431 #define S_FW_PORT_CMD_ACTION 16
1432 #define M_FW_PORT_CMD_ACTION 0xffff
1433 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1434 #define G_FW_PORT_CMD_ACTION(x) \
1435 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1437 #define S_FW_PORT_CMD_LSTATUS 31
1438 #define M_FW_PORT_CMD_LSTATUS 0x1
1439 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1440 #define G_FW_PORT_CMD_LSTATUS(x) \
1441 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1442 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1444 #define S_FW_PORT_CMD_LSPEED 24
1445 #define M_FW_PORT_CMD_LSPEED 0x3f
1446 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1447 #define G_FW_PORT_CMD_LSPEED(x) \
1448 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1450 #define S_FW_PORT_CMD_TXPAUSE 23
1451 #define M_FW_PORT_CMD_TXPAUSE 0x1
1452 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1453 #define G_FW_PORT_CMD_TXPAUSE(x) \
1454 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1455 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1457 #define S_FW_PORT_CMD_RXPAUSE 22
1458 #define M_FW_PORT_CMD_RXPAUSE 0x1
1459 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1460 #define G_FW_PORT_CMD_RXPAUSE(x) \
1461 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1462 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1464 #define S_FW_PORT_CMD_MDIOCAP 21
1465 #define M_FW_PORT_CMD_MDIOCAP 0x1
1466 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1467 #define G_FW_PORT_CMD_MDIOCAP(x) \
1468 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1469 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1471 #define S_FW_PORT_CMD_MDIOADDR 16
1472 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1473 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1474 #define G_FW_PORT_CMD_MDIOADDR(x) \
1475 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1477 #define S_FW_PORT_CMD_PTYPE 8
1478 #define M_FW_PORT_CMD_PTYPE 0x1f
1479 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1480 #define G_FW_PORT_CMD_PTYPE(x) \
1481 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1483 #define S_FW_PORT_CMD_LINKDNRC 5
1484 #define M_FW_PORT_CMD_LINKDNRC 0x7
1485 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1486 #define G_FW_PORT_CMD_LINKDNRC(x) \
1487 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1489 #define S_FW_PORT_CMD_MODTYPE 0
1490 #define M_FW_PORT_CMD_MODTYPE 0x1f
1491 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1492 #define G_FW_PORT_CMD_MODTYPE(x) \
1493 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1495 #define S_FW_PORT_CMD_LSTATUS32 31
1496 #define M_FW_PORT_CMD_LSTATUS32 0x1
1497 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1498 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1500 #define S_FW_PORT_CMD_LINKDNRC32 28
1501 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1502 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1503 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1505 #define S_FW_PORT_CMD_MDIOCAP32 26
1506 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1507 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1508 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1510 #define S_FW_PORT_CMD_MDIOADDR32 21
1511 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1512 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1513 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1515 #define S_FW_PORT_CMD_PORTTYPE32 13
1516 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1517 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1518 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1520 #define S_FW_PORT_CMD_MODTYPE32 8
1521 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1522 #define G_FW_PORT_CMD_MODTYPE32(x) \
1523 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1526 * These are configured into the VPD and hence tools that generate
1527 * VPD may use this enumeration.
1528 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1531 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1532 * with any new Firmware Port Technology Types!
1535 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1536 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1537 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1538 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1539 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1540 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1541 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1542 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1543 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1544 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1545 FW_PORT_TYPE_BP_AP = 10,
1546 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1547 FW_PORT_TYPE_BP4_AP = 11,
1548 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1549 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1550 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1551 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1552 FW_PORT_TYPE_BP40_BA = 15,
1553 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1554 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1555 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1556 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1557 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1558 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1559 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1560 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1563 /* These are read from module's EEPROM and determined once the
1564 * module is inserted.
1566 enum fw_port_module_type {
1567 FW_PORT_MOD_TYPE_NA = 0x0,
1568 FW_PORT_MOD_TYPE_LR = 0x1,
1569 FW_PORT_MOD_TYPE_SR = 0x2,
1570 FW_PORT_MOD_TYPE_ER = 0x3,
1571 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1572 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1573 FW_PORT_MOD_TYPE_LRM = 0x6,
1574 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1575 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1576 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1577 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1580 /* used by FW and tools may use this to generate VPD */
1581 enum fw_port_mod_sub_type {
1582 FW_PORT_MOD_SUB_TYPE_NA,
1583 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1584 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1585 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1586 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1587 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1588 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1589 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1590 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1593 * The following will never been in the VPD. They are TWINAX cable
1594 * lengths decoded from SFP+ module i2c PROMs. These should almost
1595 * certainly go somewhere else ...
1597 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1598 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1599 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1600 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1603 /* link down reason codes (3b) */
1604 enum fw_port_link_dn_rc {
1605 FW_PORT_LINK_DN_RC_NONE,
1606 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1607 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1608 FW_PORT_LINK_DN_RESERVED3,
1609 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1610 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1611 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1612 FW_PORT_LINK_DN_RESERVED7
1616 #define FW_NUM_PORT_STATS 50
1617 #define FW_NUM_PORT_TX_STATS 23
1618 #define FW_NUM_PORT_RX_STATS 27
1620 enum fw_port_stats_tx_index {
1621 FW_STAT_TX_PORT_BYTES_IX,
1622 FW_STAT_TX_PORT_FRAMES_IX,
1623 FW_STAT_TX_PORT_BCAST_IX,
1624 FW_STAT_TX_PORT_MCAST_IX,
1625 FW_STAT_TX_PORT_UCAST_IX,
1626 FW_STAT_TX_PORT_ERROR_IX,
1627 FW_STAT_TX_PORT_64B_IX,
1628 FW_STAT_TX_PORT_65B_127B_IX,
1629 FW_STAT_TX_PORT_128B_255B_IX,
1630 FW_STAT_TX_PORT_256B_511B_IX,
1631 FW_STAT_TX_PORT_512B_1023B_IX,
1632 FW_STAT_TX_PORT_1024B_1518B_IX,
1633 FW_STAT_TX_PORT_1519B_MAX_IX,
1634 FW_STAT_TX_PORT_DROP_IX,
1635 FW_STAT_TX_PORT_PAUSE_IX,
1636 FW_STAT_TX_PORT_PPP0_IX,
1637 FW_STAT_TX_PORT_PPP1_IX,
1638 FW_STAT_TX_PORT_PPP2_IX,
1639 FW_STAT_TX_PORT_PPP3_IX,
1640 FW_STAT_TX_PORT_PPP4_IX,
1641 FW_STAT_TX_PORT_PPP5_IX,
1642 FW_STAT_TX_PORT_PPP6_IX,
1643 FW_STAT_TX_PORT_PPP7_IX
1646 enum fw_port_stat_rx_index {
1647 FW_STAT_RX_PORT_BYTES_IX,
1648 FW_STAT_RX_PORT_FRAMES_IX,
1649 FW_STAT_RX_PORT_BCAST_IX,
1650 FW_STAT_RX_PORT_MCAST_IX,
1651 FW_STAT_RX_PORT_UCAST_IX,
1652 FW_STAT_RX_PORT_MTU_ERROR_IX,
1653 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1654 FW_STAT_RX_PORT_CRC_ERROR_IX,
1655 FW_STAT_RX_PORT_LEN_ERROR_IX,
1656 FW_STAT_RX_PORT_SYM_ERROR_IX,
1657 FW_STAT_RX_PORT_64B_IX,
1658 FW_STAT_RX_PORT_65B_127B_IX,
1659 FW_STAT_RX_PORT_128B_255B_IX,
1660 FW_STAT_RX_PORT_256B_511B_IX,
1661 FW_STAT_RX_PORT_512B_1023B_IX,
1662 FW_STAT_RX_PORT_1024B_1518B_IX,
1663 FW_STAT_RX_PORT_1519B_MAX_IX,
1664 FW_STAT_RX_PORT_PAUSE_IX,
1665 FW_STAT_RX_PORT_PPP0_IX,
1666 FW_STAT_RX_PORT_PPP1_IX,
1667 FW_STAT_RX_PORT_PPP2_IX,
1668 FW_STAT_RX_PORT_PPP3_IX,
1669 FW_STAT_RX_PORT_PPP4_IX,
1670 FW_STAT_RX_PORT_PPP5_IX,
1671 FW_STAT_RX_PORT_PPP6_IX,
1672 FW_STAT_RX_PORT_PPP7_IX,
1673 FW_STAT_RX_PORT_LESS_64B_IX
1676 struct fw_port_stats_cmd {
1677 __be32 op_to_portid;
1678 __be32 retval_len16;
1679 union fw_port_stats {
1680 struct fw_port_stats_ctl {
1692 struct fw_port_stats_all {
1701 __be64 tx_128b_255b;
1702 __be64 tx_256b_511b;
1703 __be64 tx_512b_1023b;
1704 __be64 tx_1024b_1518b;
1705 __be64 tx_1519b_max;
1721 __be64 rx_mtu_error;
1722 __be64 rx_mtu_crc_error;
1723 __be64 rx_crc_error;
1724 __be64 rx_len_error;
1725 __be64 rx_sym_error;
1728 __be64 rx_128b_255b;
1729 __be64 rx_256b_511b;
1730 __be64 rx_512b_1023b;
1731 __be64 rx_1024b_1518b;
1732 __be64 rx_1519b_max;
1749 struct fw_rss_ind_tbl_cmd {
1751 __be32 retval_len16;
1759 __be32 iq12_to_iq14;
1760 __be32 iq15_to_iq17;
1761 __be32 iq18_to_iq20;
1762 __be32 iq21_to_iq23;
1763 __be32 iq24_to_iq26;
1764 __be32 iq27_to_iq29;
1769 #define S_FW_RSS_IND_TBL_CMD_VIID 0
1770 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
1771 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
1772 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
1773 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
1775 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
1776 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
1777 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
1778 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
1779 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
1781 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
1782 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
1783 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
1784 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
1785 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
1787 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
1788 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
1789 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
1790 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
1791 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
1793 struct fw_rss_glb_config_cmd {
1795 __be32 retval_len16;
1796 union fw_rss_glb_config {
1797 struct fw_rss_glb_config_manual {
1803 struct fw_rss_glb_config_basicvirtual {
1804 __be32 mode_keymode;
1805 __be32 synmapen_to_hashtoeplitz;
1812 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
1813 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
1814 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
1815 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
1817 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
1819 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
1820 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
1821 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
1822 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
1824 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
1825 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
1826 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
1827 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
1828 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
1830 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
1831 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
1832 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
1833 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
1834 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
1836 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
1837 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
1838 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
1839 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
1840 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
1842 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
1843 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
1844 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
1845 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
1846 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
1848 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
1849 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
1850 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
1851 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
1853 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
1854 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
1855 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
1856 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
1858 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
1859 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
1860 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
1861 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
1862 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
1864 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
1865 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
1866 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
1867 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
1868 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
1870 struct fw_rss_vi_config_cmd {
1872 __be32 retval_len16;
1873 union fw_rss_vi_config {
1874 struct fw_rss_vi_config_manual {
1879 struct fw_rss_vi_config_basicvirtual {
1881 __be32 defaultq_to_udpen;
1888 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
1889 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
1890 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
1891 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
1892 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
1894 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
1895 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
1896 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1897 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1898 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1899 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
1900 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1902 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
1903 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
1904 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1905 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1906 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1907 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
1908 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1909 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
1910 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
1912 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
1913 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
1914 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1915 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1916 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1917 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
1918 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1919 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
1920 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
1922 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
1923 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
1924 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
1925 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1926 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
1927 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
1928 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1929 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
1930 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
1932 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
1933 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
1934 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
1935 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1936 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
1937 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
1938 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1939 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
1940 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
1942 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
1943 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
1944 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
1945 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
1946 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
1947 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
1949 /******************************************************************************
1950 * D E B U G C O M M A N D s
1951 ******************************************************/
1953 struct fw_debug_cmd {
1957 struct fw_debug_assert {
1962 __u8 filename_0_7[8];
1963 __u8 filename_8_15[8];
1966 struct fw_debug_prt {
1969 __be32 dprtstrparam0;
1970 __be32 dprtstrparam1;
1971 __be32 dprtstrparam2;
1972 __be32 dprtstrparam3;
1977 #define S_FW_DEBUG_CMD_TYPE 0
1978 #define M_FW_DEBUG_CMD_TYPE 0xff
1979 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
1980 #define G_FW_DEBUG_CMD_TYPE(x) \
1981 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
1983 /******************************************************************************
1984 * P C I E F W R E G I S T E R
1985 **************************************/
1988 * Register definitions for the PCIE_FW register which the firmware uses
1989 * to retain status across RESETs. This register should be considered
1990 * as a READ-ONLY register for Host Software and only to be used to
1991 * track firmware initialization/error state, etc.
1993 #define S_PCIE_FW_ERR 31
1994 #define M_PCIE_FW_ERR 0x1
1995 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
1996 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
1997 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
1999 #define S_PCIE_FW_INIT 30
2000 #define M_PCIE_FW_INIT 0x1
2001 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2002 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2003 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2005 #define S_PCIE_FW_HALT 29
2006 #define M_PCIE_FW_HALT 0x1
2007 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2008 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2009 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2011 #define S_PCIE_FW_EVAL 24
2012 #define M_PCIE_FW_EVAL 0x7
2013 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2014 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2016 #define S_PCIE_FW_MASTER_VLD 15
2017 #define M_PCIE_FW_MASTER_VLD 0x1
2018 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2019 #define G_PCIE_FW_MASTER_VLD(x) \
2020 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2021 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2023 #define S_PCIE_FW_MASTER 12
2024 #define M_PCIE_FW_MASTER 0x7
2025 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2026 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2028 /******************************************************************************
2029 * B I N A R Y H E A D E R F O R M A T
2030 **********************************************/
2033 * firmware binary header format
2037 __u8 chip; /* terminator chip family */
2038 __be16 len512; /* bin length in units of 512-bytes */
2039 __be32 fw_ver; /* firmware version */
2040 __be32 tp_microcode_ver; /* tcp processor microcode version */
2045 __u8 intfver_iscsipdu;
2047 __u8 intfver_fcoepdu;
2051 __u32 magic; /* runtime or bootstrap fw */
2053 __be32 reserved6[23];
2056 #define S_FW_HDR_FW_VER_MAJOR 24
2057 #define M_FW_HDR_FW_VER_MAJOR 0xff
2058 #define V_FW_HDR_FW_VER_MAJOR(x) \
2059 ((x) << S_FW_HDR_FW_VER_MAJOR)
2060 #define G_FW_HDR_FW_VER_MAJOR(x) \
2061 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2063 #define S_FW_HDR_FW_VER_MINOR 16
2064 #define M_FW_HDR_FW_VER_MINOR 0xff
2065 #define V_FW_HDR_FW_VER_MINOR(x) \
2066 ((x) << S_FW_HDR_FW_VER_MINOR)
2067 #define G_FW_HDR_FW_VER_MINOR(x) \
2068 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2070 #define S_FW_HDR_FW_VER_MICRO 8
2071 #define M_FW_HDR_FW_VER_MICRO 0xff
2072 #define V_FW_HDR_FW_VER_MICRO(x) \
2073 ((x) << S_FW_HDR_FW_VER_MICRO)
2074 #define G_FW_HDR_FW_VER_MICRO(x) \
2075 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2077 #define S_FW_HDR_FW_VER_BUILD 0
2078 #define M_FW_HDR_FW_VER_BUILD 0xff
2079 #define V_FW_HDR_FW_VER_BUILD(x) \
2080 ((x) << S_FW_HDR_FW_VER_BUILD)
2081 #define G_FW_HDR_FW_VER_BUILD(x) \
2082 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2084 #endif /* _T4FW_INTERFACE_H_ */