4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _T4FW_INTERFACE_H_
35 #define _T4FW_INTERFACE_H_
37 /******************************************************************************
38 * R E T U R N V A L U E S
39 ********************************/
42 FW_SUCCESS = 0, /* completed successfully */
43 FW_EPERM = 1, /* operation not permitted */
44 FW_ENOENT = 2, /* no such file or directory */
45 FW_EIO = 5, /* input/output error; hw bad */
46 FW_ENOEXEC = 8, /* exec format error; inv microcode */
47 FW_EAGAIN = 11, /* try again */
48 FW_ENOMEM = 12, /* out of memory */
49 FW_EFAULT = 14, /* bad address; fw bad */
50 FW_EBUSY = 16, /* resource busy */
51 FW_EEXIST = 17, /* file exists */
52 FW_ENODEV = 19, /* no such device */
53 FW_EINVAL = 22, /* invalid argument */
54 FW_ENOSPC = 28, /* no space left on device */
55 FW_ENOSYS = 38, /* functionality not implemented */
56 FW_ENODATA = 61, /* no data available */
57 FW_EPROTO = 71, /* protocol error */
58 FW_EADDRINUSE = 98, /* address already in use */
59 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
60 FW_ENETDOWN = 100, /* network is down */
61 FW_ENETUNREACH = 101, /* network is unreachable */
62 FW_ENOBUFS = 105, /* no buffer space available */
63 FW_ETIMEDOUT = 110, /* timeout */
64 FW_EINPROGRESS = 115, /* fw internal */
67 /******************************************************************************
68 * M E M O R Y T Y P E s
69 ******************************/
72 FW_MEMTYPE_EDC0 = 0x0,
73 FW_MEMTYPE_EDC1 = 0x1,
74 FW_MEMTYPE_EXTMEM = 0x2,
75 FW_MEMTYPE_FLASH = 0x4,
76 FW_MEMTYPE_INTERNAL = 0x5,
77 FW_MEMTYPE_EXTMEM1 = 0x6,
80 /******************************************************************************
81 * W O R K R E Q U E S T s
82 ********************************/
85 FW_ETH_TX_PKT_WR = 0x08,
86 FW_ETH_TX_PKTS_WR = 0x09,
87 FW_ETH_TX_PKTS2_WR = 0x78,
91 * Generic work request header flit0
98 /* work request opcode (hi)
100 #define S_FW_WR_OP 24
101 #define M_FW_WR_OP 0xff
102 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
103 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
105 /* work request immediate data length (hi)
107 #define S_FW_WR_IMMDLEN 0
108 #define M_FW_WR_IMMDLEN 0xff
109 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
110 #define G_FW_WR_IMMDLEN(x) \
111 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
113 /* egress queue status update to egress queue status entry (lo)
115 #define S_FW_WR_EQUEQ 30
116 #define M_FW_WR_EQUEQ 0x1
117 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
118 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
119 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
121 /* length in units of 16-bytes (lo)
123 #define S_FW_WR_LEN16 0
124 #define M_FW_WR_LEN16 0xff
125 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
126 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
128 struct fw_eth_tx_pkt_wr {
130 __be32 equiq_to_len16;
134 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
135 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
136 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
137 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
138 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
140 struct fw_eth_tx_pkts_wr {
142 __be32 equiq_to_len16;
149 /******************************************************************************
151 *********************/
154 * The maximum length of time, in miliseconds, that we expect any firmware
155 * command to take to execute and return a reply to the host. The RESET
156 * and INITIALIZE commands can take a fair amount of time to execute but
157 * most execute in far less time than this maximum. This constant is used
158 * by host software to determine how long to wait for a firmware command
159 * reply before declaring the firmware as dead/unreachable ...
161 #define FW_CMD_MAX_TIMEOUT 10000
164 * If a host driver does a HELLO and discovers that there's already a MASTER
165 * selected, we may have to wait for that MASTER to finish issuing RESET,
166 * configuration and INITIALIZE commands. Also, there's a possibility that
167 * our own HELLO may get lost if it happens right as the MASTER is issuign a
168 * RESET command, so we need to be willing to make a few retries of our HELLO.
170 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
171 #define FW_CMD_HELLO_RETRIES 3
173 enum fw_cmd_opcodes {
178 FW_INITIALIZE_CMD = 0x06,
179 FW_CAPS_CONFIG_CMD = 0x07,
180 FW_PARAMS_CMD = 0x08,
182 FW_EQ_ETH_CMD = 0x12,
184 FW_VI_MAC_CMD = 0x15,
185 FW_VI_RXMODE_CMD = 0x16,
186 FW_VI_ENABLE_CMD = 0x17,
188 FW_RSS_IND_TBL_CMD = 0x20,
189 FW_RSS_VI_CONFIG_CMD = 0x23,
194 * Generic command header flit0
201 #define S_FW_CMD_OP 24
202 #define M_FW_CMD_OP 0xff
203 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
204 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
206 #define S_FW_CMD_REQUEST 23
207 #define M_FW_CMD_REQUEST 0x1
208 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
209 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
210 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
212 #define S_FW_CMD_READ 22
213 #define M_FW_CMD_READ 0x1
214 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
215 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
216 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
218 #define S_FW_CMD_WRITE 21
219 #define M_FW_CMD_WRITE 0x1
220 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
221 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
222 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
224 #define S_FW_CMD_EXEC 20
225 #define M_FW_CMD_EXEC 0x1
226 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
227 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
228 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
230 #define S_FW_CMD_RETVAL 8
231 #define M_FW_CMD_RETVAL 0xff
232 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
233 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
235 #define S_FW_CMD_LEN16 0
236 #define M_FW_CMD_LEN16 0xff
237 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
238 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
240 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
244 enum fw_ldst_addrspc {
245 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
249 __be32 op_to_addrspace;
250 __be32 cycles_to_len16;
252 struct fw_ldst_addrval {
256 struct fw_ldst_idctxt {
258 __be32 msg_ctxtflush;
268 struct fw_ldst_mdio {
284 struct fw_ldst_func {
292 struct fw_ldst_pcie {
302 struct fw_ldst_i2c_deprecated {
326 #define S_FW_LDST_CMD_ADDRSPACE 0
327 #define M_FW_LDST_CMD_ADDRSPACE 0xff
328 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
330 struct fw_reset_cmd {
337 #define S_FW_RESET_CMD_HALT 31
338 #define M_FW_RESET_CMD_HALT 0x1
339 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
340 #define G_FW_RESET_CMD_HALT(x) \
341 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
342 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
345 FW_HELLO_CMD_STAGE_OS = 0,
348 struct fw_hello_cmd {
351 __be32 err_to_clearinit;
355 #define S_FW_HELLO_CMD_ERR 31
356 #define M_FW_HELLO_CMD_ERR 0x1
357 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
358 #define G_FW_HELLO_CMD_ERR(x) \
359 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
360 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
362 #define S_FW_HELLO_CMD_INIT 30
363 #define M_FW_HELLO_CMD_INIT 0x1
364 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
365 #define G_FW_HELLO_CMD_INIT(x) \
366 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
367 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
369 #define S_FW_HELLO_CMD_MASTERDIS 29
370 #define M_FW_HELLO_CMD_MASTERDIS 0x1
371 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
372 #define G_FW_HELLO_CMD_MASTERDIS(x) \
373 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
374 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
376 #define S_FW_HELLO_CMD_MASTERFORCE 28
377 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
378 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
379 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
380 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
381 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
383 #define S_FW_HELLO_CMD_MBMASTER 24
384 #define M_FW_HELLO_CMD_MBMASTER 0xf
385 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
386 #define G_FW_HELLO_CMD_MBMASTER(x) \
387 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
389 #define S_FW_HELLO_CMD_MBASYNCNOT 20
390 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
391 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
392 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
393 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
395 #define S_FW_HELLO_CMD_STAGE 17
396 #define M_FW_HELLO_CMD_STAGE 0x7
397 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
398 #define G_FW_HELLO_CMD_STAGE(x) \
399 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
401 #define S_FW_HELLO_CMD_CLEARINIT 16
402 #define M_FW_HELLO_CMD_CLEARINIT 0x1
403 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
404 #define G_FW_HELLO_CMD_CLEARINIT(x) \
405 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
406 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
414 struct fw_initialize_cmd {
420 enum fw_caps_config_nic {
421 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
422 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
426 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
429 struct fw_caps_config_cmd {
431 __be32 cfvalid_to_len16;
449 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
450 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
451 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
452 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
453 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
454 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
456 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
457 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
458 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
459 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
460 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
461 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
462 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
464 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
465 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
466 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
467 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
468 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
469 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
470 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
473 * params command mnemonics
475 enum fw_params_mnem {
476 FW_PARAMS_MNEM_DEV = 1, /* device params */
477 FW_PARAMS_MNEM_PFVF = 2, /* function params */
478 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
484 enum fw_params_param_dev {
485 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
486 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
487 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
491 * physical and virtual function parameters
493 enum fw_params_param_pfvf {
494 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
498 * dma queue parameters
500 enum fw_params_param_dmaq {
501 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
502 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
505 #define S_FW_PARAMS_MNEM 24
506 #define M_FW_PARAMS_MNEM 0xff
507 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
508 #define G_FW_PARAMS_MNEM(x) \
509 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
511 #define S_FW_PARAMS_PARAM_X 16
512 #define M_FW_PARAMS_PARAM_X 0xff
513 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
514 #define G_FW_PARAMS_PARAM_X(x) \
515 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
517 #define S_FW_PARAMS_PARAM_Y 8
518 #define M_FW_PARAMS_PARAM_Y 0xff
519 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
520 #define G_FW_PARAMS_PARAM_Y(x) \
521 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
523 #define S_FW_PARAMS_PARAM_Z 0
524 #define M_FW_PARAMS_PARAM_Z 0xff
525 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
526 #define G_FW_PARAMS_PARAM_Z(x) \
527 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
529 #define S_FW_PARAMS_PARAM_YZ 0
530 #define M_FW_PARAMS_PARAM_YZ 0xffff
531 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
532 #define G_FW_PARAMS_PARAM_YZ(x) \
533 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
535 struct fw_params_cmd {
538 struct fw_params_param {
544 #define S_FW_PARAMS_CMD_PFN 8
545 #define M_FW_PARAMS_CMD_PFN 0x7
546 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
547 #define G_FW_PARAMS_CMD_PFN(x) \
548 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
550 #define S_FW_PARAMS_CMD_VFN 0
551 #define M_FW_PARAMS_CMD_VFN 0xff
552 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
553 #define G_FW_PARAMS_CMD_VFN(x) \
554 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
557 * ingress queue type; the first 1K ingress queues can have associated 0,
558 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
562 FW_IQ_TYPE_FL_INT_CAP,
567 __be32 alloc_to_len16;
572 __be32 type_to_iqandstindex;
573 __be16 iqdroprss_to_iqesize;
576 __be32 iqns_to_fl0congen;
577 __be16 fl0dcaen_to_fl0cidxfthresh;
580 __be32 fl1cngchmap_to_fl1congen;
581 __be16 fl1dcaen_to_fl1cidxfthresh;
586 #define S_FW_IQ_CMD_PFN 8
587 #define M_FW_IQ_CMD_PFN 0x7
588 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
589 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
591 #define S_FW_IQ_CMD_VFN 0
592 #define M_FW_IQ_CMD_VFN 0xff
593 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
594 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
596 #define S_FW_IQ_CMD_ALLOC 31
597 #define M_FW_IQ_CMD_ALLOC 0x1
598 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
599 #define G_FW_IQ_CMD_ALLOC(x) \
600 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
601 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
603 #define S_FW_IQ_CMD_FREE 30
604 #define M_FW_IQ_CMD_FREE 0x1
605 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
606 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
607 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
609 #define S_FW_IQ_CMD_IQSTART 28
610 #define M_FW_IQ_CMD_IQSTART 0x1
611 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
612 #define G_FW_IQ_CMD_IQSTART(x) \
613 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
614 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
616 #define S_FW_IQ_CMD_IQSTOP 27
617 #define M_FW_IQ_CMD_IQSTOP 0x1
618 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
619 #define G_FW_IQ_CMD_IQSTOP(x) \
620 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
621 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
623 #define S_FW_IQ_CMD_TYPE 29
624 #define M_FW_IQ_CMD_TYPE 0x7
625 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
626 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
628 #define S_FW_IQ_CMD_IQASYNCH 28
629 #define M_FW_IQ_CMD_IQASYNCH 0x1
630 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
631 #define G_FW_IQ_CMD_IQASYNCH(x) \
632 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
633 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
635 #define S_FW_IQ_CMD_VIID 16
636 #define M_FW_IQ_CMD_VIID 0xfff
637 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
638 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
640 #define S_FW_IQ_CMD_IQANDST 15
641 #define M_FW_IQ_CMD_IQANDST 0x1
642 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
643 #define G_FW_IQ_CMD_IQANDST(x) \
644 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
645 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
647 #define S_FW_IQ_CMD_IQANUD 12
648 #define M_FW_IQ_CMD_IQANUD 0x3
649 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
650 #define G_FW_IQ_CMD_IQANUD(x) \
651 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
653 #define S_FW_IQ_CMD_IQANDSTINDEX 0
654 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
655 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
656 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
657 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
659 #define S_FW_IQ_CMD_IQGTSMODE 14
660 #define M_FW_IQ_CMD_IQGTSMODE 0x1
661 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
662 #define G_FW_IQ_CMD_IQGTSMODE(x) \
663 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
664 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
666 #define S_FW_IQ_CMD_IQPCIECH 12
667 #define M_FW_IQ_CMD_IQPCIECH 0x3
668 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
669 #define G_FW_IQ_CMD_IQPCIECH(x) \
670 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
672 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
673 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
674 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
675 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
676 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
678 #define S_FW_IQ_CMD_IQESIZE 0
679 #define M_FW_IQ_CMD_IQESIZE 0x3
680 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
681 #define G_FW_IQ_CMD_IQESIZE(x) \
682 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
684 #define S_FW_IQ_CMD_IQRO 30
685 #define M_FW_IQ_CMD_IQRO 0x1
686 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
687 #define G_FW_IQ_CMD_IQRO(x) \
688 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
689 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
691 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
692 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
693 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
694 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
695 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
696 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
698 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
699 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
700 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
701 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
702 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
704 #define S_FW_IQ_CMD_FL0DATARO 12
705 #define M_FW_IQ_CMD_FL0DATARO 0x1
706 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
707 #define G_FW_IQ_CMD_FL0DATARO(x) \
708 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
709 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
711 #define S_FW_IQ_CMD_FL0CONGCIF 11
712 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
713 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
714 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
715 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
716 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
718 #define S_FW_IQ_CMD_FL0FETCHRO 6
719 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
720 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
721 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
722 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
723 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
725 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
726 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
727 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
728 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
729 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
731 #define S_FW_IQ_CMD_FL0PADEN 2
732 #define M_FW_IQ_CMD_FL0PADEN 0x1
733 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
734 #define G_FW_IQ_CMD_FL0PADEN(x) \
735 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
736 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
738 #define S_FW_IQ_CMD_FL0PACKEN 1
739 #define M_FW_IQ_CMD_FL0PACKEN 0x1
740 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
741 #define G_FW_IQ_CMD_FL0PACKEN(x) \
742 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
743 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
745 #define S_FW_IQ_CMD_FL0CONGEN 0
746 #define M_FW_IQ_CMD_FL0CONGEN 0x1
747 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
748 #define G_FW_IQ_CMD_FL0CONGEN(x) \
749 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
750 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
752 #define S_FW_IQ_CMD_FL0FBMIN 7
753 #define M_FW_IQ_CMD_FL0FBMIN 0x7
754 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
755 #define G_FW_IQ_CMD_FL0FBMIN(x) \
756 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
758 #define S_FW_IQ_CMD_FL0FBMAX 4
759 #define M_FW_IQ_CMD_FL0FBMAX 0x7
760 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
761 #define G_FW_IQ_CMD_FL0FBMAX(x) \
762 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
764 struct fw_eq_eth_cmd {
766 __be32 alloc_to_len16;
769 __be32 fetchszm_to_iqid;
770 __be32 dcaen_to_eqsize;
772 __be32 autoequiqe_to_viid;
777 #define S_FW_EQ_ETH_CMD_PFN 8
778 #define M_FW_EQ_ETH_CMD_PFN 0x7
779 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
780 #define G_FW_EQ_ETH_CMD_PFN(x) \
781 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
783 #define S_FW_EQ_ETH_CMD_VFN 0
784 #define M_FW_EQ_ETH_CMD_VFN 0xff
785 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
786 #define G_FW_EQ_ETH_CMD_VFN(x) \
787 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
789 #define S_FW_EQ_ETH_CMD_ALLOC 31
790 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
791 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
792 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
793 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
794 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
796 #define S_FW_EQ_ETH_CMD_FREE 30
797 #define M_FW_EQ_ETH_CMD_FREE 0x1
798 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
799 #define G_FW_EQ_ETH_CMD_FREE(x) \
800 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
801 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
803 #define S_FW_EQ_ETH_CMD_EQSTART 28
804 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
805 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
806 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
807 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
808 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
810 #define S_FW_EQ_ETH_CMD_EQID 0
811 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
812 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
813 #define G_FW_EQ_ETH_CMD_EQID(x) \
814 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
816 #define S_FW_EQ_ETH_CMD_FETCHRO 22
817 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
818 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
819 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
820 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
821 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
823 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
824 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
825 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
826 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
827 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
829 #define S_FW_EQ_ETH_CMD_PCIECHN 16
830 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
831 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
832 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
833 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
835 #define S_FW_EQ_ETH_CMD_IQID 0
836 #define M_FW_EQ_ETH_CMD_IQID 0xffff
837 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
838 #define G_FW_EQ_ETH_CMD_IQID(x) \
839 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
841 #define S_FW_EQ_ETH_CMD_FBMIN 23
842 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
843 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
844 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
845 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
847 #define S_FW_EQ_ETH_CMD_FBMAX 20
848 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
849 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
850 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
851 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
853 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
854 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
855 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
856 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
857 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
859 #define S_FW_EQ_ETH_CMD_EQSIZE 0
860 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
861 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
862 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
863 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
865 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
866 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
867 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
868 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
869 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
870 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
872 #define S_FW_EQ_ETH_CMD_VIID 16
873 #define M_FW_EQ_ETH_CMD_VIID 0xfff
874 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
875 #define G_FW_EQ_ETH_CMD_VIID(x) \
876 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
884 __be32 alloc_to_len16;
890 __be16 norss_rsssize;
900 #define S_FW_VI_CMD_PFN 8
901 #define M_FW_VI_CMD_PFN 0x7
902 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
903 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
905 #define S_FW_VI_CMD_VFN 0
906 #define M_FW_VI_CMD_VFN 0xff
907 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
908 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
910 #define S_FW_VI_CMD_ALLOC 31
911 #define M_FW_VI_CMD_ALLOC 0x1
912 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
913 #define G_FW_VI_CMD_ALLOC(x) \
914 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
915 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
917 #define S_FW_VI_CMD_FREE 30
918 #define M_FW_VI_CMD_FREE 0x1
919 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
920 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
921 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
923 #define S_FW_VI_CMD_TYPE 15
924 #define M_FW_VI_CMD_TYPE 0x1
925 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
926 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
927 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
929 #define S_FW_VI_CMD_FUNC 12
930 #define M_FW_VI_CMD_FUNC 0x7
931 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
932 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
934 #define S_FW_VI_CMD_VIID 0
935 #define M_FW_VI_CMD_VIID 0xfff
936 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
937 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
939 #define S_FW_VI_CMD_PORTID 4
940 #define M_FW_VI_CMD_PORTID 0xf
941 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
942 #define G_FW_VI_CMD_PORTID(x) \
943 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
945 #define S_FW_VI_CMD_RSSSIZE 0
946 #define M_FW_VI_CMD_RSSSIZE 0x7ff
947 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
948 #define G_FW_VI_CMD_RSSSIZE(x) \
949 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
951 /* Special VI_MAC command index ids */
952 #define FW_VI_MAC_ADD_MAC 0x3FF
953 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
955 enum fw_vi_mac_smac {
956 FW_VI_MAC_MPS_TCAM_ENTRY,
957 FW_VI_MAC_SMT_AND_MPSTCAM
960 struct fw_vi_mac_cmd {
962 __be32 freemacs_to_len16;
964 struct fw_vi_mac_exact {
968 struct fw_vi_mac_hash {
974 #define S_FW_VI_MAC_CMD_VIID 0
975 #define M_FW_VI_MAC_CMD_VIID 0xfff
976 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
977 #define G_FW_VI_MAC_CMD_VIID(x) \
978 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
980 #define S_FW_VI_MAC_CMD_VALID 15
981 #define M_FW_VI_MAC_CMD_VALID 0x1
982 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
983 #define G_FW_VI_MAC_CMD_VALID(x) \
984 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
985 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
987 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
988 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
989 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
990 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
991 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
993 #define S_FW_VI_MAC_CMD_IDX 0
994 #define M_FW_VI_MAC_CMD_IDX 0x3ff
995 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
996 #define G_FW_VI_MAC_CMD_IDX(x) \
997 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
999 struct fw_vi_rxmode_cmd {
1001 __be32 retval_len16;
1002 __be32 mtu_to_vlanexen;
1006 #define S_FW_VI_RXMODE_CMD_VIID 0
1007 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1008 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1009 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1010 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1012 #define S_FW_VI_RXMODE_CMD_MTU 16
1013 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1014 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1015 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1016 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1018 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1019 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1020 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1021 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1022 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1024 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1025 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1026 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1027 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1028 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1029 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1031 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1032 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1033 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1034 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1035 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1036 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1037 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1039 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1040 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1041 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1042 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1043 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1045 struct fw_vi_enable_cmd {
1047 __be32 ien_to_len16;
1053 #define S_FW_VI_ENABLE_CMD_VIID 0
1054 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1055 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1056 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1057 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1059 #define S_FW_VI_ENABLE_CMD_IEN 31
1060 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1061 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1062 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1063 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1064 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1066 #define S_FW_VI_ENABLE_CMD_EEN 30
1067 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1068 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1069 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1070 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1071 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1073 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1074 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1075 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1076 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1077 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1078 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1080 /* VI PF stats offset definitions */
1081 #define VI_PF_NUM_STATS 17
1082 enum fw_vi_stats_pf_index {
1083 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1084 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1085 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1086 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1087 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1088 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1089 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1090 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1091 FW_VI_PF_STAT_RX_BYTES_IX,
1092 FW_VI_PF_STAT_RX_FRAMES_IX,
1093 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1094 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1095 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1096 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1097 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1098 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1099 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1102 struct fw_vi_stats_cmd {
1104 __be32 retval_len16;
1106 struct fw_vi_stats_ctl {
1117 struct fw_vi_stats_pf {
1118 __be64 tx_bcast_bytes;
1119 __be64 tx_bcast_frames;
1120 __be64 tx_mcast_bytes;
1121 __be64 tx_mcast_frames;
1122 __be64 tx_ucast_bytes;
1123 __be64 tx_ucast_frames;
1124 __be64 tx_offload_bytes;
1125 __be64 tx_offload_frames;
1127 __be64 rx_pf_frames;
1128 __be64 rx_bcast_bytes;
1129 __be64 rx_bcast_frames;
1130 __be64 rx_mcast_bytes;
1131 __be64 rx_mcast_frames;
1132 __be64 rx_ucast_bytes;
1133 __be64 rx_ucast_frames;
1134 __be64 rx_err_frames;
1136 struct fw_vi_stats_vf {
1137 __be64 tx_bcast_bytes;
1138 __be64 tx_bcast_frames;
1139 __be64 tx_mcast_bytes;
1140 __be64 tx_mcast_frames;
1141 __be64 tx_ucast_bytes;
1142 __be64 tx_ucast_frames;
1143 __be64 tx_drop_frames;
1144 __be64 tx_offload_bytes;
1145 __be64 tx_offload_frames;
1146 __be64 rx_bcast_bytes;
1147 __be64 rx_bcast_frames;
1148 __be64 rx_mcast_bytes;
1149 __be64 rx_mcast_frames;
1150 __be64 rx_ucast_bytes;
1151 __be64 rx_ucast_frames;
1152 __be64 rx_err_frames;
1157 /* old 16-bit port capabilities bitmap */
1159 FW_PORT_CAP_SPEED_100M = 0x0001,
1160 FW_PORT_CAP_SPEED_1G = 0x0002,
1161 FW_PORT_CAP_SPEED_25G = 0x0004,
1162 FW_PORT_CAP_SPEED_10G = 0x0008,
1163 FW_PORT_CAP_SPEED_40G = 0x0010,
1164 FW_PORT_CAP_SPEED_100G = 0x0020,
1165 FW_PORT_CAP_FC_RX = 0x0040,
1166 FW_PORT_CAP_FC_TX = 0x0080,
1167 FW_PORT_CAP_ANEG = 0x0100,
1168 FW_PORT_CAP_MDIX = 0x0200,
1169 FW_PORT_CAP_MDIAUTO = 0x0400,
1170 FW_PORT_CAP_FEC_RS = 0x0800,
1171 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1172 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1173 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1174 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1177 #define S_FW_PORT_CAP_SPEED 0
1178 #define M_FW_PORT_CAP_SPEED 0x3f
1179 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1180 #define G_FW_PORT_CAP_SPEED(x) \
1181 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1184 FW_PORT_CAP_MDI_AUTO,
1187 #define S_FW_PORT_CAP_MDI 9
1188 #define M_FW_PORT_CAP_MDI 3
1189 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1190 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1192 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1193 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1194 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1195 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1196 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1197 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1198 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1199 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1200 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1201 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1202 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1203 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1204 #define FW_PORT_CAP32_ANEG 0x00100000UL
1205 #define FW_PORT_CAP32_MDIX 0x00200000UL
1206 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1207 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1208 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1210 #define S_FW_PORT_CAP32_SPEED 0
1211 #define M_FW_PORT_CAP32_SPEED 0xfff
1212 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1213 #define G_FW_PORT_CAP32_SPEED(x) \
1214 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1216 enum fw_port_mdi32 {
1217 FW_PORT_CAP32_MDI_AUTO,
1220 #define S_FW_PORT_CAP32_MDI 21
1221 #define M_FW_PORT_CAP32_MDI 3
1222 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1223 #define G_FW_PORT_CAP32_MDI(x) \
1224 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1226 enum fw_port_action {
1227 FW_PORT_ACTION_L1_CFG = 0x0001,
1228 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1231 struct fw_port_cmd {
1232 __be32 op_to_portid;
1233 __be32 action_to_len16;
1235 struct fw_port_l1cfg {
1239 struct fw_port_l2cfg {
1241 __u8 ovlan3_to_ivlan0;
1243 __be16 txipg_force_pinfo;
1254 struct fw_port_info {
1255 __be32 lstatus_to_modtype;
1266 struct fw_port_diags {
1272 struct fw_port_dcb_pgid {
1279 struct fw_port_dcb_pgrate {
1283 __u8 num_tcs_supported;
1287 struct fw_port_dcb_priorate {
1291 __u8 strict_priorate[8];
1293 struct fw_port_dcb_pfc {
1300 struct fw_port_app_priority {
1309 struct fw_port_dcb_control {
1312 __be16 dcb_version_to_app_state;
1320 #define S_FW_PORT_CMD_PORTID 0
1321 #define M_FW_PORT_CMD_PORTID 0xf
1322 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1323 #define G_FW_PORT_CMD_PORTID(x) \
1324 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1326 #define S_FW_PORT_CMD_ACTION 16
1327 #define M_FW_PORT_CMD_ACTION 0xffff
1328 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1329 #define G_FW_PORT_CMD_ACTION(x) \
1330 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1332 #define S_FW_PORT_CMD_LSTATUS 31
1333 #define M_FW_PORT_CMD_LSTATUS 0x1
1334 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1335 #define G_FW_PORT_CMD_LSTATUS(x) \
1336 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1337 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1339 #define S_FW_PORT_CMD_LSPEED 24
1340 #define M_FW_PORT_CMD_LSPEED 0x3f
1341 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1342 #define G_FW_PORT_CMD_LSPEED(x) \
1343 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1345 #define S_FW_PORT_CMD_TXPAUSE 23
1346 #define M_FW_PORT_CMD_TXPAUSE 0x1
1347 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1348 #define G_FW_PORT_CMD_TXPAUSE(x) \
1349 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1350 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1352 #define S_FW_PORT_CMD_RXPAUSE 22
1353 #define M_FW_PORT_CMD_RXPAUSE 0x1
1354 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1355 #define G_FW_PORT_CMD_RXPAUSE(x) \
1356 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1357 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1359 #define S_FW_PORT_CMD_MDIOCAP 21
1360 #define M_FW_PORT_CMD_MDIOCAP 0x1
1361 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1362 #define G_FW_PORT_CMD_MDIOCAP(x) \
1363 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1364 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1366 #define S_FW_PORT_CMD_MDIOADDR 16
1367 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1368 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1369 #define G_FW_PORT_CMD_MDIOADDR(x) \
1370 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1372 #define S_FW_PORT_CMD_PTYPE 8
1373 #define M_FW_PORT_CMD_PTYPE 0x1f
1374 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1375 #define G_FW_PORT_CMD_PTYPE(x) \
1376 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1378 #define S_FW_PORT_CMD_LINKDNRC 5
1379 #define M_FW_PORT_CMD_LINKDNRC 0x7
1380 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1381 #define G_FW_PORT_CMD_LINKDNRC(x) \
1382 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1384 #define S_FW_PORT_CMD_MODTYPE 0
1385 #define M_FW_PORT_CMD_MODTYPE 0x1f
1386 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1387 #define G_FW_PORT_CMD_MODTYPE(x) \
1388 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1391 * These are configured into the VPD and hence tools that generate
1392 * VPD may use this enumeration.
1393 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1396 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1397 * with any new Firmware Port Technology Types!
1400 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1401 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1402 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1403 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1404 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1405 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1406 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1407 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1408 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1409 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1410 FW_PORT_TYPE_BP_AP = 10,
1411 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1412 FW_PORT_TYPE_BP4_AP = 11,
1413 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1414 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1415 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1416 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1417 FW_PORT_TYPE_BP40_BA = 15,
1418 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1419 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1420 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1421 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1422 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1423 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1424 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1425 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1428 /* These are read from module's EEPROM and determined once the
1429 * module is inserted.
1431 enum fw_port_module_type {
1432 FW_PORT_MOD_TYPE_NA = 0x0,
1433 FW_PORT_MOD_TYPE_LR = 0x1,
1434 FW_PORT_MOD_TYPE_SR = 0x2,
1435 FW_PORT_MOD_TYPE_ER = 0x3,
1436 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1437 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1438 FW_PORT_MOD_TYPE_LRM = 0x6,
1439 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1440 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1441 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1442 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1445 /* used by FW and tools may use this to generate VPD */
1446 enum fw_port_mod_sub_type {
1447 FW_PORT_MOD_SUB_TYPE_NA,
1448 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1449 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1450 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1451 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1452 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1453 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1454 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1455 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1458 * The following will never been in the VPD. They are TWINAX cable
1459 * lengths decoded from SFP+ module i2c PROMs. These should almost
1460 * certainly go somewhere else ...
1462 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1463 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1464 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1465 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1468 /* link down reason codes (3b) */
1469 enum fw_port_link_dn_rc {
1470 FW_PORT_LINK_DN_RC_NONE,
1471 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1472 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1473 FW_PORT_LINK_DN_RESERVED3,
1474 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1475 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1476 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1477 FW_PORT_LINK_DN_RESERVED7
1481 #define FW_NUM_PORT_STATS 50
1482 #define FW_NUM_PORT_TX_STATS 23
1483 #define FW_NUM_PORT_RX_STATS 27
1485 enum fw_port_stats_tx_index {
1486 FW_STAT_TX_PORT_BYTES_IX,
1487 FW_STAT_TX_PORT_FRAMES_IX,
1488 FW_STAT_TX_PORT_BCAST_IX,
1489 FW_STAT_TX_PORT_MCAST_IX,
1490 FW_STAT_TX_PORT_UCAST_IX,
1491 FW_STAT_TX_PORT_ERROR_IX,
1492 FW_STAT_TX_PORT_64B_IX,
1493 FW_STAT_TX_PORT_65B_127B_IX,
1494 FW_STAT_TX_PORT_128B_255B_IX,
1495 FW_STAT_TX_PORT_256B_511B_IX,
1496 FW_STAT_TX_PORT_512B_1023B_IX,
1497 FW_STAT_TX_PORT_1024B_1518B_IX,
1498 FW_STAT_TX_PORT_1519B_MAX_IX,
1499 FW_STAT_TX_PORT_DROP_IX,
1500 FW_STAT_TX_PORT_PAUSE_IX,
1501 FW_STAT_TX_PORT_PPP0_IX,
1502 FW_STAT_TX_PORT_PPP1_IX,
1503 FW_STAT_TX_PORT_PPP2_IX,
1504 FW_STAT_TX_PORT_PPP3_IX,
1505 FW_STAT_TX_PORT_PPP4_IX,
1506 FW_STAT_TX_PORT_PPP5_IX,
1507 FW_STAT_TX_PORT_PPP6_IX,
1508 FW_STAT_TX_PORT_PPP7_IX
1511 enum fw_port_stat_rx_index {
1512 FW_STAT_RX_PORT_BYTES_IX,
1513 FW_STAT_RX_PORT_FRAMES_IX,
1514 FW_STAT_RX_PORT_BCAST_IX,
1515 FW_STAT_RX_PORT_MCAST_IX,
1516 FW_STAT_RX_PORT_UCAST_IX,
1517 FW_STAT_RX_PORT_MTU_ERROR_IX,
1518 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1519 FW_STAT_RX_PORT_CRC_ERROR_IX,
1520 FW_STAT_RX_PORT_LEN_ERROR_IX,
1521 FW_STAT_RX_PORT_SYM_ERROR_IX,
1522 FW_STAT_RX_PORT_64B_IX,
1523 FW_STAT_RX_PORT_65B_127B_IX,
1524 FW_STAT_RX_PORT_128B_255B_IX,
1525 FW_STAT_RX_PORT_256B_511B_IX,
1526 FW_STAT_RX_PORT_512B_1023B_IX,
1527 FW_STAT_RX_PORT_1024B_1518B_IX,
1528 FW_STAT_RX_PORT_1519B_MAX_IX,
1529 FW_STAT_RX_PORT_PAUSE_IX,
1530 FW_STAT_RX_PORT_PPP0_IX,
1531 FW_STAT_RX_PORT_PPP1_IX,
1532 FW_STAT_RX_PORT_PPP2_IX,
1533 FW_STAT_RX_PORT_PPP3_IX,
1534 FW_STAT_RX_PORT_PPP4_IX,
1535 FW_STAT_RX_PORT_PPP5_IX,
1536 FW_STAT_RX_PORT_PPP6_IX,
1537 FW_STAT_RX_PORT_PPP7_IX,
1538 FW_STAT_RX_PORT_LESS_64B_IX
1541 struct fw_port_stats_cmd {
1542 __be32 op_to_portid;
1543 __be32 retval_len16;
1544 union fw_port_stats {
1545 struct fw_port_stats_ctl {
1557 struct fw_port_stats_all {
1566 __be64 tx_128b_255b;
1567 __be64 tx_256b_511b;
1568 __be64 tx_512b_1023b;
1569 __be64 tx_1024b_1518b;
1570 __be64 tx_1519b_max;
1586 __be64 rx_mtu_error;
1587 __be64 rx_mtu_crc_error;
1588 __be64 rx_crc_error;
1589 __be64 rx_len_error;
1590 __be64 rx_sym_error;
1593 __be64 rx_128b_255b;
1594 __be64 rx_256b_511b;
1595 __be64 rx_512b_1023b;
1596 __be64 rx_1024b_1518b;
1597 __be64 rx_1519b_max;
1614 struct fw_rss_ind_tbl_cmd {
1616 __be32 retval_len16;
1624 __be32 iq12_to_iq14;
1625 __be32 iq15_to_iq17;
1626 __be32 iq18_to_iq20;
1627 __be32 iq21_to_iq23;
1628 __be32 iq24_to_iq26;
1629 __be32 iq27_to_iq29;
1634 #define S_FW_RSS_IND_TBL_CMD_VIID 0
1635 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
1636 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
1637 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
1638 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
1640 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
1641 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
1642 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
1643 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
1644 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
1646 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
1647 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
1648 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
1649 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
1650 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
1652 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
1653 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
1654 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
1655 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
1656 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
1658 struct fw_rss_vi_config_cmd {
1660 __be32 retval_len16;
1661 union fw_rss_vi_config {
1662 struct fw_rss_vi_config_manual {
1667 struct fw_rss_vi_config_basicvirtual {
1669 __be32 defaultq_to_udpen;
1676 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
1677 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
1678 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
1679 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
1680 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
1682 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
1683 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
1684 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1685 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1686 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
1687 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
1688 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
1690 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
1691 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
1692 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1693 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1694 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
1695 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
1696 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1697 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
1698 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
1700 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
1701 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
1702 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1703 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1704 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
1705 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
1706 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1707 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
1708 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
1710 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
1711 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
1712 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
1713 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1714 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
1715 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
1716 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1717 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
1718 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
1720 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
1721 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
1722 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
1723 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1724 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
1725 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
1726 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1727 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
1728 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
1730 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
1731 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
1732 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
1733 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
1734 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
1735 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
1737 /******************************************************************************
1738 * D E B U G C O M M A N D s
1739 ******************************************************/
1741 struct fw_debug_cmd {
1745 struct fw_debug_assert {
1750 __u8 filename_0_7[8];
1751 __u8 filename_8_15[8];
1754 struct fw_debug_prt {
1757 __be32 dprtstrparam0;
1758 __be32 dprtstrparam1;
1759 __be32 dprtstrparam2;
1760 __be32 dprtstrparam3;
1765 #define S_FW_DEBUG_CMD_TYPE 0
1766 #define M_FW_DEBUG_CMD_TYPE 0xff
1767 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
1768 #define G_FW_DEBUG_CMD_TYPE(x) \
1769 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
1771 /******************************************************************************
1772 * P C I E F W R E G I S T E R
1773 **************************************/
1776 * Register definitions for the PCIE_FW register which the firmware uses
1777 * to retain status across RESETs. This register should be considered
1778 * as a READ-ONLY register for Host Software and only to be used to
1779 * track firmware initialization/error state, etc.
1781 #define S_PCIE_FW_ERR 31
1782 #define M_PCIE_FW_ERR 0x1
1783 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
1784 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
1785 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
1787 #define S_PCIE_FW_INIT 30
1788 #define M_PCIE_FW_INIT 0x1
1789 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
1790 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
1791 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
1793 #define S_PCIE_FW_HALT 29
1794 #define M_PCIE_FW_HALT 0x1
1795 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
1796 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
1797 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
1799 #define S_PCIE_FW_EVAL 24
1800 #define M_PCIE_FW_EVAL 0x7
1801 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
1802 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
1804 #define S_PCIE_FW_MASTER_VLD 15
1805 #define M_PCIE_FW_MASTER_VLD 0x1
1806 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
1807 #define G_PCIE_FW_MASTER_VLD(x) \
1808 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
1809 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
1811 #define S_PCIE_FW_MASTER 12
1812 #define M_PCIE_FW_MASTER 0x7
1813 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
1814 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
1816 /******************************************************************************
1817 * B I N A R Y H E A D E R F O R M A T
1818 **********************************************/
1821 * firmware binary header format
1825 __u8 chip; /* terminator chip family */
1826 __be16 len512; /* bin length in units of 512-bytes */
1827 __be32 fw_ver; /* firmware version */
1828 __be32 tp_microcode_ver; /* tcp processor microcode version */
1833 __u8 intfver_iscsipdu;
1835 __u8 intfver_fcoepdu;
1839 __u32 magic; /* runtime or bootstrap fw */
1841 __be32 reserved6[23];
1844 #define S_FW_HDR_FW_VER_MAJOR 24
1845 #define M_FW_HDR_FW_VER_MAJOR 0xff
1846 #define V_FW_HDR_FW_VER_MAJOR(x) \
1847 ((x) << S_FW_HDR_FW_VER_MAJOR)
1848 #define G_FW_HDR_FW_VER_MAJOR(x) \
1849 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
1851 #define S_FW_HDR_FW_VER_MINOR 16
1852 #define M_FW_HDR_FW_VER_MINOR 0xff
1853 #define V_FW_HDR_FW_VER_MINOR(x) \
1854 ((x) << S_FW_HDR_FW_VER_MINOR)
1855 #define G_FW_HDR_FW_VER_MINOR(x) \
1856 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
1858 #define S_FW_HDR_FW_VER_MICRO 8
1859 #define M_FW_HDR_FW_VER_MICRO 0xff
1860 #define V_FW_HDR_FW_VER_MICRO(x) \
1861 ((x) << S_FW_HDR_FW_VER_MICRO)
1862 #define G_FW_HDR_FW_VER_MICRO(x) \
1863 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
1865 #define S_FW_HDR_FW_VER_BUILD 0
1866 #define M_FW_HDR_FW_VER_BUILD 0xff
1867 #define V_FW_HDR_FW_VER_BUILD(x) \
1868 ((x) << S_FW_HDR_FW_VER_BUILD)
1869 #define G_FW_HDR_FW_VER_BUILD(x) \
1870 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
1872 #endif /* _T4FW_INTERFACE_H_ */