1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
60 FW_ETH_TX_PKT_WR = 0x08,
61 FW_ETH_TX_PKTS_WR = 0x09,
62 FW_ETH_TX_PKT_VM_WR = 0x11,
63 FW_ETH_TX_PKTS_VM_WR = 0x12,
65 FW_ETH_TX_PKTS2_WR = 0x78,
69 * Generic work request header flit0
76 /* work request opcode (hi)
79 #define M_FW_WR_OP 0xff
80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
81 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
83 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
85 #define S_FW_WR_ATOMIC 23
86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
88 /* work request immediate data length (hi)
90 #define S_FW_WR_IMMDLEN 0
91 #define M_FW_WR_IMMDLEN 0xff
92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
93 #define G_FW_WR_IMMDLEN(x) \
94 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
96 /* egress queue status update to egress queue status entry (lo)
98 #define S_FW_WR_EQUEQ 30
99 #define M_FW_WR_EQUEQ 0x1
100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
101 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
102 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
104 /* flow context identifier (lo)
106 #define S_FW_WR_FLOWID 8
107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
109 /* length in units of 16-bytes (lo)
111 #define S_FW_WR_LEN16 0
112 #define M_FW_WR_LEN16 0xff
113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
114 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
116 struct fw_eth_tx_pkt_wr {
118 __be32 equiq_to_len16;
122 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
123 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
124 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
125 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
126 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
128 struct fw_eth_tx_pkts_wr {
130 __be32 equiq_to_len16;
137 struct fw_eth_tx_pkt_vm_wr {
139 __be32 equiq_to_len16;
147 struct fw_eth_tx_pkts_vm_wr {
149 __be32 equiq_to_len16;
160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
161 enum fw_filter_wr_cookie {
162 FW_FILTER_WR_SUCCESS,
163 FW_FILTER_WR_FLT_ADDED,
164 FW_FILTER_WR_FLT_DELETED,
165 FW_FILTER_WR_SMT_TBL_FULL,
169 struct fw_filter2_wr {
174 __be32 del_filter_to_l2tix;
177 __u8 frag_to_ovlan_vldm;
179 __be16 rx_chan_rx_rpl_iq;
180 __be32 maci_to_matchtypem;
200 __u8 filter_type_swapmac;
201 __u8 natmode_to_ulp_type;
214 #define S_FW_FILTER_WR_TID 12
215 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
217 #define S_FW_FILTER_WR_RQTYPE 11
218 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
220 #define S_FW_FILTER_WR_NOREPLY 10
221 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
223 #define S_FW_FILTER_WR_IQ 0
224 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
226 #define S_FW_FILTER_WR_DEL_FILTER 31
227 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
228 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
230 #define S_FW_FILTER_WR_RPTTID 25
231 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
233 #define S_FW_FILTER_WR_DROP 24
234 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
236 #define S_FW_FILTER_WR_DIRSTEER 23
237 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
239 #define S_FW_FILTER_WR_MASKHASH 22
240 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
242 #define S_FW_FILTER_WR_DIRSTEERHASH 21
243 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
245 #define S_FW_FILTER_WR_LPBK 20
246 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
248 #define S_FW_FILTER_WR_DMAC 19
249 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
251 #define S_FW_FILTER_WR_SMAC 18
252 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC)
254 #define S_FW_FILTER_WR_INSVLAN 17
255 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
257 #define S_FW_FILTER_WR_RMVLAN 16
258 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
260 #define S_FW_FILTER_WR_HITCNTS 15
261 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
263 #define S_FW_FILTER_WR_TXCHAN 13
264 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
266 #define S_FW_FILTER_WR_PRIO 12
267 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
269 #define S_FW_FILTER_WR_L2TIX 0
270 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
272 #define S_FW_FILTER_WR_FRAG 7
273 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
275 #define S_FW_FILTER_WR_FRAGM 6
276 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
278 #define S_FW_FILTER_WR_IVLAN_VLD 5
279 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
281 #define S_FW_FILTER_WR_OVLAN_VLD 4
282 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
284 #define S_FW_FILTER_WR_IVLAN_VLDM 3
285 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
287 #define S_FW_FILTER_WR_OVLAN_VLDM 2
288 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
290 #define S_FW_FILTER_WR_RX_CHAN 15
291 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
293 #define S_FW_FILTER_WR_RX_RPL_IQ 0
294 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
296 #define S_FW_FILTER_WR_MACI 23
297 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
299 #define S_FW_FILTER_WR_MACIM 14
300 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
302 #define S_FW_FILTER_WR_FCOE 13
303 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
305 #define S_FW_FILTER_WR_FCOEM 12
306 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
308 #define S_FW_FILTER_WR_PORT 9
309 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
311 #define S_FW_FILTER_WR_PORTM 6
312 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
314 #define S_FW_FILTER_WR_MATCHTYPE 3
315 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
317 #define S_FW_FILTER_WR_MATCHTYPEM 0
318 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
320 #define S_FW_FILTER2_WR_SWAPMAC 0
321 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
323 #define S_FW_FILTER2_WR_NATMODE 5
324 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
326 #define S_FW_FILTER2_WR_ULP_TYPE 0
327 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
329 /******************************************************************************
331 *********************/
334 * The maximum length of time, in miliseconds, that we expect any firmware
335 * command to take to execute and return a reply to the host. The RESET
336 * and INITIALIZE commands can take a fair amount of time to execute but
337 * most execute in far less time than this maximum. This constant is used
338 * by host software to determine how long to wait for a firmware command
339 * reply before declaring the firmware as dead/unreachable ...
341 #define FW_CMD_MAX_TIMEOUT 10000
344 * If a host driver does a HELLO and discovers that there's already a MASTER
345 * selected, we may have to wait for that MASTER to finish issuing RESET,
346 * configuration and INITIALIZE commands. Also, there's a possibility that
347 * our own HELLO may get lost if it happens right as the MASTER is issuign a
348 * RESET command, so we need to be willing to make a few retries of our HELLO.
350 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
351 #define FW_CMD_HELLO_RETRIES 3
353 enum fw_cmd_opcodes {
358 FW_INITIALIZE_CMD = 0x06,
359 FW_CAPS_CONFIG_CMD = 0x07,
360 FW_PARAMS_CMD = 0x08,
363 FW_EQ_ETH_CMD = 0x12,
364 FW_EQ_CTRL_CMD = 0x13,
366 FW_VI_MAC_CMD = 0x15,
367 FW_VI_RXMODE_CMD = 0x16,
368 FW_VI_ENABLE_CMD = 0x17,
369 FW_VI_STATS_CMD = 0x1a,
371 FW_RSS_IND_TBL_CMD = 0x20,
372 FW_RSS_GLB_CONFIG_CMD = 0x22,
373 FW_RSS_VI_CONFIG_CMD = 0x23,
379 FW_CMD_CAP_PORT = 0x04,
383 * Generic command header flit0
390 #define S_FW_CMD_OP 24
391 #define M_FW_CMD_OP 0xff
392 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
393 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
395 #define S_FW_CMD_REQUEST 23
396 #define M_FW_CMD_REQUEST 0x1
397 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
398 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
399 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
401 #define S_FW_CMD_READ 22
402 #define M_FW_CMD_READ 0x1
403 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
404 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
405 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
407 #define S_FW_CMD_WRITE 21
408 #define M_FW_CMD_WRITE 0x1
409 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
410 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
411 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
413 #define S_FW_CMD_EXEC 20
414 #define M_FW_CMD_EXEC 0x1
415 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
416 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
417 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
419 #define S_FW_CMD_RETVAL 8
420 #define M_FW_CMD_RETVAL 0xff
421 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
422 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
424 #define S_FW_CMD_LEN16 0
425 #define M_FW_CMD_LEN16 0xff
426 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
427 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
429 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
433 enum fw_ldst_addrspc {
434 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
438 __be32 op_to_addrspace;
439 __be32 cycles_to_len16;
441 struct fw_ldst_addrval {
445 struct fw_ldst_idctxt {
447 __be32 msg_ctxtflush;
457 struct fw_ldst_mdio {
473 struct fw_ldst_func {
481 struct fw_ldst_pcie {
491 struct fw_ldst_i2c_deprecated {
515 #define S_FW_LDST_CMD_ADDRSPACE 0
516 #define M_FW_LDST_CMD_ADDRSPACE 0xff
517 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
519 struct fw_reset_cmd {
526 #define S_FW_RESET_CMD_HALT 31
527 #define M_FW_RESET_CMD_HALT 0x1
528 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
529 #define G_FW_RESET_CMD_HALT(x) \
530 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
531 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
534 FW_HELLO_CMD_STAGE_OS = 0,
537 struct fw_hello_cmd {
540 __be32 err_to_clearinit;
544 #define S_FW_HELLO_CMD_ERR 31
545 #define M_FW_HELLO_CMD_ERR 0x1
546 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
547 #define G_FW_HELLO_CMD_ERR(x) \
548 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
549 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
551 #define S_FW_HELLO_CMD_INIT 30
552 #define M_FW_HELLO_CMD_INIT 0x1
553 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
554 #define G_FW_HELLO_CMD_INIT(x) \
555 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
556 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
558 #define S_FW_HELLO_CMD_MASTERDIS 29
559 #define M_FW_HELLO_CMD_MASTERDIS 0x1
560 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
561 #define G_FW_HELLO_CMD_MASTERDIS(x) \
562 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
563 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
565 #define S_FW_HELLO_CMD_MASTERFORCE 28
566 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
567 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
568 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
569 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
570 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
572 #define S_FW_HELLO_CMD_MBMASTER 24
573 #define M_FW_HELLO_CMD_MBMASTER 0xf
574 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
575 #define G_FW_HELLO_CMD_MBMASTER(x) \
576 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
578 #define S_FW_HELLO_CMD_MBASYNCNOT 20
579 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
580 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
581 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
582 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
584 #define S_FW_HELLO_CMD_STAGE 17
585 #define M_FW_HELLO_CMD_STAGE 0x7
586 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
587 #define G_FW_HELLO_CMD_STAGE(x) \
588 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
590 #define S_FW_HELLO_CMD_CLEARINIT 16
591 #define M_FW_HELLO_CMD_CLEARINIT 0x1
592 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
593 #define G_FW_HELLO_CMD_CLEARINIT(x) \
594 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
595 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
603 struct fw_initialize_cmd {
609 enum fw_caps_config_nic {
610 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
611 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
615 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
618 struct fw_caps_config_cmd {
620 __be32 cfvalid_to_len16;
638 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
639 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
640 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
641 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
642 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
643 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
645 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
646 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
647 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
648 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
649 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
650 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
651 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
653 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
654 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
655 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
656 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
657 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
658 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
659 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
662 * params command mnemonics
664 enum fw_params_mnem {
665 FW_PARAMS_MNEM_DEV = 1, /* device params */
666 FW_PARAMS_MNEM_PFVF = 2, /* function params */
667 FW_PARAMS_MNEM_REG = 3, /* limited register access */
668 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
674 enum fw_params_param_dev {
675 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
676 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
677 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
678 * allocated by the device's
681 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
682 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
683 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
684 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
685 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
689 * physical and virtual function parameters
691 enum fw_params_param_pfvf {
692 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
693 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
694 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
695 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
696 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
697 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
698 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
699 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
700 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
701 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
702 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
706 * dma queue parameters
708 enum fw_params_param_dmaq {
709 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
710 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
713 #define S_FW_PARAMS_MNEM 24
714 #define M_FW_PARAMS_MNEM 0xff
715 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
716 #define G_FW_PARAMS_MNEM(x) \
717 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
719 #define S_FW_PARAMS_PARAM_X 16
720 #define M_FW_PARAMS_PARAM_X 0xff
721 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
722 #define G_FW_PARAMS_PARAM_X(x) \
723 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
725 #define S_FW_PARAMS_PARAM_Y 8
726 #define M_FW_PARAMS_PARAM_Y 0xff
727 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
728 #define G_FW_PARAMS_PARAM_Y(x) \
729 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
731 #define S_FW_PARAMS_PARAM_Z 0
732 #define M_FW_PARAMS_PARAM_Z 0xff
733 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
734 #define G_FW_PARAMS_PARAM_Z(x) \
735 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
737 #define S_FW_PARAMS_PARAM_YZ 0
738 #define M_FW_PARAMS_PARAM_YZ 0xffff
739 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
740 #define G_FW_PARAMS_PARAM_YZ(x) \
741 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
743 #define S_FW_PARAMS_PARAM_XYZ 0
744 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
745 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
747 struct fw_params_cmd {
750 struct fw_params_param {
756 #define S_FW_PARAMS_CMD_PFN 8
757 #define M_FW_PARAMS_CMD_PFN 0x7
758 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
759 #define G_FW_PARAMS_CMD_PFN(x) \
760 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
762 #define S_FW_PARAMS_CMD_VFN 0
763 #define M_FW_PARAMS_CMD_VFN 0xff
764 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
765 #define G_FW_PARAMS_CMD_VFN(x) \
766 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
773 __be32 tc_to_nexactf;
774 __be32 r_caps_to_nethctrl;
780 #define S_FW_PFVF_CMD_PFN 8
781 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
783 #define S_FW_PFVF_CMD_VFN 0
784 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
786 #define S_FW_PFVF_CMD_NIQFLINT 20
787 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
788 #define G_FW_PFVF_CMD_NIQFLINT(x) \
789 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
791 #define S_FW_PFVF_CMD_NIQ 0
792 #define M_FW_PFVF_CMD_NIQ 0xfffff
793 #define G_FW_PFVF_CMD_NIQ(x) \
794 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
796 #define S_FW_PFVF_CMD_PMASK 20
797 #define M_FW_PFVF_CMD_PMASK 0xf
798 #define G_FW_PFVF_CMD_PMASK(x) \
799 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
801 #define S_FW_PFVF_CMD_NEQ 0
802 #define M_FW_PFVF_CMD_NEQ 0xfffff
803 #define G_FW_PFVF_CMD_NEQ(x) \
804 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
806 #define S_FW_PFVF_CMD_TC 24
807 #define M_FW_PFVF_CMD_TC 0xff
808 #define G_FW_PFVF_CMD_TC(x) \
809 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
811 #define S_FW_PFVF_CMD_NVI 16
812 #define M_FW_PFVF_CMD_NVI 0xff
813 #define G_FW_PFVF_CMD_NVI(x) \
814 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
816 #define S_FW_PFVF_CMD_NEXACTF 0
817 #define M_FW_PFVF_CMD_NEXACTF 0xffff
818 #define G_FW_PFVF_CMD_NEXACTF(x) \
819 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
821 #define S_FW_PFVF_CMD_R_CAPS 24
822 #define M_FW_PFVF_CMD_R_CAPS 0xff
823 #define G_FW_PFVF_CMD_R_CAPS(x) \
824 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
826 #define S_FW_PFVF_CMD_WX_CAPS 16
827 #define M_FW_PFVF_CMD_WX_CAPS 0xff
828 #define G_FW_PFVF_CMD_WX_CAPS(x) \
829 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
831 #define S_FW_PFVF_CMD_NETHCTRL 0
832 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
833 #define G_FW_PFVF_CMD_NETHCTRL(x) \
834 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
837 * ingress queue type; the first 1K ingress queues can have associated 0,
838 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
842 FW_IQ_TYPE_FL_INT_CAP,
846 FW_IQ_IQTYPE_NIC = 1,
852 __be32 alloc_to_len16;
857 __be32 type_to_iqandstindex;
858 __be16 iqdroprss_to_iqesize;
861 __be32 iqns_to_fl0congen;
862 __be16 fl0dcaen_to_fl0cidxfthresh;
865 __be32 fl1cngchmap_to_fl1congen;
866 __be16 fl1dcaen_to_fl1cidxfthresh;
871 #define S_FW_IQ_CMD_PFN 8
872 #define M_FW_IQ_CMD_PFN 0x7
873 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
874 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
876 #define S_FW_IQ_CMD_VFN 0
877 #define M_FW_IQ_CMD_VFN 0xff
878 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
879 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
881 #define S_FW_IQ_CMD_ALLOC 31
882 #define M_FW_IQ_CMD_ALLOC 0x1
883 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
884 #define G_FW_IQ_CMD_ALLOC(x) \
885 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
886 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
888 #define S_FW_IQ_CMD_FREE 30
889 #define M_FW_IQ_CMD_FREE 0x1
890 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
891 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
892 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
894 #define S_FW_IQ_CMD_IQSTART 28
895 #define M_FW_IQ_CMD_IQSTART 0x1
896 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
897 #define G_FW_IQ_CMD_IQSTART(x) \
898 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
899 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
901 #define S_FW_IQ_CMD_IQSTOP 27
902 #define M_FW_IQ_CMD_IQSTOP 0x1
903 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
904 #define G_FW_IQ_CMD_IQSTOP(x) \
905 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
906 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
908 #define S_FW_IQ_CMD_TYPE 29
909 #define M_FW_IQ_CMD_TYPE 0x7
910 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
911 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
913 #define S_FW_IQ_CMD_IQASYNCH 28
914 #define M_FW_IQ_CMD_IQASYNCH 0x1
915 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
916 #define G_FW_IQ_CMD_IQASYNCH(x) \
917 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
918 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
920 #define S_FW_IQ_CMD_VIID 16
921 #define M_FW_IQ_CMD_VIID 0xfff
922 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
923 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
925 #define S_FW_IQ_CMD_IQANDST 15
926 #define M_FW_IQ_CMD_IQANDST 0x1
927 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
928 #define G_FW_IQ_CMD_IQANDST(x) \
929 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
930 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
932 #define S_FW_IQ_CMD_IQANUD 12
933 #define M_FW_IQ_CMD_IQANUD 0x3
934 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
935 #define G_FW_IQ_CMD_IQANUD(x) \
936 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
938 #define S_FW_IQ_CMD_IQANDSTINDEX 0
939 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
940 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
941 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
942 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
944 #define S_FW_IQ_CMD_IQGTSMODE 14
945 #define M_FW_IQ_CMD_IQGTSMODE 0x1
946 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
947 #define G_FW_IQ_CMD_IQGTSMODE(x) \
948 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
949 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
951 #define S_FW_IQ_CMD_IQPCIECH 12
952 #define M_FW_IQ_CMD_IQPCIECH 0x3
953 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
954 #define G_FW_IQ_CMD_IQPCIECH(x) \
955 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
957 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
958 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
959 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
960 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
961 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
963 #define S_FW_IQ_CMD_IQESIZE 0
964 #define M_FW_IQ_CMD_IQESIZE 0x3
965 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
966 #define G_FW_IQ_CMD_IQESIZE(x) \
967 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
969 #define S_FW_IQ_CMD_IQRO 30
970 #define M_FW_IQ_CMD_IQRO 0x1
971 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
972 #define G_FW_IQ_CMD_IQRO(x) \
973 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
974 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
976 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
977 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
978 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
979 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
980 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
981 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
983 #define S_FW_IQ_CMD_IQTYPE 24
984 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
986 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
987 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
988 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
989 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
990 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
992 #define S_FW_IQ_CMD_FL0DATARO 12
993 #define M_FW_IQ_CMD_FL0DATARO 0x1
994 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
995 #define G_FW_IQ_CMD_FL0DATARO(x) \
996 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
997 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
999 #define S_FW_IQ_CMD_FL0CONGCIF 11
1000 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
1001 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
1002 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
1003 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
1004 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
1006 #define S_FW_IQ_CMD_FL0FETCHRO 6
1007 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
1008 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
1009 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
1010 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
1011 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
1013 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
1014 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
1015 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
1016 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
1017 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
1019 #define S_FW_IQ_CMD_FL0PADEN 2
1020 #define M_FW_IQ_CMD_FL0PADEN 0x1
1021 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
1022 #define G_FW_IQ_CMD_FL0PADEN(x) \
1023 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
1024 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
1026 #define S_FW_IQ_CMD_FL0PACKEN 1
1027 #define M_FW_IQ_CMD_FL0PACKEN 0x1
1028 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
1029 #define G_FW_IQ_CMD_FL0PACKEN(x) \
1030 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
1031 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
1033 #define S_FW_IQ_CMD_FL0CONGEN 0
1034 #define M_FW_IQ_CMD_FL0CONGEN 0x1
1035 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
1036 #define G_FW_IQ_CMD_FL0CONGEN(x) \
1037 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
1038 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
1040 #define S_FW_IQ_CMD_FL0FBMIN 7
1041 #define M_FW_IQ_CMD_FL0FBMIN 0x7
1042 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
1043 #define G_FW_IQ_CMD_FL0FBMIN(x) \
1044 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
1046 #define S_FW_IQ_CMD_FL0FBMAX 4
1047 #define M_FW_IQ_CMD_FL0FBMAX 0x7
1048 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
1049 #define G_FW_IQ_CMD_FL0FBMAX(x) \
1050 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
1052 struct fw_eq_eth_cmd {
1054 __be32 alloc_to_len16;
1056 __be32 physeqid_pkd;
1057 __be32 fetchszm_to_iqid;
1058 __be32 dcaen_to_eqsize;
1060 __be32 autoequiqe_to_viid;
1065 #define S_FW_EQ_ETH_CMD_PFN 8
1066 #define M_FW_EQ_ETH_CMD_PFN 0x7
1067 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
1068 #define G_FW_EQ_ETH_CMD_PFN(x) \
1069 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
1071 #define S_FW_EQ_ETH_CMD_VFN 0
1072 #define M_FW_EQ_ETH_CMD_VFN 0xff
1073 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
1074 #define G_FW_EQ_ETH_CMD_VFN(x) \
1075 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
1077 #define S_FW_EQ_ETH_CMD_ALLOC 31
1078 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
1079 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
1080 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
1081 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
1082 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
1084 #define S_FW_EQ_ETH_CMD_FREE 30
1085 #define M_FW_EQ_ETH_CMD_FREE 0x1
1086 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
1087 #define G_FW_EQ_ETH_CMD_FREE(x) \
1088 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
1089 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
1091 #define S_FW_EQ_ETH_CMD_EQSTART 28
1092 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
1093 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
1094 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
1095 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
1096 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
1098 #define S_FW_EQ_ETH_CMD_EQID 0
1099 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
1100 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
1101 #define G_FW_EQ_ETH_CMD_EQID(x) \
1102 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
1104 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
1105 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
1106 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
1107 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
1109 #define S_FW_EQ_ETH_CMD_FETCHRO 22
1110 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
1111 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
1112 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
1113 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
1114 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
1116 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
1117 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
1118 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
1119 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
1120 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
1122 #define S_FW_EQ_ETH_CMD_PCIECHN 16
1123 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
1124 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
1125 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
1126 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
1128 #define S_FW_EQ_ETH_CMD_IQID 0
1129 #define M_FW_EQ_ETH_CMD_IQID 0xffff
1130 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
1131 #define G_FW_EQ_ETH_CMD_IQID(x) \
1132 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
1134 #define S_FW_EQ_ETH_CMD_FBMIN 23
1135 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
1136 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
1137 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
1138 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
1140 #define S_FW_EQ_ETH_CMD_FBMAX 20
1141 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
1142 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
1143 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
1144 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
1146 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
1147 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
1148 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
1149 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
1150 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
1152 #define S_FW_EQ_ETH_CMD_EQSIZE 0
1153 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
1154 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
1155 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
1156 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
1158 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
1159 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
1160 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
1161 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
1162 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
1163 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
1165 #define S_FW_EQ_ETH_CMD_VIID 16
1166 #define M_FW_EQ_ETH_CMD_VIID 0xfff
1167 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
1168 #define G_FW_EQ_ETH_CMD_VIID(x) \
1169 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
1171 struct fw_eq_ctrl_cmd {
1173 __be32 alloc_to_len16;
1174 __be32 cmpliqid_eqid;
1175 __be32 physeqid_pkd;
1176 __be32 fetchszm_to_iqid;
1177 __be32 dcaen_to_eqsize;
1181 #define S_FW_EQ_CTRL_CMD_PFN 8
1182 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
1184 #define S_FW_EQ_CTRL_CMD_VFN 0
1185 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
1187 #define S_FW_EQ_CTRL_CMD_ALLOC 31
1188 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
1189 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
1191 #define S_FW_EQ_CTRL_CMD_FREE 30
1192 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
1193 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
1195 #define S_FW_EQ_CTRL_CMD_EQSTART 28
1196 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
1197 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
1199 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
1200 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
1202 #define S_FW_EQ_CTRL_CMD_EQID 0
1203 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
1204 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
1205 #define G_FW_EQ_CTRL_CMD_EQID(x) \
1206 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1208 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1209 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1210 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1211 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1212 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1214 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1215 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1216 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1218 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1219 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1220 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1222 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1223 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1225 #define S_FW_EQ_CTRL_CMD_IQID 0
1226 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1228 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1229 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1231 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1232 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1234 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1235 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1237 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1238 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1244 /* Macros for VIID parsing:
1245 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1248 #define S_FW_VIID_VIVLD 7
1249 #define M_FW_VIID_VIVLD 0x1
1250 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
1252 #define S_FW_VIID_VIN 0
1253 #define M_FW_VIID_VIN 0x7F
1254 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
1258 __be32 alloc_to_len16;
1259 __be16 type_to_viid;
1264 __be16 norss_rsssize;
1274 #define S_FW_VI_CMD_PFN 8
1275 #define M_FW_VI_CMD_PFN 0x7
1276 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1277 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1279 #define S_FW_VI_CMD_VFN 0
1280 #define M_FW_VI_CMD_VFN 0xff
1281 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1282 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1284 #define S_FW_VI_CMD_ALLOC 31
1285 #define M_FW_VI_CMD_ALLOC 0x1
1286 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1287 #define G_FW_VI_CMD_ALLOC(x) \
1288 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1289 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1291 #define S_FW_VI_CMD_FREE 30
1292 #define M_FW_VI_CMD_FREE 0x1
1293 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1294 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1295 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1297 #define S_FW_VI_CMD_VFVLD 24
1298 #define M_FW_VI_CMD_VFVLD 0x1
1299 #define G_FW_VI_CMD_VFVLD(x) \
1300 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
1302 #define S_FW_VI_CMD_VIN 16
1303 #define M_FW_VI_CMD_VIN 0xff
1304 #define G_FW_VI_CMD_VIN(x) \
1305 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
1307 #define S_FW_VI_CMD_TYPE 15
1308 #define M_FW_VI_CMD_TYPE 0x1
1309 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1310 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1311 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1313 #define S_FW_VI_CMD_FUNC 12
1314 #define M_FW_VI_CMD_FUNC 0x7
1315 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1316 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1318 #define S_FW_VI_CMD_VIID 0
1319 #define M_FW_VI_CMD_VIID 0xfff
1320 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1321 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1323 #define S_FW_VI_CMD_PORTID 4
1324 #define M_FW_VI_CMD_PORTID 0xf
1325 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1326 #define G_FW_VI_CMD_PORTID(x) \
1327 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1329 #define S_FW_VI_CMD_RSSSIZE 0
1330 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1331 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1332 #define G_FW_VI_CMD_RSSSIZE(x) \
1333 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1335 /* Special VI_MAC command index ids */
1336 #define FW_VI_MAC_ADD_MAC 0x3FF
1337 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1338 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
1340 enum fw_vi_mac_smac {
1341 FW_VI_MAC_MPS_TCAM_ENTRY = 0x0,
1342 FW_VI_MAC_SMT_AND_MPSTCAM = 0x3
1345 enum fw_vi_mac_entry_types {
1346 FW_VI_MAC_TYPE_RAW = 0x2,
1349 struct fw_vi_mac_cmd {
1351 __be32 freemacs_to_len16;
1353 struct fw_vi_mac_exact {
1354 __be16 valid_to_idx;
1357 struct fw_vi_mac_hash {
1360 struct fw_vi_mac_raw {
1370 #define S_FW_VI_MAC_CMD_VIID 0
1371 #define M_FW_VI_MAC_CMD_VIID 0xfff
1372 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1373 #define G_FW_VI_MAC_CMD_VIID(x) \
1374 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1376 #define S_FW_VI_MAC_CMD_FREEMACS 31
1377 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
1379 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
1380 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
1382 #define S_FW_VI_MAC_CMD_VALID 15
1383 #define M_FW_VI_MAC_CMD_VALID 0x1
1384 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1385 #define G_FW_VI_MAC_CMD_VALID(x) \
1386 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1387 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1389 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1390 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1391 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1392 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1393 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1395 #define S_FW_VI_MAC_CMD_IDX 0
1396 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1397 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1398 #define G_FW_VI_MAC_CMD_IDX(x) \
1399 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1401 #define S_FW_VI_MAC_CMD_RAW_IDX 16
1402 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
1403 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
1404 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
1405 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
1407 struct fw_vi_rxmode_cmd {
1409 __be32 retval_len16;
1410 __be32 mtu_to_vlanexen;
1414 #define S_FW_VI_RXMODE_CMD_VIID 0
1415 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1416 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1417 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1418 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1420 #define S_FW_VI_RXMODE_CMD_MTU 16
1421 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1422 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1423 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1424 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1426 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1427 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1428 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1429 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1430 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1432 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1433 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1434 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1435 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1436 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1437 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1439 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1440 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1441 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1442 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1443 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1444 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1445 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1447 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1448 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1449 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1450 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1451 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1453 struct fw_vi_enable_cmd {
1455 __be32 ien_to_len16;
1461 #define S_FW_VI_ENABLE_CMD_VIID 0
1462 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1463 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1464 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1465 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1467 #define S_FW_VI_ENABLE_CMD_IEN 31
1468 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1469 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1470 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1471 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1472 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1474 #define S_FW_VI_ENABLE_CMD_EEN 30
1475 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1476 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1477 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1478 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1479 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1481 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1482 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1483 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1484 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1485 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1486 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1488 /* VI VF stats offset definitions */
1489 #define VI_VF_NUM_STATS 16
1491 /* VI PF stats offset definitions */
1492 #define VI_PF_NUM_STATS 17
1493 enum fw_vi_stats_pf_index {
1494 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1495 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1496 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1497 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1498 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1499 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1500 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1501 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1502 FW_VI_PF_STAT_RX_BYTES_IX,
1503 FW_VI_PF_STAT_RX_FRAMES_IX,
1504 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1505 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1506 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1507 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1508 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1509 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1510 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1513 struct fw_vi_stats_cmd {
1515 __be32 retval_len16;
1517 struct fw_vi_stats_ctl {
1528 struct fw_vi_stats_pf {
1529 __be64 tx_bcast_bytes;
1530 __be64 tx_bcast_frames;
1531 __be64 tx_mcast_bytes;
1532 __be64 tx_mcast_frames;
1533 __be64 tx_ucast_bytes;
1534 __be64 tx_ucast_frames;
1535 __be64 tx_offload_bytes;
1536 __be64 tx_offload_frames;
1538 __be64 rx_pf_frames;
1539 __be64 rx_bcast_bytes;
1540 __be64 rx_bcast_frames;
1541 __be64 rx_mcast_bytes;
1542 __be64 rx_mcast_frames;
1543 __be64 rx_ucast_bytes;
1544 __be64 rx_ucast_frames;
1545 __be64 rx_err_frames;
1547 struct fw_vi_stats_vf {
1548 __be64 tx_bcast_bytes;
1549 __be64 tx_bcast_frames;
1550 __be64 tx_mcast_bytes;
1551 __be64 tx_mcast_frames;
1552 __be64 tx_ucast_bytes;
1553 __be64 tx_ucast_frames;
1554 __be64 tx_drop_frames;
1555 __be64 tx_offload_bytes;
1556 __be64 tx_offload_frames;
1557 __be64 rx_bcast_bytes;
1558 __be64 rx_bcast_frames;
1559 __be64 rx_mcast_bytes;
1560 __be64 rx_mcast_frames;
1561 __be64 rx_ucast_bytes;
1562 __be64 rx_ucast_frames;
1563 __be64 rx_err_frames;
1568 #define S_FW_VI_STATS_CMD_VIID 0
1569 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1571 #define S_FW_VI_STATS_CMD_NSTATS 12
1572 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1574 #define S_FW_VI_STATS_CMD_IX 0
1575 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1577 /* old 16-bit port capabilities bitmap */
1579 FW_PORT_CAP_SPEED_100M = 0x0001,
1580 FW_PORT_CAP_SPEED_1G = 0x0002,
1581 FW_PORT_CAP_SPEED_25G = 0x0004,
1582 FW_PORT_CAP_SPEED_10G = 0x0008,
1583 FW_PORT_CAP_SPEED_40G = 0x0010,
1584 FW_PORT_CAP_SPEED_100G = 0x0020,
1585 FW_PORT_CAP_FC_RX = 0x0040,
1586 FW_PORT_CAP_FC_TX = 0x0080,
1587 FW_PORT_CAP_ANEG = 0x0100,
1588 FW_PORT_CAP_MDIX = 0x0200,
1589 FW_PORT_CAP_MDIAUTO = 0x0400,
1590 FW_PORT_CAP_FEC_RS = 0x0800,
1591 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1592 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1593 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1594 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1597 #define S_FW_PORT_CAP_SPEED 0
1598 #define M_FW_PORT_CAP_SPEED 0x3f
1599 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1600 #define G_FW_PORT_CAP_SPEED(x) \
1601 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1604 FW_PORT_CAP_MDI_AUTO,
1607 #define S_FW_PORT_CAP_MDI 9
1608 #define M_FW_PORT_CAP_MDI 3
1609 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1610 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1612 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1613 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1614 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1615 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1616 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1617 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1618 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1619 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1620 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1621 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1622 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1623 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1624 #define FW_PORT_CAP32_ANEG 0x00100000UL
1625 #define FW_PORT_CAP32_MDIX 0x00200000UL
1626 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1627 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1628 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1630 #define S_FW_PORT_CAP32_SPEED 0
1631 #define M_FW_PORT_CAP32_SPEED 0xfff
1632 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1633 #define G_FW_PORT_CAP32_SPEED(x) \
1634 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1636 enum fw_port_mdi32 {
1637 FW_PORT_CAP32_MDI_AUTO,
1640 #define S_FW_PORT_CAP32_MDI 21
1641 #define M_FW_PORT_CAP32_MDI 3
1642 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1643 #define G_FW_PORT_CAP32_MDI(x) \
1644 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1646 enum fw_port_action {
1647 FW_PORT_ACTION_L1_CFG = 0x0001,
1648 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1649 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1650 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1653 struct fw_port_cmd {
1654 __be32 op_to_portid;
1655 __be32 action_to_len16;
1657 struct fw_port_l1cfg {
1661 struct fw_port_l2cfg {
1663 __u8 ovlan3_to_ivlan0;
1665 __be16 txipg_force_pinfo;
1676 struct fw_port_info {
1677 __be32 lstatus_to_modtype;
1688 struct fw_port_diags {
1694 struct fw_port_dcb_pgid {
1701 struct fw_port_dcb_pgrate {
1705 __u8 num_tcs_supported;
1709 struct fw_port_dcb_priorate {
1713 __u8 strict_priorate[8];
1715 struct fw_port_dcb_pfc {
1722 struct fw_port_app_priority {
1731 struct fw_port_dcb_control {
1734 __be16 dcb_version_to_app_state;
1739 struct fw_port_l1cfg32 {
1743 struct fw_port_info32 {
1744 __be32 lstatus32_to_cbllen32;
1745 __be32 auxlinfo32_mtu32;
1754 #define S_FW_PORT_CMD_PORTID 0
1755 #define M_FW_PORT_CMD_PORTID 0xf
1756 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1757 #define G_FW_PORT_CMD_PORTID(x) \
1758 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1760 #define S_FW_PORT_CMD_ACTION 16
1761 #define M_FW_PORT_CMD_ACTION 0xffff
1762 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1763 #define G_FW_PORT_CMD_ACTION(x) \
1764 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1766 #define S_FW_PORT_CMD_LSTATUS 31
1767 #define M_FW_PORT_CMD_LSTATUS 0x1
1768 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1769 #define G_FW_PORT_CMD_LSTATUS(x) \
1770 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1771 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1773 #define S_FW_PORT_CMD_LSPEED 24
1774 #define M_FW_PORT_CMD_LSPEED 0x3f
1775 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1776 #define G_FW_PORT_CMD_LSPEED(x) \
1777 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1779 #define S_FW_PORT_CMD_TXPAUSE 23
1780 #define M_FW_PORT_CMD_TXPAUSE 0x1
1781 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1782 #define G_FW_PORT_CMD_TXPAUSE(x) \
1783 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1784 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1786 #define S_FW_PORT_CMD_RXPAUSE 22
1787 #define M_FW_PORT_CMD_RXPAUSE 0x1
1788 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1789 #define G_FW_PORT_CMD_RXPAUSE(x) \
1790 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1791 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1793 #define S_FW_PORT_CMD_MDIOCAP 21
1794 #define M_FW_PORT_CMD_MDIOCAP 0x1
1795 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1796 #define G_FW_PORT_CMD_MDIOCAP(x) \
1797 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1798 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1800 #define S_FW_PORT_CMD_MDIOADDR 16
1801 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1802 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1803 #define G_FW_PORT_CMD_MDIOADDR(x) \
1804 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1806 #define S_FW_PORT_CMD_PTYPE 8
1807 #define M_FW_PORT_CMD_PTYPE 0x1f
1808 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1809 #define G_FW_PORT_CMD_PTYPE(x) \
1810 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1812 #define S_FW_PORT_CMD_LINKDNRC 5
1813 #define M_FW_PORT_CMD_LINKDNRC 0x7
1814 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1815 #define G_FW_PORT_CMD_LINKDNRC(x) \
1816 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1818 #define S_FW_PORT_CMD_MODTYPE 0
1819 #define M_FW_PORT_CMD_MODTYPE 0x1f
1820 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1821 #define G_FW_PORT_CMD_MODTYPE(x) \
1822 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1824 #define S_FW_PORT_CMD_LSTATUS32 31
1825 #define M_FW_PORT_CMD_LSTATUS32 0x1
1826 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1827 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1829 #define S_FW_PORT_CMD_LINKDNRC32 28
1830 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1831 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1832 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1834 #define S_FW_PORT_CMD_MDIOCAP32 26
1835 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1836 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1837 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1839 #define S_FW_PORT_CMD_MDIOADDR32 21
1840 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1841 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1842 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1844 #define S_FW_PORT_CMD_PORTTYPE32 13
1845 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1846 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1847 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1849 #define S_FW_PORT_CMD_MODTYPE32 8
1850 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1851 #define G_FW_PORT_CMD_MODTYPE32(x) \
1852 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1855 * These are configured into the VPD and hence tools that generate
1856 * VPD may use this enumeration.
1857 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1860 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1861 * with any new Firmware Port Technology Types!
1864 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1865 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1866 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1867 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1868 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1869 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1870 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1871 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1872 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1873 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1874 FW_PORT_TYPE_BP_AP = 10,
1875 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1876 FW_PORT_TYPE_BP4_AP = 11,
1877 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1878 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1879 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1880 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1881 FW_PORT_TYPE_BP40_BA = 15,
1882 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1883 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1884 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1885 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1886 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1887 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1888 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1889 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1892 /* These are read from module's EEPROM and determined once the
1893 * module is inserted.
1895 enum fw_port_module_type {
1896 FW_PORT_MOD_TYPE_NA = 0x0,
1897 FW_PORT_MOD_TYPE_LR = 0x1,
1898 FW_PORT_MOD_TYPE_SR = 0x2,
1899 FW_PORT_MOD_TYPE_ER = 0x3,
1900 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1901 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1902 FW_PORT_MOD_TYPE_LRM = 0x6,
1903 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1904 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1905 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1906 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1909 /* used by FW and tools may use this to generate VPD */
1910 enum fw_port_mod_sub_type {
1911 FW_PORT_MOD_SUB_TYPE_NA,
1912 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1913 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1914 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1915 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1916 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1917 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1918 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1919 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1922 * The following will never been in the VPD. They are TWINAX cable
1923 * lengths decoded from SFP+ module i2c PROMs. These should almost
1924 * certainly go somewhere else ...
1926 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1927 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1928 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1929 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1932 /* link down reason codes (3b) */
1933 enum fw_port_link_dn_rc {
1934 FW_PORT_LINK_DN_RC_NONE,
1935 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1936 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1937 FW_PORT_LINK_DN_RESERVED3,
1938 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1939 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1940 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1941 FW_PORT_LINK_DN_RESERVED7
1945 #define FW_NUM_PORT_STATS 50
1946 #define FW_NUM_PORT_TX_STATS 23
1947 #define FW_NUM_PORT_RX_STATS 27
1949 enum fw_port_stats_tx_index {
1950 FW_STAT_TX_PORT_BYTES_IX,
1951 FW_STAT_TX_PORT_FRAMES_IX,
1952 FW_STAT_TX_PORT_BCAST_IX,
1953 FW_STAT_TX_PORT_MCAST_IX,
1954 FW_STAT_TX_PORT_UCAST_IX,
1955 FW_STAT_TX_PORT_ERROR_IX,
1956 FW_STAT_TX_PORT_64B_IX,
1957 FW_STAT_TX_PORT_65B_127B_IX,
1958 FW_STAT_TX_PORT_128B_255B_IX,
1959 FW_STAT_TX_PORT_256B_511B_IX,
1960 FW_STAT_TX_PORT_512B_1023B_IX,
1961 FW_STAT_TX_PORT_1024B_1518B_IX,
1962 FW_STAT_TX_PORT_1519B_MAX_IX,
1963 FW_STAT_TX_PORT_DROP_IX,
1964 FW_STAT_TX_PORT_PAUSE_IX,
1965 FW_STAT_TX_PORT_PPP0_IX,
1966 FW_STAT_TX_PORT_PPP1_IX,
1967 FW_STAT_TX_PORT_PPP2_IX,
1968 FW_STAT_TX_PORT_PPP3_IX,
1969 FW_STAT_TX_PORT_PPP4_IX,
1970 FW_STAT_TX_PORT_PPP5_IX,
1971 FW_STAT_TX_PORT_PPP6_IX,
1972 FW_STAT_TX_PORT_PPP7_IX
1975 enum fw_port_stat_rx_index {
1976 FW_STAT_RX_PORT_BYTES_IX,
1977 FW_STAT_RX_PORT_FRAMES_IX,
1978 FW_STAT_RX_PORT_BCAST_IX,
1979 FW_STAT_RX_PORT_MCAST_IX,
1980 FW_STAT_RX_PORT_UCAST_IX,
1981 FW_STAT_RX_PORT_MTU_ERROR_IX,
1982 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1983 FW_STAT_RX_PORT_CRC_ERROR_IX,
1984 FW_STAT_RX_PORT_LEN_ERROR_IX,
1985 FW_STAT_RX_PORT_SYM_ERROR_IX,
1986 FW_STAT_RX_PORT_64B_IX,
1987 FW_STAT_RX_PORT_65B_127B_IX,
1988 FW_STAT_RX_PORT_128B_255B_IX,
1989 FW_STAT_RX_PORT_256B_511B_IX,
1990 FW_STAT_RX_PORT_512B_1023B_IX,
1991 FW_STAT_RX_PORT_1024B_1518B_IX,
1992 FW_STAT_RX_PORT_1519B_MAX_IX,
1993 FW_STAT_RX_PORT_PAUSE_IX,
1994 FW_STAT_RX_PORT_PPP0_IX,
1995 FW_STAT_RX_PORT_PPP1_IX,
1996 FW_STAT_RX_PORT_PPP2_IX,
1997 FW_STAT_RX_PORT_PPP3_IX,
1998 FW_STAT_RX_PORT_PPP4_IX,
1999 FW_STAT_RX_PORT_PPP5_IX,
2000 FW_STAT_RX_PORT_PPP6_IX,
2001 FW_STAT_RX_PORT_PPP7_IX,
2002 FW_STAT_RX_PORT_LESS_64B_IX
2005 struct fw_port_stats_cmd {
2006 __be32 op_to_portid;
2007 __be32 retval_len16;
2008 union fw_port_stats {
2009 struct fw_port_stats_ctl {
2021 struct fw_port_stats_all {
2030 __be64 tx_128b_255b;
2031 __be64 tx_256b_511b;
2032 __be64 tx_512b_1023b;
2033 __be64 tx_1024b_1518b;
2034 __be64 tx_1519b_max;
2050 __be64 rx_mtu_error;
2051 __be64 rx_mtu_crc_error;
2052 __be64 rx_crc_error;
2053 __be64 rx_len_error;
2054 __be64 rx_sym_error;
2057 __be64 rx_128b_255b;
2058 __be64 rx_256b_511b;
2059 __be64 rx_512b_1023b;
2060 __be64 rx_1024b_1518b;
2061 __be64 rx_1519b_max;
2078 struct fw_rss_ind_tbl_cmd {
2080 __be32 retval_len16;
2088 __be32 iq12_to_iq14;
2089 __be32 iq15_to_iq17;
2090 __be32 iq18_to_iq20;
2091 __be32 iq21_to_iq23;
2092 __be32 iq24_to_iq26;
2093 __be32 iq27_to_iq29;
2098 #define S_FW_RSS_IND_TBL_CMD_VIID 0
2099 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
2100 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
2101 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
2102 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
2104 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
2105 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
2106 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
2107 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
2108 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
2110 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
2111 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
2112 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
2113 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
2114 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
2116 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
2117 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
2118 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
2119 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
2120 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
2122 struct fw_rss_glb_config_cmd {
2124 __be32 retval_len16;
2125 union fw_rss_glb_config {
2126 struct fw_rss_glb_config_manual {
2132 struct fw_rss_glb_config_basicvirtual {
2133 __be32 mode_keymode;
2134 __be32 synmapen_to_hashtoeplitz;
2141 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
2142 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
2143 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
2144 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
2146 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2148 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
2149 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
2150 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
2151 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
2153 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
2154 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
2155 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
2156 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
2157 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
2159 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
2160 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
2161 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
2162 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
2163 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
2165 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
2166 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
2167 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
2168 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
2169 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
2171 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
2172 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
2173 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
2174 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
2175 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
2177 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
2178 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
2179 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
2180 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
2182 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
2183 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
2184 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
2185 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
2187 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
2188 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
2189 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
2190 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
2191 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
2193 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
2194 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
2195 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
2196 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
2197 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
2199 struct fw_rss_vi_config_cmd {
2201 __be32 retval_len16;
2202 union fw_rss_vi_config {
2203 struct fw_rss_vi_config_manual {
2208 struct fw_rss_vi_config_basicvirtual {
2210 __be32 defaultq_to_udpen;
2217 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
2218 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
2219 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
2220 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
2221 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
2223 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
2224 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
2225 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2226 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2227 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2228 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
2229 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2231 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
2232 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
2233 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2234 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2235 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2236 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
2237 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2238 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
2239 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
2241 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
2242 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
2243 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2244 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2245 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2246 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
2247 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2248 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
2249 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
2251 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
2252 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2253 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2254 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2255 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2256 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2257 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2258 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2259 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2261 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2262 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2263 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2264 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2265 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2266 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2267 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2268 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2269 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2271 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2272 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2273 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2274 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2275 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2276 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2278 struct fw_clip_cmd {
2280 __be32 alloc_to_len16;
2286 #define S_FW_CLIP_CMD_ALLOC 31
2287 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
2288 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
2290 #define S_FW_CLIP_CMD_FREE 30
2291 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
2292 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
2294 /******************************************************************************
2295 * D E B U G C O M M A N D s
2296 ******************************************************/
2298 struct fw_debug_cmd {
2302 struct fw_debug_assert {
2307 __u8 filename_0_7[8];
2308 __u8 filename_8_15[8];
2311 struct fw_debug_prt {
2314 __be32 dprtstrparam0;
2315 __be32 dprtstrparam1;
2316 __be32 dprtstrparam2;
2317 __be32 dprtstrparam3;
2322 #define S_FW_DEBUG_CMD_TYPE 0
2323 #define M_FW_DEBUG_CMD_TYPE 0xff
2324 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2325 #define G_FW_DEBUG_CMD_TYPE(x) \
2326 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2328 /******************************************************************************
2329 * P C I E F W R E G I S T E R
2330 **************************************/
2333 * Register definitions for the PCIE_FW register which the firmware uses
2334 * to retain status across RESETs. This register should be considered
2335 * as a READ-ONLY register for Host Software and only to be used to
2336 * track firmware initialization/error state, etc.
2338 #define S_PCIE_FW_ERR 31
2339 #define M_PCIE_FW_ERR 0x1
2340 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2341 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2342 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2344 #define S_PCIE_FW_INIT 30
2345 #define M_PCIE_FW_INIT 0x1
2346 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2347 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2348 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2350 #define S_PCIE_FW_HALT 29
2351 #define M_PCIE_FW_HALT 0x1
2352 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2353 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2354 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2356 #define S_PCIE_FW_EVAL 24
2357 #define M_PCIE_FW_EVAL 0x7
2358 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2359 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2361 #define S_PCIE_FW_MASTER_VLD 15
2362 #define M_PCIE_FW_MASTER_VLD 0x1
2363 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2364 #define G_PCIE_FW_MASTER_VLD(x) \
2365 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2366 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2368 #define S_PCIE_FW_MASTER 12
2369 #define M_PCIE_FW_MASTER 0x7
2370 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2371 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2373 /******************************************************************************
2374 * B I N A R Y H E A D E R F O R M A T
2375 **********************************************/
2378 * firmware binary header format
2382 __u8 chip; /* terminator chip family */
2383 __be16 len512; /* bin length in units of 512-bytes */
2384 __be32 fw_ver; /* firmware version */
2385 __be32 tp_microcode_ver; /* tcp processor microcode version */
2390 __u8 intfver_iscsipdu;
2392 __u8 intfver_fcoepdu;
2396 __u32 magic; /* runtime or bootstrap fw */
2398 __be32 reserved6[23];
2401 #define S_FW_HDR_FW_VER_MAJOR 24
2402 #define M_FW_HDR_FW_VER_MAJOR 0xff
2403 #define V_FW_HDR_FW_VER_MAJOR(x) \
2404 ((x) << S_FW_HDR_FW_VER_MAJOR)
2405 #define G_FW_HDR_FW_VER_MAJOR(x) \
2406 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2408 #define S_FW_HDR_FW_VER_MINOR 16
2409 #define M_FW_HDR_FW_VER_MINOR 0xff
2410 #define V_FW_HDR_FW_VER_MINOR(x) \
2411 ((x) << S_FW_HDR_FW_VER_MINOR)
2412 #define G_FW_HDR_FW_VER_MINOR(x) \
2413 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2415 #define S_FW_HDR_FW_VER_MICRO 8
2416 #define M_FW_HDR_FW_VER_MICRO 0xff
2417 #define V_FW_HDR_FW_VER_MICRO(x) \
2418 ((x) << S_FW_HDR_FW_VER_MICRO)
2419 #define G_FW_HDR_FW_VER_MICRO(x) \
2420 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2422 #define S_FW_HDR_FW_VER_BUILD 0
2423 #define M_FW_HDR_FW_VER_BUILD 0xff
2424 #define V_FW_HDR_FW_VER_BUILD(x) \
2425 ((x) << S_FW_HDR_FW_VER_BUILD)
2426 #define G_FW_HDR_FW_VER_BUILD(x) \
2427 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2429 #endif /* _T4FW_INTERFACE_H_ */