1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
59 FW_ETH_TX_PKT_WR = 0x08,
60 FW_ETH_TX_PKTS_WR = 0x09,
61 FW_ETH_TX_PKT_VM_WR = 0x11,
62 FW_ETH_TX_PKTS_VM_WR = 0x12,
63 FW_ETH_TX_PKTS2_WR = 0x78,
67 * Generic work request header flit0
74 /* work request opcode (hi)
77 #define M_FW_WR_OP 0xff
78 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
79 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
81 /* work request immediate data length (hi)
83 #define S_FW_WR_IMMDLEN 0
84 #define M_FW_WR_IMMDLEN 0xff
85 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
86 #define G_FW_WR_IMMDLEN(x) \
87 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
89 /* egress queue status update to egress queue status entry (lo)
91 #define S_FW_WR_EQUEQ 30
92 #define M_FW_WR_EQUEQ 0x1
93 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
94 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
95 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
97 /* flow context identifier (lo)
99 #define S_FW_WR_FLOWID 8
100 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
102 /* length in units of 16-bytes (lo)
104 #define S_FW_WR_LEN16 0
105 #define M_FW_WR_LEN16 0xff
106 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
107 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
109 struct fw_eth_tx_pkt_wr {
111 __be32 equiq_to_len16;
115 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
116 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
117 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
118 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
119 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
121 struct fw_eth_tx_pkts_wr {
123 __be32 equiq_to_len16;
130 struct fw_eth_tx_pkt_vm_wr {
132 __be32 equiq_to_len16;
140 struct fw_eth_tx_pkts_vm_wr {
142 __be32 equiq_to_len16;
153 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
154 enum fw_filter_wr_cookie {
155 FW_FILTER_WR_SUCCESS,
156 FW_FILTER_WR_FLT_ADDED,
157 FW_FILTER_WR_FLT_DELETED,
158 FW_FILTER_WR_SMT_TBL_FULL,
162 struct fw_filter_wr {
167 __be32 del_filter_to_l2tix;
170 __u8 frag_to_ovlan_vldm;
172 __be16 rx_chan_rx_rpl_iq;
173 __be32 maci_to_matchtypem;
194 #define S_FW_FILTER_WR_TID 12
195 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
197 #define S_FW_FILTER_WR_RQTYPE 11
198 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
200 #define S_FW_FILTER_WR_NOREPLY 10
201 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
203 #define S_FW_FILTER_WR_IQ 0
204 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
206 #define S_FW_FILTER_WR_DEL_FILTER 31
207 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
208 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
210 #define S_FW_FILTER_WR_RPTTID 25
211 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
213 #define S_FW_FILTER_WR_DROP 24
214 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
216 #define S_FW_FILTER_WR_DIRSTEER 23
217 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
219 #define S_FW_FILTER_WR_MASKHASH 22
220 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
222 #define S_FW_FILTER_WR_DIRSTEERHASH 21
223 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
225 #define S_FW_FILTER_WR_LPBK 20
226 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
228 #define S_FW_FILTER_WR_DMAC 19
229 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
231 #define S_FW_FILTER_WR_INSVLAN 17
232 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
234 #define S_FW_FILTER_WR_RMVLAN 16
235 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
237 #define S_FW_FILTER_WR_HITCNTS 15
238 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
240 #define S_FW_FILTER_WR_TXCHAN 13
241 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
243 #define S_FW_FILTER_WR_PRIO 12
244 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
246 #define S_FW_FILTER_WR_L2TIX 0
247 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
249 #define S_FW_FILTER_WR_FRAG 7
250 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
252 #define S_FW_FILTER_WR_FRAGM 6
253 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
255 #define S_FW_FILTER_WR_IVLAN_VLD 5
256 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
258 #define S_FW_FILTER_WR_OVLAN_VLD 4
259 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
261 #define S_FW_FILTER_WR_IVLAN_VLDM 3
262 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
264 #define S_FW_FILTER_WR_OVLAN_VLDM 2
265 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
267 #define S_FW_FILTER_WR_RX_CHAN 15
268 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
270 #define S_FW_FILTER_WR_RX_RPL_IQ 0
271 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
273 #define S_FW_FILTER_WR_MACI 23
274 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
276 #define S_FW_FILTER_WR_MACIM 14
277 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
279 #define S_FW_FILTER_WR_FCOE 13
280 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
282 #define S_FW_FILTER_WR_FCOEM 12
283 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
285 #define S_FW_FILTER_WR_PORT 9
286 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
288 #define S_FW_FILTER_WR_PORTM 6
289 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
291 #define S_FW_FILTER_WR_MATCHTYPE 3
292 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
294 #define S_FW_FILTER_WR_MATCHTYPEM 0
295 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
297 /******************************************************************************
299 *********************/
302 * The maximum length of time, in miliseconds, that we expect any firmware
303 * command to take to execute and return a reply to the host. The RESET
304 * and INITIALIZE commands can take a fair amount of time to execute but
305 * most execute in far less time than this maximum. This constant is used
306 * by host software to determine how long to wait for a firmware command
307 * reply before declaring the firmware as dead/unreachable ...
309 #define FW_CMD_MAX_TIMEOUT 10000
312 * If a host driver does a HELLO and discovers that there's already a MASTER
313 * selected, we may have to wait for that MASTER to finish issuing RESET,
314 * configuration and INITIALIZE commands. Also, there's a possibility that
315 * our own HELLO may get lost if it happens right as the MASTER is issuign a
316 * RESET command, so we need to be willing to make a few retries of our HELLO.
318 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
319 #define FW_CMD_HELLO_RETRIES 3
321 enum fw_cmd_opcodes {
326 FW_INITIALIZE_CMD = 0x06,
327 FW_CAPS_CONFIG_CMD = 0x07,
328 FW_PARAMS_CMD = 0x08,
331 FW_EQ_ETH_CMD = 0x12,
332 FW_EQ_CTRL_CMD = 0x13,
334 FW_VI_MAC_CMD = 0x15,
335 FW_VI_RXMODE_CMD = 0x16,
336 FW_VI_ENABLE_CMD = 0x17,
337 FW_VI_STATS_CMD = 0x1a,
339 FW_RSS_IND_TBL_CMD = 0x20,
340 FW_RSS_GLB_CONFIG_CMD = 0x22,
341 FW_RSS_VI_CONFIG_CMD = 0x23,
347 FW_CMD_CAP_PORT = 0x04,
351 * Generic command header flit0
358 #define S_FW_CMD_OP 24
359 #define M_FW_CMD_OP 0xff
360 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
361 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
363 #define S_FW_CMD_REQUEST 23
364 #define M_FW_CMD_REQUEST 0x1
365 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
366 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
367 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
369 #define S_FW_CMD_READ 22
370 #define M_FW_CMD_READ 0x1
371 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
372 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
373 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
375 #define S_FW_CMD_WRITE 21
376 #define M_FW_CMD_WRITE 0x1
377 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
378 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
379 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
381 #define S_FW_CMD_EXEC 20
382 #define M_FW_CMD_EXEC 0x1
383 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
384 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
385 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
387 #define S_FW_CMD_RETVAL 8
388 #define M_FW_CMD_RETVAL 0xff
389 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
390 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
392 #define S_FW_CMD_LEN16 0
393 #define M_FW_CMD_LEN16 0xff
394 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
395 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
397 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
401 enum fw_ldst_addrspc {
402 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
406 __be32 op_to_addrspace;
407 __be32 cycles_to_len16;
409 struct fw_ldst_addrval {
413 struct fw_ldst_idctxt {
415 __be32 msg_ctxtflush;
425 struct fw_ldst_mdio {
441 struct fw_ldst_func {
449 struct fw_ldst_pcie {
459 struct fw_ldst_i2c_deprecated {
483 #define S_FW_LDST_CMD_ADDRSPACE 0
484 #define M_FW_LDST_CMD_ADDRSPACE 0xff
485 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
487 struct fw_reset_cmd {
494 #define S_FW_RESET_CMD_HALT 31
495 #define M_FW_RESET_CMD_HALT 0x1
496 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
497 #define G_FW_RESET_CMD_HALT(x) \
498 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
499 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
502 FW_HELLO_CMD_STAGE_OS = 0,
505 struct fw_hello_cmd {
508 __be32 err_to_clearinit;
512 #define S_FW_HELLO_CMD_ERR 31
513 #define M_FW_HELLO_CMD_ERR 0x1
514 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
515 #define G_FW_HELLO_CMD_ERR(x) \
516 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
517 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
519 #define S_FW_HELLO_CMD_INIT 30
520 #define M_FW_HELLO_CMD_INIT 0x1
521 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
522 #define G_FW_HELLO_CMD_INIT(x) \
523 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
524 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
526 #define S_FW_HELLO_CMD_MASTERDIS 29
527 #define M_FW_HELLO_CMD_MASTERDIS 0x1
528 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
529 #define G_FW_HELLO_CMD_MASTERDIS(x) \
530 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
531 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
533 #define S_FW_HELLO_CMD_MASTERFORCE 28
534 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
535 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
536 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
537 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
538 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
540 #define S_FW_HELLO_CMD_MBMASTER 24
541 #define M_FW_HELLO_CMD_MBMASTER 0xf
542 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
543 #define G_FW_HELLO_CMD_MBMASTER(x) \
544 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
546 #define S_FW_HELLO_CMD_MBASYNCNOT 20
547 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
548 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
549 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
550 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
552 #define S_FW_HELLO_CMD_STAGE 17
553 #define M_FW_HELLO_CMD_STAGE 0x7
554 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
555 #define G_FW_HELLO_CMD_STAGE(x) \
556 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
558 #define S_FW_HELLO_CMD_CLEARINIT 16
559 #define M_FW_HELLO_CMD_CLEARINIT 0x1
560 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
561 #define G_FW_HELLO_CMD_CLEARINIT(x) \
562 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
563 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
571 struct fw_initialize_cmd {
577 enum fw_caps_config_nic {
578 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
579 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
583 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
586 struct fw_caps_config_cmd {
588 __be32 cfvalid_to_len16;
606 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
607 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
608 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
609 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
610 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
611 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
613 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
614 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
615 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
616 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
617 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
618 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
619 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
621 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
622 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
623 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
624 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
625 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
626 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
627 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
630 * params command mnemonics
632 enum fw_params_mnem {
633 FW_PARAMS_MNEM_DEV = 1, /* device params */
634 FW_PARAMS_MNEM_PFVF = 2, /* function params */
635 FW_PARAMS_MNEM_REG = 3, /* limited register access */
636 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
642 enum fw_params_param_dev {
643 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
644 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
645 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
646 * allocated by the device's
649 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
650 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
651 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
655 * physical and virtual function parameters
657 enum fw_params_param_pfvf {
658 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
659 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
660 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
661 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
662 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
663 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
667 * dma queue parameters
669 enum fw_params_param_dmaq {
670 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
671 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
674 #define S_FW_PARAMS_MNEM 24
675 #define M_FW_PARAMS_MNEM 0xff
676 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
677 #define G_FW_PARAMS_MNEM(x) \
678 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
680 #define S_FW_PARAMS_PARAM_X 16
681 #define M_FW_PARAMS_PARAM_X 0xff
682 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
683 #define G_FW_PARAMS_PARAM_X(x) \
684 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
686 #define S_FW_PARAMS_PARAM_Y 8
687 #define M_FW_PARAMS_PARAM_Y 0xff
688 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
689 #define G_FW_PARAMS_PARAM_Y(x) \
690 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
692 #define S_FW_PARAMS_PARAM_Z 0
693 #define M_FW_PARAMS_PARAM_Z 0xff
694 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
695 #define G_FW_PARAMS_PARAM_Z(x) \
696 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
698 #define S_FW_PARAMS_PARAM_YZ 0
699 #define M_FW_PARAMS_PARAM_YZ 0xffff
700 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
701 #define G_FW_PARAMS_PARAM_YZ(x) \
702 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
704 #define S_FW_PARAMS_PARAM_XYZ 0
705 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
706 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
708 struct fw_params_cmd {
711 struct fw_params_param {
717 #define S_FW_PARAMS_CMD_PFN 8
718 #define M_FW_PARAMS_CMD_PFN 0x7
719 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
720 #define G_FW_PARAMS_CMD_PFN(x) \
721 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
723 #define S_FW_PARAMS_CMD_VFN 0
724 #define M_FW_PARAMS_CMD_VFN 0xff
725 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
726 #define G_FW_PARAMS_CMD_VFN(x) \
727 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
734 __be32 tc_to_nexactf;
735 __be32 r_caps_to_nethctrl;
741 #define S_FW_PFVF_CMD_NIQFLINT 20
742 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
743 #define G_FW_PFVF_CMD_NIQFLINT(x) \
744 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
746 #define S_FW_PFVF_CMD_NIQ 0
747 #define M_FW_PFVF_CMD_NIQ 0xfffff
748 #define G_FW_PFVF_CMD_NIQ(x) \
749 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
751 #define S_FW_PFVF_CMD_PMASK 20
752 #define M_FW_PFVF_CMD_PMASK 0xf
753 #define G_FW_PFVF_CMD_PMASK(x) \
754 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
756 #define S_FW_PFVF_CMD_NEQ 0
757 #define M_FW_PFVF_CMD_NEQ 0xfffff
758 #define G_FW_PFVF_CMD_NEQ(x) \
759 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
761 #define S_FW_PFVF_CMD_TC 24
762 #define M_FW_PFVF_CMD_TC 0xff
763 #define G_FW_PFVF_CMD_TC(x) \
764 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
766 #define S_FW_PFVF_CMD_NVI 16
767 #define M_FW_PFVF_CMD_NVI 0xff
768 #define G_FW_PFVF_CMD_NVI(x) \
769 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
771 #define S_FW_PFVF_CMD_NEXACTF 0
772 #define M_FW_PFVF_CMD_NEXACTF 0xffff
773 #define G_FW_PFVF_CMD_NEXACTF(x) \
774 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
776 #define S_FW_PFVF_CMD_R_CAPS 24
777 #define M_FW_PFVF_CMD_R_CAPS 0xff
778 #define G_FW_PFVF_CMD_R_CAPS(x) \
779 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
781 #define S_FW_PFVF_CMD_WX_CAPS 16
782 #define M_FW_PFVF_CMD_WX_CAPS 0xff
783 #define G_FW_PFVF_CMD_WX_CAPS(x) \
784 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
786 #define S_FW_PFVF_CMD_NETHCTRL 0
787 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
788 #define G_FW_PFVF_CMD_NETHCTRL(x) \
789 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
792 * ingress queue type; the first 1K ingress queues can have associated 0,
793 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
797 FW_IQ_TYPE_FL_INT_CAP,
802 __be32 alloc_to_len16;
807 __be32 type_to_iqandstindex;
808 __be16 iqdroprss_to_iqesize;
811 __be32 iqns_to_fl0congen;
812 __be16 fl0dcaen_to_fl0cidxfthresh;
815 __be32 fl1cngchmap_to_fl1congen;
816 __be16 fl1dcaen_to_fl1cidxfthresh;
821 #define S_FW_IQ_CMD_PFN 8
822 #define M_FW_IQ_CMD_PFN 0x7
823 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
824 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
826 #define S_FW_IQ_CMD_VFN 0
827 #define M_FW_IQ_CMD_VFN 0xff
828 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
829 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
831 #define S_FW_IQ_CMD_ALLOC 31
832 #define M_FW_IQ_CMD_ALLOC 0x1
833 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
834 #define G_FW_IQ_CMD_ALLOC(x) \
835 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
836 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
838 #define S_FW_IQ_CMD_FREE 30
839 #define M_FW_IQ_CMD_FREE 0x1
840 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
841 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
842 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
844 #define S_FW_IQ_CMD_IQSTART 28
845 #define M_FW_IQ_CMD_IQSTART 0x1
846 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
847 #define G_FW_IQ_CMD_IQSTART(x) \
848 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
849 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
851 #define S_FW_IQ_CMD_IQSTOP 27
852 #define M_FW_IQ_CMD_IQSTOP 0x1
853 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
854 #define G_FW_IQ_CMD_IQSTOP(x) \
855 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
856 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
858 #define S_FW_IQ_CMD_TYPE 29
859 #define M_FW_IQ_CMD_TYPE 0x7
860 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
861 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
863 #define S_FW_IQ_CMD_IQASYNCH 28
864 #define M_FW_IQ_CMD_IQASYNCH 0x1
865 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
866 #define G_FW_IQ_CMD_IQASYNCH(x) \
867 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
868 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
870 #define S_FW_IQ_CMD_VIID 16
871 #define M_FW_IQ_CMD_VIID 0xfff
872 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
873 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
875 #define S_FW_IQ_CMD_IQANDST 15
876 #define M_FW_IQ_CMD_IQANDST 0x1
877 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
878 #define G_FW_IQ_CMD_IQANDST(x) \
879 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
880 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
882 #define S_FW_IQ_CMD_IQANUD 12
883 #define M_FW_IQ_CMD_IQANUD 0x3
884 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
885 #define G_FW_IQ_CMD_IQANUD(x) \
886 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
888 #define S_FW_IQ_CMD_IQANDSTINDEX 0
889 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
890 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
891 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
892 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
894 #define S_FW_IQ_CMD_IQGTSMODE 14
895 #define M_FW_IQ_CMD_IQGTSMODE 0x1
896 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
897 #define G_FW_IQ_CMD_IQGTSMODE(x) \
898 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
899 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
901 #define S_FW_IQ_CMD_IQPCIECH 12
902 #define M_FW_IQ_CMD_IQPCIECH 0x3
903 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
904 #define G_FW_IQ_CMD_IQPCIECH(x) \
905 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
907 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
908 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
909 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
910 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
911 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
913 #define S_FW_IQ_CMD_IQESIZE 0
914 #define M_FW_IQ_CMD_IQESIZE 0x3
915 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
916 #define G_FW_IQ_CMD_IQESIZE(x) \
917 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
919 #define S_FW_IQ_CMD_IQRO 30
920 #define M_FW_IQ_CMD_IQRO 0x1
921 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
922 #define G_FW_IQ_CMD_IQRO(x) \
923 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
924 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
926 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
927 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
928 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
929 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
930 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
931 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
933 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
934 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
935 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
936 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
937 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
939 #define S_FW_IQ_CMD_FL0DATARO 12
940 #define M_FW_IQ_CMD_FL0DATARO 0x1
941 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
942 #define G_FW_IQ_CMD_FL0DATARO(x) \
943 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
944 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
946 #define S_FW_IQ_CMD_FL0CONGCIF 11
947 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
948 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
949 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
950 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
951 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
953 #define S_FW_IQ_CMD_FL0FETCHRO 6
954 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
955 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
956 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
957 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
958 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
960 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
961 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
962 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
963 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
964 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
966 #define S_FW_IQ_CMD_FL0PADEN 2
967 #define M_FW_IQ_CMD_FL0PADEN 0x1
968 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
969 #define G_FW_IQ_CMD_FL0PADEN(x) \
970 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
971 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
973 #define S_FW_IQ_CMD_FL0PACKEN 1
974 #define M_FW_IQ_CMD_FL0PACKEN 0x1
975 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
976 #define G_FW_IQ_CMD_FL0PACKEN(x) \
977 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
978 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
980 #define S_FW_IQ_CMD_FL0CONGEN 0
981 #define M_FW_IQ_CMD_FL0CONGEN 0x1
982 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
983 #define G_FW_IQ_CMD_FL0CONGEN(x) \
984 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
985 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
987 #define S_FW_IQ_CMD_FL0FBMIN 7
988 #define M_FW_IQ_CMD_FL0FBMIN 0x7
989 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
990 #define G_FW_IQ_CMD_FL0FBMIN(x) \
991 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
993 #define S_FW_IQ_CMD_FL0FBMAX 4
994 #define M_FW_IQ_CMD_FL0FBMAX 0x7
995 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
996 #define G_FW_IQ_CMD_FL0FBMAX(x) \
997 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
999 struct fw_eq_eth_cmd {
1001 __be32 alloc_to_len16;
1003 __be32 physeqid_pkd;
1004 __be32 fetchszm_to_iqid;
1005 __be32 dcaen_to_eqsize;
1007 __be32 autoequiqe_to_viid;
1012 #define S_FW_EQ_ETH_CMD_PFN 8
1013 #define M_FW_EQ_ETH_CMD_PFN 0x7
1014 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
1015 #define G_FW_EQ_ETH_CMD_PFN(x) \
1016 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
1018 #define S_FW_EQ_ETH_CMD_VFN 0
1019 #define M_FW_EQ_ETH_CMD_VFN 0xff
1020 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
1021 #define G_FW_EQ_ETH_CMD_VFN(x) \
1022 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
1024 #define S_FW_EQ_ETH_CMD_ALLOC 31
1025 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
1026 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
1027 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
1028 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
1029 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
1031 #define S_FW_EQ_ETH_CMD_FREE 30
1032 #define M_FW_EQ_ETH_CMD_FREE 0x1
1033 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
1034 #define G_FW_EQ_ETH_CMD_FREE(x) \
1035 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
1036 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
1038 #define S_FW_EQ_ETH_CMD_EQSTART 28
1039 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
1040 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
1041 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
1042 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
1043 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
1045 #define S_FW_EQ_ETH_CMD_EQID 0
1046 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
1047 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
1048 #define G_FW_EQ_ETH_CMD_EQID(x) \
1049 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
1051 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
1052 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
1053 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
1054 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
1056 #define S_FW_EQ_ETH_CMD_FETCHRO 22
1057 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
1058 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
1059 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
1060 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
1061 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
1063 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
1064 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
1065 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
1066 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
1067 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
1069 #define S_FW_EQ_ETH_CMD_PCIECHN 16
1070 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
1071 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
1072 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
1073 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
1075 #define S_FW_EQ_ETH_CMD_IQID 0
1076 #define M_FW_EQ_ETH_CMD_IQID 0xffff
1077 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
1078 #define G_FW_EQ_ETH_CMD_IQID(x) \
1079 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
1081 #define S_FW_EQ_ETH_CMD_FBMIN 23
1082 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
1083 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
1084 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
1085 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
1087 #define S_FW_EQ_ETH_CMD_FBMAX 20
1088 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
1089 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
1090 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
1091 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
1093 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
1094 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
1095 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
1096 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
1097 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
1099 #define S_FW_EQ_ETH_CMD_EQSIZE 0
1100 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
1101 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
1102 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
1103 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
1105 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
1106 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
1107 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
1108 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
1109 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
1110 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
1112 #define S_FW_EQ_ETH_CMD_VIID 16
1113 #define M_FW_EQ_ETH_CMD_VIID 0xfff
1114 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
1115 #define G_FW_EQ_ETH_CMD_VIID(x) \
1116 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
1118 struct fw_eq_ctrl_cmd {
1120 __be32 alloc_to_len16;
1121 __be32 cmpliqid_eqid;
1122 __be32 physeqid_pkd;
1123 __be32 fetchszm_to_iqid;
1124 __be32 dcaen_to_eqsize;
1128 #define S_FW_EQ_CTRL_CMD_PFN 8
1129 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
1131 #define S_FW_EQ_CTRL_CMD_VFN 0
1132 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
1134 #define S_FW_EQ_CTRL_CMD_ALLOC 31
1135 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
1136 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
1138 #define S_FW_EQ_CTRL_CMD_FREE 30
1139 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
1140 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
1142 #define S_FW_EQ_CTRL_CMD_EQSTART 28
1143 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
1144 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
1146 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
1147 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
1149 #define S_FW_EQ_CTRL_CMD_EQID 0
1150 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
1151 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
1152 #define G_FW_EQ_CTRL_CMD_EQID(x) \
1153 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1155 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1156 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1157 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1158 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1159 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1161 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1162 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1163 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1165 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1166 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1167 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1169 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1170 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1172 #define S_FW_EQ_CTRL_CMD_IQID 0
1173 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1175 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1176 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1178 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1179 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1181 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1182 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1184 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1185 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1193 __be32 alloc_to_len16;
1194 __be16 type_to_viid;
1199 __be16 norss_rsssize;
1209 #define S_FW_VI_CMD_PFN 8
1210 #define M_FW_VI_CMD_PFN 0x7
1211 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1212 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1214 #define S_FW_VI_CMD_VFN 0
1215 #define M_FW_VI_CMD_VFN 0xff
1216 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1217 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1219 #define S_FW_VI_CMD_ALLOC 31
1220 #define M_FW_VI_CMD_ALLOC 0x1
1221 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1222 #define G_FW_VI_CMD_ALLOC(x) \
1223 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1224 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1226 #define S_FW_VI_CMD_FREE 30
1227 #define M_FW_VI_CMD_FREE 0x1
1228 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1229 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1230 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1232 #define S_FW_VI_CMD_TYPE 15
1233 #define M_FW_VI_CMD_TYPE 0x1
1234 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1235 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1236 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1238 #define S_FW_VI_CMD_FUNC 12
1239 #define M_FW_VI_CMD_FUNC 0x7
1240 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1241 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1243 #define S_FW_VI_CMD_VIID 0
1244 #define M_FW_VI_CMD_VIID 0xfff
1245 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1246 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1248 #define S_FW_VI_CMD_PORTID 4
1249 #define M_FW_VI_CMD_PORTID 0xf
1250 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1251 #define G_FW_VI_CMD_PORTID(x) \
1252 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1254 #define S_FW_VI_CMD_RSSSIZE 0
1255 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1256 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1257 #define G_FW_VI_CMD_RSSSIZE(x) \
1258 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1260 /* Special VI_MAC command index ids */
1261 #define FW_VI_MAC_ADD_MAC 0x3FF
1262 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1264 enum fw_vi_mac_smac {
1265 FW_VI_MAC_MPS_TCAM_ENTRY,
1266 FW_VI_MAC_SMT_AND_MPSTCAM
1269 struct fw_vi_mac_cmd {
1271 __be32 freemacs_to_len16;
1273 struct fw_vi_mac_exact {
1274 __be16 valid_to_idx;
1277 struct fw_vi_mac_hash {
1283 #define S_FW_VI_MAC_CMD_VIID 0
1284 #define M_FW_VI_MAC_CMD_VIID 0xfff
1285 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1286 #define G_FW_VI_MAC_CMD_VIID(x) \
1287 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1289 #define S_FW_VI_MAC_CMD_VALID 15
1290 #define M_FW_VI_MAC_CMD_VALID 0x1
1291 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1292 #define G_FW_VI_MAC_CMD_VALID(x) \
1293 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1294 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1296 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1297 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1298 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1299 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1300 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1302 #define S_FW_VI_MAC_CMD_IDX 0
1303 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1304 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1305 #define G_FW_VI_MAC_CMD_IDX(x) \
1306 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1308 struct fw_vi_rxmode_cmd {
1310 __be32 retval_len16;
1311 __be32 mtu_to_vlanexen;
1315 #define S_FW_VI_RXMODE_CMD_VIID 0
1316 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1317 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1318 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1319 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1321 #define S_FW_VI_RXMODE_CMD_MTU 16
1322 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1323 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1324 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1325 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1327 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1328 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1329 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1330 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1331 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1333 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1334 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1335 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1336 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1337 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1338 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1340 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1341 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1342 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1343 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1344 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1345 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1346 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1348 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1349 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1350 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1351 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1352 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1354 struct fw_vi_enable_cmd {
1356 __be32 ien_to_len16;
1362 #define S_FW_VI_ENABLE_CMD_VIID 0
1363 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1364 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1365 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1366 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1368 #define S_FW_VI_ENABLE_CMD_IEN 31
1369 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1370 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1371 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1372 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1373 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1375 #define S_FW_VI_ENABLE_CMD_EEN 30
1376 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1377 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1378 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1379 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1380 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1382 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1383 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1384 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1385 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1386 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1387 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1389 /* VI VF stats offset definitions */
1390 #define VI_VF_NUM_STATS 16
1392 /* VI PF stats offset definitions */
1393 #define VI_PF_NUM_STATS 17
1394 enum fw_vi_stats_pf_index {
1395 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1396 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1397 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1398 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1399 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1400 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1401 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1402 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1403 FW_VI_PF_STAT_RX_BYTES_IX,
1404 FW_VI_PF_STAT_RX_FRAMES_IX,
1405 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1406 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1407 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1408 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1409 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1410 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1411 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1414 struct fw_vi_stats_cmd {
1416 __be32 retval_len16;
1418 struct fw_vi_stats_ctl {
1429 struct fw_vi_stats_pf {
1430 __be64 tx_bcast_bytes;
1431 __be64 tx_bcast_frames;
1432 __be64 tx_mcast_bytes;
1433 __be64 tx_mcast_frames;
1434 __be64 tx_ucast_bytes;
1435 __be64 tx_ucast_frames;
1436 __be64 tx_offload_bytes;
1437 __be64 tx_offload_frames;
1439 __be64 rx_pf_frames;
1440 __be64 rx_bcast_bytes;
1441 __be64 rx_bcast_frames;
1442 __be64 rx_mcast_bytes;
1443 __be64 rx_mcast_frames;
1444 __be64 rx_ucast_bytes;
1445 __be64 rx_ucast_frames;
1446 __be64 rx_err_frames;
1448 struct fw_vi_stats_vf {
1449 __be64 tx_bcast_bytes;
1450 __be64 tx_bcast_frames;
1451 __be64 tx_mcast_bytes;
1452 __be64 tx_mcast_frames;
1453 __be64 tx_ucast_bytes;
1454 __be64 tx_ucast_frames;
1455 __be64 tx_drop_frames;
1456 __be64 tx_offload_bytes;
1457 __be64 tx_offload_frames;
1458 __be64 rx_bcast_bytes;
1459 __be64 rx_bcast_frames;
1460 __be64 rx_mcast_bytes;
1461 __be64 rx_mcast_frames;
1462 __be64 rx_ucast_bytes;
1463 __be64 rx_ucast_frames;
1464 __be64 rx_err_frames;
1469 #define S_FW_VI_STATS_CMD_VIID 0
1470 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1472 #define S_FW_VI_STATS_CMD_NSTATS 12
1473 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1475 #define S_FW_VI_STATS_CMD_IX 0
1476 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1478 /* old 16-bit port capabilities bitmap */
1480 FW_PORT_CAP_SPEED_100M = 0x0001,
1481 FW_PORT_CAP_SPEED_1G = 0x0002,
1482 FW_PORT_CAP_SPEED_25G = 0x0004,
1483 FW_PORT_CAP_SPEED_10G = 0x0008,
1484 FW_PORT_CAP_SPEED_40G = 0x0010,
1485 FW_PORT_CAP_SPEED_100G = 0x0020,
1486 FW_PORT_CAP_FC_RX = 0x0040,
1487 FW_PORT_CAP_FC_TX = 0x0080,
1488 FW_PORT_CAP_ANEG = 0x0100,
1489 FW_PORT_CAP_MDIX = 0x0200,
1490 FW_PORT_CAP_MDIAUTO = 0x0400,
1491 FW_PORT_CAP_FEC_RS = 0x0800,
1492 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1493 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1494 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1495 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1498 #define S_FW_PORT_CAP_SPEED 0
1499 #define M_FW_PORT_CAP_SPEED 0x3f
1500 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1501 #define G_FW_PORT_CAP_SPEED(x) \
1502 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1505 FW_PORT_CAP_MDI_AUTO,
1508 #define S_FW_PORT_CAP_MDI 9
1509 #define M_FW_PORT_CAP_MDI 3
1510 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1511 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1513 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1514 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1515 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1516 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1517 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1518 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1519 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1520 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1521 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1522 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1523 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1524 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1525 #define FW_PORT_CAP32_ANEG 0x00100000UL
1526 #define FW_PORT_CAP32_MDIX 0x00200000UL
1527 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1528 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1529 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1531 #define S_FW_PORT_CAP32_SPEED 0
1532 #define M_FW_PORT_CAP32_SPEED 0xfff
1533 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1534 #define G_FW_PORT_CAP32_SPEED(x) \
1535 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1537 enum fw_port_mdi32 {
1538 FW_PORT_CAP32_MDI_AUTO,
1541 #define S_FW_PORT_CAP32_MDI 21
1542 #define M_FW_PORT_CAP32_MDI 3
1543 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1544 #define G_FW_PORT_CAP32_MDI(x) \
1545 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1547 enum fw_port_action {
1548 FW_PORT_ACTION_L1_CFG = 0x0001,
1549 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1550 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1551 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1554 struct fw_port_cmd {
1555 __be32 op_to_portid;
1556 __be32 action_to_len16;
1558 struct fw_port_l1cfg {
1562 struct fw_port_l2cfg {
1564 __u8 ovlan3_to_ivlan0;
1566 __be16 txipg_force_pinfo;
1577 struct fw_port_info {
1578 __be32 lstatus_to_modtype;
1589 struct fw_port_diags {
1595 struct fw_port_dcb_pgid {
1602 struct fw_port_dcb_pgrate {
1606 __u8 num_tcs_supported;
1610 struct fw_port_dcb_priorate {
1614 __u8 strict_priorate[8];
1616 struct fw_port_dcb_pfc {
1623 struct fw_port_app_priority {
1632 struct fw_port_dcb_control {
1635 __be16 dcb_version_to_app_state;
1640 struct fw_port_l1cfg32 {
1644 struct fw_port_info32 {
1645 __be32 lstatus32_to_cbllen32;
1646 __be32 auxlinfo32_mtu32;
1655 #define S_FW_PORT_CMD_PORTID 0
1656 #define M_FW_PORT_CMD_PORTID 0xf
1657 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1658 #define G_FW_PORT_CMD_PORTID(x) \
1659 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1661 #define S_FW_PORT_CMD_ACTION 16
1662 #define M_FW_PORT_CMD_ACTION 0xffff
1663 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1664 #define G_FW_PORT_CMD_ACTION(x) \
1665 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1667 #define S_FW_PORT_CMD_LSTATUS 31
1668 #define M_FW_PORT_CMD_LSTATUS 0x1
1669 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1670 #define G_FW_PORT_CMD_LSTATUS(x) \
1671 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1672 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1674 #define S_FW_PORT_CMD_LSPEED 24
1675 #define M_FW_PORT_CMD_LSPEED 0x3f
1676 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1677 #define G_FW_PORT_CMD_LSPEED(x) \
1678 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1680 #define S_FW_PORT_CMD_TXPAUSE 23
1681 #define M_FW_PORT_CMD_TXPAUSE 0x1
1682 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1683 #define G_FW_PORT_CMD_TXPAUSE(x) \
1684 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1685 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1687 #define S_FW_PORT_CMD_RXPAUSE 22
1688 #define M_FW_PORT_CMD_RXPAUSE 0x1
1689 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1690 #define G_FW_PORT_CMD_RXPAUSE(x) \
1691 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1692 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1694 #define S_FW_PORT_CMD_MDIOCAP 21
1695 #define M_FW_PORT_CMD_MDIOCAP 0x1
1696 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1697 #define G_FW_PORT_CMD_MDIOCAP(x) \
1698 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1699 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1701 #define S_FW_PORT_CMD_MDIOADDR 16
1702 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1703 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1704 #define G_FW_PORT_CMD_MDIOADDR(x) \
1705 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1707 #define S_FW_PORT_CMD_PTYPE 8
1708 #define M_FW_PORT_CMD_PTYPE 0x1f
1709 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1710 #define G_FW_PORT_CMD_PTYPE(x) \
1711 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1713 #define S_FW_PORT_CMD_LINKDNRC 5
1714 #define M_FW_PORT_CMD_LINKDNRC 0x7
1715 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1716 #define G_FW_PORT_CMD_LINKDNRC(x) \
1717 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1719 #define S_FW_PORT_CMD_MODTYPE 0
1720 #define M_FW_PORT_CMD_MODTYPE 0x1f
1721 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1722 #define G_FW_PORT_CMD_MODTYPE(x) \
1723 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1725 #define S_FW_PORT_CMD_LSTATUS32 31
1726 #define M_FW_PORT_CMD_LSTATUS32 0x1
1727 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1728 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1730 #define S_FW_PORT_CMD_LINKDNRC32 28
1731 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1732 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1733 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1735 #define S_FW_PORT_CMD_MDIOCAP32 26
1736 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1737 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1738 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1740 #define S_FW_PORT_CMD_MDIOADDR32 21
1741 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1742 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1743 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1745 #define S_FW_PORT_CMD_PORTTYPE32 13
1746 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1747 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1748 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1750 #define S_FW_PORT_CMD_MODTYPE32 8
1751 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1752 #define G_FW_PORT_CMD_MODTYPE32(x) \
1753 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1756 * These are configured into the VPD and hence tools that generate
1757 * VPD may use this enumeration.
1758 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1761 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1762 * with any new Firmware Port Technology Types!
1765 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1766 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1767 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1768 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1769 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1770 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1771 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1772 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1773 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1774 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1775 FW_PORT_TYPE_BP_AP = 10,
1776 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1777 FW_PORT_TYPE_BP4_AP = 11,
1778 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1779 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1780 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1781 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1782 FW_PORT_TYPE_BP40_BA = 15,
1783 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1784 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1785 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1786 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1787 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1788 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1789 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1790 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1793 /* These are read from module's EEPROM and determined once the
1794 * module is inserted.
1796 enum fw_port_module_type {
1797 FW_PORT_MOD_TYPE_NA = 0x0,
1798 FW_PORT_MOD_TYPE_LR = 0x1,
1799 FW_PORT_MOD_TYPE_SR = 0x2,
1800 FW_PORT_MOD_TYPE_ER = 0x3,
1801 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1802 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1803 FW_PORT_MOD_TYPE_LRM = 0x6,
1804 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1805 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1806 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1807 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1810 /* used by FW and tools may use this to generate VPD */
1811 enum fw_port_mod_sub_type {
1812 FW_PORT_MOD_SUB_TYPE_NA,
1813 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1814 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1815 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1816 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1817 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1818 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1819 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1820 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1823 * The following will never been in the VPD. They are TWINAX cable
1824 * lengths decoded from SFP+ module i2c PROMs. These should almost
1825 * certainly go somewhere else ...
1827 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1828 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1829 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1830 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1833 /* link down reason codes (3b) */
1834 enum fw_port_link_dn_rc {
1835 FW_PORT_LINK_DN_RC_NONE,
1836 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1837 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1838 FW_PORT_LINK_DN_RESERVED3,
1839 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1840 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1841 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1842 FW_PORT_LINK_DN_RESERVED7
1846 #define FW_NUM_PORT_STATS 50
1847 #define FW_NUM_PORT_TX_STATS 23
1848 #define FW_NUM_PORT_RX_STATS 27
1850 enum fw_port_stats_tx_index {
1851 FW_STAT_TX_PORT_BYTES_IX,
1852 FW_STAT_TX_PORT_FRAMES_IX,
1853 FW_STAT_TX_PORT_BCAST_IX,
1854 FW_STAT_TX_PORT_MCAST_IX,
1855 FW_STAT_TX_PORT_UCAST_IX,
1856 FW_STAT_TX_PORT_ERROR_IX,
1857 FW_STAT_TX_PORT_64B_IX,
1858 FW_STAT_TX_PORT_65B_127B_IX,
1859 FW_STAT_TX_PORT_128B_255B_IX,
1860 FW_STAT_TX_PORT_256B_511B_IX,
1861 FW_STAT_TX_PORT_512B_1023B_IX,
1862 FW_STAT_TX_PORT_1024B_1518B_IX,
1863 FW_STAT_TX_PORT_1519B_MAX_IX,
1864 FW_STAT_TX_PORT_DROP_IX,
1865 FW_STAT_TX_PORT_PAUSE_IX,
1866 FW_STAT_TX_PORT_PPP0_IX,
1867 FW_STAT_TX_PORT_PPP1_IX,
1868 FW_STAT_TX_PORT_PPP2_IX,
1869 FW_STAT_TX_PORT_PPP3_IX,
1870 FW_STAT_TX_PORT_PPP4_IX,
1871 FW_STAT_TX_PORT_PPP5_IX,
1872 FW_STAT_TX_PORT_PPP6_IX,
1873 FW_STAT_TX_PORT_PPP7_IX
1876 enum fw_port_stat_rx_index {
1877 FW_STAT_RX_PORT_BYTES_IX,
1878 FW_STAT_RX_PORT_FRAMES_IX,
1879 FW_STAT_RX_PORT_BCAST_IX,
1880 FW_STAT_RX_PORT_MCAST_IX,
1881 FW_STAT_RX_PORT_UCAST_IX,
1882 FW_STAT_RX_PORT_MTU_ERROR_IX,
1883 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1884 FW_STAT_RX_PORT_CRC_ERROR_IX,
1885 FW_STAT_RX_PORT_LEN_ERROR_IX,
1886 FW_STAT_RX_PORT_SYM_ERROR_IX,
1887 FW_STAT_RX_PORT_64B_IX,
1888 FW_STAT_RX_PORT_65B_127B_IX,
1889 FW_STAT_RX_PORT_128B_255B_IX,
1890 FW_STAT_RX_PORT_256B_511B_IX,
1891 FW_STAT_RX_PORT_512B_1023B_IX,
1892 FW_STAT_RX_PORT_1024B_1518B_IX,
1893 FW_STAT_RX_PORT_1519B_MAX_IX,
1894 FW_STAT_RX_PORT_PAUSE_IX,
1895 FW_STAT_RX_PORT_PPP0_IX,
1896 FW_STAT_RX_PORT_PPP1_IX,
1897 FW_STAT_RX_PORT_PPP2_IX,
1898 FW_STAT_RX_PORT_PPP3_IX,
1899 FW_STAT_RX_PORT_PPP4_IX,
1900 FW_STAT_RX_PORT_PPP5_IX,
1901 FW_STAT_RX_PORT_PPP6_IX,
1902 FW_STAT_RX_PORT_PPP7_IX,
1903 FW_STAT_RX_PORT_LESS_64B_IX
1906 struct fw_port_stats_cmd {
1907 __be32 op_to_portid;
1908 __be32 retval_len16;
1909 union fw_port_stats {
1910 struct fw_port_stats_ctl {
1922 struct fw_port_stats_all {
1931 __be64 tx_128b_255b;
1932 __be64 tx_256b_511b;
1933 __be64 tx_512b_1023b;
1934 __be64 tx_1024b_1518b;
1935 __be64 tx_1519b_max;
1951 __be64 rx_mtu_error;
1952 __be64 rx_mtu_crc_error;
1953 __be64 rx_crc_error;
1954 __be64 rx_len_error;
1955 __be64 rx_sym_error;
1958 __be64 rx_128b_255b;
1959 __be64 rx_256b_511b;
1960 __be64 rx_512b_1023b;
1961 __be64 rx_1024b_1518b;
1962 __be64 rx_1519b_max;
1979 struct fw_rss_ind_tbl_cmd {
1981 __be32 retval_len16;
1989 __be32 iq12_to_iq14;
1990 __be32 iq15_to_iq17;
1991 __be32 iq18_to_iq20;
1992 __be32 iq21_to_iq23;
1993 __be32 iq24_to_iq26;
1994 __be32 iq27_to_iq29;
1999 #define S_FW_RSS_IND_TBL_CMD_VIID 0
2000 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
2001 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
2002 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
2003 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
2005 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
2006 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
2007 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
2008 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
2009 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
2011 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
2012 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
2013 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
2014 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
2015 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
2017 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
2018 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
2019 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
2020 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
2021 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
2023 struct fw_rss_glb_config_cmd {
2025 __be32 retval_len16;
2026 union fw_rss_glb_config {
2027 struct fw_rss_glb_config_manual {
2033 struct fw_rss_glb_config_basicvirtual {
2034 __be32 mode_keymode;
2035 __be32 synmapen_to_hashtoeplitz;
2042 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
2043 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
2044 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
2045 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
2047 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2049 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
2050 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
2051 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
2052 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
2054 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
2055 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
2056 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
2057 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
2058 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
2060 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
2061 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
2062 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
2063 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
2064 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
2066 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
2067 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
2068 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
2069 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
2070 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
2072 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
2073 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
2074 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
2075 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
2076 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
2078 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
2079 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
2080 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
2081 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
2083 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
2084 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
2085 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
2086 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
2088 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
2089 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
2090 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
2091 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
2092 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
2094 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
2095 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
2096 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
2097 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
2098 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
2100 struct fw_rss_vi_config_cmd {
2102 __be32 retval_len16;
2103 union fw_rss_vi_config {
2104 struct fw_rss_vi_config_manual {
2109 struct fw_rss_vi_config_basicvirtual {
2111 __be32 defaultq_to_udpen;
2118 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
2119 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
2120 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
2121 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
2122 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
2124 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
2125 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
2126 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2127 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2128 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2129 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
2130 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2132 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
2133 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
2134 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2135 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2136 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2137 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
2138 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2139 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
2140 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
2142 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
2143 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
2144 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2145 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2146 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2147 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
2148 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2149 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
2150 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
2152 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
2153 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2154 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2155 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2156 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2157 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2158 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2159 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2160 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2162 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2163 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2164 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2165 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2166 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2167 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2168 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2169 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2170 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2172 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2173 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2174 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2175 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2176 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2177 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2179 struct fw_clip_cmd {
2181 __be32 alloc_to_len16;
2187 #define S_FW_CLIP_CMD_ALLOC 31
2188 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
2189 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
2191 #define S_FW_CLIP_CMD_FREE 30
2192 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
2193 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
2195 /******************************************************************************
2196 * D E B U G C O M M A N D s
2197 ******************************************************/
2199 struct fw_debug_cmd {
2203 struct fw_debug_assert {
2208 __u8 filename_0_7[8];
2209 __u8 filename_8_15[8];
2212 struct fw_debug_prt {
2215 __be32 dprtstrparam0;
2216 __be32 dprtstrparam1;
2217 __be32 dprtstrparam2;
2218 __be32 dprtstrparam3;
2223 #define S_FW_DEBUG_CMD_TYPE 0
2224 #define M_FW_DEBUG_CMD_TYPE 0xff
2225 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2226 #define G_FW_DEBUG_CMD_TYPE(x) \
2227 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2229 /******************************************************************************
2230 * P C I E F W R E G I S T E R
2231 **************************************/
2234 * Register definitions for the PCIE_FW register which the firmware uses
2235 * to retain status across RESETs. This register should be considered
2236 * as a READ-ONLY register for Host Software and only to be used to
2237 * track firmware initialization/error state, etc.
2239 #define S_PCIE_FW_ERR 31
2240 #define M_PCIE_FW_ERR 0x1
2241 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2242 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2243 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2245 #define S_PCIE_FW_INIT 30
2246 #define M_PCIE_FW_INIT 0x1
2247 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2248 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2249 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2251 #define S_PCIE_FW_HALT 29
2252 #define M_PCIE_FW_HALT 0x1
2253 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2254 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2255 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2257 #define S_PCIE_FW_EVAL 24
2258 #define M_PCIE_FW_EVAL 0x7
2259 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2260 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2262 #define S_PCIE_FW_MASTER_VLD 15
2263 #define M_PCIE_FW_MASTER_VLD 0x1
2264 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2265 #define G_PCIE_FW_MASTER_VLD(x) \
2266 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2267 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2269 #define S_PCIE_FW_MASTER 12
2270 #define M_PCIE_FW_MASTER 0x7
2271 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2272 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2274 /******************************************************************************
2275 * B I N A R Y H E A D E R F O R M A T
2276 **********************************************/
2279 * firmware binary header format
2283 __u8 chip; /* terminator chip family */
2284 __be16 len512; /* bin length in units of 512-bytes */
2285 __be32 fw_ver; /* firmware version */
2286 __be32 tp_microcode_ver; /* tcp processor microcode version */
2291 __u8 intfver_iscsipdu;
2293 __u8 intfver_fcoepdu;
2297 __u32 magic; /* runtime or bootstrap fw */
2299 __be32 reserved6[23];
2302 #define S_FW_HDR_FW_VER_MAJOR 24
2303 #define M_FW_HDR_FW_VER_MAJOR 0xff
2304 #define V_FW_HDR_FW_VER_MAJOR(x) \
2305 ((x) << S_FW_HDR_FW_VER_MAJOR)
2306 #define G_FW_HDR_FW_VER_MAJOR(x) \
2307 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2309 #define S_FW_HDR_FW_VER_MINOR 16
2310 #define M_FW_HDR_FW_VER_MINOR 0xff
2311 #define V_FW_HDR_FW_VER_MINOR(x) \
2312 ((x) << S_FW_HDR_FW_VER_MINOR)
2313 #define G_FW_HDR_FW_VER_MINOR(x) \
2314 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2316 #define S_FW_HDR_FW_VER_MICRO 8
2317 #define M_FW_HDR_FW_VER_MICRO 0xff
2318 #define V_FW_HDR_FW_VER_MICRO(x) \
2319 ((x) << S_FW_HDR_FW_VER_MICRO)
2320 #define G_FW_HDR_FW_VER_MICRO(x) \
2321 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2323 #define S_FW_HDR_FW_VER_BUILD 0
2324 #define M_FW_HDR_FW_VER_BUILD 0xff
2325 #define V_FW_HDR_FW_VER_BUILD(x) \
2326 ((x) << S_FW_HDR_FW_VER_BUILD)
2327 #define G_FW_HDR_FW_VER_BUILD(x) \
2328 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2330 #endif /* _T4FW_INTERFACE_H_ */