drivers/net/cxgbe/cxgbe.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _CXGBE_H_
   7 #define _CXGBE_H_
   8
   9 #include "base/common.h"
  10 #include "base/t4_regs.h"
  11
  12 #define CXGBE_MIN_RING_DESC_SIZE      128  /* Min TX/RX descriptor ring size */
  13 #define CXGBE_MAX_RING_DESC_SIZE      4096 /* Max TX/RX descriptor ring size */
  14
  15 #define CXGBE_DEFAULT_TX_DESC_SIZE    1024 /* Default TX ring size */
  16 #define CXGBE_DEFAULT_RX_DESC_SIZE    1024 /* Default RX ring size */
  17
  18 #define CXGBE_MIN_RX_BUFSIZE RTE_ETHER_MIN_MTU /* min buf size */
  19 #define CXGBE_MAX_RX_PKTLEN (9000 + RTE_ETHER_HDR_LEN + \
  20                                 RTE_ETHER_CRC_LEN) /* max pkt */
  21
  22 /* The max frame size with default MTU */
  23 #define CXGBE_ETH_MAX_LEN (RTE_ETHER_MTU + \
  24                 RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN)
  25
  26 /* Max poll time is 100 * 100msec = 10 sec */
  27 #define CXGBE_LINK_STATUS_POLL_MS 100 /* 100ms */
  28 #define CXGBE_LINK_STATUS_POLL_CNT 100 /* Max number of times to poll */
  29
  30 #define CXGBE_DEFAULT_RSS_KEY_LEN     40 /* 320-bits */
  31 #define CXGBE_RSS_HF_IPV4_MASK (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
  32                                 ETH_RSS_NONFRAG_IPV4_OTHER)
  33 #define CXGBE_RSS_HF_IPV6_MASK (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | \
  34                                 ETH_RSS_NONFRAG_IPV6_OTHER | \
  35                                 ETH_RSS_IPV6_EX)
  36 #define CXGBE_RSS_HF_TCP_IPV6_MASK (ETH_RSS_NONFRAG_IPV6_TCP | \
  37                                     ETH_RSS_IPV6_TCP_EX)
  38 #define CXGBE_RSS_HF_UDP_IPV6_MASK (ETH_RSS_NONFRAG_IPV6_UDP | \
  39                                     ETH_RSS_IPV6_UDP_EX)
  40 #define CXGBE_RSS_HF_ALL (ETH_RSS_IP | ETH_RSS_TCP | ETH_RSS_UDP)
  41
  42 /* Tx/Rx Offloads supported */
  43 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT | \
  44                            DEV_TX_OFFLOAD_IPV4_CKSUM | \
  45                            DEV_TX_OFFLOAD_UDP_CKSUM | \
  46                            DEV_TX_OFFLOAD_TCP_CKSUM | \
  47                            DEV_TX_OFFLOAD_TCP_TSO | \
  48                            DEV_TX_OFFLOAD_MULTI_SEGS)
  49
  50 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP | \
  51                            DEV_RX_OFFLOAD_IPV4_CKSUM | \
  52                            DEV_RX_OFFLOAD_UDP_CKSUM | \
  53                            DEV_RX_OFFLOAD_TCP_CKSUM | \
  54                            DEV_RX_OFFLOAD_JUMBO_FRAME | \
  55                            DEV_RX_OFFLOAD_SCATTER | \
  56                            DEV_RX_OFFLOAD_RSS_HASH)
  57
  58 /* Devargs filtermode and filtermask representation */
  59 enum cxgbe_devargs_filter_mode_flags {
  60         CXGBE_DEVARGS_FILTER_MODE_PHYSICAL_PORT = (1 << 0),
  61         CXGBE_DEVARGS_FILTER_MODE_PF_VF = (1 << 1),
  62
  63         CXGBE_DEVARGS_FILTER_MODE_ETHERNET_DSTMAC = (1 << 2),
  64         CXGBE_DEVARGS_FILTER_MODE_ETHERNET_ETHTYPE = (1 << 3),
  65         CXGBE_DEVARGS_FILTER_MODE_VLAN_INNER = (1 << 4),
  66         CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER = (1 << 5),
  67         CXGBE_DEVARGS_FILTER_MODE_IP_TOS = (1 << 6),
  68         CXGBE_DEVARGS_FILTER_MODE_IP_PROTOCOL = (1 << 7),
  69         CXGBE_DEVARGS_FILTER_MODE_MAX = (1 << 8),
  70 };
  71
  72 enum cxgbe_filter_vnic_mode {
  73         CXGBE_FILTER_VNIC_MODE_NONE,
  74         CXGBE_FILTER_VNIC_MODE_PFVF,
  75         CXGBE_FILTER_VNIC_MODE_OVLAN,
  76 };
  77
  78 /* Common PF and VF devargs */
  79 #define CXGBE_DEVARG_CMN_KEEP_OVLAN "keep_ovlan"
  80 #define CXGBE_DEVARG_CMN_TX_MODE_LATENCY "tx_mode_latency"
  81
  82 /* VF only devargs */
  83 #define CXGBE_DEVARG_VF_FORCE_LINK_UP "force_link_up"
  84
  85 /* Filter Mode/Mask devargs */
  86 #define CXGBE_DEVARG_PF_FILTER_MODE "filtermode"
  87 #define CXGBE_DEVARG_PF_FILTER_MASK "filtermask"
  88
  89 bool cxgbe_force_linkup(struct adapter *adap);
  90 int cxgbe_probe(struct adapter *adapter);
  91 int cxgbevf_probe(struct adapter *adapter);
  92 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps);
  93 int cxgbe_set_link_status(struct port_info *pi, bool status);
  94 int cxgbe_up(struct adapter *adap);
  95 int cxgbe_down(struct port_info *pi);
  96 void cxgbe_close(struct adapter *adapter);
  97 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats);
  98 void cxgbevf_stats_get(struct port_info *pi, struct port_stats *stats);
  99 void cxgbe_stats_reset(struct port_info *pi);
 100 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int us,
 101                               unsigned int cnt, struct t4_completion *c);
 102 int cxgbe_link_start(struct port_info *pi);
 103 int cxgbe_setup_sge_fwevtq(struct adapter *adapter);
 104 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter);
 105 int cxgbe_cfg_queues(struct rte_eth_dev *eth_dev);
 106 void cxgbe_cfg_queues_free(struct adapter *adapter);
 107 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev);
 108 int cxgbe_init_rss(struct adapter *adap);
 109 int cxgbe_setup_rss(struct port_info *pi);
 110 void cxgbe_enable_rx_queues(struct port_info *pi);
 111 void cxgbe_print_port_info(struct adapter *adap);
 112 void cxgbe_print_adapter_info(struct adapter *adap);
 113 void cxgbe_process_devargs(struct adapter *adap);
 114 void cxgbe_configure_max_ethqsets(struct adapter *adapter);
 115
 116 #endif /* _CXGBE_H_ */