4 * Copyright(c) 2014-2017 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_ethdev_pci.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
68 * Macros needed to support the PCI Device ID Table ...
70 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
71 static const struct rte_pci_id cxgb4_pci_tbl[] = {
72 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
74 #define PCI_VENDOR_ID_CHELSIO 0x1425
76 #define CH_PCI_ID_TABLE_ENTRY(devid) \
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
79 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
84 *... and the PCI ID Table itself ...
86 #include "t4_pci_id_tbl.h"
88 static uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
91 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
92 uint16_t pkts_sent, pkts_remain;
93 uint16_t total_sent = 0;
96 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
97 __func__, txq, tx_pkts, nb_pkts);
99 t4_os_lock(&txq->txq_lock);
100 /* free up desc from already completed tx */
101 reclaim_completed_tx(&txq->q);
102 while (total_sent < nb_pkts) {
103 pkts_remain = nb_pkts - total_sent;
105 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
106 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
113 total_sent += pkts_sent;
114 /* reclaim as much as possible */
115 reclaim_completed_tx(&txq->q);
118 t4_os_unlock(&txq->txq_lock);
122 static uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
125 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
126 unsigned int work_done;
128 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
129 __func__, rxq->rspq.cntxt_id, nb_pkts);
131 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
132 dev_err(adapter, "error in cxgbe poll\n");
134 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
138 static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
139 struct rte_eth_dev_info *device_info)
141 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
142 struct adapter *adapter = pi->adapter;
143 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
145 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
146 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
147 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
151 device_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
153 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
154 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
155 device_info->max_rx_queues = max_queues;
156 device_info->max_tx_queues = max_queues;
157 device_info->max_mac_addrs = 1;
158 /* XXX: For now we support one MAC/port */
159 device_info->max_vfs = adapter->params.arch.vfcount;
160 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
162 device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
163 DEV_RX_OFFLOAD_IPV4_CKSUM |
164 DEV_RX_OFFLOAD_UDP_CKSUM |
165 DEV_RX_OFFLOAD_TCP_CKSUM;
167 device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
168 DEV_TX_OFFLOAD_IPV4_CKSUM |
169 DEV_TX_OFFLOAD_UDP_CKSUM |
170 DEV_TX_OFFLOAD_TCP_CKSUM |
171 DEV_TX_OFFLOAD_TCP_TSO;
173 device_info->reta_size = pi->rss_size;
175 device_info->rx_desc_lim = cxgbe_desc_lim;
176 device_info->tx_desc_lim = cxgbe_desc_lim;
177 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
180 static void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
182 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
183 struct adapter *adapter = pi->adapter;
185 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
186 1, -1, 1, -1, false);
189 static void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
191 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
192 struct adapter *adapter = pi->adapter;
194 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
195 0, -1, 1, -1, false);
198 static void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
200 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
201 struct adapter *adapter = pi->adapter;
203 /* TODO: address filters ?? */
205 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
206 -1, 1, 1, -1, false);
209 static void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
211 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
212 struct adapter *adapter = pi->adapter;
214 /* TODO: address filters ?? */
216 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
217 -1, 0, 1, -1, false);
220 static int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
221 __rte_unused int wait_to_complete)
223 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
224 struct adapter *adapter = pi->adapter;
225 struct sge *s = &adapter->sge;
226 struct rte_eth_link *old_link = ð_dev->data->dev_link;
227 unsigned int work_done, budget = 4;
229 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
230 if (old_link->link_status == pi->link_cfg.link_ok)
231 return -1; /* link not changed */
233 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
234 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
235 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
237 /* link has changed */
241 static int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
243 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
244 struct adapter *adapter = pi->adapter;
245 struct rte_eth_dev_info dev_info;
247 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
249 cxgbe_dev_info_get(eth_dev, &dev_info);
251 /* Must accommodate at least ETHER_MIN_MTU */
252 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
255 /* set to jumbo mode if needed */
256 if (new_mtu > ETHER_MAX_LEN)
257 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
259 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
261 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
264 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
269 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
270 uint16_t tx_queue_id);
271 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
272 uint16_t tx_queue_id);
273 static void cxgbe_dev_tx_queue_release(void *q);
274 static void cxgbe_dev_rx_queue_release(void *q);
279 static void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
281 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
282 struct adapter *adapter = pi->adapter;
287 if (!(adapter->flags & FULL_INIT_DONE))
293 * We clear queues only if both tx and rx path of the port
296 t4_sge_eth_clear_queues(pi);
298 /* See if all ports are down */
299 for_each_port(adapter, i) {
300 pi = adap2pinfo(adapter, i);
302 * Skip first port of the adapter since it will be closed
307 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
310 /* If rest of the ports are stopped, then free up resources */
311 if (dev_down == (adapter->params.nports - 1))
312 cxgbe_close(adapter);
316 * It returns 0 on success.
318 static int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
320 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
321 struct adapter *adapter = pi->adapter;
327 * If we don't have a connection to the firmware there's nothing we
330 if (!(adapter->flags & FW_OK)) {
335 if (!(adapter->flags & FULL_INIT_DONE)) {
336 err = cxgbe_up(adapter);
341 cxgbe_enable_rx_queues(pi);
347 for (i = 0; i < pi->n_tx_qsets; i++) {
348 err = cxgbe_dev_tx_queue_start(eth_dev, i);
353 for (i = 0; i < pi->n_rx_qsets; i++) {
354 err = cxgbe_dev_rx_queue_start(eth_dev, i);
359 err = link_start(pi);
368 * Stop device: disable rx and tx functions to allow for reconfiguring.
370 static void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
372 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
373 struct adapter *adapter = pi->adapter;
377 if (!(adapter->flags & FULL_INIT_DONE))
383 * We clear queues only if both tx and rx path of the port
386 t4_sge_eth_clear_queues(pi);
389 static int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
391 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
392 struct adapter *adapter = pi->adapter;
397 if (!(adapter->flags & FW_QUEUE_BOUND)) {
398 err = setup_sge_fwevtq(adapter);
401 adapter->flags |= FW_QUEUE_BOUND;
404 err = cfg_queue_count(eth_dev);
411 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
412 uint16_t tx_queue_id)
415 struct sge_eth_txq *txq = (struct sge_eth_txq *)
416 (eth_dev->data->tx_queues[tx_queue_id]);
418 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
420 ret = t4_sge_eth_txq_start(txq);
422 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
427 static int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,
428 uint16_t tx_queue_id)
431 struct sge_eth_txq *txq = (struct sge_eth_txq *)
432 (eth_dev->data->tx_queues[tx_queue_id]);
434 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
436 ret = t4_sge_eth_txq_stop(txq);
438 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
443 static int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
444 uint16_t queue_idx, uint16_t nb_desc,
445 unsigned int socket_id,
446 const struct rte_eth_txconf *tx_conf)
448 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
449 struct adapter *adapter = pi->adapter;
450 struct sge *s = &adapter->sge;
451 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
453 unsigned int temp_nb_desc;
455 RTE_SET_USED(tx_conf);
457 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
458 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
459 socket_id, pi->first_qset);
461 /* Free up the existing queue */
462 if (eth_dev->data->tx_queues[queue_idx]) {
463 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
464 eth_dev->data->tx_queues[queue_idx] = NULL;
467 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
471 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
473 temp_nb_desc = nb_desc;
474 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
475 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
476 __func__, CXGBE_MIN_RING_DESC_SIZE,
477 CXGBE_DEFAULT_TX_DESC_SIZE);
478 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
479 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
480 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
481 __func__, CXGBE_MIN_RING_DESC_SIZE,
482 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
486 txq->q.size = temp_nb_desc;
488 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
489 s->fw_evtq.cntxt_id, socket_id);
491 dev_debug(adapter, "%s: txq->q.cntxt_id= %d err = %d\n",
492 __func__, txq->q.cntxt_id, err);
497 static void cxgbe_dev_tx_queue_release(void *q)
499 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
502 struct port_info *pi = (struct port_info *)
503 (txq->eth_dev->data->dev_private);
504 struct adapter *adap = pi->adapter;
506 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
507 __func__, pi->port_id, txq->q.cntxt_id);
509 t4_sge_eth_txq_release(adap, txq);
513 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
514 uint16_t rx_queue_id)
517 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
518 struct adapter *adap = pi->adapter;
521 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
522 __func__, pi->port_id, rx_queue_id);
524 q = eth_dev->data->rx_queues[rx_queue_id];
526 ret = t4_sge_eth_rxq_start(adap, q);
528 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
533 static int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,
534 uint16_t rx_queue_id)
537 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
538 struct adapter *adap = pi->adapter;
541 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
542 __func__, pi->port_id, rx_queue_id);
544 q = eth_dev->data->rx_queues[rx_queue_id];
545 ret = t4_sge_eth_rxq_stop(adap, q);
547 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
552 static int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
553 uint16_t queue_idx, uint16_t nb_desc,
554 unsigned int socket_id,
555 const struct rte_eth_rxconf *rx_conf,
556 struct rte_mempool *mp)
558 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
559 struct adapter *adapter = pi->adapter;
560 struct sge *s = &adapter->sge;
561 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
564 unsigned int temp_nb_desc;
565 struct rte_eth_dev_info dev_info;
566 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
568 RTE_SET_USED(rx_conf);
570 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
571 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
574 cxgbe_dev_info_get(eth_dev, &dev_info);
576 /* Must accommodate at least ETHER_MIN_MTU */
577 if ((pkt_len < dev_info.min_rx_bufsize) ||
578 (pkt_len > dev_info.max_rx_pktlen)) {
579 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
580 __func__, dev_info.min_rx_bufsize,
581 dev_info.max_rx_pktlen);
585 /* Free up the existing queue */
586 if (eth_dev->data->rx_queues[queue_idx]) {
587 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
588 eth_dev->data->rx_queues[queue_idx] = NULL;
591 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
595 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
597 temp_nb_desc = nb_desc;
598 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
599 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
600 __func__, CXGBE_MIN_RING_DESC_SIZE,
601 CXGBE_DEFAULT_RX_DESC_SIZE);
602 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
603 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
604 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
605 __func__, CXGBE_MIN_RING_DESC_SIZE,
606 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
610 rxq->rspq.size = temp_nb_desc;
611 if ((&rxq->fl) != NULL)
612 rxq->fl.size = temp_nb_desc;
614 /* Set to jumbo mode if necessary */
615 if (pkt_len > ETHER_MAX_LEN)
616 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
618 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
620 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
621 &rxq->fl, t4_ethrx_handler,
622 t4_get_tp_ch_map(adapter, pi->tx_chan), mp,
623 queue_idx, socket_id);
625 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u\n",
626 __func__, err, pi->port_id, rxq->rspq.cntxt_id);
630 static void cxgbe_dev_rx_queue_release(void *q)
632 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
633 struct sge_rspq *rq = &rxq->rspq;
636 struct port_info *pi = (struct port_info *)
637 (rq->eth_dev->data->dev_private);
638 struct adapter *adap = pi->adapter;
640 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
641 __func__, pi->port_id, rxq->rspq.cntxt_id);
643 t4_sge_eth_rxq_release(adap, rxq);
648 * Get port statistics.
650 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
651 struct rte_eth_stats *eth_stats)
653 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
654 struct adapter *adapter = pi->adapter;
655 struct sge *s = &adapter->sge;
656 struct port_stats ps;
659 cxgbe_stats_get(pi, &ps);
662 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
663 ps.rx_ovflow2 + ps.rx_ovflow3 +
664 ps.rx_trunc0 + ps.rx_trunc1 +
665 ps.rx_trunc2 + ps.rx_trunc3;
666 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
667 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
671 eth_stats->opackets = ps.tx_frames;
672 eth_stats->obytes = ps.tx_octets;
673 eth_stats->oerrors = ps.tx_error_frames;
675 for (i = 0; i < pi->n_rx_qsets; i++) {
676 struct sge_eth_rxq *rxq =
677 &s->ethrxq[pi->first_qset + i];
679 eth_stats->q_ipackets[i] = rxq->stats.pkts;
680 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
681 eth_stats->ipackets += eth_stats->q_ipackets[i];
682 eth_stats->ibytes += eth_stats->q_ibytes[i];
685 for (i = 0; i < pi->n_tx_qsets; i++) {
686 struct sge_eth_txq *txq =
687 &s->ethtxq[pi->first_qset + i];
689 eth_stats->q_opackets[i] = txq->stats.pkts;
690 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
691 eth_stats->q_errors[i] = txq->stats.mapping_err;
697 * Reset port statistics.
699 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
701 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
702 struct adapter *adapter = pi->adapter;
703 struct sge *s = &adapter->sge;
706 cxgbe_stats_reset(pi);
707 for (i = 0; i < pi->n_rx_qsets; i++) {
708 struct sge_eth_rxq *rxq =
709 &s->ethrxq[pi->first_qset + i];
712 rxq->stats.rx_bytes = 0;
714 for (i = 0; i < pi->n_tx_qsets; i++) {
715 struct sge_eth_txq *txq =
716 &s->ethtxq[pi->first_qset + i];
719 txq->stats.tx_bytes = 0;
720 txq->stats.mapping_err = 0;
724 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
725 struct rte_eth_fc_conf *fc_conf)
727 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
728 struct link_config *lc = &pi->link_cfg;
729 int rx_pause, tx_pause;
731 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
732 rx_pause = lc->fc & PAUSE_RX;
733 tx_pause = lc->fc & PAUSE_TX;
735 if (rx_pause && tx_pause)
736 fc_conf->mode = RTE_FC_FULL;
738 fc_conf->mode = RTE_FC_RX_PAUSE;
740 fc_conf->mode = RTE_FC_TX_PAUSE;
742 fc_conf->mode = RTE_FC_NONE;
746 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
747 struct rte_eth_fc_conf *fc_conf)
749 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
750 struct adapter *adapter = pi->adapter;
751 struct link_config *lc = &pi->link_cfg;
753 if (lc->supported & FW_PORT_CAP_ANEG) {
754 if (fc_conf->autoneg)
755 lc->requested_fc |= PAUSE_AUTONEG;
757 lc->requested_fc &= ~PAUSE_AUTONEG;
760 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
761 (fc_conf->mode & RTE_FC_RX_PAUSE))
762 lc->requested_fc |= PAUSE_RX;
764 lc->requested_fc &= ~PAUSE_RX;
766 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
767 (fc_conf->mode & RTE_FC_TX_PAUSE))
768 lc->requested_fc |= PAUSE_TX;
770 lc->requested_fc &= ~PAUSE_TX;
772 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
776 static const uint32_t *
777 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
779 static const uint32_t ptypes[] = {
785 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
790 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
797 * eeprom_ptov - translate a physical EEPROM address to virtual
798 * @phys_addr: the physical EEPROM address
799 * @fn: the PCI function number
800 * @sz: size of function-specific area
802 * Translate a physical EEPROM address to virtual. The first 1K is
803 * accessed through virtual addresses starting at 31K, the rest is
804 * accessed through virtual addresses starting at 0.
806 * The mapping is as follows:
807 * [0..1K) -> [31K..32K)
808 * [1K..1K+A) -> [31K-A..31K)
809 * [1K+A..ES) -> [0..ES-A-1K)
811 * where A = @fn * @sz, and ES = EEPROM size.
813 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
816 if (phys_addr < 1024)
817 return phys_addr + (31 << 10);
818 if (phys_addr < 1024 + fn)
819 return fn + phys_addr - 1024;
820 if (phys_addr < EEPROMSIZE)
821 return phys_addr - 1024 - fn;
822 if (phys_addr < EEPROMVSIZE)
823 return phys_addr - 1024;
827 /* The next two routines implement eeprom read/write from physical addresses.
829 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
831 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
834 vaddr = t4_seeprom_read(adap, vaddr, v);
835 return vaddr < 0 ? vaddr : 0;
838 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
840 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
843 vaddr = t4_seeprom_write(adap, vaddr, v);
844 return vaddr < 0 ? vaddr : 0;
847 #define EEPROM_MAGIC 0x38E2F10C
849 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
850 struct rte_dev_eeprom_info *e)
852 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
853 struct adapter *adapter = pi->adapter;
855 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
860 e->magic = EEPROM_MAGIC;
861 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
862 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
865 rte_memcpy(e->data, buf + e->offset, e->length);
870 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
871 struct rte_dev_eeprom_info *eeprom)
873 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
874 struct adapter *adapter = pi->adapter;
877 u32 aligned_offset, aligned_len, *p;
879 if (eeprom->magic != EEPROM_MAGIC)
882 aligned_offset = eeprom->offset & ~3;
883 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
885 if (adapter->pf > 0) {
886 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
888 if (aligned_offset < start ||
889 aligned_offset + aligned_len > start + EEPROMPFSIZE)
893 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
894 /* RMW possibly needed for first or last words.
896 buf = rte_zmalloc(NULL, aligned_len, 0);
899 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
900 if (!err && aligned_len > 4)
901 err = eeprom_rd_phys(adapter,
902 aligned_offset + aligned_len - 4,
903 (u32 *)&buf[aligned_len - 4]);
906 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
912 err = t4_seeprom_wp(adapter, false);
916 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
917 err = eeprom_wr_phys(adapter, aligned_offset, *p);
922 err = t4_seeprom_wp(adapter, true);
924 if (buf != eeprom->data)
929 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
931 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
932 struct adapter *adapter = pi->adapter;
934 return t4_get_regs_len(adapter) / sizeof(uint32_t);
937 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
938 struct rte_dev_reg_info *regs)
940 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
941 struct adapter *adapter = pi->adapter;
943 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
944 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
947 if (regs->data == NULL) {
948 regs->length = cxgbe_get_regs_len(eth_dev);
949 regs->width = sizeof(uint32_t);
954 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
959 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
960 .dev_start = cxgbe_dev_start,
961 .dev_stop = cxgbe_dev_stop,
962 .dev_close = cxgbe_dev_close,
963 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
964 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
965 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
966 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
967 .dev_configure = cxgbe_dev_configure,
968 .dev_infos_get = cxgbe_dev_info_get,
969 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
970 .link_update = cxgbe_dev_link_update,
971 .mtu_set = cxgbe_dev_mtu_set,
972 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
973 .tx_queue_start = cxgbe_dev_tx_queue_start,
974 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
975 .tx_queue_release = cxgbe_dev_tx_queue_release,
976 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
977 .rx_queue_start = cxgbe_dev_rx_queue_start,
978 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
979 .rx_queue_release = cxgbe_dev_rx_queue_release,
980 .stats_get = cxgbe_dev_stats_get,
981 .stats_reset = cxgbe_dev_stats_reset,
982 .flow_ctrl_get = cxgbe_flow_ctrl_get,
983 .flow_ctrl_set = cxgbe_flow_ctrl_set,
984 .get_eeprom_length = cxgbe_get_eeprom_length,
985 .get_eeprom = cxgbe_get_eeprom,
986 .set_eeprom = cxgbe_set_eeprom,
987 .get_reg = cxgbe_get_regs,
992 * It returns 0 on success.
994 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
996 struct rte_pci_device *pci_dev;
997 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
998 struct adapter *adapter = NULL;
999 char name[RTE_ETH_NAME_MAX_LEN];
1004 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1005 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1006 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1008 /* for secondary processes, we don't initialise any further as primary
1009 * has already done this work.
1011 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1014 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1016 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1017 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1021 adapter->use_unpacked_mode = 1;
1022 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1023 if (!adapter->regs) {
1024 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1026 goto out_free_adapter;
1028 adapter->pdev = pci_dev;
1029 adapter->eth_dev = eth_dev;
1030 pi->adapter = adapter;
1032 err = cxgbe_probe(adapter);
1034 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1036 goto out_free_adapter;
1046 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1047 struct rte_pci_device *pci_dev)
1049 return rte_eth_dev_pci_generic_probe(pci_dev,
1050 sizeof(struct port_info), eth_cxgbe_dev_init);
1053 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1055 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1058 static struct rte_pci_driver rte_cxgbe_pmd = {
1059 .id_table = cxgb4_pci_tbl,
1060 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1061 .probe = eth_cxgbe_pci_probe,
1062 .remove = eth_cxgbe_pci_remove,
1065 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1066 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1067 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");