1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
39 #include "cxgbe_flow.h"
44 * Macros needed to support the PCI Device ID Table ...
46 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
47 static const struct rte_pci_id cxgb4_pci_tbl[] = {
48 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
50 #define PCI_VENDOR_ID_CHELSIO 0x1425
52 #define CH_PCI_ID_TABLE_ENTRY(devid) \
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
55 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
60 *... and the PCI ID Table itself ...
62 #include "base/t4_pci_id_tbl.h"
64 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
67 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
68 uint16_t pkts_sent, pkts_remain;
69 uint16_t total_sent = 0;
72 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
73 __func__, txq, tx_pkts, nb_pkts);
75 t4_os_lock(&txq->txq_lock);
76 /* free up desc from already completed tx */
77 reclaim_completed_tx(&txq->q);
78 while (total_sent < nb_pkts) {
79 pkts_remain = nb_pkts - total_sent;
81 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
82 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
89 total_sent += pkts_sent;
90 /* reclaim as much as possible */
91 reclaim_completed_tx(&txq->q);
94 t4_os_unlock(&txq->txq_lock);
98 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
101 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
102 unsigned int work_done;
104 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
105 __func__, rxq->rspq.cntxt_id, nb_pkts);
107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
108 dev_err(adapter, "error in cxgbe poll\n");
110 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
115 struct rte_eth_dev_info *device_info)
117 struct port_info *pi = eth_dev->data->dev_private;
118 struct adapter *adapter = pi->adapter;
119 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
121 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
122 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
123 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
127 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
128 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
129 device_info->max_rx_queues = max_queues;
130 device_info->max_tx_queues = max_queues;
131 device_info->max_mac_addrs = 1;
132 /* XXX: For now we support one MAC/port */
133 device_info->max_vfs = adapter->params.arch.vfcount;
134 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
136 device_info->rx_queue_offload_capa = 0UL;
137 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
139 device_info->tx_queue_offload_capa = 0UL;
140 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
142 device_info->reta_size = pi->rss_size;
143 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
144 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
146 device_info->rx_desc_lim = cxgbe_desc_lim;
147 device_info->tx_desc_lim = cxgbe_desc_lim;
148 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
153 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
155 struct port_info *pi = eth_dev->data->dev_private;
156 struct adapter *adapter = pi->adapter;
158 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
159 1, -1, 1, -1, false);
162 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
164 struct port_info *pi = eth_dev->data->dev_private;
165 struct adapter *adapter = pi->adapter;
167 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
168 0, -1, 1, -1, false);
171 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
173 struct port_info *pi = eth_dev->data->dev_private;
174 struct adapter *adapter = pi->adapter;
176 /* TODO: address filters ?? */
178 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
179 -1, 1, 1, -1, false);
182 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
184 struct port_info *pi = eth_dev->data->dev_private;
185 struct adapter *adapter = pi->adapter;
187 /* TODO: address filters ?? */
189 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
190 -1, 0, 1, -1, false);
193 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
194 int wait_to_complete)
196 struct port_info *pi = eth_dev->data->dev_private;
197 struct adapter *adapter = pi->adapter;
198 struct sge *s = &adapter->sge;
199 struct rte_eth_link new_link = { 0 };
200 unsigned int i, work_done, budget = 32;
201 u8 old_link = pi->link_cfg.link_ok;
203 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
204 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
206 /* Exit if link status changed or always forced up */
207 if (pi->link_cfg.link_ok != old_link ||
208 cxgbe_force_linkup(adapter))
211 if (!wait_to_complete)
214 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
217 new_link.link_status = cxgbe_force_linkup(adapter) ?
218 ETH_LINK_UP : pi->link_cfg.link_ok;
219 new_link.link_autoneg = pi->link_cfg.autoneg;
220 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
221 new_link.link_speed = pi->link_cfg.speed;
223 return rte_eth_linkstatus_set(eth_dev, &new_link);
227 * Set device link up.
229 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
231 struct port_info *pi = dev->data->dev_private;
232 struct adapter *adapter = pi->adapter;
233 unsigned int work_done, budget = 32;
234 struct sge *s = &adapter->sge;
237 /* Flush all link events */
238 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
240 /* If link already up, nothing to do */
241 if (pi->link_cfg.link_ok)
244 ret = cxgbe_set_link_status(pi, true);
248 cxgbe_dev_link_update(dev, 1);
253 * Set device link down.
255 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
257 struct port_info *pi = dev->data->dev_private;
258 struct adapter *adapter = pi->adapter;
259 unsigned int work_done, budget = 32;
260 struct sge *s = &adapter->sge;
263 /* Flush all link events */
264 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
266 /* If link already down, nothing to do */
267 if (!pi->link_cfg.link_ok)
270 ret = cxgbe_set_link_status(pi, false);
274 cxgbe_dev_link_update(dev, 0);
278 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
280 struct port_info *pi = eth_dev->data->dev_private;
281 struct adapter *adapter = pi->adapter;
282 struct rte_eth_dev_info dev_info;
284 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
286 err = cxgbe_dev_info_get(eth_dev, &dev_info);
290 /* Must accommodate at least RTE_ETHER_MIN_MTU */
291 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen)
294 /* set to jumbo mode if needed */
295 if (new_mtu > RTE_ETHER_MAX_LEN)
296 eth_dev->data->dev_conf.rxmode.offloads |=
297 DEV_RX_OFFLOAD_JUMBO_FRAME;
299 eth_dev->data->dev_conf.rxmode.offloads &=
300 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
302 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
305 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
313 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
315 struct port_info *pi = eth_dev->data->dev_private;
316 struct adapter *adapter = pi->adapter;
320 if (!(adapter->flags & FULL_INIT_DONE))
326 * We clear queues only if both tx and rx path of the port
329 t4_sge_eth_clear_queues(pi);
333 * It returns 0 on success.
335 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
337 struct port_info *pi = eth_dev->data->dev_private;
338 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode;
339 struct adapter *adapter = pi->adapter;
345 * If we don't have a connection to the firmware there's nothing we
348 if (!(adapter->flags & FW_OK)) {
353 if (!(adapter->flags & FULL_INIT_DONE)) {
354 err = cxgbe_up(adapter);
359 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
360 eth_dev->data->scattered_rx = 1;
362 eth_dev->data->scattered_rx = 0;
364 cxgbe_enable_rx_queues(pi);
366 err = cxgbe_setup_rss(pi);
370 for (i = 0; i < pi->n_tx_qsets; i++) {
371 err = cxgbe_dev_tx_queue_start(eth_dev, i);
376 for (i = 0; i < pi->n_rx_qsets; i++) {
377 err = cxgbe_dev_rx_queue_start(eth_dev, i);
382 err = cxgbe_link_start(pi);
391 * Stop device: disable rx and tx functions to allow for reconfiguring.
393 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
395 struct port_info *pi = eth_dev->data->dev_private;
396 struct adapter *adapter = pi->adapter;
400 if (!(adapter->flags & FULL_INIT_DONE))
406 * We clear queues only if both tx and rx path of the port
409 t4_sge_eth_clear_queues(pi);
410 eth_dev->data->scattered_rx = 0;
413 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
415 struct port_info *pi = eth_dev->data->dev_private;
416 struct adapter *adapter = pi->adapter;
421 if (!(adapter->flags & FW_QUEUE_BOUND)) {
422 err = cxgbe_setup_sge_fwevtq(adapter);
425 adapter->flags |= FW_QUEUE_BOUND;
426 if (is_pf4(adapter)) {
427 err = cxgbe_setup_sge_ctrl_txq(adapter);
433 err = cxgbe_cfg_queue_count(eth_dev);
440 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
443 struct sge_eth_txq *txq = (struct sge_eth_txq *)
444 (eth_dev->data->tx_queues[tx_queue_id]);
446 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
448 ret = t4_sge_eth_txq_start(txq);
450 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
455 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
458 struct sge_eth_txq *txq = (struct sge_eth_txq *)
459 (eth_dev->data->tx_queues[tx_queue_id]);
461 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
463 ret = t4_sge_eth_txq_stop(txq);
465 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
470 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
471 uint16_t queue_idx, uint16_t nb_desc,
472 unsigned int socket_id,
473 const struct rte_eth_txconf *tx_conf __rte_unused)
475 struct port_info *pi = eth_dev->data->dev_private;
476 struct adapter *adapter = pi->adapter;
477 struct sge *s = &adapter->sge;
478 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
480 unsigned int temp_nb_desc;
482 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
483 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
484 socket_id, pi->first_qset);
486 /* Free up the existing queue */
487 if (eth_dev->data->tx_queues[queue_idx]) {
488 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
489 eth_dev->data->tx_queues[queue_idx] = NULL;
492 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
496 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
498 temp_nb_desc = nb_desc;
499 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
500 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
501 __func__, CXGBE_MIN_RING_DESC_SIZE,
502 CXGBE_DEFAULT_TX_DESC_SIZE);
503 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
504 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
505 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
506 __func__, CXGBE_MIN_RING_DESC_SIZE,
507 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
511 txq->q.size = temp_nb_desc;
513 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
514 s->fw_evtq.cntxt_id, socket_id);
516 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
517 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
521 void cxgbe_dev_tx_queue_release(void *q)
523 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
526 struct port_info *pi = (struct port_info *)
527 (txq->eth_dev->data->dev_private);
528 struct adapter *adap = pi->adapter;
530 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
531 __func__, pi->port_id, txq->q.cntxt_id);
533 t4_sge_eth_txq_release(adap, txq);
537 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
540 struct port_info *pi = eth_dev->data->dev_private;
541 struct adapter *adap = pi->adapter;
544 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
545 __func__, pi->port_id, rx_queue_id);
547 q = eth_dev->data->rx_queues[rx_queue_id];
549 ret = t4_sge_eth_rxq_start(adap, q);
551 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
556 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
559 struct port_info *pi = eth_dev->data->dev_private;
560 struct adapter *adap = pi->adapter;
563 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
564 __func__, pi->port_id, rx_queue_id);
566 q = eth_dev->data->rx_queues[rx_queue_id];
567 ret = t4_sge_eth_rxq_stop(adap, q);
569 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
574 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
575 uint16_t queue_idx, uint16_t nb_desc,
576 unsigned int socket_id,
577 const struct rte_eth_rxconf *rx_conf __rte_unused,
578 struct rte_mempool *mp)
580 struct port_info *pi = eth_dev->data->dev_private;
581 struct adapter *adapter = pi->adapter;
582 struct sge *s = &adapter->sge;
583 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
586 unsigned int temp_nb_desc;
587 struct rte_eth_dev_info dev_info;
588 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
590 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
591 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
594 err = cxgbe_dev_info_get(eth_dev, &dev_info);
596 dev_err(adap, "%s: error during getting ethernet device info",
601 /* Must accommodate at least RTE_ETHER_MIN_MTU */
602 if ((pkt_len < dev_info.min_rx_bufsize) ||
603 (pkt_len > dev_info.max_rx_pktlen)) {
604 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
605 __func__, dev_info.min_rx_bufsize,
606 dev_info.max_rx_pktlen);
610 /* Free up the existing queue */
611 if (eth_dev->data->rx_queues[queue_idx]) {
612 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
613 eth_dev->data->rx_queues[queue_idx] = NULL;
616 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
620 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
622 temp_nb_desc = nb_desc;
623 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
624 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
625 __func__, CXGBE_MIN_RING_DESC_SIZE,
626 CXGBE_DEFAULT_RX_DESC_SIZE);
627 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
628 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
629 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
630 __func__, CXGBE_MIN_RING_DESC_SIZE,
631 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
635 rxq->rspq.size = temp_nb_desc;
636 if ((&rxq->fl) != NULL)
637 rxq->fl.size = temp_nb_desc;
639 /* Set to jumbo mode if necessary */
640 if (pkt_len > RTE_ETHER_MAX_LEN)
641 eth_dev->data->dev_conf.rxmode.offloads |=
642 DEV_RX_OFFLOAD_JUMBO_FRAME;
644 eth_dev->data->dev_conf.rxmode.offloads &=
645 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
647 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
650 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
651 queue_idx, socket_id);
653 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
654 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
659 void cxgbe_dev_rx_queue_release(void *q)
661 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
662 struct sge_rspq *rq = &rxq->rspq;
665 struct port_info *pi = (struct port_info *)
666 (rq->eth_dev->data->dev_private);
667 struct adapter *adap = pi->adapter;
669 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
670 __func__, pi->port_id, rxq->rspq.cntxt_id);
672 t4_sge_eth_rxq_release(adap, rxq);
677 * Get port statistics.
679 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
680 struct rte_eth_stats *eth_stats)
682 struct port_info *pi = eth_dev->data->dev_private;
683 struct adapter *adapter = pi->adapter;
684 struct sge *s = &adapter->sge;
685 struct port_stats ps;
688 cxgbe_stats_get(pi, &ps);
691 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
692 ps.rx_ovflow2 + ps.rx_ovflow3 +
693 ps.rx_trunc0 + ps.rx_trunc1 +
694 ps.rx_trunc2 + ps.rx_trunc3;
695 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
696 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
700 eth_stats->opackets = ps.tx_frames;
701 eth_stats->obytes = ps.tx_octets;
702 eth_stats->oerrors = ps.tx_error_frames;
704 for (i = 0; i < pi->n_rx_qsets; i++) {
705 struct sge_eth_rxq *rxq =
706 &s->ethrxq[pi->first_qset + i];
708 eth_stats->q_ipackets[i] = rxq->stats.pkts;
709 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
710 eth_stats->ipackets += eth_stats->q_ipackets[i];
711 eth_stats->ibytes += eth_stats->q_ibytes[i];
714 for (i = 0; i < pi->n_tx_qsets; i++) {
715 struct sge_eth_txq *txq =
716 &s->ethtxq[pi->first_qset + i];
718 eth_stats->q_opackets[i] = txq->stats.pkts;
719 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
725 * Reset port statistics.
727 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
729 struct port_info *pi = eth_dev->data->dev_private;
730 struct adapter *adapter = pi->adapter;
731 struct sge *s = &adapter->sge;
734 cxgbe_stats_reset(pi);
735 for (i = 0; i < pi->n_rx_qsets; i++) {
736 struct sge_eth_rxq *rxq =
737 &s->ethrxq[pi->first_qset + i];
740 rxq->stats.rx_bytes = 0;
742 for (i = 0; i < pi->n_tx_qsets; i++) {
743 struct sge_eth_txq *txq =
744 &s->ethtxq[pi->first_qset + i];
747 txq->stats.tx_bytes = 0;
748 txq->stats.mapping_err = 0;
752 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
753 struct rte_eth_fc_conf *fc_conf)
755 struct port_info *pi = eth_dev->data->dev_private;
756 struct link_config *lc = &pi->link_cfg;
757 int rx_pause, tx_pause;
759 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
760 rx_pause = lc->fc & PAUSE_RX;
761 tx_pause = lc->fc & PAUSE_TX;
763 if (rx_pause && tx_pause)
764 fc_conf->mode = RTE_FC_FULL;
766 fc_conf->mode = RTE_FC_RX_PAUSE;
768 fc_conf->mode = RTE_FC_TX_PAUSE;
770 fc_conf->mode = RTE_FC_NONE;
774 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
775 struct rte_eth_fc_conf *fc_conf)
777 struct port_info *pi = eth_dev->data->dev_private;
778 struct adapter *adapter = pi->adapter;
779 struct link_config *lc = &pi->link_cfg;
781 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
782 if (fc_conf->autoneg)
783 lc->requested_fc |= PAUSE_AUTONEG;
785 lc->requested_fc &= ~PAUSE_AUTONEG;
788 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
789 (fc_conf->mode & RTE_FC_RX_PAUSE))
790 lc->requested_fc |= PAUSE_RX;
792 lc->requested_fc &= ~PAUSE_RX;
794 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
795 (fc_conf->mode & RTE_FC_TX_PAUSE))
796 lc->requested_fc |= PAUSE_TX;
798 lc->requested_fc &= ~PAUSE_TX;
800 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
805 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
807 static const uint32_t ptypes[] = {
813 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
818 /* Update RSS hash configuration
820 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
821 struct rte_eth_rss_conf *rss_conf)
823 struct port_info *pi = dev->data->dev_private;
824 struct adapter *adapter = pi->adapter;
827 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
831 pi->rss_hf = rss_conf->rss_hf;
833 if (rss_conf->rss_key) {
834 u32 key[10], mod_key[10];
837 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
839 for (i = 9, j = 0; i >= 0; i--, j++)
840 mod_key[j] = cpu_to_be32(key[i]);
842 t4_write_rss_key(adapter, mod_key, -1);
848 /* Get RSS hash configuration
850 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
851 struct rte_eth_rss_conf *rss_conf)
853 struct port_info *pi = dev->data->dev_private;
854 struct adapter *adapter = pi->adapter;
859 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
865 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
866 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
867 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
868 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
871 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
872 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
874 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
875 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
876 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
877 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
880 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
881 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
883 rss_conf->rss_hf = rss_hf;
885 if (rss_conf->rss_key) {
886 u32 key[10], mod_key[10];
889 t4_read_rss_key(adapter, key);
891 for (i = 9, j = 0; i >= 0; i--, j++)
892 mod_key[j] = be32_to_cpu(key[i]);
894 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
900 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
907 * eeprom_ptov - translate a physical EEPROM address to virtual
908 * @phys_addr: the physical EEPROM address
909 * @fn: the PCI function number
910 * @sz: size of function-specific area
912 * Translate a physical EEPROM address to virtual. The first 1K is
913 * accessed through virtual addresses starting at 31K, the rest is
914 * accessed through virtual addresses starting at 0.
916 * The mapping is as follows:
917 * [0..1K) -> [31K..32K)
918 * [1K..1K+A) -> [31K-A..31K)
919 * [1K+A..ES) -> [0..ES-A-1K)
921 * where A = @fn * @sz, and ES = EEPROM size.
923 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
926 if (phys_addr < 1024)
927 return phys_addr + (31 << 10);
928 if (phys_addr < 1024 + fn)
929 return fn + phys_addr - 1024;
930 if (phys_addr < EEPROMSIZE)
931 return phys_addr - 1024 - fn;
932 if (phys_addr < EEPROMVSIZE)
933 return phys_addr - 1024;
937 /* The next two routines implement eeprom read/write from physical addresses.
939 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
941 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
944 vaddr = t4_seeprom_read(adap, vaddr, v);
945 return vaddr < 0 ? vaddr : 0;
948 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
950 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
953 vaddr = t4_seeprom_write(adap, vaddr, v);
954 return vaddr < 0 ? vaddr : 0;
957 #define EEPROM_MAGIC 0x38E2F10C
959 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
960 struct rte_dev_eeprom_info *e)
962 struct port_info *pi = dev->data->dev_private;
963 struct adapter *adapter = pi->adapter;
965 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
970 e->magic = EEPROM_MAGIC;
971 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
972 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
975 rte_memcpy(e->data, buf + e->offset, e->length);
980 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
981 struct rte_dev_eeprom_info *eeprom)
983 struct port_info *pi = dev->data->dev_private;
984 struct adapter *adapter = pi->adapter;
987 u32 aligned_offset, aligned_len, *p;
989 if (eeprom->magic != EEPROM_MAGIC)
992 aligned_offset = eeprom->offset & ~3;
993 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
995 if (adapter->pf > 0) {
996 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
998 if (aligned_offset < start ||
999 aligned_offset + aligned_len > start + EEPROMPFSIZE)
1003 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1004 /* RMW possibly needed for first or last words.
1006 buf = rte_zmalloc(NULL, aligned_len, 0);
1009 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1010 if (!err && aligned_len > 4)
1011 err = eeprom_rd_phys(adapter,
1012 aligned_offset + aligned_len - 4,
1013 (u32 *)&buf[aligned_len - 4]);
1016 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1022 err = t4_seeprom_wp(adapter, false);
1026 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1027 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1028 aligned_offset += 4;
1032 err = t4_seeprom_wp(adapter, true);
1034 if (buf != eeprom->data)
1039 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1041 struct port_info *pi = eth_dev->data->dev_private;
1042 struct adapter *adapter = pi->adapter;
1044 return t4_get_regs_len(adapter) / sizeof(uint32_t);
1047 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1048 struct rte_dev_reg_info *regs)
1050 struct port_info *pi = eth_dev->data->dev_private;
1051 struct adapter *adapter = pi->adapter;
1053 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1054 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1057 if (regs->data == NULL) {
1058 regs->length = cxgbe_get_regs_len(eth_dev);
1059 regs->width = sizeof(uint32_t);
1064 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1069 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1071 struct port_info *pi = dev->data->dev_private;
1074 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1076 dev_err(adapter, "failed to set mac addr; err = %d\n",
1080 pi->xact_addr_filt = ret;
1084 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1085 .dev_start = cxgbe_dev_start,
1086 .dev_stop = cxgbe_dev_stop,
1087 .dev_close = cxgbe_dev_close,
1088 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1089 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1090 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1091 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1092 .dev_configure = cxgbe_dev_configure,
1093 .dev_infos_get = cxgbe_dev_info_get,
1094 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1095 .link_update = cxgbe_dev_link_update,
1096 .dev_set_link_up = cxgbe_dev_set_link_up,
1097 .dev_set_link_down = cxgbe_dev_set_link_down,
1098 .mtu_set = cxgbe_dev_mtu_set,
1099 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1100 .tx_queue_start = cxgbe_dev_tx_queue_start,
1101 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1102 .tx_queue_release = cxgbe_dev_tx_queue_release,
1103 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1104 .rx_queue_start = cxgbe_dev_rx_queue_start,
1105 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1106 .rx_queue_release = cxgbe_dev_rx_queue_release,
1107 .filter_ctrl = cxgbe_dev_filter_ctrl,
1108 .stats_get = cxgbe_dev_stats_get,
1109 .stats_reset = cxgbe_dev_stats_reset,
1110 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1111 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1112 .get_eeprom_length = cxgbe_get_eeprom_length,
1113 .get_eeprom = cxgbe_get_eeprom,
1114 .set_eeprom = cxgbe_set_eeprom,
1115 .get_reg = cxgbe_get_regs,
1116 .rss_hash_update = cxgbe_dev_rss_hash_update,
1117 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1118 .mac_addr_set = cxgbe_mac_addr_set,
1123 * It returns 0 on success.
1125 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1127 struct rte_pci_device *pci_dev;
1128 struct port_info *pi = eth_dev->data->dev_private;
1129 struct adapter *adapter = NULL;
1130 char name[RTE_ETH_NAME_MAX_LEN];
1135 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1136 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1137 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1138 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1140 /* for secondary processes, we attach to ethdevs allocated by primary
1141 * and do minimal initialization.
1143 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1146 for (i = 1; i < MAX_NPORTS; i++) {
1147 struct rte_eth_dev *rest_eth_dev;
1148 char namei[RTE_ETH_NAME_MAX_LEN];
1150 snprintf(namei, sizeof(namei), "%s_%d",
1151 pci_dev->device.name, i);
1152 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1154 rest_eth_dev->device = &pci_dev->device;
1155 rest_eth_dev->dev_ops =
1157 rest_eth_dev->rx_pkt_burst =
1158 eth_dev->rx_pkt_burst;
1159 rest_eth_dev->tx_pkt_burst =
1160 eth_dev->tx_pkt_burst;
1161 rte_eth_dev_probing_finish(rest_eth_dev);
1167 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1168 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1172 adapter->use_unpacked_mode = 1;
1173 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1174 if (!adapter->regs) {
1175 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1177 goto out_free_adapter;
1179 adapter->pdev = pci_dev;
1180 adapter->eth_dev = eth_dev;
1181 pi->adapter = adapter;
1183 err = cxgbe_probe(adapter);
1185 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1187 goto out_free_adapter;
1197 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1199 struct port_info *pi = eth_dev->data->dev_private;
1200 struct adapter *adap = pi->adapter;
1202 /* Free up other ports and all resources */
1207 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1208 struct rte_pci_device *pci_dev)
1210 return rte_eth_dev_pci_generic_probe(pci_dev,
1211 sizeof(struct port_info), eth_cxgbe_dev_init);
1214 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1216 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1219 static struct rte_pci_driver rte_cxgbe_pmd = {
1220 .id_table = cxgb4_pci_tbl,
1221 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1222 .probe = eth_cxgbe_pci_probe,
1223 .remove = eth_cxgbe_pci_remove,
1226 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1227 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1228 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1229 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1230 CXGBE_DEVARG_KEEP_OVLAN "=<0|1> "
1231 CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> ");
1233 RTE_INIT(cxgbe_init_log)
1235 cxgbe_logtype = rte_log_register("pmd.net.cxgbe");
1236 if (cxgbe_logtype >= 0)
1237 rte_log_set_level(cxgbe_logtype, RTE_LOG_NOTICE);