drivers/net/cxgbe/cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_tailq.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <ethdev_driver.h>
  31 #include <ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35
  36 #include "cxgbe.h"
  37 #include "cxgbe_pfvf.h"
  38 #include "cxgbe_flow.h"
  39
  40 /*
  41  * Macros needed to support the PCI Device ID Table ...
  42  */
  43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  44         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  46
  47 #define PCI_VENDOR_ID_CHELSIO 0x1425
  48
  49 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  50                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  51
  52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  53                 { .vendor_id = 0, } \
  54         }
  55
  56 /*
  57  *... and the PCI ID Table itself ...
  58  */
  59 #include "base/t4_pci_id_tbl.h"
  60
  61 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  62                          uint16_t nb_pkts)
  63 {
  64         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  65         uint16_t pkts_sent, pkts_remain;
  66         uint16_t total_sent = 0;
  67         uint16_t idx = 0;
  68         int ret = 0;
  69
  70         t4_os_lock(&txq->txq_lock);
  71         /* free up desc from already completed tx */
  72         reclaim_completed_tx(&txq->q);
  73         if (unlikely(!nb_pkts))
  74                 goto out_unlock;
  75
  76         rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
  77         while (total_sent < nb_pkts) {
  78                 pkts_remain = nb_pkts - total_sent;
  79
  80                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  81                         idx = total_sent + pkts_sent;
  82                         if ((idx + 1) < nb_pkts)
  83                                 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
  84                                                         volatile void *));
  85                         ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
  86                         if (ret < 0)
  87                                 break;
  88                 }
  89                 if (!pkts_sent)
  90                         break;
  91                 total_sent += pkts_sent;
  92                 /* reclaim as much as possible */
  93                 reclaim_completed_tx(&txq->q);
  94         }
  95
  96 out_unlock:
  97         t4_os_unlock(&txq->txq_lock);
  98         return total_sent;
  99 }
 100
 101 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 102                          uint16_t nb_pkts)
 103 {
 104         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 105         unsigned int work_done;
 106
 107         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 108                 dev_err(adapter, "error in cxgbe poll\n");
 109
 110         return work_done;
 111 }
 112
 113 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 114                         struct rte_eth_dev_info *device_info)
 115 {
 116         struct port_info *pi = eth_dev->data->dev_private;
 117         struct adapter *adapter = pi->adapter;
 118
 119         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 120                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 121                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 122                 .nb_align = 1,
 123         };
 124
 125         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 126         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 127         device_info->max_rx_queues = adapter->sge.max_ethqsets;
 128         device_info->max_tx_queues = adapter->sge.max_ethqsets;
 129         device_info->max_mac_addrs = 1;
 130         /* XXX: For now we support one MAC/port */
 131         device_info->max_vfs = adapter->params.arch.vfcount;
 132         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 133
 134         device_info->rx_queue_offload_capa = 0UL;
 135         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 136
 137         device_info->tx_queue_offload_capa = 0UL;
 138         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 139
 140         device_info->reta_size = pi->rss_size;
 141         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 142         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 143
 144         device_info->rx_desc_lim = cxgbe_desc_lim;
 145         device_info->tx_desc_lim = cxgbe_desc_lim;
 146         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 147
 148         return 0;
 149 }
 150
 151 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 152 {
 153         struct port_info *pi = eth_dev->data->dev_private;
 154         struct adapter *adapter = pi->adapter;
 155         int ret;
 156
 157         if (adapter->params.rawf_size != 0) {
 158                 ret = cxgbe_mpstcam_rawf_enable(pi);
 159                 if (ret < 0)
 160                         return ret;
 161         }
 162
 163         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 164                              1, -1, 1, -1, false);
 165 }
 166
 167 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 168 {
 169         struct port_info *pi = eth_dev->data->dev_private;
 170         struct adapter *adapter = pi->adapter;
 171         int ret;
 172
 173         if (adapter->params.rawf_size != 0) {
 174                 ret = cxgbe_mpstcam_rawf_disable(pi);
 175                 if (ret < 0)
 176                         return ret;
 177         }
 178
 179         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 180                              0, -1, 1, -1, false);
 181 }
 182
 183 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 184 {
 185         struct port_info *pi = eth_dev->data->dev_private;
 186         struct adapter *adapter = pi->adapter;
 187
 188         /* TODO: address filters ?? */
 189
 190         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 191                              -1, 1, 1, -1, false);
 192 }
 193
 194 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 195 {
 196         struct port_info *pi = eth_dev->data->dev_private;
 197         struct adapter *adapter = pi->adapter;
 198
 199         /* TODO: address filters ?? */
 200
 201         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 202                              -1, 0, 1, -1, false);
 203 }
 204
 205 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 206                           int wait_to_complete)
 207 {
 208         struct port_info *pi = eth_dev->data->dev_private;
 209         unsigned int i, work_done, budget = 32;
 210         struct link_config *lc = &pi->link_cfg;
 211         struct adapter *adapter = pi->adapter;
 212         struct rte_eth_link new_link = { 0 };
 213         u8 old_link = pi->link_cfg.link_ok;
 214         struct sge *s = &adapter->sge;
 215
 216         for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
 217                 if (!s->fw_evtq.desc)
 218                         break;
 219
 220                 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 221
 222                 /* Exit if link status changed or always forced up */
 223                 if (pi->link_cfg.link_ok != old_link ||
 224                     cxgbe_force_linkup(adapter))
 225                         break;
 226
 227                 if (!wait_to_complete)
 228                         break;
 229
 230                 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
 231         }
 232
 233         new_link.link_status = cxgbe_force_linkup(adapter) ?
 234                                ETH_LINK_UP : pi->link_cfg.link_ok;
 235         new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0;
 236         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 237         new_link.link_speed = t4_fwcap_to_speed(lc->link_caps);
 238
 239         return rte_eth_linkstatus_set(eth_dev, &new_link);
 240 }
 241
 242 /**
 243  * Set device link up.
 244  */
 245 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
 246 {
 247         struct port_info *pi = dev->data->dev_private;
 248         struct adapter *adapter = pi->adapter;
 249         unsigned int work_done, budget = 32;
 250         struct sge *s = &adapter->sge;
 251         int ret;
 252
 253         if (!s->fw_evtq.desc)
 254                 return -ENOMEM;
 255
 256         /* Flush all link events */
 257         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 258
 259         /* If link already up, nothing to do */
 260         if (pi->link_cfg.link_ok)
 261                 return 0;
 262
 263         ret = cxgbe_set_link_status(pi, true);
 264         if (ret)
 265                 return ret;
 266
 267         cxgbe_dev_link_update(dev, 1);
 268         return 0;
 269 }
 270
 271 /**
 272  * Set device link down.
 273  */
 274 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
 275 {
 276         struct port_info *pi = dev->data->dev_private;
 277         struct adapter *adapter = pi->adapter;
 278         unsigned int work_done, budget = 32;
 279         struct sge *s = &adapter->sge;
 280         int ret;
 281
 282         if (!s->fw_evtq.desc)
 283                 return -ENOMEM;
 284
 285         /* Flush all link events */
 286         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 287
 288         /* If link already down, nothing to do */
 289         if (!pi->link_cfg.link_ok)
 290                 return 0;
 291
 292         ret = cxgbe_set_link_status(pi, false);
 293         if (ret)
 294                 return ret;
 295
 296         cxgbe_dev_link_update(dev, 0);
 297         return 0;
 298 }
 299
 300 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 301 {
 302         struct port_info *pi = eth_dev->data->dev_private;
 303         struct adapter *adapter = pi->adapter;
 304         uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
 305
 306         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 307                             -1, -1, true);
 308 }
 309
 310 /*
 311  * Stop device.
 312  */
 313 int cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 314 {
 315         struct port_info *temp_pi, *pi = eth_dev->data->dev_private;
 316         struct adapter *adapter = pi->adapter;
 317         u8 i;
 318
 319         CXGBE_FUNC_TRACE();
 320
 321         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 322                 return 0;
 323
 324         if (!(adapter->flags & FULL_INIT_DONE))
 325                 return 0;
 326
 327         if (!pi->viid)
 328                 return 0;
 329
 330         cxgbe_down(pi);
 331         t4_sge_eth_release_queues(pi);
 332         t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid);
 333         pi->viid = 0;
 334
 335         /* Free up the adapter-wide resources only after all the ports
 336          * under this PF have been closed.
 337          */
 338         for_each_port(adapter, i) {
 339                 temp_pi = adap2pinfo(adapter, i);
 340                 if (temp_pi->viid)
 341                         return 0;
 342         }
 343
 344         cxgbe_close(adapter);
 345         rte_free(adapter);
 346
 347         return 0;
 348 }
 349
 350 /* Start the device.
 351  * It returns 0 on success.
 352  */
 353 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 354 {
 355         struct port_info *pi = eth_dev->data->dev_private;
 356         struct rte_eth_rxmode *rx_conf = &eth_dev->data->dev_conf.rxmode;
 357         struct adapter *adapter = pi->adapter;
 358         int err = 0, i;
 359
 360         CXGBE_FUNC_TRACE();
 361
 362         /*
 363          * If we don't have a connection to the firmware there's nothing we
 364          * can do.
 365          */
 366         if (!(adapter->flags & FW_OK)) {
 367                 err = -ENXIO;
 368                 goto out;
 369         }
 370
 371         if (!(adapter->flags & FULL_INIT_DONE)) {
 372                 err = cxgbe_up(adapter);
 373                 if (err < 0)
 374                         goto out;
 375         }
 376
 377         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
 378                 eth_dev->data->scattered_rx = 1;
 379         else
 380                 eth_dev->data->scattered_rx = 0;
 381
 382         cxgbe_enable_rx_queues(pi);
 383
 384         err = cxgbe_setup_rss(pi);
 385         if (err)
 386                 goto out;
 387
 388         for (i = 0; i < pi->n_tx_qsets; i++) {
 389                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 390                 if (err)
 391                         goto out;
 392         }
 393
 394         for (i = 0; i < pi->n_rx_qsets; i++) {
 395                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 396                 if (err)
 397                         goto out;
 398         }
 399
 400         err = cxgbe_link_start(pi);
 401         if (err)
 402                 goto out;
 403
 404 out:
 405         return err;
 406 }
 407
 408 /*
 409  * Stop device: disable rx and tx functions to allow for reconfiguring.
 410  */
 411 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 412 {
 413         struct port_info *pi = eth_dev->data->dev_private;
 414         struct adapter *adapter = pi->adapter;
 415
 416         CXGBE_FUNC_TRACE();
 417
 418         if (!(adapter->flags & FULL_INIT_DONE))
 419                 return 0;
 420
 421         cxgbe_down(pi);
 422
 423         /*
 424          *  We clear queues only if both tx and rx path of the port
 425          *  have been disabled
 426          */
 427         t4_sge_eth_clear_queues(pi);
 428         eth_dev->data->scattered_rx = 0;
 429
 430         return 0;
 431 }
 432
 433 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 434 {
 435         struct port_info *pi = eth_dev->data->dev_private;
 436         struct adapter *adapter = pi->adapter;
 437         int err;
 438
 439         CXGBE_FUNC_TRACE();
 440
 441         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 442                 eth_dev->data->dev_conf.rxmode.offloads |=
 443                         DEV_RX_OFFLOAD_RSS_HASH;
 444
 445         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 446                 err = cxgbe_setup_sge_fwevtq(adapter);
 447                 if (err)
 448                         return err;
 449                 adapter->flags |= FW_QUEUE_BOUND;
 450                 if (is_pf4(adapter)) {
 451                         err = cxgbe_setup_sge_ctrl_txq(adapter);
 452                         if (err)
 453                                 return err;
 454                 }
 455         }
 456
 457         err = cxgbe_cfg_queue_count(eth_dev);
 458         if (err)
 459                 return err;
 460
 461         return 0;
 462 }
 463
 464 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 465 {
 466         int ret;
 467         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 468                                   (eth_dev->data->tx_queues[tx_queue_id]);
 469
 470         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 471
 472         ret = t4_sge_eth_txq_start(txq);
 473         if (ret == 0)
 474                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 475
 476         return ret;
 477 }
 478
 479 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 480 {
 481         int ret;
 482         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 483                                   (eth_dev->data->tx_queues[tx_queue_id]);
 484
 485         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 486
 487         ret = t4_sge_eth_txq_stop(txq);
 488         if (ret == 0)
 489                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 490
 491         return ret;
 492 }
 493
 494 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 495                              uint16_t queue_idx, uint16_t nb_desc,
 496                              unsigned int socket_id,
 497                              const struct rte_eth_txconf *tx_conf __rte_unused)
 498 {
 499         struct port_info *pi = eth_dev->data->dev_private;
 500         struct adapter *adapter = pi->adapter;
 501         struct sge *s = &adapter->sge;
 502         unsigned int temp_nb_desc;
 503         struct sge_eth_txq *txq;
 504         int err = 0;
 505
 506         txq = &s->ethtxq[pi->first_txqset + queue_idx];
 507         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 508                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 509                   socket_id, pi->first_txqset);
 510
 511         /*  Free up the existing queue  */
 512         if (eth_dev->data->tx_queues[queue_idx]) {
 513                 cxgbe_dev_tx_queue_release(eth_dev, queue_idx);
 514                 eth_dev->data->tx_queues[queue_idx] = NULL;
 515         }
 516
 517         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 518
 519         /* Sanity Checking
 520          *
 521          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 522          */
 523         temp_nb_desc = nb_desc;
 524         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 525                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 526                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 527                          CXGBE_DEFAULT_TX_DESC_SIZE);
 528                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 529         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 530                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 531                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 532                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 533                 return -(EINVAL);
 534         }
 535
 536         txq->q.size = temp_nb_desc;
 537
 538         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 539                                    s->fw_evtq.cntxt_id, socket_id);
 540
 541         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 542                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 543         return err;
 544 }
 545
 546 void cxgbe_dev_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 547 {
 548         struct sge_eth_txq *txq = eth_dev->data->tx_queues[qid];
 549
 550         if (txq) {
 551                 struct port_info *pi = (struct port_info *)
 552                                        (txq->eth_dev->data->dev_private);
 553                 struct adapter *adap = pi->adapter;
 554
 555                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 556                           __func__, pi->port_id, txq->q.cntxt_id);
 557
 558                 t4_sge_eth_txq_release(adap, txq);
 559         }
 560 }
 561
 562 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 563 {
 564         struct port_info *pi = eth_dev->data->dev_private;
 565         struct adapter *adap = pi->adapter;
 566         struct sge_eth_rxq *rxq;
 567         int ret;
 568
 569         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 570                   __func__, pi->port_id, rx_queue_id);
 571
 572         rxq = eth_dev->data->rx_queues[rx_queue_id];
 573         ret = t4_sge_eth_rxq_start(adap, rxq);
 574         if (ret == 0)
 575                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 576
 577         return ret;
 578 }
 579
 580 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 581 {
 582         struct port_info *pi = eth_dev->data->dev_private;
 583         struct adapter *adap = pi->adapter;
 584         struct sge_eth_rxq *rxq;
 585         int ret;
 586
 587         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 588                   __func__, pi->port_id, rx_queue_id);
 589
 590         rxq = eth_dev->data->rx_queues[rx_queue_id];
 591         ret = t4_sge_eth_rxq_stop(adap, rxq);
 592         if (ret == 0)
 593                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 594
 595         return ret;
 596 }
 597
 598 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 599                              uint16_t queue_idx, uint16_t nb_desc,
 600                              unsigned int socket_id,
 601                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 602                              struct rte_mempool *mp)
 603 {
 604         unsigned int pkt_len = eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
 605                 RTE_ETHER_CRC_LEN;
 606         struct port_info *pi = eth_dev->data->dev_private;
 607         struct adapter *adapter = pi->adapter;
 608         struct rte_eth_dev_info dev_info;
 609         struct sge *s = &adapter->sge;
 610         unsigned int temp_nb_desc;
 611         int err = 0, msi_idx = 0;
 612         struct sge_eth_rxq *rxq;
 613
 614         rxq = &s->ethrxq[pi->first_rxqset + queue_idx];
 615         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 616                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 617                   socket_id, mp);
 618
 619         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 620         if (err != 0) {
 621                 dev_err(adap, "%s: error during getting ethernet device info",
 622                         __func__);
 623                 return err;
 624         }
 625
 626         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 627         if ((pkt_len < dev_info.min_rx_bufsize) ||
 628             (pkt_len > dev_info.max_rx_pktlen)) {
 629                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 630                         __func__, dev_info.min_rx_bufsize,
 631                         dev_info.max_rx_pktlen);
 632                 return -EINVAL;
 633         }
 634
 635         /*  Free up the existing queue  */
 636         if (eth_dev->data->rx_queues[queue_idx]) {
 637                 cxgbe_dev_rx_queue_release(eth_dev, queue_idx);
 638                 eth_dev->data->rx_queues[queue_idx] = NULL;
 639         }
 640
 641         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 642
 643         /* Sanity Checking
 644          *
 645          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 646          */
 647         temp_nb_desc = nb_desc;
 648         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 649                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 650                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 651                          CXGBE_DEFAULT_RX_DESC_SIZE);
 652                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 653         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 654                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 655                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 656                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 657                 return -(EINVAL);
 658         }
 659
 660         rxq->rspq.size = temp_nb_desc;
 661         rxq->fl.size = temp_nb_desc;
 662
 663         /* Set to jumbo mode if necessary */
 664         if (eth_dev->data->mtu > RTE_ETHER_MTU)
 665                 eth_dev->data->dev_conf.rxmode.offloads |=
 666                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 667         else
 668                 eth_dev->data->dev_conf.rxmode.offloads &=
 669                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 670
 671         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 672                                &rxq->fl, NULL,
 673                                is_pf4(adapter) ?
 674                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 675                                queue_idx, socket_id);
 676
 677         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 678                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 679                   rxq->rspq.abs_id);
 680         return err;
 681 }
 682
 683 void cxgbe_dev_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 684 {
 685         struct sge_eth_rxq *rxq = eth_dev->data->rx_queues[qid];
 686
 687         if (rxq) {
 688                 struct port_info *pi = (struct port_info *)
 689                                        (rxq->rspq.eth_dev->data->dev_private);
 690                 struct adapter *adap = pi->adapter;
 691
 692                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 693                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 694
 695                 t4_sge_eth_rxq_release(adap, rxq);
 696         }
 697 }
 698
 699 /*
 700  * Get port statistics.
 701  */
 702 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 703                                 struct rte_eth_stats *eth_stats)
 704 {
 705         struct port_info *pi = eth_dev->data->dev_private;
 706         struct adapter *adapter = pi->adapter;
 707         struct sge *s = &adapter->sge;
 708         struct port_stats ps;
 709         unsigned int i;
 710
 711         cxgbe_stats_get(pi, &ps);
 712
 713         /* RX Stats */
 714         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 715                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 716                               ps.rx_trunc0 + ps.rx_trunc1 +
 717                               ps.rx_trunc2 + ps.rx_trunc3;
 718         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 719                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 720                               ps.rx_len_err;
 721
 722         /* TX Stats */
 723         eth_stats->opackets = ps.tx_frames;
 724         eth_stats->obytes   = ps.tx_octets;
 725         eth_stats->oerrors  = ps.tx_error_frames;
 726
 727         for (i = 0; i < pi->n_rx_qsets; i++) {
 728                 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i];
 729
 730                 eth_stats->ipackets += rxq->stats.pkts;
 731                 eth_stats->ibytes += rxq->stats.rx_bytes;
 732         }
 733
 734         return 0;
 735 }
 736
 737 /*
 738  * Reset port statistics.
 739  */
 740 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 741 {
 742         struct port_info *pi = eth_dev->data->dev_private;
 743         struct adapter *adapter = pi->adapter;
 744         struct sge *s = &adapter->sge;
 745         unsigned int i;
 746
 747         cxgbe_stats_reset(pi);
 748         for (i = 0; i < pi->n_rx_qsets; i++) {
 749                 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i];
 750
 751                 memset(&rxq->stats, 0, sizeof(rxq->stats));
 752         }
 753         for (i = 0; i < pi->n_tx_qsets; i++) {
 754                 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + i];
 755
 756                 memset(&txq->stats, 0, sizeof(txq->stats));
 757         }
 758
 759         return 0;
 760 }
 761
 762 /* Store extended statistics names and its offset in stats structure  */
 763 struct cxgbe_dev_xstats_name_off {
 764         char name[RTE_ETH_XSTATS_NAME_SIZE];
 765         unsigned int offset;
 766 };
 767
 768 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_rxq_stats_strings[] = {
 769         {"packets", offsetof(struct sge_eth_rx_stats, pkts)},
 770         {"bytes", offsetof(struct sge_eth_rx_stats, rx_bytes)},
 771         {"checksum_offloads", offsetof(struct sge_eth_rx_stats, rx_cso)},
 772         {"vlan_extractions", offsetof(struct sge_eth_rx_stats, vlan_ex)},
 773         {"dropped_packets", offsetof(struct sge_eth_rx_stats, rx_drops)},
 774 };
 775
 776 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_txq_stats_strings[] = {
 777         {"packets", offsetof(struct sge_eth_tx_stats, pkts)},
 778         {"bytes", offsetof(struct sge_eth_tx_stats, tx_bytes)},
 779         {"tso_requests", offsetof(struct sge_eth_tx_stats, tso)},
 780         {"checksum_offloads", offsetof(struct sge_eth_tx_stats, tx_cso)},
 781         {"vlan_insertions", offsetof(struct sge_eth_tx_stats, vlan_ins)},
 782         {"packet_mapping_errors",
 783          offsetof(struct sge_eth_tx_stats, mapping_err)},
 784         {"coalesced_wrs", offsetof(struct sge_eth_tx_stats, coal_wr)},
 785         {"coalesced_packets", offsetof(struct sge_eth_tx_stats, coal_pkts)},
 786 };
 787
 788 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_port_stats_strings[] = {
 789         {"tx_bytes", offsetof(struct port_stats, tx_octets)},
 790         {"tx_packets", offsetof(struct port_stats, tx_frames)},
 791         {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)},
 792         {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)},
 793         {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)},
 794         {"tx_error_packets", offsetof(struct port_stats, tx_error_frames)},
 795         {"tx_size_64_packets", offsetof(struct port_stats, tx_frames_64)},
 796         {"tx_size_65_to_127_packets",
 797          offsetof(struct port_stats, tx_frames_65_127)},
 798         {"tx_size_128_to_255_packets",
 799          offsetof(struct port_stats, tx_frames_128_255)},
 800         {"tx_size_256_to_511_packets",
 801          offsetof(struct port_stats, tx_frames_256_511)},
 802         {"tx_size_512_to_1023_packets",
 803          offsetof(struct port_stats, tx_frames_512_1023)},
 804         {"tx_size_1024_to_1518_packets",
 805          offsetof(struct port_stats, tx_frames_1024_1518)},
 806         {"tx_size_1519_to_max_packets",
 807          offsetof(struct port_stats, tx_frames_1519_max)},
 808         {"tx_drop_packets", offsetof(struct port_stats, tx_drop)},
 809         {"tx_pause_frames", offsetof(struct port_stats, tx_pause)},
 810         {"tx_ppp_pri0_packets", offsetof(struct port_stats, tx_ppp0)},
 811         {"tx_ppp_pri1_packets", offsetof(struct port_stats, tx_ppp1)},
 812         {"tx_ppp_pri2_packets", offsetof(struct port_stats, tx_ppp2)},
 813         {"tx_ppp_pri3_packets", offsetof(struct port_stats, tx_ppp3)},
 814         {"tx_ppp_pri4_packets", offsetof(struct port_stats, tx_ppp4)},
 815         {"tx_ppp_pri5_packets", offsetof(struct port_stats, tx_ppp5)},
 816         {"tx_ppp_pri6_packets", offsetof(struct port_stats, tx_ppp6)},
 817         {"tx_ppp_pri7_packets", offsetof(struct port_stats, tx_ppp7)},
 818         {"rx_bytes", offsetof(struct port_stats, rx_octets)},
 819         {"rx_packets", offsetof(struct port_stats, rx_frames)},
 820         {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)},
 821         {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)},
 822         {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)},
 823         {"rx_too_long_packets", offsetof(struct port_stats, rx_too_long)},
 824         {"rx_jabber_packets", offsetof(struct port_stats, rx_jabber)},
 825         {"rx_fcs_error_packets", offsetof(struct port_stats, rx_fcs_err)},
 826         {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)},
 827         {"rx_symbol_error_packets",
 828          offsetof(struct port_stats, rx_symbol_err)},
 829         {"rx_short_packets", offsetof(struct port_stats, rx_runt)},
 830         {"rx_size_64_packets", offsetof(struct port_stats, rx_frames_64)},
 831         {"rx_size_65_to_127_packets",
 832          offsetof(struct port_stats, rx_frames_65_127)},
 833         {"rx_size_128_to_255_packets",
 834          offsetof(struct port_stats, rx_frames_128_255)},
 835         {"rx_size_256_to_511_packets",
 836          offsetof(struct port_stats, rx_frames_256_511)},
 837         {"rx_size_512_to_1023_packets",
 838          offsetof(struct port_stats, rx_frames_512_1023)},
 839         {"rx_size_1024_to_1518_packets",
 840          offsetof(struct port_stats, rx_frames_1024_1518)},
 841         {"rx_size_1519_to_max_packets",
 842          offsetof(struct port_stats, rx_frames_1519_max)},
 843         {"rx_pause_packets", offsetof(struct port_stats, rx_pause)},
 844         {"rx_ppp_pri0_packets", offsetof(struct port_stats, rx_ppp0)},
 845         {"rx_ppp_pri1_packets", offsetof(struct port_stats, rx_ppp1)},
 846         {"rx_ppp_pri2_packets", offsetof(struct port_stats, rx_ppp2)},
 847         {"rx_ppp_pri3_packets", offsetof(struct port_stats, rx_ppp3)},
 848         {"rx_ppp_pri4_packets", offsetof(struct port_stats, rx_ppp4)},
 849         {"rx_ppp_pri5_packets", offsetof(struct port_stats, rx_ppp5)},
 850         {"rx_ppp_pri6_packets", offsetof(struct port_stats, rx_ppp6)},
 851         {"rx_ppp_pri7_packets", offsetof(struct port_stats, rx_ppp7)},
 852         {"rx_bg0_dropped_packets", offsetof(struct port_stats, rx_ovflow0)},
 853         {"rx_bg1_dropped_packets", offsetof(struct port_stats, rx_ovflow1)},
 854         {"rx_bg2_dropped_packets", offsetof(struct port_stats, rx_ovflow2)},
 855         {"rx_bg3_dropped_packets", offsetof(struct port_stats, rx_ovflow3)},
 856         {"rx_bg0_truncated_packets", offsetof(struct port_stats, rx_trunc0)},
 857         {"rx_bg1_truncated_packets", offsetof(struct port_stats, rx_trunc1)},
 858         {"rx_bg2_truncated_packets", offsetof(struct port_stats, rx_trunc2)},
 859         {"rx_bg3_truncated_packets", offsetof(struct port_stats, rx_trunc3)},
 860 };
 861
 862 static const struct cxgbe_dev_xstats_name_off
 863 cxgbevf_dev_port_stats_strings[] = {
 864         {"tx_bytes", offsetof(struct port_stats, tx_octets)},
 865         {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)},
 866         {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)},
 867         {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)},
 868         {"tx_drop_packets", offsetof(struct port_stats, tx_drop)},
 869         {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)},
 870         {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)},
 871         {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)},
 872         {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)},
 873 };
 874
 875 #define CXGBE_NB_RXQ_STATS RTE_DIM(cxgbe_dev_rxq_stats_strings)
 876 #define CXGBE_NB_TXQ_STATS RTE_DIM(cxgbe_dev_txq_stats_strings)
 877 #define CXGBE_NB_PORT_STATS RTE_DIM(cxgbe_dev_port_stats_strings)
 878 #define CXGBEVF_NB_PORT_STATS RTE_DIM(cxgbevf_dev_port_stats_strings)
 879
 880 static u16 cxgbe_dev_xstats_count(struct port_info *pi)
 881 {
 882         u16 count;
 883
 884         count = (pi->n_tx_qsets * CXGBE_NB_TXQ_STATS) +
 885                 (pi->n_rx_qsets * CXGBE_NB_RXQ_STATS);
 886
 887         if (is_pf4(pi->adapter) != 0)
 888                 count += CXGBE_NB_PORT_STATS;
 889         else
 890                 count += CXGBEVF_NB_PORT_STATS;
 891
 892         return count;
 893 }
 894
 895 static int cxgbe_dev_xstats(struct rte_eth_dev *dev,
 896                             struct rte_eth_xstat_name *xstats_names,
 897                             struct rte_eth_xstat *xstats, unsigned int size)
 898 {
 899         const struct cxgbe_dev_xstats_name_off *xstats_str;
 900         struct port_info *pi = dev->data->dev_private;
 901         struct adapter *adap = pi->adapter;
 902         struct sge *s = &adap->sge;
 903         u16 count, i, qid, nstats;
 904         struct port_stats ps;
 905         u64 *stats_ptr;
 906
 907         count = cxgbe_dev_xstats_count(pi);
 908         if (size < count)
 909                 return count;
 910
 911         if (is_pf4(adap) != 0) {
 912                 /* port stats for PF*/
 913                 cxgbe_stats_get(pi, &ps);
 914                 xstats_str = cxgbe_dev_port_stats_strings;
 915                 nstats = CXGBE_NB_PORT_STATS;
 916         } else {
 917                 /* port stats for VF*/
 918                 cxgbevf_stats_get(pi, &ps);
 919                 xstats_str = cxgbevf_dev_port_stats_strings;
 920                 nstats = CXGBEVF_NB_PORT_STATS;
 921         }
 922
 923         count = 0;
 924         for (i = 0; i < nstats; i++, count++) {
 925                 if (xstats_names != NULL)
 926                         snprintf(xstats_names[count].name,
 927                                  sizeof(xstats_names[count].name),
 928                                  "%s", xstats_str[i].name);
 929                 if (xstats != NULL) {
 930                         stats_ptr = RTE_PTR_ADD(&ps,
 931                                                 xstats_str[i].offset);
 932                         xstats[count].value = *stats_ptr;
 933                         xstats[count].id = count;
 934                 }
 935         }
 936
 937         /* per-txq stats */
 938         xstats_str = cxgbe_dev_txq_stats_strings;
 939         for (qid = 0; qid < pi->n_tx_qsets; qid++) {
 940                 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + qid];
 941
 942                 for (i = 0; i < CXGBE_NB_TXQ_STATS; i++, count++) {
 943                         if (xstats_names != NULL)
 944                                 snprintf(xstats_names[count].name,
 945                                          sizeof(xstats_names[count].name),
 946                                          "tx_q%u_%s",
 947                                          qid, xstats_str[i].name);
 948                         if (xstats != NULL) {
 949                                 stats_ptr = RTE_PTR_ADD(&txq->stats,
 950                                                         xstats_str[i].offset);
 951                                 xstats[count].value = *stats_ptr;
 952                                 xstats[count].id = count;
 953                         }
 954                 }
 955         }
 956
 957         /* per-rxq stats */
 958         xstats_str = cxgbe_dev_rxq_stats_strings;
 959         for (qid = 0; qid < pi->n_rx_qsets; qid++) {
 960                 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + qid];
 961
 962                 for (i = 0; i < CXGBE_NB_RXQ_STATS; i++, count++) {
 963                         if (xstats_names != NULL)
 964                                 snprintf(xstats_names[count].name,
 965                                          sizeof(xstats_names[count].name),
 966                                          "rx_q%u_%s",
 967                                          qid, xstats_str[i].name);
 968                         if (xstats != NULL) {
 969                                 stats_ptr = RTE_PTR_ADD(&rxq->stats,
 970                                                         xstats_str[i].offset);
 971                                 xstats[count].value = *stats_ptr;
 972                                 xstats[count].id = count;
 973                         }
 974                 }
 975         }
 976
 977         return count;
 978 }
 979
 980 /* Get port extended statistics by ID. */
 981 int cxgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev,
 982                                const uint64_t *ids, uint64_t *values,
 983                                unsigned int n)
 984 {
 985         struct port_info *pi = dev->data->dev_private;
 986         struct rte_eth_xstat *xstats_copy;
 987         u16 count, i;
 988         int ret = 0;
 989
 990         count = cxgbe_dev_xstats_count(pi);
 991         if (ids == NULL || values == NULL)
 992                 return count;
 993
 994         xstats_copy = rte_calloc(NULL, count, sizeof(*xstats_copy), 0);
 995         if (xstats_copy == NULL)
 996                 return -ENOMEM;
 997
 998         cxgbe_dev_xstats(dev, NULL, xstats_copy, count);
 999
1000         for (i = 0; i < n; i++) {
1001                 if (ids[i] >= count) {
1002                         ret = -EINVAL;
1003                         goto out_err;
1004                 }
1005                 values[i] = xstats_copy[ids[i]].value;
1006         }
1007
1008         ret = n;
1009
1010 out_err:
1011         rte_free(xstats_copy);
1012         return ret;
1013 }
1014
1015 /* Get names of port extended statistics by ID. */
1016 int cxgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
1017                                             const uint64_t *ids,
1018                                             struct rte_eth_xstat_name *xnames,
1019                                             unsigned int n)
1020 {
1021         struct port_info *pi = dev->data->dev_private;
1022         struct rte_eth_xstat_name *xnames_copy;
1023         u16 count, i;
1024         int ret = 0;
1025
1026         count = cxgbe_dev_xstats_count(pi);
1027         if (ids == NULL || xnames == NULL)
1028                 return count;
1029
1030         xnames_copy = rte_calloc(NULL, count, sizeof(*xnames_copy), 0);
1031         if (xnames_copy == NULL)
1032                 return -ENOMEM;
1033
1034         cxgbe_dev_xstats(dev, xnames_copy, NULL, count);
1035
1036         for (i = 0; i < n; i++) {
1037                 if (ids[i] >= count) {
1038                         ret = -EINVAL;
1039                         goto out_err;
1040                 }
1041                 rte_strlcpy(xnames[i].name, xnames_copy[ids[i]].name,
1042                             sizeof(xnames[i].name));
1043         }
1044
1045         ret = n;
1046
1047 out_err:
1048         rte_free(xnames_copy);
1049         return ret;
1050 }
1051
1052 /* Get port extended statistics. */
1053 int cxgbe_dev_xstats_get(struct rte_eth_dev *dev,
1054                          struct rte_eth_xstat *xstats, unsigned int n)
1055 {
1056         return cxgbe_dev_xstats(dev, NULL, xstats, n);
1057 }
1058
1059 /* Get names of port extended statistics. */
1060 int cxgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
1061                                struct rte_eth_xstat_name *xstats_names,
1062                                unsigned int n)
1063 {
1064         return cxgbe_dev_xstats(dev, xstats_names, NULL, n);
1065 }
1066
1067 /* Reset port extended statistics. */
1068 static int cxgbe_dev_xstats_reset(struct rte_eth_dev *dev)
1069 {
1070         return cxgbe_dev_stats_reset(dev);
1071 }
1072
1073 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1074                                struct rte_eth_fc_conf *fc_conf)
1075 {
1076         struct port_info *pi = eth_dev->data->dev_private;
1077         struct link_config *lc = &pi->link_cfg;
1078         u8 rx_pause = 0, tx_pause = 0;
1079         u32 caps = lc->link_caps;
1080
1081         if (caps & FW_PORT_CAP32_ANEG)
1082                 fc_conf->autoneg = 1;
1083
1084         if (caps & FW_PORT_CAP32_FC_TX)
1085                 tx_pause = 1;
1086
1087         if (caps & FW_PORT_CAP32_FC_RX)
1088                 rx_pause = 1;
1089
1090         if (rx_pause && tx_pause)
1091                 fc_conf->mode = RTE_FC_FULL;
1092         else if (rx_pause)
1093                 fc_conf->mode = RTE_FC_RX_PAUSE;
1094         else if (tx_pause)
1095                 fc_conf->mode = RTE_FC_TX_PAUSE;
1096         else
1097                 fc_conf->mode = RTE_FC_NONE;
1098         return 0;
1099 }
1100
1101 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1102                                struct rte_eth_fc_conf *fc_conf)
1103 {
1104         struct port_info *pi = eth_dev->data->dev_private;
1105         struct link_config *lc = &pi->link_cfg;
1106         u32 new_caps = lc->admin_caps;
1107         u8 tx_pause = 0, rx_pause = 0;
1108         int ret;
1109
1110         if (fc_conf->mode == RTE_FC_FULL) {
1111                 tx_pause = 1;
1112                 rx_pause = 1;
1113         } else if (fc_conf->mode == RTE_FC_TX_PAUSE) {
1114                 tx_pause = 1;
1115         } else if (fc_conf->mode == RTE_FC_RX_PAUSE) {
1116                 rx_pause = 1;
1117         }
1118
1119         ret = t4_set_link_pause(pi, fc_conf->autoneg, tx_pause,
1120                                 rx_pause, &new_caps);
1121         if (ret != 0)
1122                 return ret;
1123
1124         if (!fc_conf->autoneg) {
1125                 if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)
1126                         new_caps |= FW_PORT_CAP32_FORCE_PAUSE;
1127         } else {
1128                 new_caps &= ~FW_PORT_CAP32_FORCE_PAUSE;
1129         }
1130
1131         if (new_caps != lc->admin_caps) {
1132                 ret = t4_link_l1cfg(pi, new_caps);
1133                 if (ret == 0)
1134                         lc->admin_caps = new_caps;
1135         }
1136
1137         return ret;
1138 }
1139
1140 const uint32_t *
1141 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1142 {
1143         static const uint32_t ptypes[] = {
1144                 RTE_PTYPE_L3_IPV4,
1145                 RTE_PTYPE_L3_IPV6,
1146                 RTE_PTYPE_UNKNOWN
1147         };
1148
1149         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
1150                 return ptypes;
1151         return NULL;
1152 }
1153
1154 /* Update RSS hash configuration
1155  */
1156 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
1157                                      struct rte_eth_rss_conf *rss_conf)
1158 {
1159         struct port_info *pi = dev->data->dev_private;
1160         struct adapter *adapter = pi->adapter;
1161         int err;
1162
1163         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
1164         if (err)
1165                 return err;
1166
1167         pi->rss_hf = rss_conf->rss_hf;
1168
1169         if (rss_conf->rss_key) {
1170                 u32 key[10], mod_key[10];
1171                 int i, j;
1172
1173                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
1174
1175                 for (i = 9, j = 0; i >= 0; i--, j++)
1176                         mod_key[j] = cpu_to_be32(key[i]);
1177
1178                 t4_write_rss_key(adapter, mod_key, -1);
1179         }
1180
1181         return 0;
1182 }
1183
1184 /* Get RSS hash configuration
1185  */
1186 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1187                                        struct rte_eth_rss_conf *rss_conf)
1188 {
1189         struct port_info *pi = dev->data->dev_private;
1190         struct adapter *adapter = pi->adapter;
1191         u64 rss_hf = 0;
1192         u64 flags = 0;
1193         int err;
1194
1195         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
1196                                     &flags, NULL);
1197
1198         if (err)
1199                 return err;
1200
1201         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
1202                 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
1203                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
1204                         rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
1205         }
1206
1207         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1208                 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
1209
1210         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
1211                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1212                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
1213                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1214         }
1215
1216         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1217                 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
1218
1219         rss_conf->rss_hf = rss_hf;
1220
1221         if (rss_conf->rss_key) {
1222                 u32 key[10], mod_key[10];
1223                 int i, j;
1224
1225                 t4_read_rss_key(adapter, key);
1226
1227                 for (i = 9, j = 0; i >= 0; i--, j++)
1228                         mod_key[j] = be32_to_cpu(key[i]);
1229
1230                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
1231         }
1232
1233         return 0;
1234 }
1235
1236 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
1237                                      struct rte_eth_rss_reta_entry64 *reta_conf,
1238                                      uint16_t reta_size)
1239 {
1240         struct port_info *pi = dev->data->dev_private;
1241         struct adapter *adapter = pi->adapter;
1242         u16 i, idx, shift, *rss;
1243         int ret;
1244
1245         if (!(adapter->flags & FULL_INIT_DONE))
1246                 return -ENOMEM;
1247
1248         if (!reta_size || reta_size > pi->rss_size)
1249                 return -EINVAL;
1250
1251         rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0);
1252         if (!rss)
1253                 return -ENOMEM;
1254
1255         rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16));
1256         for (i = 0; i < reta_size; i++) {
1257                 idx = i / RTE_RETA_GROUP_SIZE;
1258                 shift = i % RTE_RETA_GROUP_SIZE;
1259                 if (!(reta_conf[idx].mask & (1ULL << shift)))
1260                         continue;
1261
1262                 rss[i] = reta_conf[idx].reta[shift];
1263         }
1264
1265         ret = cxgbe_write_rss(pi, rss);
1266         if (!ret)
1267                 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16));
1268
1269         rte_free(rss);
1270         return ret;
1271 }
1272
1273 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
1274                                     struct rte_eth_rss_reta_entry64 *reta_conf,
1275                                     uint16_t reta_size)
1276 {
1277         struct port_info *pi = dev->data->dev_private;
1278         struct adapter *adapter = pi->adapter;
1279         u16 i, idx, shift;
1280
1281         if (!(adapter->flags & FULL_INIT_DONE))
1282                 return -ENOMEM;
1283
1284         if (!reta_size || reta_size > pi->rss_size)
1285                 return -EINVAL;
1286
1287         for (i = 0; i < reta_size; i++) {
1288                 idx = i / RTE_RETA_GROUP_SIZE;
1289                 shift = i % RTE_RETA_GROUP_SIZE;
1290                 if (!(reta_conf[idx].mask & (1ULL << shift)))
1291                         continue;
1292
1293                 reta_conf[idx].reta[shift] = pi->rss[i];
1294         }
1295
1296         return 0;
1297 }
1298
1299 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
1300 {
1301         RTE_SET_USED(dev);
1302         return EEPROMSIZE;
1303 }
1304
1305 /**
1306  * eeprom_ptov - translate a physical EEPROM address to virtual
1307  * @phys_addr: the physical EEPROM address
1308  * @fn: the PCI function number
1309  * @sz: size of function-specific area
1310  *
1311  * Translate a physical EEPROM address to virtual.  The first 1K is
1312  * accessed through virtual addresses starting at 31K, the rest is
1313  * accessed through virtual addresses starting at 0.
1314  *
1315  * The mapping is as follows:
1316  * [0..1K) -> [31K..32K)
1317  * [1K..1K+A) -> [31K-A..31K)
1318  * [1K+A..ES) -> [0..ES-A-1K)
1319  *
1320  * where A = @fn * @sz, and ES = EEPROM size.
1321  */
1322 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
1323 {
1324         fn *= sz;
1325         if (phys_addr < 1024)
1326                 return phys_addr + (31 << 10);
1327         if (phys_addr < 1024 + fn)
1328                 return fn + phys_addr - 1024;
1329         if (phys_addr < EEPROMSIZE)
1330                 return phys_addr - 1024 - fn;
1331         if (phys_addr < EEPROMVSIZE)
1332                 return phys_addr - 1024;
1333         return -EINVAL;
1334 }
1335
1336 /* The next two routines implement eeprom read/write from physical addresses.
1337  */
1338 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
1339 {
1340         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1341
1342         if (vaddr >= 0)
1343                 vaddr = t4_seeprom_read(adap, vaddr, v);
1344         return vaddr < 0 ? vaddr : 0;
1345 }
1346
1347 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
1348 {
1349         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1350
1351         if (vaddr >= 0)
1352                 vaddr = t4_seeprom_write(adap, vaddr, v);
1353         return vaddr < 0 ? vaddr : 0;
1354 }
1355
1356 #define EEPROM_MAGIC 0x38E2F10C
1357
1358 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
1359                             struct rte_dev_eeprom_info *e)
1360 {
1361         struct port_info *pi = dev->data->dev_private;
1362         struct adapter *adapter = pi->adapter;
1363         u32 i, err = 0;
1364         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
1365
1366         if (!buf)
1367                 return -ENOMEM;
1368
1369         e->magic = EEPROM_MAGIC;
1370         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
1371                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1372
1373         if (!err)
1374                 rte_memcpy(e->data, buf + e->offset, e->length);
1375         rte_free(buf);
1376         return err;
1377 }
1378
1379 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
1380                             struct rte_dev_eeprom_info *eeprom)
1381 {
1382         struct port_info *pi = dev->data->dev_private;
1383         struct adapter *adapter = pi->adapter;
1384         u8 *buf;
1385         int err = 0;
1386         u32 aligned_offset, aligned_len, *p;
1387
1388         if (eeprom->magic != EEPROM_MAGIC)
1389                 return -EINVAL;
1390
1391         aligned_offset = eeprom->offset & ~3;
1392         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1393
1394         if (adapter->pf > 0) {
1395                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1396
1397                 if (aligned_offset < start ||
1398                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
1399                         return -EPERM;
1400         }
1401
1402         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1403                 /* RMW possibly needed for first or last words.
1404                  */
1405                 buf = rte_zmalloc(NULL, aligned_len, 0);
1406                 if (!buf)
1407                         return -ENOMEM;
1408                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1409                 if (!err && aligned_len > 4)
1410                         err = eeprom_rd_phys(adapter,
1411                                              aligned_offset + aligned_len - 4,
1412                                              (u32 *)&buf[aligned_len - 4]);
1413                 if (err)
1414                         goto out;
1415                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1416                            eeprom->length);
1417         } else {
1418                 buf = eeprom->data;
1419         }
1420
1421         err = t4_seeprom_wp(adapter, false);
1422         if (err)
1423                 goto out;
1424
1425         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1426                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1427                 aligned_offset += 4;
1428         }
1429
1430         if (!err)
1431                 err = t4_seeprom_wp(adapter, true);
1432 out:
1433         if (buf != eeprom->data)
1434                 rte_free(buf);
1435         return err;
1436 }
1437
1438 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1439 {
1440         struct port_info *pi = eth_dev->data->dev_private;
1441         struct adapter *adapter = pi->adapter;
1442
1443         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1444 }
1445
1446 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1447                           struct rte_dev_reg_info *regs)
1448 {
1449         struct port_info *pi = eth_dev->data->dev_private;
1450         struct adapter *adapter = pi->adapter;
1451
1452         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1453                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1454                 (1 << 16);
1455
1456         if (regs->data == NULL) {
1457                 regs->length = cxgbe_get_regs_len(eth_dev);
1458                 regs->width = sizeof(uint32_t);
1459
1460                 return 0;
1461         }
1462
1463         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1464
1465         return 0;
1466 }
1467
1468 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1469 {
1470         struct port_info *pi = dev->data->dev_private;
1471         int ret;
1472
1473         ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1474         if (ret < 0) {
1475                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1476                         ret);
1477                 return ret;
1478         }
1479         pi->xact_addr_filt = ret;
1480         return 0;
1481 }
1482
1483 static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc,
1484                                            struct rte_eth_fec_capa *capa_arr)
1485 {
1486         int num = 0;
1487
1488         if (lc->pcaps & FW_PORT_CAP32_SPEED_100G) {
1489                 if (capa_arr) {
1490                         capa_arr[num].speed = ETH_SPEED_NUM_100G;
1491                         capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1492                                              RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1493                 }
1494                 num++;
1495         }
1496
1497         if (lc->pcaps & FW_PORT_CAP32_SPEED_50G) {
1498                 if (capa_arr) {
1499                         capa_arr[num].speed = ETH_SPEED_NUM_50G;
1500                         capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1501                                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
1502                 }
1503                 num++;
1504         }
1505
1506         if (lc->pcaps & FW_PORT_CAP32_SPEED_25G) {
1507                 if (capa_arr) {
1508                         capa_arr[num].speed = ETH_SPEED_NUM_25G;
1509                         capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1510                                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
1511                                              RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1512                 }
1513                 num++;
1514         }
1515
1516         return num;
1517 }
1518
1519 static int cxgbe_fec_get_capability(struct rte_eth_dev *dev,
1520                                     struct rte_eth_fec_capa *speed_fec_capa,
1521                                     unsigned int num)
1522 {
1523         struct port_info *pi = dev->data->dev_private;
1524         struct link_config *lc = &pi->link_cfg;
1525         u8 num_entries;
1526
1527         if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1528                 return -EOPNOTSUPP;
1529
1530         num_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL);
1531         if (!speed_fec_capa || num < num_entries)
1532                 return num_entries;
1533
1534         return cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa);
1535 }
1536
1537 static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
1538 {
1539         struct port_info *pi = dev->data->dev_private;
1540         struct link_config *lc = &pi->link_cfg;
1541         u32 fec_caps = 0, caps = lc->link_caps;
1542
1543         if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1544                 return -EOPNOTSUPP;
1545
1546         if (caps & FW_PORT_CAP32_FEC_RS)
1547                 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1548         else if (caps & FW_PORT_CAP32_FEC_BASER_RS)
1549                 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
1550         else
1551                 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
1552
1553         *fec_capa = fec_caps;
1554         return 0;
1555 }
1556
1557 static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa)
1558 {
1559         struct port_info *pi = dev->data->dev_private;
1560         u8 fec_rs = 0, fec_baser = 0, fec_none = 0;
1561         struct link_config *lc = &pi->link_cfg;
1562         u32 new_caps = lc->admin_caps;
1563         int ret;
1564
1565         if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1566                 return -EOPNOTSUPP;
1567
1568         if (!fec_capa)
1569                 return -EINVAL;
1570
1571         if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO))
1572                 goto set_fec;
1573
1574         if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC))
1575                 fec_none = 1;
1576
1577         if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER))
1578                 fec_baser = 1;
1579
1580         if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS))
1581                 fec_rs = 1;
1582
1583 set_fec:
1584         ret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps);
1585         if (ret != 0)
1586                 return ret;
1587
1588         if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
1589                 new_caps |= FW_PORT_CAP32_FORCE_FEC;
1590         else
1591                 new_caps &= ~FW_PORT_CAP32_FORCE_FEC;
1592
1593         if (new_caps != lc->admin_caps) {
1594                 ret = t4_link_l1cfg(pi, new_caps);
1595                 if (ret == 0)
1596                         lc->admin_caps = new_caps;
1597         }
1598
1599         return ret;
1600 }
1601
1602 int cxgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
1603                          size_t fw_size)
1604 {
1605         struct port_info *pi = dev->data->dev_private;
1606         struct adapter *adapter = pi->adapter;
1607         int ret;
1608
1609         if (adapter->params.fw_vers == 0)
1610                 return -EIO;
1611
1612         ret = snprintf(fw_version, fw_size, "%u.%u.%u.%u",
1613                        G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
1614                        G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
1615                        G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
1616                        G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
1617         if (ret < 0)
1618                 return -EINVAL;
1619
1620         ret += 1;
1621         if (fw_size < (size_t)ret)
1622                 return ret;
1623
1624         return 0;
1625 }
1626
1627 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1628         .dev_start              = cxgbe_dev_start,
1629         .dev_stop               = cxgbe_dev_stop,
1630         .dev_close              = cxgbe_dev_close,
1631         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1632         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1633         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1634         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1635         .dev_configure          = cxgbe_dev_configure,
1636         .dev_infos_get          = cxgbe_dev_info_get,
1637         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1638         .link_update            = cxgbe_dev_link_update,
1639         .dev_set_link_up        = cxgbe_dev_set_link_up,
1640         .dev_set_link_down      = cxgbe_dev_set_link_down,
1641         .mtu_set                = cxgbe_dev_mtu_set,
1642         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1643         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1644         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1645         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1646         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1647         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1648         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1649         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1650         .flow_ops_get           = cxgbe_dev_flow_ops_get,
1651         .stats_get              = cxgbe_dev_stats_get,
1652         .stats_reset            = cxgbe_dev_stats_reset,
1653         .xstats_get             = cxgbe_dev_xstats_get,
1654         .xstats_get_by_id       = cxgbe_dev_xstats_get_by_id,
1655         .xstats_get_names       = cxgbe_dev_xstats_get_names,
1656         .xstats_get_names_by_id = cxgbe_dev_xstats_get_names_by_id,
1657         .xstats_reset           = cxgbe_dev_xstats_reset,
1658         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1659         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1660         .get_eeprom_length      = cxgbe_get_eeprom_length,
1661         .get_eeprom             = cxgbe_get_eeprom,
1662         .set_eeprom             = cxgbe_set_eeprom,
1663         .get_reg                = cxgbe_get_regs,
1664         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1665         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1666         .mac_addr_set           = cxgbe_mac_addr_set,
1667         .reta_update            = cxgbe_dev_rss_reta_update,
1668         .reta_query             = cxgbe_dev_rss_reta_query,
1669         .fec_get_capability     = cxgbe_fec_get_capability,
1670         .fec_get                = cxgbe_fec_get,
1671         .fec_set                = cxgbe_fec_set,
1672         .fw_version_get         = cxgbe_fw_version_get,
1673 };
1674
1675 /*
1676  * Initialize driver
1677  * It returns 0 on success.
1678  */
1679 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1680 {
1681         struct rte_pci_device *pci_dev;
1682         struct port_info *pi = eth_dev->data->dev_private;
1683         struct adapter *adapter = NULL;
1684         char name[RTE_ETH_NAME_MAX_LEN];
1685         int err = 0;
1686
1687         CXGBE_FUNC_TRACE();
1688
1689         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1690         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1691         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1692         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1693
1694         /* for secondary processes, we attach to ethdevs allocated by primary
1695          * and do minimal initialization.
1696          */
1697         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1698                 int i;
1699
1700                 for (i = 1; i < MAX_NPORTS; i++) {
1701                         struct rte_eth_dev *rest_eth_dev;
1702                         char namei[RTE_ETH_NAME_MAX_LEN];
1703
1704                         snprintf(namei, sizeof(namei), "%s_%d",
1705                                  pci_dev->device.name, i);
1706                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1707                         if (rest_eth_dev) {
1708                                 rest_eth_dev->device = &pci_dev->device;
1709                                 rest_eth_dev->dev_ops =
1710                                         eth_dev->dev_ops;
1711                                 rest_eth_dev->rx_pkt_burst =
1712                                         eth_dev->rx_pkt_burst;
1713                                 rest_eth_dev->tx_pkt_burst =
1714                                         eth_dev->tx_pkt_burst;
1715                                 rte_eth_dev_probing_finish(rest_eth_dev);
1716                         }
1717                 }
1718                 return 0;
1719         }
1720
1721         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1722         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1723         if (!adapter)
1724                 return -1;
1725
1726         adapter->use_unpacked_mode = 1;
1727         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1728         if (!adapter->regs) {
1729                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1730                 err = -ENOMEM;
1731                 goto out_free_adapter;
1732         }
1733         adapter->pdev = pci_dev;
1734         adapter->eth_dev = eth_dev;
1735         pi->adapter = adapter;
1736
1737         cxgbe_process_devargs(adapter);
1738
1739         err = cxgbe_probe(adapter);
1740         if (err) {
1741                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1742                         __func__, err);
1743                 goto out_free_adapter;
1744         }
1745
1746         return 0;
1747
1748 out_free_adapter:
1749         rte_free(adapter);
1750         return err;
1751 }
1752
1753 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1754 {
1755         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1756         uint16_t port_id;
1757         int err = 0;
1758
1759         /* Free up other ports and all resources */
1760         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
1761                 err |= rte_eth_dev_close(port_id);
1762
1763         return err == 0 ? 0 : -EIO;
1764 }
1765
1766 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1767         struct rte_pci_device *pci_dev)
1768 {
1769         return rte_eth_dev_pci_generic_probe(pci_dev,
1770                 sizeof(struct port_info), eth_cxgbe_dev_init);
1771 }
1772
1773 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1774 {
1775         return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1776 }
1777
1778 static struct rte_pci_driver rte_cxgbe_pmd = {
1779         .id_table = cxgb4_pci_tbl,
1780         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1781         .probe = eth_cxgbe_pci_probe,
1782         .remove = eth_cxgbe_pci_remove,
1783 };
1784
1785 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1786 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1787 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1788 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1789                               CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "
1790                               CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> "
1791                               CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> "
1792                               CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> ");
1793 RTE_LOG_REGISTER_DEFAULT(cxgbe_logtype, NOTICE);
1794 RTE_LOG_REGISTER_SUFFIX(cxgbe_mbox_logtype, mbox, NOTICE);