drivers/net/cxgbe/cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_ethdev_pci.h>
  33 #include <rte_malloc.h>
  34 #include <rte_random.h>
  35 #include <rte_dev.h>
  36
  37 #include "cxgbe.h"
  38 #include "cxgbe_pfvf.h"
  39 #include "cxgbe_flow.h"
  40
  41 /*
  42  * Macros needed to support the PCI Device ID Table ...
  43  */
  44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  45         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  47
  48 #define PCI_VENDOR_ID_CHELSIO 0x1425
  49
  50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  51                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  52
  53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  54                 { .vendor_id = 0, } \
  55         }
  56
  57 /*
  58  *... and the PCI ID Table itself ...
  59  */
  60 #include "base/t4_pci_id_tbl.h"
  61
  62 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  63                          uint16_t nb_pkts)
  64 {
  65         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  66         uint16_t pkts_sent, pkts_remain;
  67         uint16_t total_sent = 0;
  68         uint16_t idx = 0;
  69         int ret = 0;
  70
  71         t4_os_lock(&txq->txq_lock);
  72         /* free up desc from already completed tx */
  73         reclaim_completed_tx(&txq->q);
  74         if (unlikely(!nb_pkts))
  75                 goto out_unlock;
  76
  77         rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
  78         while (total_sent < nb_pkts) {
  79                 pkts_remain = nb_pkts - total_sent;
  80
  81                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  82                         idx = total_sent + pkts_sent;
  83                         if ((idx + 1) < nb_pkts)
  84                                 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
  85                                                         volatile void *));
  86                         ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
  87                         if (ret < 0)
  88                                 break;
  89                 }
  90                 if (!pkts_sent)
  91                         break;
  92                 total_sent += pkts_sent;
  93                 /* reclaim as much as possible */
  94                 reclaim_completed_tx(&txq->q);
  95         }
  96
  97 out_unlock:
  98         t4_os_unlock(&txq->txq_lock);
  99         return total_sent;
 100 }
 101
 102 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 103                          uint16_t nb_pkts)
 104 {
 105         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 106         unsigned int work_done;
 107
 108         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 109                 dev_err(adapter, "error in cxgbe poll\n");
 110
 111         return work_done;
 112 }
 113
 114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 115                         struct rte_eth_dev_info *device_info)
 116 {
 117         struct port_info *pi = eth_dev->data->dev_private;
 118         struct adapter *adapter = pi->adapter;
 119         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
 120
 121         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 122                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 123                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 124                 .nb_align = 1,
 125         };
 126
 127         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 128         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 129         device_info->max_rx_queues = max_queues;
 130         device_info->max_tx_queues = max_queues;
 131         device_info->max_mac_addrs = 1;
 132         /* XXX: For now we support one MAC/port */
 133         device_info->max_vfs = adapter->params.arch.vfcount;
 134         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 135
 136         device_info->rx_queue_offload_capa = 0UL;
 137         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 138
 139         device_info->tx_queue_offload_capa = 0UL;
 140         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 141
 142         device_info->reta_size = pi->rss_size;
 143         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 144         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 145
 146         device_info->rx_desc_lim = cxgbe_desc_lim;
 147         device_info->tx_desc_lim = cxgbe_desc_lim;
 148         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 149
 150         return 0;
 151 }
 152
 153 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 154 {
 155         struct port_info *pi = eth_dev->data->dev_private;
 156         struct adapter *adapter = pi->adapter;
 157
 158         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 159                              1, -1, 1, -1, false);
 160 }
 161
 162 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 163 {
 164         struct port_info *pi = eth_dev->data->dev_private;
 165         struct adapter *adapter = pi->adapter;
 166
 167         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 168                              0, -1, 1, -1, false);
 169 }
 170
 171 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 172 {
 173         struct port_info *pi = eth_dev->data->dev_private;
 174         struct adapter *adapter = pi->adapter;
 175
 176         /* TODO: address filters ?? */
 177
 178         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 179                              -1, 1, 1, -1, false);
 180 }
 181
 182 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 183 {
 184         struct port_info *pi = eth_dev->data->dev_private;
 185         struct adapter *adapter = pi->adapter;
 186
 187         /* TODO: address filters ?? */
 188
 189         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 190                              -1, 0, 1, -1, false);
 191 }
 192
 193 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 194                           int wait_to_complete)
 195 {
 196         struct port_info *pi = eth_dev->data->dev_private;
 197         struct adapter *adapter = pi->adapter;
 198         struct sge *s = &adapter->sge;
 199         struct rte_eth_link new_link = { 0 };
 200         unsigned int i, work_done, budget = 32;
 201         u8 old_link = pi->link_cfg.link_ok;
 202
 203         for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
 204                 if (!s->fw_evtq.desc)
 205                         break;
 206
 207                 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 208
 209                 /* Exit if link status changed or always forced up */
 210                 if (pi->link_cfg.link_ok != old_link ||
 211                     cxgbe_force_linkup(adapter))
 212                         break;
 213
 214                 if (!wait_to_complete)
 215                         break;
 216
 217                 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
 218         }
 219
 220         new_link.link_status = cxgbe_force_linkup(adapter) ?
 221                                ETH_LINK_UP : pi->link_cfg.link_ok;
 222         new_link.link_autoneg = pi->link_cfg.autoneg;
 223         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 224         new_link.link_speed = pi->link_cfg.speed;
 225
 226         return rte_eth_linkstatus_set(eth_dev, &new_link);
 227 }
 228
 229 /**
 230  * Set device link up.
 231  */
 232 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
 233 {
 234         struct port_info *pi = dev->data->dev_private;
 235         struct adapter *adapter = pi->adapter;
 236         unsigned int work_done, budget = 32;
 237         struct sge *s = &adapter->sge;
 238         int ret;
 239
 240         if (!s->fw_evtq.desc)
 241                 return -ENOMEM;
 242
 243         /* Flush all link events */
 244         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 245
 246         /* If link already up, nothing to do */
 247         if (pi->link_cfg.link_ok)
 248                 return 0;
 249
 250         ret = cxgbe_set_link_status(pi, true);
 251         if (ret)
 252                 return ret;
 253
 254         cxgbe_dev_link_update(dev, 1);
 255         return 0;
 256 }
 257
 258 /**
 259  * Set device link down.
 260  */
 261 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
 262 {
 263         struct port_info *pi = dev->data->dev_private;
 264         struct adapter *adapter = pi->adapter;
 265         unsigned int work_done, budget = 32;
 266         struct sge *s = &adapter->sge;
 267         int ret;
 268
 269         if (!s->fw_evtq.desc)
 270                 return -ENOMEM;
 271
 272         /* Flush all link events */
 273         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 274
 275         /* If link already down, nothing to do */
 276         if (!pi->link_cfg.link_ok)
 277                 return 0;
 278
 279         ret = cxgbe_set_link_status(pi, false);
 280         if (ret)
 281                 return ret;
 282
 283         cxgbe_dev_link_update(dev, 0);
 284         return 0;
 285 }
 286
 287 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 288 {
 289         struct port_info *pi = eth_dev->data->dev_private;
 290         struct adapter *adapter = pi->adapter;
 291         struct rte_eth_dev_info dev_info;
 292         int err;
 293         uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
 294
 295         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 296         if (err != 0)
 297                 return err;
 298
 299         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 300         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen)
 301                 return -EINVAL;
 302
 303         /* set to jumbo mode if needed */
 304         if (new_mtu > RTE_ETHER_MAX_LEN)
 305                 eth_dev->data->dev_conf.rxmode.offloads |=
 306                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 307         else
 308                 eth_dev->data->dev_conf.rxmode.offloads &=
 309                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 310
 311         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 312                             -1, -1, true);
 313         if (!err)
 314                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 315
 316         return err;
 317 }
 318
 319 /*
 320  * Stop device.
 321  */
 322 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 323 {
 324         struct port_info *temp_pi, *pi = eth_dev->data->dev_private;
 325         struct adapter *adapter = pi->adapter;
 326         u8 i;
 327
 328         CXGBE_FUNC_TRACE();
 329
 330         if (!(adapter->flags & FULL_INIT_DONE))
 331                 return;
 332
 333         if (!pi->viid)
 334                 return;
 335
 336         cxgbe_down(pi);
 337         t4_sge_eth_release_queues(pi);
 338         t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid);
 339         pi->viid = 0;
 340
 341         /* Free up the adapter-wide resources only after all the ports
 342          * under this PF have been closed.
 343          */
 344         for_each_port(adapter, i) {
 345                 temp_pi = adap2pinfo(adapter, i);
 346                 if (temp_pi->viid)
 347                         return;
 348         }
 349
 350         cxgbe_close(adapter);
 351         rte_free(adapter);
 352 }
 353
 354 /* Start the device.
 355  * It returns 0 on success.
 356  */
 357 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 358 {
 359         struct port_info *pi = eth_dev->data->dev_private;
 360         struct rte_eth_rxmode *rx_conf = &eth_dev->data->dev_conf.rxmode;
 361         struct adapter *adapter = pi->adapter;
 362         int err = 0, i;
 363
 364         CXGBE_FUNC_TRACE();
 365
 366         /*
 367          * If we don't have a connection to the firmware there's nothing we
 368          * can do.
 369          */
 370         if (!(adapter->flags & FW_OK)) {
 371                 err = -ENXIO;
 372                 goto out;
 373         }
 374
 375         if (!(adapter->flags & FULL_INIT_DONE)) {
 376                 err = cxgbe_up(adapter);
 377                 if (err < 0)
 378                         goto out;
 379         }
 380
 381         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
 382                 eth_dev->data->scattered_rx = 1;
 383         else
 384                 eth_dev->data->scattered_rx = 0;
 385
 386         cxgbe_enable_rx_queues(pi);
 387
 388         err = cxgbe_setup_rss(pi);
 389         if (err)
 390                 goto out;
 391
 392         for (i = 0; i < pi->n_tx_qsets; i++) {
 393                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 394                 if (err)
 395                         goto out;
 396         }
 397
 398         for (i = 0; i < pi->n_rx_qsets; i++) {
 399                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 400                 if (err)
 401                         goto out;
 402         }
 403
 404         err = cxgbe_link_start(pi);
 405         if (err)
 406                 goto out;
 407
 408 out:
 409         return err;
 410 }
 411
 412 /*
 413  * Stop device: disable rx and tx functions to allow for reconfiguring.
 414  */
 415 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 416 {
 417         struct port_info *pi = eth_dev->data->dev_private;
 418         struct adapter *adapter = pi->adapter;
 419
 420         CXGBE_FUNC_TRACE();
 421
 422         if (!(adapter->flags & FULL_INIT_DONE))
 423                 return;
 424
 425         cxgbe_down(pi);
 426
 427         /*
 428          *  We clear queues only if both tx and rx path of the port
 429          *  have been disabled
 430          */
 431         t4_sge_eth_clear_queues(pi);
 432         eth_dev->data->scattered_rx = 0;
 433 }
 434
 435 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 436 {
 437         struct port_info *pi = eth_dev->data->dev_private;
 438         struct adapter *adapter = pi->adapter;
 439         int err;
 440
 441         CXGBE_FUNC_TRACE();
 442
 443         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 444                 eth_dev->data->dev_conf.rxmode.offloads |=
 445                         DEV_RX_OFFLOAD_RSS_HASH;
 446
 447         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 448                 err = cxgbe_setup_sge_fwevtq(adapter);
 449                 if (err)
 450                         return err;
 451                 adapter->flags |= FW_QUEUE_BOUND;
 452                 if (is_pf4(adapter)) {
 453                         err = cxgbe_setup_sge_ctrl_txq(adapter);
 454                         if (err)
 455                                 return err;
 456                 }
 457         }
 458
 459         err = cxgbe_cfg_queue_count(eth_dev);
 460         if (err)
 461                 return err;
 462
 463         return 0;
 464 }
 465
 466 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 467 {
 468         int ret;
 469         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 470                                   (eth_dev->data->tx_queues[tx_queue_id]);
 471
 472         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 473
 474         ret = t4_sge_eth_txq_start(txq);
 475         if (ret == 0)
 476                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 477
 478         return ret;
 479 }
 480
 481 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 482 {
 483         int ret;
 484         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 485                                   (eth_dev->data->tx_queues[tx_queue_id]);
 486
 487         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 488
 489         ret = t4_sge_eth_txq_stop(txq);
 490         if (ret == 0)
 491                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 492
 493         return ret;
 494 }
 495
 496 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 497                              uint16_t queue_idx, uint16_t nb_desc,
 498                              unsigned int socket_id,
 499                              const struct rte_eth_txconf *tx_conf __rte_unused)
 500 {
 501         struct port_info *pi = eth_dev->data->dev_private;
 502         struct adapter *adapter = pi->adapter;
 503         struct sge *s = &adapter->sge;
 504         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
 505         int err = 0;
 506         unsigned int temp_nb_desc;
 507
 508         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 509                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 510                   socket_id, pi->first_qset);
 511
 512         /*  Free up the existing queue  */
 513         if (eth_dev->data->tx_queues[queue_idx]) {
 514                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 515                 eth_dev->data->tx_queues[queue_idx] = NULL;
 516         }
 517
 518         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 519
 520         /* Sanity Checking
 521          *
 522          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 523          */
 524         temp_nb_desc = nb_desc;
 525         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 526                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 527                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 528                          CXGBE_DEFAULT_TX_DESC_SIZE);
 529                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 530         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 531                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 532                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 533                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 534                 return -(EINVAL);
 535         }
 536
 537         txq->q.size = temp_nb_desc;
 538
 539         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 540                                    s->fw_evtq.cntxt_id, socket_id);
 541
 542         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 543                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 544         return err;
 545 }
 546
 547 void cxgbe_dev_tx_queue_release(void *q)
 548 {
 549         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 550
 551         if (txq) {
 552                 struct port_info *pi = (struct port_info *)
 553                                        (txq->eth_dev->data->dev_private);
 554                 struct adapter *adap = pi->adapter;
 555
 556                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 557                           __func__, pi->port_id, txq->q.cntxt_id);
 558
 559                 t4_sge_eth_txq_release(adap, txq);
 560         }
 561 }
 562
 563 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 564 {
 565         int ret;
 566         struct port_info *pi = eth_dev->data->dev_private;
 567         struct adapter *adap = pi->adapter;
 568         struct sge_rspq *q;
 569
 570         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 571                   __func__, pi->port_id, rx_queue_id);
 572
 573         q = eth_dev->data->rx_queues[rx_queue_id];
 574
 575         ret = t4_sge_eth_rxq_start(adap, q);
 576         if (ret == 0)
 577                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 578
 579         return ret;
 580 }
 581
 582 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 583 {
 584         int ret;
 585         struct port_info *pi = eth_dev->data->dev_private;
 586         struct adapter *adap = pi->adapter;
 587         struct sge_rspq *q;
 588
 589         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 590                   __func__, pi->port_id, rx_queue_id);
 591
 592         q = eth_dev->data->rx_queues[rx_queue_id];
 593         ret = t4_sge_eth_rxq_stop(adap, q);
 594         if (ret == 0)
 595                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 596
 597         return ret;
 598 }
 599
 600 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 601                              uint16_t queue_idx, uint16_t nb_desc,
 602                              unsigned int socket_id,
 603                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 604                              struct rte_mempool *mp)
 605 {
 606         struct port_info *pi = eth_dev->data->dev_private;
 607         struct adapter *adapter = pi->adapter;
 608         struct sge *s = &adapter->sge;
 609         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
 610         int err = 0;
 611         int msi_idx = 0;
 612         unsigned int temp_nb_desc;
 613         struct rte_eth_dev_info dev_info;
 614         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 615
 616         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 617                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 618                   socket_id, mp);
 619
 620         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 621         if (err != 0) {
 622                 dev_err(adap, "%s: error during getting ethernet device info",
 623                         __func__);
 624                 return err;
 625         }
 626
 627         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 628         if ((pkt_len < dev_info.min_rx_bufsize) ||
 629             (pkt_len > dev_info.max_rx_pktlen)) {
 630                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 631                         __func__, dev_info.min_rx_bufsize,
 632                         dev_info.max_rx_pktlen);
 633                 return -EINVAL;
 634         }
 635
 636         /*  Free up the existing queue  */
 637         if (eth_dev->data->rx_queues[queue_idx]) {
 638                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 639                 eth_dev->data->rx_queues[queue_idx] = NULL;
 640         }
 641
 642         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 643
 644         /* Sanity Checking
 645          *
 646          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 647          */
 648         temp_nb_desc = nb_desc;
 649         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 650                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 651                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 652                          CXGBE_DEFAULT_RX_DESC_SIZE);
 653                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 654         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 655                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 656                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 657                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 658                 return -(EINVAL);
 659         }
 660
 661         rxq->rspq.size = temp_nb_desc;
 662         if ((&rxq->fl) != NULL)
 663                 rxq->fl.size = temp_nb_desc;
 664
 665         /* Set to jumbo mode if necessary */
 666         if (pkt_len > RTE_ETHER_MAX_LEN)
 667                 eth_dev->data->dev_conf.rxmode.offloads |=
 668                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 669         else
 670                 eth_dev->data->dev_conf.rxmode.offloads &=
 671                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 672
 673         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 674                                &rxq->fl, NULL,
 675                                is_pf4(adapter) ?
 676                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 677                                queue_idx, socket_id);
 678
 679         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 680                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 681                   rxq->rspq.abs_id);
 682         return err;
 683 }
 684
 685 void cxgbe_dev_rx_queue_release(void *q)
 686 {
 687         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 688         struct sge_rspq *rq = &rxq->rspq;
 689
 690         if (rq) {
 691                 struct port_info *pi = (struct port_info *)
 692                                        (rq->eth_dev->data->dev_private);
 693                 struct adapter *adap = pi->adapter;
 694
 695                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 696                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 697
 698                 t4_sge_eth_rxq_release(adap, rxq);
 699         }
 700 }
 701
 702 /*
 703  * Get port statistics.
 704  */
 705 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 706                                 struct rte_eth_stats *eth_stats)
 707 {
 708         struct port_info *pi = eth_dev->data->dev_private;
 709         struct adapter *adapter = pi->adapter;
 710         struct sge *s = &adapter->sge;
 711         struct port_stats ps;
 712         unsigned int i;
 713
 714         cxgbe_stats_get(pi, &ps);
 715
 716         /* RX Stats */
 717         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 718                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 719                               ps.rx_trunc0 + ps.rx_trunc1 +
 720                               ps.rx_trunc2 + ps.rx_trunc3;
 721         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 722                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 723                               ps.rx_len_err;
 724
 725         /* TX Stats */
 726         eth_stats->opackets = ps.tx_frames;
 727         eth_stats->obytes   = ps.tx_octets;
 728         eth_stats->oerrors  = ps.tx_error_frames;
 729
 730         for (i = 0; i < pi->n_rx_qsets; i++) {
 731                 struct sge_eth_rxq *rxq =
 732                         &s->ethrxq[pi->first_qset + i];
 733
 734                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 735                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 736                 eth_stats->ipackets += eth_stats->q_ipackets[i];
 737                 eth_stats->ibytes += eth_stats->q_ibytes[i];
 738         }
 739
 740         for (i = 0; i < pi->n_tx_qsets; i++) {
 741                 struct sge_eth_txq *txq =
 742                         &s->ethtxq[pi->first_qset + i];
 743
 744                 eth_stats->q_opackets[i] = txq->stats.pkts;
 745                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 746         }
 747         return 0;
 748 }
 749
 750 /*
 751  * Reset port statistics.
 752  */
 753 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 754 {
 755         struct port_info *pi = eth_dev->data->dev_private;
 756         struct adapter *adapter = pi->adapter;
 757         struct sge *s = &adapter->sge;
 758         unsigned int i;
 759
 760         cxgbe_stats_reset(pi);
 761         for (i = 0; i < pi->n_rx_qsets; i++) {
 762                 struct sge_eth_rxq *rxq =
 763                         &s->ethrxq[pi->first_qset + i];
 764
 765                 rxq->stats.pkts = 0;
 766                 rxq->stats.rx_bytes = 0;
 767         }
 768         for (i = 0; i < pi->n_tx_qsets; i++) {
 769                 struct sge_eth_txq *txq =
 770                         &s->ethtxq[pi->first_qset + i];
 771
 772                 txq->stats.pkts = 0;
 773                 txq->stats.tx_bytes = 0;
 774                 txq->stats.mapping_err = 0;
 775         }
 776
 777         return 0;
 778 }
 779
 780 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 781                                struct rte_eth_fc_conf *fc_conf)
 782 {
 783         struct port_info *pi = eth_dev->data->dev_private;
 784         struct link_config *lc = &pi->link_cfg;
 785         int rx_pause, tx_pause;
 786
 787         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 788         rx_pause = lc->fc & PAUSE_RX;
 789         tx_pause = lc->fc & PAUSE_TX;
 790
 791         if (rx_pause && tx_pause)
 792                 fc_conf->mode = RTE_FC_FULL;
 793         else if (rx_pause)
 794                 fc_conf->mode = RTE_FC_RX_PAUSE;
 795         else if (tx_pause)
 796                 fc_conf->mode = RTE_FC_TX_PAUSE;
 797         else
 798                 fc_conf->mode = RTE_FC_NONE;
 799         return 0;
 800 }
 801
 802 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 803                                struct rte_eth_fc_conf *fc_conf)
 804 {
 805         struct port_info *pi = eth_dev->data->dev_private;
 806         struct adapter *adapter = pi->adapter;
 807         struct link_config *lc = &pi->link_cfg;
 808
 809         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
 810                 if (fc_conf->autoneg)
 811                         lc->requested_fc |= PAUSE_AUTONEG;
 812                 else
 813                         lc->requested_fc &= ~PAUSE_AUTONEG;
 814         }
 815
 816         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 817             (fc_conf->mode & RTE_FC_RX_PAUSE))
 818                 lc->requested_fc |= PAUSE_RX;
 819         else
 820                 lc->requested_fc &= ~PAUSE_RX;
 821
 822         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 823             (fc_conf->mode & RTE_FC_TX_PAUSE))
 824                 lc->requested_fc |= PAUSE_TX;
 825         else
 826                 lc->requested_fc &= ~PAUSE_TX;
 827
 828         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 829                              &pi->link_cfg);
 830 }
 831
 832 const uint32_t *
 833 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 834 {
 835         static const uint32_t ptypes[] = {
 836                 RTE_PTYPE_L3_IPV4,
 837                 RTE_PTYPE_L3_IPV6,
 838                 RTE_PTYPE_UNKNOWN
 839         };
 840
 841         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 842                 return ptypes;
 843         return NULL;
 844 }
 845
 846 /* Update RSS hash configuration
 847  */
 848 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 849                                      struct rte_eth_rss_conf *rss_conf)
 850 {
 851         struct port_info *pi = dev->data->dev_private;
 852         struct adapter *adapter = pi->adapter;
 853         int err;
 854
 855         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
 856         if (err)
 857                 return err;
 858
 859         pi->rss_hf = rss_conf->rss_hf;
 860
 861         if (rss_conf->rss_key) {
 862                 u32 key[10], mod_key[10];
 863                 int i, j;
 864
 865                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 866
 867                 for (i = 9, j = 0; i >= 0; i--, j++)
 868                         mod_key[j] = cpu_to_be32(key[i]);
 869
 870                 t4_write_rss_key(adapter, mod_key, -1);
 871         }
 872
 873         return 0;
 874 }
 875
 876 /* Get RSS hash configuration
 877  */
 878 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 879                                        struct rte_eth_rss_conf *rss_conf)
 880 {
 881         struct port_info *pi = dev->data->dev_private;
 882         struct adapter *adapter = pi->adapter;
 883         u64 rss_hf = 0;
 884         u64 flags = 0;
 885         int err;
 886
 887         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
 888                                     &flags, NULL);
 889
 890         if (err)
 891                 return err;
 892
 893         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
 894                 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
 895                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 896                         rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
 897         }
 898
 899         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
 900                 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
 901
 902         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
 903                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 904                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 905                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 906         }
 907
 908         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
 909                 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
 910
 911         rss_conf->rss_hf = rss_hf;
 912
 913         if (rss_conf->rss_key) {
 914                 u32 key[10], mod_key[10];
 915                 int i, j;
 916
 917                 t4_read_rss_key(adapter, key);
 918
 919                 for (i = 9, j = 0; i >= 0; i--, j++)
 920                         mod_key[j] = be32_to_cpu(key[i]);
 921
 922                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 923         }
 924
 925         return 0;
 926 }
 927
 928 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 929 {
 930         RTE_SET_USED(dev);
 931         return EEPROMSIZE;
 932 }
 933
 934 /**
 935  * eeprom_ptov - translate a physical EEPROM address to virtual
 936  * @phys_addr: the physical EEPROM address
 937  * @fn: the PCI function number
 938  * @sz: size of function-specific area
 939  *
 940  * Translate a physical EEPROM address to virtual.  The first 1K is
 941  * accessed through virtual addresses starting at 31K, the rest is
 942  * accessed through virtual addresses starting at 0.
 943  *
 944  * The mapping is as follows:
 945  * [0..1K) -> [31K..32K)
 946  * [1K..1K+A) -> [31K-A..31K)
 947  * [1K+A..ES) -> [0..ES-A-1K)
 948  *
 949  * where A = @fn * @sz, and ES = EEPROM size.
 950  */
 951 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
 952 {
 953         fn *= sz;
 954         if (phys_addr < 1024)
 955                 return phys_addr + (31 << 10);
 956         if (phys_addr < 1024 + fn)
 957                 return fn + phys_addr - 1024;
 958         if (phys_addr < EEPROMSIZE)
 959                 return phys_addr - 1024 - fn;
 960         if (phys_addr < EEPROMVSIZE)
 961                 return phys_addr - 1024;
 962         return -EINVAL;
 963 }
 964
 965 /* The next two routines implement eeprom read/write from physical addresses.
 966  */
 967 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
 968 {
 969         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 970
 971         if (vaddr >= 0)
 972                 vaddr = t4_seeprom_read(adap, vaddr, v);
 973         return vaddr < 0 ? vaddr : 0;
 974 }
 975
 976 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
 977 {
 978         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 979
 980         if (vaddr >= 0)
 981                 vaddr = t4_seeprom_write(adap, vaddr, v);
 982         return vaddr < 0 ? vaddr : 0;
 983 }
 984
 985 #define EEPROM_MAGIC 0x38E2F10C
 986
 987 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
 988                             struct rte_dev_eeprom_info *e)
 989 {
 990         struct port_info *pi = dev->data->dev_private;
 991         struct adapter *adapter = pi->adapter;
 992         u32 i, err = 0;
 993         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
 994
 995         if (!buf)
 996                 return -ENOMEM;
 997
 998         e->magic = EEPROM_MAGIC;
 999         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
1000                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1001
1002         if (!err)
1003                 rte_memcpy(e->data, buf + e->offset, e->length);
1004         rte_free(buf);
1005         return err;
1006 }
1007
1008 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
1009                             struct rte_dev_eeprom_info *eeprom)
1010 {
1011         struct port_info *pi = dev->data->dev_private;
1012         struct adapter *adapter = pi->adapter;
1013         u8 *buf;
1014         int err = 0;
1015         u32 aligned_offset, aligned_len, *p;
1016
1017         if (eeprom->magic != EEPROM_MAGIC)
1018                 return -EINVAL;
1019
1020         aligned_offset = eeprom->offset & ~3;
1021         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1022
1023         if (adapter->pf > 0) {
1024                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1025
1026                 if (aligned_offset < start ||
1027                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
1028                         return -EPERM;
1029         }
1030
1031         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1032                 /* RMW possibly needed for first or last words.
1033                  */
1034                 buf = rte_zmalloc(NULL, aligned_len, 0);
1035                 if (!buf)
1036                         return -ENOMEM;
1037                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1038                 if (!err && aligned_len > 4)
1039                         err = eeprom_rd_phys(adapter,
1040                                              aligned_offset + aligned_len - 4,
1041                                              (u32 *)&buf[aligned_len - 4]);
1042                 if (err)
1043                         goto out;
1044                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1045                            eeprom->length);
1046         } else {
1047                 buf = eeprom->data;
1048         }
1049
1050         err = t4_seeprom_wp(adapter, false);
1051         if (err)
1052                 goto out;
1053
1054         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1055                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1056                 aligned_offset += 4;
1057         }
1058
1059         if (!err)
1060                 err = t4_seeprom_wp(adapter, true);
1061 out:
1062         if (buf != eeprom->data)
1063                 rte_free(buf);
1064         return err;
1065 }
1066
1067 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1068 {
1069         struct port_info *pi = eth_dev->data->dev_private;
1070         struct adapter *adapter = pi->adapter;
1071
1072         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1073 }
1074
1075 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1076                           struct rte_dev_reg_info *regs)
1077 {
1078         struct port_info *pi = eth_dev->data->dev_private;
1079         struct adapter *adapter = pi->adapter;
1080
1081         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1082                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1083                 (1 << 16);
1084
1085         if (regs->data == NULL) {
1086                 regs->length = cxgbe_get_regs_len(eth_dev);
1087                 regs->width = sizeof(uint32_t);
1088
1089                 return 0;
1090         }
1091
1092         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1093
1094         return 0;
1095 }
1096
1097 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1098 {
1099         struct port_info *pi = dev->data->dev_private;
1100         int ret;
1101
1102         ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1103         if (ret < 0) {
1104                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1105                         ret);
1106                 return ret;
1107         }
1108         pi->xact_addr_filt = ret;
1109         return 0;
1110 }
1111
1112 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1113         .dev_start              = cxgbe_dev_start,
1114         .dev_stop               = cxgbe_dev_stop,
1115         .dev_close              = cxgbe_dev_close,
1116         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1117         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1118         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1119         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1120         .dev_configure          = cxgbe_dev_configure,
1121         .dev_infos_get          = cxgbe_dev_info_get,
1122         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1123         .link_update            = cxgbe_dev_link_update,
1124         .dev_set_link_up        = cxgbe_dev_set_link_up,
1125         .dev_set_link_down      = cxgbe_dev_set_link_down,
1126         .mtu_set                = cxgbe_dev_mtu_set,
1127         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1128         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1129         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1130         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1131         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1132         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1133         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1134         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1135         .filter_ctrl            = cxgbe_dev_filter_ctrl,
1136         .stats_get              = cxgbe_dev_stats_get,
1137         .stats_reset            = cxgbe_dev_stats_reset,
1138         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1139         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1140         .get_eeprom_length      = cxgbe_get_eeprom_length,
1141         .get_eeprom             = cxgbe_get_eeprom,
1142         .set_eeprom             = cxgbe_set_eeprom,
1143         .get_reg                = cxgbe_get_regs,
1144         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1145         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1146         .mac_addr_set           = cxgbe_mac_addr_set,
1147 };
1148
1149 /*
1150  * Initialize driver
1151  * It returns 0 on success.
1152  */
1153 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1154 {
1155         struct rte_pci_device *pci_dev;
1156         struct port_info *pi = eth_dev->data->dev_private;
1157         struct adapter *adapter = NULL;
1158         char name[RTE_ETH_NAME_MAX_LEN];
1159         int err = 0;
1160
1161         CXGBE_FUNC_TRACE();
1162
1163         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1164         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1165         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1166         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1167
1168         /* for secondary processes, we attach to ethdevs allocated by primary
1169          * and do minimal initialization.
1170          */
1171         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1172                 int i;
1173
1174                 for (i = 1; i < MAX_NPORTS; i++) {
1175                         struct rte_eth_dev *rest_eth_dev;
1176                         char namei[RTE_ETH_NAME_MAX_LEN];
1177
1178                         snprintf(namei, sizeof(namei), "%s_%d",
1179                                  pci_dev->device.name, i);
1180                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1181                         if (rest_eth_dev) {
1182                                 rest_eth_dev->device = &pci_dev->device;
1183                                 rest_eth_dev->dev_ops =
1184                                         eth_dev->dev_ops;
1185                                 rest_eth_dev->rx_pkt_burst =
1186                                         eth_dev->rx_pkt_burst;
1187                                 rest_eth_dev->tx_pkt_burst =
1188                                         eth_dev->tx_pkt_burst;
1189                                 rte_eth_dev_probing_finish(rest_eth_dev);
1190                         }
1191                 }
1192                 return 0;
1193         }
1194
1195         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1196         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1197         if (!adapter)
1198                 return -1;
1199
1200         adapter->use_unpacked_mode = 1;
1201         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1202         if (!adapter->regs) {
1203                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1204                 err = -ENOMEM;
1205                 goto out_free_adapter;
1206         }
1207         adapter->pdev = pci_dev;
1208         adapter->eth_dev = eth_dev;
1209         pi->adapter = adapter;
1210
1211         cxgbe_process_devargs(adapter);
1212
1213         err = cxgbe_probe(adapter);
1214         if (err) {
1215                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1216                         __func__, err);
1217                 goto out_free_adapter;
1218         }
1219
1220         return 0;
1221
1222 out_free_adapter:
1223         rte_free(adapter);
1224         return err;
1225 }
1226
1227 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1228 {
1229         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1230         uint16_t port_id;
1231
1232         /* Free up other ports and all resources */
1233         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
1234                 rte_eth_dev_close(port_id);
1235
1236         return 0;
1237 }
1238
1239 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1240         struct rte_pci_device *pci_dev)
1241 {
1242         return rte_eth_dev_pci_generic_probe(pci_dev,
1243                 sizeof(struct port_info), eth_cxgbe_dev_init);
1244 }
1245
1246 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1247 {
1248         return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1249 }
1250
1251 static struct rte_pci_driver rte_cxgbe_pmd = {
1252         .id_table = cxgb4_pci_tbl,
1253         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1254         .probe = eth_cxgbe_pci_probe,
1255         .remove = eth_cxgbe_pci_remove,
1256 };
1257
1258 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1259 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1260 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1261 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1262                               CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "
1263                               CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> "
1264                               CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> "
1265                               CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> ");
1266 RTE_LOG_REGISTER(cxgbe_logtype, pmd.net.cxgbe, NOTICE);
1267 RTE_LOG_REGISTER(cxgbe_mbox_logtype, pmd.net.cxgbe.mbox, NOTICE);