drivers/net/cxgbe/cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_tailq.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <ethdev_driver.h>
  31 #include <ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35
  36 #include "cxgbe.h"
  37 #include "cxgbe_pfvf.h"
  38 #include "cxgbe_flow.h"
  39
  40 /*
  41  * Macros needed to support the PCI Device ID Table ...
  42  */
  43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  44         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  46
  47 #define PCI_VENDOR_ID_CHELSIO 0x1425
  48
  49 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  50                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  51
  52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  53                 { .vendor_id = 0, } \
  54         }
  55
  56 /*
  57  *... and the PCI ID Table itself ...
  58  */
  59 #include "base/t4_pci_id_tbl.h"
  60
  61 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  62                          uint16_t nb_pkts)
  63 {
  64         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  65         uint16_t pkts_sent, pkts_remain;
  66         uint16_t total_sent = 0;
  67         uint16_t idx = 0;
  68         int ret = 0;
  69
  70         t4_os_lock(&txq->txq_lock);
  71         /* free up desc from already completed tx */
  72         reclaim_completed_tx(&txq->q);
  73         if (unlikely(!nb_pkts))
  74                 goto out_unlock;
  75
  76         rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
  77         while (total_sent < nb_pkts) {
  78                 pkts_remain = nb_pkts - total_sent;
  79
  80                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  81                         idx = total_sent + pkts_sent;
  82                         if ((idx + 1) < nb_pkts)
  83                                 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
  84                                                         volatile void *));
  85                         ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
  86                         if (ret < 0)
  87                                 break;
  88                 }
  89                 if (!pkts_sent)
  90                         break;
  91                 total_sent += pkts_sent;
  92                 /* reclaim as much as possible */
  93                 reclaim_completed_tx(&txq->q);
  94         }
  95
  96 out_unlock:
  97         t4_os_unlock(&txq->txq_lock);
  98         return total_sent;
  99 }
 100
 101 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 102                          uint16_t nb_pkts)
 103 {
 104         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 105         unsigned int work_done;
 106
 107         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 108                 dev_err(adapter, "error in cxgbe poll\n");
 109
 110         return work_done;
 111 }
 112
 113 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 114                         struct rte_eth_dev_info *device_info)
 115 {
 116         struct port_info *pi = eth_dev->data->dev_private;
 117         struct adapter *adapter = pi->adapter;
 118
 119         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 120                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 121                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 122                 .nb_align = 1,
 123         };
 124
 125         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 126         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 127         device_info->max_rx_queues = adapter->sge.max_ethqsets;
 128         device_info->max_tx_queues = adapter->sge.max_ethqsets;
 129         device_info->max_mac_addrs = 1;
 130         /* XXX: For now we support one MAC/port */
 131         device_info->max_vfs = adapter->params.arch.vfcount;
 132         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 133
 134         device_info->rx_queue_offload_capa = 0UL;
 135         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 136
 137         device_info->tx_queue_offload_capa = 0UL;
 138         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 139
 140         device_info->reta_size = pi->rss_size;
 141         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 142         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 143
 144         device_info->rx_desc_lim = cxgbe_desc_lim;
 145         device_info->tx_desc_lim = cxgbe_desc_lim;
 146         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 147
 148         return 0;
 149 }
 150
 151 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 152 {
 153         struct port_info *pi = eth_dev->data->dev_private;
 154         struct adapter *adapter = pi->adapter;
 155         int ret;
 156
 157         if (adapter->params.rawf_size != 0) {
 158                 ret = cxgbe_mpstcam_rawf_enable(pi);
 159                 if (ret < 0)
 160                         return ret;
 161         }
 162
 163         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 164                              1, -1, 1, -1, false);
 165 }
 166
 167 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 168 {
 169         struct port_info *pi = eth_dev->data->dev_private;
 170         struct adapter *adapter = pi->adapter;
 171         int ret;
 172
 173         if (adapter->params.rawf_size != 0) {
 174                 ret = cxgbe_mpstcam_rawf_disable(pi);
 175                 if (ret < 0)
 176                         return ret;
 177         }
 178
 179         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 180                              0, -1, 1, -1, false);
 181 }
 182
 183 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 184 {
 185         struct port_info *pi = eth_dev->data->dev_private;
 186         struct adapter *adapter = pi->adapter;
 187
 188         /* TODO: address filters ?? */
 189
 190         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 191                              -1, 1, 1, -1, false);
 192 }
 193
 194 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 195 {
 196         struct port_info *pi = eth_dev->data->dev_private;
 197         struct adapter *adapter = pi->adapter;
 198
 199         /* TODO: address filters ?? */
 200
 201         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 202                              -1, 0, 1, -1, false);
 203 }
 204
 205 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 206                           int wait_to_complete)
 207 {
 208         struct port_info *pi = eth_dev->data->dev_private;
 209         unsigned int i, work_done, budget = 32;
 210         struct link_config *lc = &pi->link_cfg;
 211         struct adapter *adapter = pi->adapter;
 212         struct rte_eth_link new_link = { 0 };
 213         u8 old_link = pi->link_cfg.link_ok;
 214         struct sge *s = &adapter->sge;
 215
 216         for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
 217                 if (!s->fw_evtq.desc)
 218                         break;
 219
 220                 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 221
 222                 /* Exit if link status changed or always forced up */
 223                 if (pi->link_cfg.link_ok != old_link ||
 224                     cxgbe_force_linkup(adapter))
 225                         break;
 226
 227                 if (!wait_to_complete)
 228                         break;
 229
 230                 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
 231         }
 232
 233         new_link.link_status = cxgbe_force_linkup(adapter) ?
 234                                ETH_LINK_UP : pi->link_cfg.link_ok;
 235         new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0;
 236         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 237         new_link.link_speed = t4_fwcap_to_speed(lc->link_caps);
 238
 239         return rte_eth_linkstatus_set(eth_dev, &new_link);
 240 }
 241
 242 /**
 243  * Set device link up.
 244  */
 245 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
 246 {
 247         struct port_info *pi = dev->data->dev_private;
 248         struct adapter *adapter = pi->adapter;
 249         unsigned int work_done, budget = 32;
 250         struct sge *s = &adapter->sge;
 251         int ret;
 252
 253         if (!s->fw_evtq.desc)
 254                 return -ENOMEM;
 255
 256         /* Flush all link events */
 257         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 258
 259         /* If link already up, nothing to do */
 260         if (pi->link_cfg.link_ok)
 261                 return 0;
 262
 263         ret = cxgbe_set_link_status(pi, true);
 264         if (ret)
 265                 return ret;
 266
 267         cxgbe_dev_link_update(dev, 1);
 268         return 0;
 269 }
 270
 271 /**
 272  * Set device link down.
 273  */
 274 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
 275 {
 276         struct port_info *pi = dev->data->dev_private;
 277         struct adapter *adapter = pi->adapter;
 278         unsigned int work_done, budget = 32;
 279         struct sge *s = &adapter->sge;
 280         int ret;
 281
 282         if (!s->fw_evtq.desc)
 283                 return -ENOMEM;
 284
 285         /* Flush all link events */
 286         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 287
 288         /* If link already down, nothing to do */
 289         if (!pi->link_cfg.link_ok)
 290                 return 0;
 291
 292         ret = cxgbe_set_link_status(pi, false);
 293         if (ret)
 294                 return ret;
 295
 296         cxgbe_dev_link_update(dev, 0);
 297         return 0;
 298 }
 299
 300 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 301 {
 302         struct port_info *pi = eth_dev->data->dev_private;
 303         struct adapter *adapter = pi->adapter;
 304         struct rte_eth_dev_info dev_info;
 305         int err;
 306         uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
 307
 308         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 309         if (err != 0)
 310                 return err;
 311
 312         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 313         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen)
 314                 return -EINVAL;
 315
 316         /* set to jumbo mode if needed */
 317         if (new_mtu > CXGBE_ETH_MAX_LEN)
 318                 eth_dev->data->dev_conf.rxmode.offloads |=
 319                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 320         else
 321                 eth_dev->data->dev_conf.rxmode.offloads &=
 322                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 323
 324         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 325                             -1, -1, true);
 326         if (!err)
 327                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 328
 329         return err;
 330 }
 331
 332 /*
 333  * Stop device.
 334  */
 335 int cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 336 {
 337         struct port_info *temp_pi, *pi = eth_dev->data->dev_private;
 338         struct adapter *adapter = pi->adapter;
 339         u8 i;
 340
 341         CXGBE_FUNC_TRACE();
 342
 343         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 344                 return 0;
 345
 346         if (!(adapter->flags & FULL_INIT_DONE))
 347                 return 0;
 348
 349         if (!pi->viid)
 350                 return 0;
 351
 352         cxgbe_down(pi);
 353         t4_sge_eth_release_queues(pi);
 354         t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid);
 355         pi->viid = 0;
 356
 357         /* Free up the adapter-wide resources only after all the ports
 358          * under this PF have been closed.
 359          */
 360         for_each_port(adapter, i) {
 361                 temp_pi = adap2pinfo(adapter, i);
 362                 if (temp_pi->viid)
 363                         return 0;
 364         }
 365
 366         cxgbe_close(adapter);
 367         rte_free(adapter);
 368
 369         return 0;
 370 }
 371
 372 /* Start the device.
 373  * It returns 0 on success.
 374  */
 375 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 376 {
 377         struct port_info *pi = eth_dev->data->dev_private;
 378         struct rte_eth_rxmode *rx_conf = &eth_dev->data->dev_conf.rxmode;
 379         struct adapter *adapter = pi->adapter;
 380         int err = 0, i;
 381
 382         CXGBE_FUNC_TRACE();
 383
 384         /*
 385          * If we don't have a connection to the firmware there's nothing we
 386          * can do.
 387          */
 388         if (!(adapter->flags & FW_OK)) {
 389                 err = -ENXIO;
 390                 goto out;
 391         }
 392
 393         if (!(adapter->flags & FULL_INIT_DONE)) {
 394                 err = cxgbe_up(adapter);
 395                 if (err < 0)
 396                         goto out;
 397         }
 398
 399         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
 400                 eth_dev->data->scattered_rx = 1;
 401         else
 402                 eth_dev->data->scattered_rx = 0;
 403
 404         cxgbe_enable_rx_queues(pi);
 405
 406         err = cxgbe_setup_rss(pi);
 407         if (err)
 408                 goto out;
 409
 410         for (i = 0; i < pi->n_tx_qsets; i++) {
 411                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 412                 if (err)
 413                         goto out;
 414         }
 415
 416         for (i = 0; i < pi->n_rx_qsets; i++) {
 417                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 418                 if (err)
 419                         goto out;
 420         }
 421
 422         err = cxgbe_link_start(pi);
 423         if (err)
 424                 goto out;
 425
 426 out:
 427         return err;
 428 }
 429
 430 /*
 431  * Stop device: disable rx and tx functions to allow for reconfiguring.
 432  */
 433 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 434 {
 435         struct port_info *pi = eth_dev->data->dev_private;
 436         struct adapter *adapter = pi->adapter;
 437
 438         CXGBE_FUNC_TRACE();
 439
 440         if (!(adapter->flags & FULL_INIT_DONE))
 441                 return 0;
 442
 443         cxgbe_down(pi);
 444
 445         /*
 446          *  We clear queues only if both tx and rx path of the port
 447          *  have been disabled
 448          */
 449         t4_sge_eth_clear_queues(pi);
 450         eth_dev->data->scattered_rx = 0;
 451
 452         return 0;
 453 }
 454
 455 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 456 {
 457         struct port_info *pi = eth_dev->data->dev_private;
 458         struct adapter *adapter = pi->adapter;
 459         int err;
 460
 461         CXGBE_FUNC_TRACE();
 462
 463         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 464                 eth_dev->data->dev_conf.rxmode.offloads |=
 465                         DEV_RX_OFFLOAD_RSS_HASH;
 466
 467         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 468                 err = cxgbe_setup_sge_fwevtq(adapter);
 469                 if (err)
 470                         return err;
 471                 adapter->flags |= FW_QUEUE_BOUND;
 472                 if (is_pf4(adapter)) {
 473                         err = cxgbe_setup_sge_ctrl_txq(adapter);
 474                         if (err)
 475                                 return err;
 476                 }
 477         }
 478
 479         err = cxgbe_cfg_queue_count(eth_dev);
 480         if (err)
 481                 return err;
 482
 483         return 0;
 484 }
 485
 486 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 487 {
 488         int ret;
 489         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 490                                   (eth_dev->data->tx_queues[tx_queue_id]);
 491
 492         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 493
 494         ret = t4_sge_eth_txq_start(txq);
 495         if (ret == 0)
 496                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 497
 498         return ret;
 499 }
 500
 501 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 502 {
 503         int ret;
 504         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 505                                   (eth_dev->data->tx_queues[tx_queue_id]);
 506
 507         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 508
 509         ret = t4_sge_eth_txq_stop(txq);
 510         if (ret == 0)
 511                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 512
 513         return ret;
 514 }
 515
 516 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 517                              uint16_t queue_idx, uint16_t nb_desc,
 518                              unsigned int socket_id,
 519                              const struct rte_eth_txconf *tx_conf __rte_unused)
 520 {
 521         struct port_info *pi = eth_dev->data->dev_private;
 522         struct adapter *adapter = pi->adapter;
 523         struct sge *s = &adapter->sge;
 524         unsigned int temp_nb_desc;
 525         struct sge_eth_txq *txq;
 526         int err = 0;
 527
 528         txq = &s->ethtxq[pi->first_txqset + queue_idx];
 529         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 530                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 531                   socket_id, pi->first_txqset);
 532
 533         /*  Free up the existing queue  */
 534         if (eth_dev->data->tx_queues[queue_idx]) {
 535                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 536                 eth_dev->data->tx_queues[queue_idx] = NULL;
 537         }
 538
 539         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 540
 541         /* Sanity Checking
 542          *
 543          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 544          */
 545         temp_nb_desc = nb_desc;
 546         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 547                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 548                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 549                          CXGBE_DEFAULT_TX_DESC_SIZE);
 550                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 551         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 552                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 553                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 554                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 555                 return -(EINVAL);
 556         }
 557
 558         txq->q.size = temp_nb_desc;
 559
 560         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 561                                    s->fw_evtq.cntxt_id, socket_id);
 562
 563         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 564                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 565         return err;
 566 }
 567
 568 void cxgbe_dev_tx_queue_release(void *q)
 569 {
 570         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 571
 572         if (txq) {
 573                 struct port_info *pi = (struct port_info *)
 574                                        (txq->eth_dev->data->dev_private);
 575                 struct adapter *adap = pi->adapter;
 576
 577                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 578                           __func__, pi->port_id, txq->q.cntxt_id);
 579
 580                 t4_sge_eth_txq_release(adap, txq);
 581         }
 582 }
 583
 584 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 585 {
 586         struct port_info *pi = eth_dev->data->dev_private;
 587         struct adapter *adap = pi->adapter;
 588         struct sge_eth_rxq *rxq;
 589         int ret;
 590
 591         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 592                   __func__, pi->port_id, rx_queue_id);
 593
 594         rxq = eth_dev->data->rx_queues[rx_queue_id];
 595         ret = t4_sge_eth_rxq_start(adap, rxq);
 596         if (ret == 0)
 597                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 598
 599         return ret;
 600 }
 601
 602 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 603 {
 604         struct port_info *pi = eth_dev->data->dev_private;
 605         struct adapter *adap = pi->adapter;
 606         struct sge_eth_rxq *rxq;
 607         int ret;
 608
 609         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 610                   __func__, pi->port_id, rx_queue_id);
 611
 612         rxq = eth_dev->data->rx_queues[rx_queue_id];
 613         ret = t4_sge_eth_rxq_stop(adap, rxq);
 614         if (ret == 0)
 615                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 616
 617         return ret;
 618 }
 619
 620 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 621                              uint16_t queue_idx, uint16_t nb_desc,
 622                              unsigned int socket_id,
 623                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 624                              struct rte_mempool *mp)
 625 {
 626         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 627         struct port_info *pi = eth_dev->data->dev_private;
 628         struct adapter *adapter = pi->adapter;
 629         struct rte_eth_dev_info dev_info;
 630         struct sge *s = &adapter->sge;
 631         unsigned int temp_nb_desc;
 632         int err = 0, msi_idx = 0;
 633         struct sge_eth_rxq *rxq;
 634
 635         rxq = &s->ethrxq[pi->first_rxqset + queue_idx];
 636         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 637                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 638                   socket_id, mp);
 639
 640         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 641         if (err != 0) {
 642                 dev_err(adap, "%s: error during getting ethernet device info",
 643                         __func__);
 644                 return err;
 645         }
 646
 647         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 648         if ((pkt_len < dev_info.min_rx_bufsize) ||
 649             (pkt_len > dev_info.max_rx_pktlen)) {
 650                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 651                         __func__, dev_info.min_rx_bufsize,
 652                         dev_info.max_rx_pktlen);
 653                 return -EINVAL;
 654         }
 655
 656         /*  Free up the existing queue  */
 657         if (eth_dev->data->rx_queues[queue_idx]) {
 658                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 659                 eth_dev->data->rx_queues[queue_idx] = NULL;
 660         }
 661
 662         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 663
 664         /* Sanity Checking
 665          *
 666          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 667          */
 668         temp_nb_desc = nb_desc;
 669         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 670                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 671                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 672                          CXGBE_DEFAULT_RX_DESC_SIZE);
 673                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 674         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 675                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 676                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 677                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 678                 return -(EINVAL);
 679         }
 680
 681         rxq->rspq.size = temp_nb_desc;
 682         if ((&rxq->fl) != NULL)
 683                 rxq->fl.size = temp_nb_desc;
 684
 685         /* Set to jumbo mode if necessary */
 686         if (pkt_len > CXGBE_ETH_MAX_LEN)
 687                 eth_dev->data->dev_conf.rxmode.offloads |=
 688                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 689         else
 690                 eth_dev->data->dev_conf.rxmode.offloads &=
 691                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 692
 693         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 694                                &rxq->fl, NULL,
 695                                is_pf4(adapter) ?
 696                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 697                                queue_idx, socket_id);
 698
 699         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 700                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 701                   rxq->rspq.abs_id);
 702         return err;
 703 }
 704
 705 void cxgbe_dev_rx_queue_release(void *q)
 706 {
 707         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 708
 709         if (rxq) {
 710                 struct port_info *pi = (struct port_info *)
 711                                        (rxq->rspq.eth_dev->data->dev_private);
 712                 struct adapter *adap = pi->adapter;
 713
 714                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 715                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 716
 717                 t4_sge_eth_rxq_release(adap, rxq);
 718         }
 719 }
 720
 721 /*
 722  * Get port statistics.
 723  */
 724 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 725                                 struct rte_eth_stats *eth_stats)
 726 {
 727         struct port_info *pi = eth_dev->data->dev_private;
 728         struct adapter *adapter = pi->adapter;
 729         struct sge *s = &adapter->sge;
 730         struct port_stats ps;
 731         unsigned int i;
 732
 733         cxgbe_stats_get(pi, &ps);
 734
 735         /* RX Stats */
 736         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 737                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 738                               ps.rx_trunc0 + ps.rx_trunc1 +
 739                               ps.rx_trunc2 + ps.rx_trunc3;
 740         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 741                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 742                               ps.rx_len_err;
 743
 744         /* TX Stats */
 745         eth_stats->opackets = ps.tx_frames;
 746         eth_stats->obytes   = ps.tx_octets;
 747         eth_stats->oerrors  = ps.tx_error_frames;
 748
 749         for (i = 0; i < pi->n_rx_qsets; i++) {
 750                 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i];
 751
 752                 eth_stats->ipackets += rxq->stats.pkts;
 753                 eth_stats->ibytes += rxq->stats.rx_bytes;
 754         }
 755
 756         return 0;
 757 }
 758
 759 /*
 760  * Reset port statistics.
 761  */
 762 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 763 {
 764         struct port_info *pi = eth_dev->data->dev_private;
 765         struct adapter *adapter = pi->adapter;
 766         struct sge *s = &adapter->sge;
 767         unsigned int i;
 768
 769         cxgbe_stats_reset(pi);
 770         for (i = 0; i < pi->n_rx_qsets; i++) {
 771                 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i];
 772
 773                 memset(&rxq->stats, 0, sizeof(rxq->stats));
 774         }
 775         for (i = 0; i < pi->n_tx_qsets; i++) {
 776                 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + i];
 777
 778                 memset(&txq->stats, 0, sizeof(txq->stats));
 779         }
 780
 781         return 0;
 782 }
 783
 784 /* Store extended statistics names and its offset in stats structure  */
 785 struct cxgbe_dev_xstats_name_off {
 786         char name[RTE_ETH_XSTATS_NAME_SIZE];
 787         unsigned int offset;
 788 };
 789
 790 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_rxq_stats_strings[] = {
 791         {"packets", offsetof(struct sge_eth_rx_stats, pkts)},
 792         {"bytes", offsetof(struct sge_eth_rx_stats, rx_bytes)},
 793         {"checksum_offloads", offsetof(struct sge_eth_rx_stats, rx_cso)},
 794         {"vlan_extractions", offsetof(struct sge_eth_rx_stats, vlan_ex)},
 795         {"dropped_packets", offsetof(struct sge_eth_rx_stats, rx_drops)},
 796 };
 797
 798 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_txq_stats_strings[] = {
 799         {"packets", offsetof(struct sge_eth_tx_stats, pkts)},
 800         {"bytes", offsetof(struct sge_eth_tx_stats, tx_bytes)},
 801         {"tso_requests", offsetof(struct sge_eth_tx_stats, tso)},
 802         {"checksum_offloads", offsetof(struct sge_eth_tx_stats, tx_cso)},
 803         {"vlan_insertions", offsetof(struct sge_eth_tx_stats, vlan_ins)},
 804         {"packet_mapping_errors",
 805          offsetof(struct sge_eth_tx_stats, mapping_err)},
 806         {"coalesced_wrs", offsetof(struct sge_eth_tx_stats, coal_wr)},
 807         {"coalesced_packets", offsetof(struct sge_eth_tx_stats, coal_pkts)},
 808 };
 809
 810 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_port_stats_strings[] = {
 811         {"tx_bytes", offsetof(struct port_stats, tx_octets)},
 812         {"tx_packets", offsetof(struct port_stats, tx_frames)},
 813         {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)},
 814         {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)},
 815         {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)},
 816         {"tx_error_packets", offsetof(struct port_stats, tx_error_frames)},
 817         {"tx_size_64_packets", offsetof(struct port_stats, tx_frames_64)},
 818         {"tx_size_65_to_127_packets",
 819          offsetof(struct port_stats, tx_frames_65_127)},
 820         {"tx_size_128_to_255_packets",
 821          offsetof(struct port_stats, tx_frames_128_255)},
 822         {"tx_size_256_to_511_packets",
 823          offsetof(struct port_stats, tx_frames_256_511)},
 824         {"tx_size_512_to_1023_packets",
 825          offsetof(struct port_stats, tx_frames_512_1023)},
 826         {"tx_size_1024_to_1518_packets",
 827          offsetof(struct port_stats, tx_frames_1024_1518)},
 828         {"tx_size_1519_to_max_packets",
 829          offsetof(struct port_stats, tx_frames_1519_max)},
 830         {"tx_drop_packets", offsetof(struct port_stats, tx_drop)},
 831         {"tx_pause_frames", offsetof(struct port_stats, tx_pause)},
 832         {"tx_ppp_pri0_packets", offsetof(struct port_stats, tx_ppp0)},
 833         {"tx_ppp_pri1_packets", offsetof(struct port_stats, tx_ppp1)},
 834         {"tx_ppp_pri2_packets", offsetof(struct port_stats, tx_ppp2)},
 835         {"tx_ppp_pri3_packets", offsetof(struct port_stats, tx_ppp3)},
 836         {"tx_ppp_pri4_packets", offsetof(struct port_stats, tx_ppp4)},
 837         {"tx_ppp_pri5_packets", offsetof(struct port_stats, tx_ppp5)},
 838         {"tx_ppp_pri6_packets", offsetof(struct port_stats, tx_ppp6)},
 839         {"tx_ppp_pri7_packets", offsetof(struct port_stats, tx_ppp7)},
 840         {"rx_bytes", offsetof(struct port_stats, rx_octets)},
 841         {"rx_packets", offsetof(struct port_stats, rx_frames)},
 842         {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)},
 843         {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)},
 844         {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)},
 845         {"rx_too_long_packets", offsetof(struct port_stats, rx_too_long)},
 846         {"rx_jabber_packets", offsetof(struct port_stats, rx_jabber)},
 847         {"rx_fcs_error_packets", offsetof(struct port_stats, rx_fcs_err)},
 848         {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)},
 849         {"rx_symbol_error_packets",
 850          offsetof(struct port_stats, rx_symbol_err)},
 851         {"rx_short_packets", offsetof(struct port_stats, rx_runt)},
 852         {"rx_size_64_packets", offsetof(struct port_stats, rx_frames_64)},
 853         {"rx_size_65_to_127_packets",
 854          offsetof(struct port_stats, rx_frames_65_127)},
 855         {"rx_size_128_to_255_packets",
 856          offsetof(struct port_stats, rx_frames_128_255)},
 857         {"rx_size_256_to_511_packets",
 858          offsetof(struct port_stats, rx_frames_256_511)},
 859         {"rx_size_512_to_1023_packets",
 860          offsetof(struct port_stats, rx_frames_512_1023)},
 861         {"rx_size_1024_to_1518_packets",
 862          offsetof(struct port_stats, rx_frames_1024_1518)},
 863         {"rx_size_1519_to_max_packets",
 864          offsetof(struct port_stats, rx_frames_1519_max)},
 865         {"rx_pause_packets", offsetof(struct port_stats, rx_pause)},
 866         {"rx_ppp_pri0_packets", offsetof(struct port_stats, rx_ppp0)},
 867         {"rx_ppp_pri1_packets", offsetof(struct port_stats, rx_ppp1)},
 868         {"rx_ppp_pri2_packets", offsetof(struct port_stats, rx_ppp2)},
 869         {"rx_ppp_pri3_packets", offsetof(struct port_stats, rx_ppp3)},
 870         {"rx_ppp_pri4_packets", offsetof(struct port_stats, rx_ppp4)},
 871         {"rx_ppp_pri5_packets", offsetof(struct port_stats, rx_ppp5)},
 872         {"rx_ppp_pri6_packets", offsetof(struct port_stats, rx_ppp6)},
 873         {"rx_ppp_pri7_packets", offsetof(struct port_stats, rx_ppp7)},
 874         {"rx_bg0_dropped_packets", offsetof(struct port_stats, rx_ovflow0)},
 875         {"rx_bg1_dropped_packets", offsetof(struct port_stats, rx_ovflow1)},
 876         {"rx_bg2_dropped_packets", offsetof(struct port_stats, rx_ovflow2)},
 877         {"rx_bg3_dropped_packets", offsetof(struct port_stats, rx_ovflow3)},
 878         {"rx_bg0_truncated_packets", offsetof(struct port_stats, rx_trunc0)},
 879         {"rx_bg1_truncated_packets", offsetof(struct port_stats, rx_trunc1)},
 880         {"rx_bg2_truncated_packets", offsetof(struct port_stats, rx_trunc2)},
 881         {"rx_bg3_truncated_packets", offsetof(struct port_stats, rx_trunc3)},
 882 };
 883
 884 static const struct cxgbe_dev_xstats_name_off
 885 cxgbevf_dev_port_stats_strings[] = {
 886         {"tx_bytes", offsetof(struct port_stats, tx_octets)},
 887         {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)},
 888         {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)},
 889         {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)},
 890         {"tx_drop_packets", offsetof(struct port_stats, tx_drop)},
 891         {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)},
 892         {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)},
 893         {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)},
 894         {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)},
 895 };
 896
 897 #define CXGBE_NB_RXQ_STATS RTE_DIM(cxgbe_dev_rxq_stats_strings)
 898 #define CXGBE_NB_TXQ_STATS RTE_DIM(cxgbe_dev_txq_stats_strings)
 899 #define CXGBE_NB_PORT_STATS RTE_DIM(cxgbe_dev_port_stats_strings)
 900 #define CXGBEVF_NB_PORT_STATS RTE_DIM(cxgbevf_dev_port_stats_strings)
 901
 902 static u16 cxgbe_dev_xstats_count(struct port_info *pi)
 903 {
 904         u16 count;
 905
 906         count = (pi->n_tx_qsets * CXGBE_NB_TXQ_STATS) +
 907                 (pi->n_rx_qsets * CXGBE_NB_RXQ_STATS);
 908
 909         if (is_pf4(pi->adapter) != 0)
 910                 count += CXGBE_NB_PORT_STATS;
 911         else
 912                 count += CXGBEVF_NB_PORT_STATS;
 913
 914         return count;
 915 }
 916
 917 static int cxgbe_dev_xstats(struct rte_eth_dev *dev,
 918                             struct rte_eth_xstat_name *xstats_names,
 919                             struct rte_eth_xstat *xstats, unsigned int size)
 920 {
 921         const struct cxgbe_dev_xstats_name_off *xstats_str;
 922         struct port_info *pi = dev->data->dev_private;
 923         struct adapter *adap = pi->adapter;
 924         struct sge *s = &adap->sge;
 925         u16 count, i, qid, nstats;
 926         struct port_stats ps;
 927         u64 *stats_ptr;
 928
 929         count = cxgbe_dev_xstats_count(pi);
 930         if (size < count)
 931                 return count;
 932
 933         if (is_pf4(adap) != 0) {
 934                 /* port stats for PF*/
 935                 cxgbe_stats_get(pi, &ps);
 936                 xstats_str = cxgbe_dev_port_stats_strings;
 937                 nstats = CXGBE_NB_PORT_STATS;
 938         } else {
 939                 /* port stats for VF*/
 940                 cxgbevf_stats_get(pi, &ps);
 941                 xstats_str = cxgbevf_dev_port_stats_strings;
 942                 nstats = CXGBEVF_NB_PORT_STATS;
 943         }
 944
 945         count = 0;
 946         for (i = 0; i < nstats; i++, count++) {
 947                 if (xstats_names != NULL)
 948                         snprintf(xstats_names[count].name,
 949                                  sizeof(xstats_names[count].name),
 950                                  "%s", xstats_str[i].name);
 951                 if (xstats != NULL) {
 952                         stats_ptr = RTE_PTR_ADD(&ps,
 953                                                 xstats_str[i].offset);
 954                         xstats[count].value = *stats_ptr;
 955                         xstats[count].id = count;
 956                 }
 957         }
 958
 959         /* per-txq stats */
 960         xstats_str = cxgbe_dev_txq_stats_strings;
 961         for (qid = 0; qid < pi->n_tx_qsets; qid++) {
 962                 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + qid];
 963
 964                 for (i = 0; i < CXGBE_NB_TXQ_STATS; i++, count++) {
 965                         if (xstats_names != NULL)
 966                                 snprintf(xstats_names[count].name,
 967                                          sizeof(xstats_names[count].name),
 968                                          "tx_q%u_%s",
 969                                          qid, xstats_str[i].name);
 970                         if (xstats != NULL) {
 971                                 stats_ptr = RTE_PTR_ADD(&txq->stats,
 972                                                         xstats_str[i].offset);
 973                                 xstats[count].value = *stats_ptr;
 974                                 xstats[count].id = count;
 975                         }
 976                 }
 977         }
 978
 979         /* per-rxq stats */
 980         xstats_str = cxgbe_dev_rxq_stats_strings;
 981         for (qid = 0; qid < pi->n_rx_qsets; qid++) {
 982                 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + qid];
 983
 984                 for (i = 0; i < CXGBE_NB_RXQ_STATS; i++, count++) {
 985                         if (xstats_names != NULL)
 986                                 snprintf(xstats_names[count].name,
 987                                          sizeof(xstats_names[count].name),
 988                                          "rx_q%u_%s",
 989                                          qid, xstats_str[i].name);
 990                         if (xstats != NULL) {
 991                                 stats_ptr = RTE_PTR_ADD(&rxq->stats,
 992                                                         xstats_str[i].offset);
 993                                 xstats[count].value = *stats_ptr;
 994                                 xstats[count].id = count;
 995                         }
 996                 }
 997         }
 998
 999         return count;
1000 }
1001
1002 /* Get port extended statistics by ID. */
1003 int cxgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev,
1004                                const uint64_t *ids, uint64_t *values,
1005                                unsigned int n)
1006 {
1007         struct port_info *pi = dev->data->dev_private;
1008         struct rte_eth_xstat *xstats_copy;
1009         u16 count, i;
1010         int ret = 0;
1011
1012         count = cxgbe_dev_xstats_count(pi);
1013         if (ids == NULL || values == NULL)
1014                 return count;
1015
1016         xstats_copy = rte_calloc(NULL, count, sizeof(*xstats_copy), 0);
1017         if (xstats_copy == NULL)
1018                 return -ENOMEM;
1019
1020         cxgbe_dev_xstats(dev, NULL, xstats_copy, count);
1021
1022         for (i = 0; i < n; i++) {
1023                 if (ids[i] >= count) {
1024                         ret = -EINVAL;
1025                         goto out_err;
1026                 }
1027                 values[i] = xstats_copy[ids[i]].value;
1028         }
1029
1030         ret = n;
1031
1032 out_err:
1033         rte_free(xstats_copy);
1034         return ret;
1035 }
1036
1037 /* Get names of port extended statistics by ID. */
1038 int cxgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
1039                                             const uint64_t *ids,
1040                                             struct rte_eth_xstat_name *xnames,
1041                                             unsigned int n)
1042 {
1043         struct port_info *pi = dev->data->dev_private;
1044         struct rte_eth_xstat_name *xnames_copy;
1045         u16 count, i;
1046         int ret = 0;
1047
1048         count = cxgbe_dev_xstats_count(pi);
1049         if (ids == NULL || xnames == NULL)
1050                 return count;
1051
1052         xnames_copy = rte_calloc(NULL, count, sizeof(*xnames_copy), 0);
1053         if (xnames_copy == NULL)
1054                 return -ENOMEM;
1055
1056         cxgbe_dev_xstats(dev, xnames_copy, NULL, count);
1057
1058         for (i = 0; i < n; i++) {
1059                 if (ids[i] >= count) {
1060                         ret = -EINVAL;
1061                         goto out_err;
1062                 }
1063                 rte_strlcpy(xnames[i].name, xnames_copy[ids[i]].name,
1064                             sizeof(xnames[i].name));
1065         }
1066
1067         ret = n;
1068
1069 out_err:
1070         rte_free(xnames_copy);
1071         return ret;
1072 }
1073
1074 /* Get port extended statistics. */
1075 int cxgbe_dev_xstats_get(struct rte_eth_dev *dev,
1076                          struct rte_eth_xstat *xstats, unsigned int n)
1077 {
1078         return cxgbe_dev_xstats(dev, NULL, xstats, n);
1079 }
1080
1081 /* Get names of port extended statistics. */
1082 int cxgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
1083                                struct rte_eth_xstat_name *xstats_names,
1084                                unsigned int n)
1085 {
1086         return cxgbe_dev_xstats(dev, xstats_names, NULL, n);
1087 }
1088
1089 /* Reset port extended statistics. */
1090 static int cxgbe_dev_xstats_reset(struct rte_eth_dev *dev)
1091 {
1092         return cxgbe_dev_stats_reset(dev);
1093 }
1094
1095 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1096                                struct rte_eth_fc_conf *fc_conf)
1097 {
1098         struct port_info *pi = eth_dev->data->dev_private;
1099         struct link_config *lc = &pi->link_cfg;
1100         u8 rx_pause = 0, tx_pause = 0;
1101         u32 caps = lc->link_caps;
1102
1103         if (caps & FW_PORT_CAP32_ANEG)
1104                 fc_conf->autoneg = 1;
1105
1106         if (caps & FW_PORT_CAP32_FC_TX)
1107                 tx_pause = 1;
1108
1109         if (caps & FW_PORT_CAP32_FC_RX)
1110                 rx_pause = 1;
1111
1112         if (rx_pause && tx_pause)
1113                 fc_conf->mode = RTE_FC_FULL;
1114         else if (rx_pause)
1115                 fc_conf->mode = RTE_FC_RX_PAUSE;
1116         else if (tx_pause)
1117                 fc_conf->mode = RTE_FC_TX_PAUSE;
1118         else
1119                 fc_conf->mode = RTE_FC_NONE;
1120         return 0;
1121 }
1122
1123 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1124                                struct rte_eth_fc_conf *fc_conf)
1125 {
1126         struct port_info *pi = eth_dev->data->dev_private;
1127         struct link_config *lc = &pi->link_cfg;
1128         u32 new_caps = lc->admin_caps;
1129         u8 tx_pause = 0, rx_pause = 0;
1130         int ret;
1131
1132         if (fc_conf->mode == RTE_FC_FULL) {
1133                 tx_pause = 1;
1134                 rx_pause = 1;
1135         } else if (fc_conf->mode == RTE_FC_TX_PAUSE) {
1136                 tx_pause = 1;
1137         } else if (fc_conf->mode == RTE_FC_RX_PAUSE) {
1138                 rx_pause = 1;
1139         }
1140
1141         ret = t4_set_link_pause(pi, fc_conf->autoneg, tx_pause,
1142                                 rx_pause, &new_caps);
1143         if (ret != 0)
1144                 return ret;
1145
1146         if (!fc_conf->autoneg) {
1147                 if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)
1148                         new_caps |= FW_PORT_CAP32_FORCE_PAUSE;
1149         } else {
1150                 new_caps &= ~FW_PORT_CAP32_FORCE_PAUSE;
1151         }
1152
1153         if (new_caps != lc->admin_caps) {
1154                 ret = t4_link_l1cfg(pi, new_caps);
1155                 if (ret == 0)
1156                         lc->admin_caps = new_caps;
1157         }
1158
1159         return ret;
1160 }
1161
1162 const uint32_t *
1163 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1164 {
1165         static const uint32_t ptypes[] = {
1166                 RTE_PTYPE_L3_IPV4,
1167                 RTE_PTYPE_L3_IPV6,
1168                 RTE_PTYPE_UNKNOWN
1169         };
1170
1171         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
1172                 return ptypes;
1173         return NULL;
1174 }
1175
1176 /* Update RSS hash configuration
1177  */
1178 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
1179                                      struct rte_eth_rss_conf *rss_conf)
1180 {
1181         struct port_info *pi = dev->data->dev_private;
1182         struct adapter *adapter = pi->adapter;
1183         int err;
1184
1185         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
1186         if (err)
1187                 return err;
1188
1189         pi->rss_hf = rss_conf->rss_hf;
1190
1191         if (rss_conf->rss_key) {
1192                 u32 key[10], mod_key[10];
1193                 int i, j;
1194
1195                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
1196
1197                 for (i = 9, j = 0; i >= 0; i--, j++)
1198                         mod_key[j] = cpu_to_be32(key[i]);
1199
1200                 t4_write_rss_key(adapter, mod_key, -1);
1201         }
1202
1203         return 0;
1204 }
1205
1206 /* Get RSS hash configuration
1207  */
1208 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1209                                        struct rte_eth_rss_conf *rss_conf)
1210 {
1211         struct port_info *pi = dev->data->dev_private;
1212         struct adapter *adapter = pi->adapter;
1213         u64 rss_hf = 0;
1214         u64 flags = 0;
1215         int err;
1216
1217         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
1218                                     &flags, NULL);
1219
1220         if (err)
1221                 return err;
1222
1223         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
1224                 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
1225                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
1226                         rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
1227         }
1228
1229         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1230                 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
1231
1232         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
1233                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1234                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
1235                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1236         }
1237
1238         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1239                 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
1240
1241         rss_conf->rss_hf = rss_hf;
1242
1243         if (rss_conf->rss_key) {
1244                 u32 key[10], mod_key[10];
1245                 int i, j;
1246
1247                 t4_read_rss_key(adapter, key);
1248
1249                 for (i = 9, j = 0; i >= 0; i--, j++)
1250                         mod_key[j] = be32_to_cpu(key[i]);
1251
1252                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
1253         }
1254
1255         return 0;
1256 }
1257
1258 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
1259                                      struct rte_eth_rss_reta_entry64 *reta_conf,
1260                                      uint16_t reta_size)
1261 {
1262         struct port_info *pi = dev->data->dev_private;
1263         struct adapter *adapter = pi->adapter;
1264         u16 i, idx, shift, *rss;
1265         int ret;
1266
1267         if (!(adapter->flags & FULL_INIT_DONE))
1268                 return -ENOMEM;
1269
1270         if (!reta_size || reta_size > pi->rss_size)
1271                 return -EINVAL;
1272
1273         rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0);
1274         if (!rss)
1275                 return -ENOMEM;
1276
1277         rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16));
1278         for (i = 0; i < reta_size; i++) {
1279                 idx = i / RTE_RETA_GROUP_SIZE;
1280                 shift = i % RTE_RETA_GROUP_SIZE;
1281                 if (!(reta_conf[idx].mask & (1ULL << shift)))
1282                         continue;
1283
1284                 rss[i] = reta_conf[idx].reta[shift];
1285         }
1286
1287         ret = cxgbe_write_rss(pi, rss);
1288         if (!ret)
1289                 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16));
1290
1291         rte_free(rss);
1292         return ret;
1293 }
1294
1295 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
1296                                     struct rte_eth_rss_reta_entry64 *reta_conf,
1297                                     uint16_t reta_size)
1298 {
1299         struct port_info *pi = dev->data->dev_private;
1300         struct adapter *adapter = pi->adapter;
1301         u16 i, idx, shift;
1302
1303         if (!(adapter->flags & FULL_INIT_DONE))
1304                 return -ENOMEM;
1305
1306         if (!reta_size || reta_size > pi->rss_size)
1307                 return -EINVAL;
1308
1309         for (i = 0; i < reta_size; i++) {
1310                 idx = i / RTE_RETA_GROUP_SIZE;
1311                 shift = i % RTE_RETA_GROUP_SIZE;
1312                 if (!(reta_conf[idx].mask & (1ULL << shift)))
1313                         continue;
1314
1315                 reta_conf[idx].reta[shift] = pi->rss[i];
1316         }
1317
1318         return 0;
1319 }
1320
1321 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
1322 {
1323         RTE_SET_USED(dev);
1324         return EEPROMSIZE;
1325 }
1326
1327 /**
1328  * eeprom_ptov - translate a physical EEPROM address to virtual
1329  * @phys_addr: the physical EEPROM address
1330  * @fn: the PCI function number
1331  * @sz: size of function-specific area
1332  *
1333  * Translate a physical EEPROM address to virtual.  The first 1K is
1334  * accessed through virtual addresses starting at 31K, the rest is
1335  * accessed through virtual addresses starting at 0.
1336  *
1337  * The mapping is as follows:
1338  * [0..1K) -> [31K..32K)
1339  * [1K..1K+A) -> [31K-A..31K)
1340  * [1K+A..ES) -> [0..ES-A-1K)
1341  *
1342  * where A = @fn * @sz, and ES = EEPROM size.
1343  */
1344 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
1345 {
1346         fn *= sz;
1347         if (phys_addr < 1024)
1348                 return phys_addr + (31 << 10);
1349         if (phys_addr < 1024 + fn)
1350                 return fn + phys_addr - 1024;
1351         if (phys_addr < EEPROMSIZE)
1352                 return phys_addr - 1024 - fn;
1353         if (phys_addr < EEPROMVSIZE)
1354                 return phys_addr - 1024;
1355         return -EINVAL;
1356 }
1357
1358 /* The next two routines implement eeprom read/write from physical addresses.
1359  */
1360 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
1361 {
1362         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1363
1364         if (vaddr >= 0)
1365                 vaddr = t4_seeprom_read(adap, vaddr, v);
1366         return vaddr < 0 ? vaddr : 0;
1367 }
1368
1369 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
1370 {
1371         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1372
1373         if (vaddr >= 0)
1374                 vaddr = t4_seeprom_write(adap, vaddr, v);
1375         return vaddr < 0 ? vaddr : 0;
1376 }
1377
1378 #define EEPROM_MAGIC 0x38E2F10C
1379
1380 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
1381                             struct rte_dev_eeprom_info *e)
1382 {
1383         struct port_info *pi = dev->data->dev_private;
1384         struct adapter *adapter = pi->adapter;
1385         u32 i, err = 0;
1386         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
1387
1388         if (!buf)
1389                 return -ENOMEM;
1390
1391         e->magic = EEPROM_MAGIC;
1392         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
1393                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1394
1395         if (!err)
1396                 rte_memcpy(e->data, buf + e->offset, e->length);
1397         rte_free(buf);
1398         return err;
1399 }
1400
1401 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
1402                             struct rte_dev_eeprom_info *eeprom)
1403 {
1404         struct port_info *pi = dev->data->dev_private;
1405         struct adapter *adapter = pi->adapter;
1406         u8 *buf;
1407         int err = 0;
1408         u32 aligned_offset, aligned_len, *p;
1409
1410         if (eeprom->magic != EEPROM_MAGIC)
1411                 return -EINVAL;
1412
1413         aligned_offset = eeprom->offset & ~3;
1414         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1415
1416         if (adapter->pf > 0) {
1417                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1418
1419                 if (aligned_offset < start ||
1420                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
1421                         return -EPERM;
1422         }
1423
1424         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1425                 /* RMW possibly needed for first or last words.
1426                  */
1427                 buf = rte_zmalloc(NULL, aligned_len, 0);
1428                 if (!buf)
1429                         return -ENOMEM;
1430                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1431                 if (!err && aligned_len > 4)
1432                         err = eeprom_rd_phys(adapter,
1433                                              aligned_offset + aligned_len - 4,
1434                                              (u32 *)&buf[aligned_len - 4]);
1435                 if (err)
1436                         goto out;
1437                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1438                            eeprom->length);
1439         } else {
1440                 buf = eeprom->data;
1441         }
1442
1443         err = t4_seeprom_wp(adapter, false);
1444         if (err)
1445                 goto out;
1446
1447         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1448                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1449                 aligned_offset += 4;
1450         }
1451
1452         if (!err)
1453                 err = t4_seeprom_wp(adapter, true);
1454 out:
1455         if (buf != eeprom->data)
1456                 rte_free(buf);
1457         return err;
1458 }
1459
1460 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1461 {
1462         struct port_info *pi = eth_dev->data->dev_private;
1463         struct adapter *adapter = pi->adapter;
1464
1465         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1466 }
1467
1468 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1469                           struct rte_dev_reg_info *regs)
1470 {
1471         struct port_info *pi = eth_dev->data->dev_private;
1472         struct adapter *adapter = pi->adapter;
1473
1474         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1475                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1476                 (1 << 16);
1477
1478         if (regs->data == NULL) {
1479                 regs->length = cxgbe_get_regs_len(eth_dev);
1480                 regs->width = sizeof(uint32_t);
1481
1482                 return 0;
1483         }
1484
1485         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1486
1487         return 0;
1488 }
1489
1490 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1491 {
1492         struct port_info *pi = dev->data->dev_private;
1493         int ret;
1494
1495         ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1496         if (ret < 0) {
1497                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1498                         ret);
1499                 return ret;
1500         }
1501         pi->xact_addr_filt = ret;
1502         return 0;
1503 }
1504
1505 static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc,
1506                                            struct rte_eth_fec_capa *capa_arr)
1507 {
1508         int num = 0;
1509
1510         if (lc->pcaps & FW_PORT_CAP32_SPEED_100G) {
1511                 if (capa_arr) {
1512                         capa_arr[num].speed = ETH_SPEED_NUM_100G;
1513                         capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1514                                              RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1515                 }
1516                 num++;
1517         }
1518
1519         if (lc->pcaps & FW_PORT_CAP32_SPEED_50G) {
1520                 if (capa_arr) {
1521                         capa_arr[num].speed = ETH_SPEED_NUM_50G;
1522                         capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1523                                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
1524                 }
1525                 num++;
1526         }
1527
1528         if (lc->pcaps & FW_PORT_CAP32_SPEED_25G) {
1529                 if (capa_arr) {
1530                         capa_arr[num].speed = ETH_SPEED_NUM_25G;
1531                         capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1532                                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
1533                                              RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1534                 }
1535                 num++;
1536         }
1537
1538         return num;
1539 }
1540
1541 static int cxgbe_fec_get_capability(struct rte_eth_dev *dev,
1542                                     struct rte_eth_fec_capa *speed_fec_capa,
1543                                     unsigned int num)
1544 {
1545         struct port_info *pi = dev->data->dev_private;
1546         struct link_config *lc = &pi->link_cfg;
1547         u8 num_entries;
1548
1549         if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1550                 return -EOPNOTSUPP;
1551
1552         num_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL);
1553         if (!speed_fec_capa || num < num_entries)
1554                 return num_entries;
1555
1556         return cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa);
1557 }
1558
1559 static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
1560 {
1561         struct port_info *pi = dev->data->dev_private;
1562         struct link_config *lc = &pi->link_cfg;
1563         u32 fec_caps = 0, caps = lc->link_caps;
1564
1565         if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1566                 return -EOPNOTSUPP;
1567
1568         if (caps & FW_PORT_CAP32_FEC_RS)
1569                 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1570         else if (caps & FW_PORT_CAP32_FEC_BASER_RS)
1571                 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
1572         else
1573                 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
1574
1575         *fec_capa = fec_caps;
1576         return 0;
1577 }
1578
1579 static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa)
1580 {
1581         struct port_info *pi = dev->data->dev_private;
1582         u8 fec_rs = 0, fec_baser = 0, fec_none = 0;
1583         struct link_config *lc = &pi->link_cfg;
1584         u32 new_caps = lc->admin_caps;
1585         int ret;
1586
1587         if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1588                 return -EOPNOTSUPP;
1589
1590         if (!fec_capa)
1591                 return -EINVAL;
1592
1593         if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO))
1594                 goto set_fec;
1595
1596         if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC))
1597                 fec_none = 1;
1598
1599         if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER))
1600                 fec_baser = 1;
1601
1602         if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS))
1603                 fec_rs = 1;
1604
1605 set_fec:
1606         ret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps);
1607         if (ret != 0)
1608                 return ret;
1609
1610         if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
1611                 new_caps |= FW_PORT_CAP32_FORCE_FEC;
1612         else
1613                 new_caps &= ~FW_PORT_CAP32_FORCE_FEC;
1614
1615         if (new_caps != lc->admin_caps) {
1616                 ret = t4_link_l1cfg(pi, new_caps);
1617                 if (ret == 0)
1618                         lc->admin_caps = new_caps;
1619         }
1620
1621         return ret;
1622 }
1623
1624 int cxgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
1625                          size_t fw_size)
1626 {
1627         struct port_info *pi = dev->data->dev_private;
1628         struct adapter *adapter = pi->adapter;
1629         int ret;
1630
1631         if (adapter->params.fw_vers == 0)
1632                 return -EIO;
1633
1634         ret = snprintf(fw_version, fw_size, "%u.%u.%u.%u",
1635                        G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
1636                        G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
1637                        G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
1638                        G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
1639         if (ret < 0)
1640                 return -EINVAL;
1641
1642         ret += 1;
1643         if (fw_size < (size_t)ret)
1644                 return ret;
1645
1646         return 0;
1647 }
1648
1649 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1650         .dev_start              = cxgbe_dev_start,
1651         .dev_stop               = cxgbe_dev_stop,
1652         .dev_close              = cxgbe_dev_close,
1653         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1654         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1655         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1656         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1657         .dev_configure          = cxgbe_dev_configure,
1658         .dev_infos_get          = cxgbe_dev_info_get,
1659         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1660         .link_update            = cxgbe_dev_link_update,
1661         .dev_set_link_up        = cxgbe_dev_set_link_up,
1662         .dev_set_link_down      = cxgbe_dev_set_link_down,
1663         .mtu_set                = cxgbe_dev_mtu_set,
1664         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1665         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1666         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1667         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1668         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1669         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1670         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1671         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1672         .flow_ops_get           = cxgbe_dev_flow_ops_get,
1673         .stats_get              = cxgbe_dev_stats_get,
1674         .stats_reset            = cxgbe_dev_stats_reset,
1675         .xstats_get             = cxgbe_dev_xstats_get,
1676         .xstats_get_by_id       = cxgbe_dev_xstats_get_by_id,
1677         .xstats_get_names       = cxgbe_dev_xstats_get_names,
1678         .xstats_get_names_by_id = cxgbe_dev_xstats_get_names_by_id,
1679         .xstats_reset           = cxgbe_dev_xstats_reset,
1680         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1681         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1682         .get_eeprom_length      = cxgbe_get_eeprom_length,
1683         .get_eeprom             = cxgbe_get_eeprom,
1684         .set_eeprom             = cxgbe_set_eeprom,
1685         .get_reg                = cxgbe_get_regs,
1686         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1687         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1688         .mac_addr_set           = cxgbe_mac_addr_set,
1689         .reta_update            = cxgbe_dev_rss_reta_update,
1690         .reta_query             = cxgbe_dev_rss_reta_query,
1691         .fec_get_capability     = cxgbe_fec_get_capability,
1692         .fec_get                = cxgbe_fec_get,
1693         .fec_set                = cxgbe_fec_set,
1694         .fw_version_get         = cxgbe_fw_version_get,
1695 };
1696
1697 /*
1698  * Initialize driver
1699  * It returns 0 on success.
1700  */
1701 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1702 {
1703         struct rte_pci_device *pci_dev;
1704         struct port_info *pi = eth_dev->data->dev_private;
1705         struct adapter *adapter = NULL;
1706         char name[RTE_ETH_NAME_MAX_LEN];
1707         int err = 0;
1708
1709         CXGBE_FUNC_TRACE();
1710
1711         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1712         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1713         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1714         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1715
1716         /* for secondary processes, we attach to ethdevs allocated by primary
1717          * and do minimal initialization.
1718          */
1719         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1720                 int i;
1721
1722                 for (i = 1; i < MAX_NPORTS; i++) {
1723                         struct rte_eth_dev *rest_eth_dev;
1724                         char namei[RTE_ETH_NAME_MAX_LEN];
1725
1726                         snprintf(namei, sizeof(namei), "%s_%d",
1727                                  pci_dev->device.name, i);
1728                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1729                         if (rest_eth_dev) {
1730                                 rest_eth_dev->device = &pci_dev->device;
1731                                 rest_eth_dev->dev_ops =
1732                                         eth_dev->dev_ops;
1733                                 rest_eth_dev->rx_pkt_burst =
1734                                         eth_dev->rx_pkt_burst;
1735                                 rest_eth_dev->tx_pkt_burst =
1736                                         eth_dev->tx_pkt_burst;
1737                                 rte_eth_dev_probing_finish(rest_eth_dev);
1738                         }
1739                 }
1740                 return 0;
1741         }
1742
1743         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1744         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1745         if (!adapter)
1746                 return -1;
1747
1748         adapter->use_unpacked_mode = 1;
1749         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1750         if (!adapter->regs) {
1751                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1752                 err = -ENOMEM;
1753                 goto out_free_adapter;
1754         }
1755         adapter->pdev = pci_dev;
1756         adapter->eth_dev = eth_dev;
1757         pi->adapter = adapter;
1758
1759         cxgbe_process_devargs(adapter);
1760
1761         err = cxgbe_probe(adapter);
1762         if (err) {
1763                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1764                         __func__, err);
1765                 goto out_free_adapter;
1766         }
1767
1768         return 0;
1769
1770 out_free_adapter:
1771         rte_free(adapter);
1772         return err;
1773 }
1774
1775 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1776 {
1777         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1778         uint16_t port_id;
1779         int err = 0;
1780
1781         /* Free up other ports and all resources */
1782         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
1783                 err |= rte_eth_dev_close(port_id);
1784
1785         return err == 0 ? 0 : -EIO;
1786 }
1787
1788 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1789         struct rte_pci_device *pci_dev)
1790 {
1791         return rte_eth_dev_pci_generic_probe(pci_dev,
1792                 sizeof(struct port_info), eth_cxgbe_dev_init);
1793 }
1794
1795 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1796 {
1797         return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1798 }
1799
1800 static struct rte_pci_driver rte_cxgbe_pmd = {
1801         .id_table = cxgb4_pci_tbl,
1802         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1803         .probe = eth_cxgbe_pci_probe,
1804         .remove = eth_cxgbe_pci_remove,
1805 };
1806
1807 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1808 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1809 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1810 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1811                               CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "
1812                               CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> "
1813                               CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> "
1814                               CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> ");
1815 RTE_LOG_REGISTER_DEFAULT(cxgbe_logtype, NOTICE);
1816 RTE_LOG_REGISTER_SUFFIX(cxgbe_mbox_logtype, mbox, NOTICE);