1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
39 #include "cxgbe_flow.h"
42 int cxgbe_mbox_logtype;
45 * Macros needed to support the PCI Device ID Table ...
47 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
48 static const struct rte_pci_id cxgb4_pci_tbl[] = {
49 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
51 #define PCI_VENDOR_ID_CHELSIO 0x1425
53 #define CH_PCI_ID_TABLE_ENTRY(devid) \
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
56 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
61 *... and the PCI ID Table itself ...
63 #include "base/t4_pci_id_tbl.h"
65 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
68 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
69 uint16_t pkts_sent, pkts_remain;
70 uint16_t total_sent = 0;
74 t4_os_lock(&txq->txq_lock);
75 /* free up desc from already completed tx */
76 reclaim_completed_tx(&txq->q);
77 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
78 while (total_sent < nb_pkts) {
79 pkts_remain = nb_pkts - total_sent;
81 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
82 idx = total_sent + pkts_sent;
83 if ((idx + 1) < nb_pkts)
84 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
86 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
92 total_sent += pkts_sent;
93 /* reclaim as much as possible */
94 reclaim_completed_tx(&txq->q);
97 t4_os_unlock(&txq->txq_lock);
101 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
104 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
105 unsigned int work_done;
107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
108 dev_err(adapter, "error in cxgbe poll\n");
113 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
114 struct rte_eth_dev_info *device_info)
116 struct port_info *pi = eth_dev->data->dev_private;
117 struct adapter *adapter = pi->adapter;
118 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
120 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
121 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
122 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
126 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
127 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
128 device_info->max_rx_queues = max_queues;
129 device_info->max_tx_queues = max_queues;
130 device_info->max_mac_addrs = 1;
131 /* XXX: For now we support one MAC/port */
132 device_info->max_vfs = adapter->params.arch.vfcount;
133 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
135 device_info->rx_queue_offload_capa = 0UL;
136 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
138 device_info->tx_queue_offload_capa = 0UL;
139 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
141 device_info->reta_size = pi->rss_size;
142 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
143 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
145 device_info->rx_desc_lim = cxgbe_desc_lim;
146 device_info->tx_desc_lim = cxgbe_desc_lim;
147 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
152 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
154 struct port_info *pi = eth_dev->data->dev_private;
155 struct adapter *adapter = pi->adapter;
157 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
158 1, -1, 1, -1, false);
161 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
163 struct port_info *pi = eth_dev->data->dev_private;
164 struct adapter *adapter = pi->adapter;
166 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
167 0, -1, 1, -1, false);
170 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
172 struct port_info *pi = eth_dev->data->dev_private;
173 struct adapter *adapter = pi->adapter;
175 /* TODO: address filters ?? */
177 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
178 -1, 1, 1, -1, false);
181 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
183 struct port_info *pi = eth_dev->data->dev_private;
184 struct adapter *adapter = pi->adapter;
186 /* TODO: address filters ?? */
188 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
189 -1, 0, 1, -1, false);
192 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
193 int wait_to_complete)
195 struct port_info *pi = eth_dev->data->dev_private;
196 struct adapter *adapter = pi->adapter;
197 struct sge *s = &adapter->sge;
198 struct rte_eth_link new_link = { 0 };
199 unsigned int i, work_done, budget = 32;
200 u8 old_link = pi->link_cfg.link_ok;
202 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
203 if (!s->fw_evtq.desc)
206 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
208 /* Exit if link status changed or always forced up */
209 if (pi->link_cfg.link_ok != old_link ||
210 cxgbe_force_linkup(adapter))
213 if (!wait_to_complete)
216 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
219 new_link.link_status = cxgbe_force_linkup(adapter) ?
220 ETH_LINK_UP : pi->link_cfg.link_ok;
221 new_link.link_autoneg = pi->link_cfg.autoneg;
222 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
223 new_link.link_speed = pi->link_cfg.speed;
225 return rte_eth_linkstatus_set(eth_dev, &new_link);
229 * Set device link up.
231 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
233 struct port_info *pi = dev->data->dev_private;
234 struct adapter *adapter = pi->adapter;
235 unsigned int work_done, budget = 32;
236 struct sge *s = &adapter->sge;
239 if (!s->fw_evtq.desc)
242 /* Flush all link events */
243 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
245 /* If link already up, nothing to do */
246 if (pi->link_cfg.link_ok)
249 ret = cxgbe_set_link_status(pi, true);
253 cxgbe_dev_link_update(dev, 1);
258 * Set device link down.
260 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
262 struct port_info *pi = dev->data->dev_private;
263 struct adapter *adapter = pi->adapter;
264 unsigned int work_done, budget = 32;
265 struct sge *s = &adapter->sge;
268 if (!s->fw_evtq.desc)
271 /* Flush all link events */
272 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
274 /* If link already down, nothing to do */
275 if (!pi->link_cfg.link_ok)
278 ret = cxgbe_set_link_status(pi, false);
282 cxgbe_dev_link_update(dev, 0);
286 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
288 struct port_info *pi = eth_dev->data->dev_private;
289 struct adapter *adapter = pi->adapter;
290 struct rte_eth_dev_info dev_info;
292 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
294 err = cxgbe_dev_info_get(eth_dev, &dev_info);
298 /* Must accommodate at least RTE_ETHER_MIN_MTU */
299 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen)
302 /* set to jumbo mode if needed */
303 if (new_mtu > RTE_ETHER_MAX_LEN)
304 eth_dev->data->dev_conf.rxmode.offloads |=
305 DEV_RX_OFFLOAD_JUMBO_FRAME;
307 eth_dev->data->dev_conf.rxmode.offloads &=
308 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
310 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
313 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
321 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
323 struct port_info *pi = eth_dev->data->dev_private;
324 struct adapter *adapter = pi->adapter;
328 if (!(adapter->flags & FULL_INIT_DONE))
334 * We clear queues only if both tx and rx path of the port
337 t4_sge_eth_clear_queues(pi);
341 * It returns 0 on success.
343 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
345 struct port_info *pi = eth_dev->data->dev_private;
346 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode;
347 struct adapter *adapter = pi->adapter;
353 * If we don't have a connection to the firmware there's nothing we
356 if (!(adapter->flags & FW_OK)) {
361 if (!(adapter->flags & FULL_INIT_DONE)) {
362 err = cxgbe_up(adapter);
367 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
368 eth_dev->data->scattered_rx = 1;
370 eth_dev->data->scattered_rx = 0;
372 cxgbe_enable_rx_queues(pi);
374 err = cxgbe_setup_rss(pi);
378 for (i = 0; i < pi->n_tx_qsets; i++) {
379 err = cxgbe_dev_tx_queue_start(eth_dev, i);
384 for (i = 0; i < pi->n_rx_qsets; i++) {
385 err = cxgbe_dev_rx_queue_start(eth_dev, i);
390 err = cxgbe_link_start(pi);
399 * Stop device: disable rx and tx functions to allow for reconfiguring.
401 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
403 struct port_info *pi = eth_dev->data->dev_private;
404 struct adapter *adapter = pi->adapter;
408 if (!(adapter->flags & FULL_INIT_DONE))
414 * We clear queues only if both tx and rx path of the port
417 t4_sge_eth_clear_queues(pi);
418 eth_dev->data->scattered_rx = 0;
421 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
423 struct port_info *pi = eth_dev->data->dev_private;
424 struct adapter *adapter = pi->adapter;
429 eth_dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
431 if (!(adapter->flags & FW_QUEUE_BOUND)) {
432 err = cxgbe_setup_sge_fwevtq(adapter);
435 adapter->flags |= FW_QUEUE_BOUND;
436 if (is_pf4(adapter)) {
437 err = cxgbe_setup_sge_ctrl_txq(adapter);
443 err = cxgbe_cfg_queue_count(eth_dev);
450 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
453 struct sge_eth_txq *txq = (struct sge_eth_txq *)
454 (eth_dev->data->tx_queues[tx_queue_id]);
456 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
458 ret = t4_sge_eth_txq_start(txq);
460 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
465 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
468 struct sge_eth_txq *txq = (struct sge_eth_txq *)
469 (eth_dev->data->tx_queues[tx_queue_id]);
471 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
473 ret = t4_sge_eth_txq_stop(txq);
475 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
480 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
481 uint16_t queue_idx, uint16_t nb_desc,
482 unsigned int socket_id,
483 const struct rte_eth_txconf *tx_conf __rte_unused)
485 struct port_info *pi = eth_dev->data->dev_private;
486 struct adapter *adapter = pi->adapter;
487 struct sge *s = &adapter->sge;
488 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
490 unsigned int temp_nb_desc;
492 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
493 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
494 socket_id, pi->first_qset);
496 /* Free up the existing queue */
497 if (eth_dev->data->tx_queues[queue_idx]) {
498 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
499 eth_dev->data->tx_queues[queue_idx] = NULL;
502 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
506 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
508 temp_nb_desc = nb_desc;
509 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
510 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
511 __func__, CXGBE_MIN_RING_DESC_SIZE,
512 CXGBE_DEFAULT_TX_DESC_SIZE);
513 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
514 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
515 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
516 __func__, CXGBE_MIN_RING_DESC_SIZE,
517 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
521 txq->q.size = temp_nb_desc;
523 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
524 s->fw_evtq.cntxt_id, socket_id);
526 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
527 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
531 void cxgbe_dev_tx_queue_release(void *q)
533 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
536 struct port_info *pi = (struct port_info *)
537 (txq->eth_dev->data->dev_private);
538 struct adapter *adap = pi->adapter;
540 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
541 __func__, pi->port_id, txq->q.cntxt_id);
543 t4_sge_eth_txq_release(adap, txq);
547 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
550 struct port_info *pi = eth_dev->data->dev_private;
551 struct adapter *adap = pi->adapter;
554 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
555 __func__, pi->port_id, rx_queue_id);
557 q = eth_dev->data->rx_queues[rx_queue_id];
559 ret = t4_sge_eth_rxq_start(adap, q);
561 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
566 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
569 struct port_info *pi = eth_dev->data->dev_private;
570 struct adapter *adap = pi->adapter;
573 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
574 __func__, pi->port_id, rx_queue_id);
576 q = eth_dev->data->rx_queues[rx_queue_id];
577 ret = t4_sge_eth_rxq_stop(adap, q);
579 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
584 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
585 uint16_t queue_idx, uint16_t nb_desc,
586 unsigned int socket_id,
587 const struct rte_eth_rxconf *rx_conf __rte_unused,
588 struct rte_mempool *mp)
590 struct port_info *pi = eth_dev->data->dev_private;
591 struct adapter *adapter = pi->adapter;
592 struct sge *s = &adapter->sge;
593 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
596 unsigned int temp_nb_desc;
597 struct rte_eth_dev_info dev_info;
598 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
600 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
601 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
604 err = cxgbe_dev_info_get(eth_dev, &dev_info);
606 dev_err(adap, "%s: error during getting ethernet device info",
611 /* Must accommodate at least RTE_ETHER_MIN_MTU */
612 if ((pkt_len < dev_info.min_rx_bufsize) ||
613 (pkt_len > dev_info.max_rx_pktlen)) {
614 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
615 __func__, dev_info.min_rx_bufsize,
616 dev_info.max_rx_pktlen);
620 /* Free up the existing queue */
621 if (eth_dev->data->rx_queues[queue_idx]) {
622 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
623 eth_dev->data->rx_queues[queue_idx] = NULL;
626 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
630 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
632 temp_nb_desc = nb_desc;
633 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
634 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
635 __func__, CXGBE_MIN_RING_DESC_SIZE,
636 CXGBE_DEFAULT_RX_DESC_SIZE);
637 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
638 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
639 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
640 __func__, CXGBE_MIN_RING_DESC_SIZE,
641 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
645 rxq->rspq.size = temp_nb_desc;
646 if ((&rxq->fl) != NULL)
647 rxq->fl.size = temp_nb_desc;
649 /* Set to jumbo mode if necessary */
650 if (pkt_len > RTE_ETHER_MAX_LEN)
651 eth_dev->data->dev_conf.rxmode.offloads |=
652 DEV_RX_OFFLOAD_JUMBO_FRAME;
654 eth_dev->data->dev_conf.rxmode.offloads &=
655 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
657 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
660 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
661 queue_idx, socket_id);
663 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
664 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
669 void cxgbe_dev_rx_queue_release(void *q)
671 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
672 struct sge_rspq *rq = &rxq->rspq;
675 struct port_info *pi = (struct port_info *)
676 (rq->eth_dev->data->dev_private);
677 struct adapter *adap = pi->adapter;
679 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
680 __func__, pi->port_id, rxq->rspq.cntxt_id);
682 t4_sge_eth_rxq_release(adap, rxq);
687 * Get port statistics.
689 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
690 struct rte_eth_stats *eth_stats)
692 struct port_info *pi = eth_dev->data->dev_private;
693 struct adapter *adapter = pi->adapter;
694 struct sge *s = &adapter->sge;
695 struct port_stats ps;
698 cxgbe_stats_get(pi, &ps);
701 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
702 ps.rx_ovflow2 + ps.rx_ovflow3 +
703 ps.rx_trunc0 + ps.rx_trunc1 +
704 ps.rx_trunc2 + ps.rx_trunc3;
705 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
706 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
710 eth_stats->opackets = ps.tx_frames;
711 eth_stats->obytes = ps.tx_octets;
712 eth_stats->oerrors = ps.tx_error_frames;
714 for (i = 0; i < pi->n_rx_qsets; i++) {
715 struct sge_eth_rxq *rxq =
716 &s->ethrxq[pi->first_qset + i];
718 eth_stats->q_ipackets[i] = rxq->stats.pkts;
719 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
720 eth_stats->ipackets += eth_stats->q_ipackets[i];
721 eth_stats->ibytes += eth_stats->q_ibytes[i];
724 for (i = 0; i < pi->n_tx_qsets; i++) {
725 struct sge_eth_txq *txq =
726 &s->ethtxq[pi->first_qset + i];
728 eth_stats->q_opackets[i] = txq->stats.pkts;
729 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
735 * Reset port statistics.
737 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
739 struct port_info *pi = eth_dev->data->dev_private;
740 struct adapter *adapter = pi->adapter;
741 struct sge *s = &adapter->sge;
744 cxgbe_stats_reset(pi);
745 for (i = 0; i < pi->n_rx_qsets; i++) {
746 struct sge_eth_rxq *rxq =
747 &s->ethrxq[pi->first_qset + i];
750 rxq->stats.rx_bytes = 0;
752 for (i = 0; i < pi->n_tx_qsets; i++) {
753 struct sge_eth_txq *txq =
754 &s->ethtxq[pi->first_qset + i];
757 txq->stats.tx_bytes = 0;
758 txq->stats.mapping_err = 0;
764 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
765 struct rte_eth_fc_conf *fc_conf)
767 struct port_info *pi = eth_dev->data->dev_private;
768 struct link_config *lc = &pi->link_cfg;
769 int rx_pause, tx_pause;
771 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
772 rx_pause = lc->fc & PAUSE_RX;
773 tx_pause = lc->fc & PAUSE_TX;
775 if (rx_pause && tx_pause)
776 fc_conf->mode = RTE_FC_FULL;
778 fc_conf->mode = RTE_FC_RX_PAUSE;
780 fc_conf->mode = RTE_FC_TX_PAUSE;
782 fc_conf->mode = RTE_FC_NONE;
786 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
787 struct rte_eth_fc_conf *fc_conf)
789 struct port_info *pi = eth_dev->data->dev_private;
790 struct adapter *adapter = pi->adapter;
791 struct link_config *lc = &pi->link_cfg;
793 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
794 if (fc_conf->autoneg)
795 lc->requested_fc |= PAUSE_AUTONEG;
797 lc->requested_fc &= ~PAUSE_AUTONEG;
800 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
801 (fc_conf->mode & RTE_FC_RX_PAUSE))
802 lc->requested_fc |= PAUSE_RX;
804 lc->requested_fc &= ~PAUSE_RX;
806 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
807 (fc_conf->mode & RTE_FC_TX_PAUSE))
808 lc->requested_fc |= PAUSE_TX;
810 lc->requested_fc &= ~PAUSE_TX;
812 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
817 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
819 static const uint32_t ptypes[] = {
825 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
830 /* Update RSS hash configuration
832 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
833 struct rte_eth_rss_conf *rss_conf)
835 struct port_info *pi = dev->data->dev_private;
836 struct adapter *adapter = pi->adapter;
839 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
843 pi->rss_hf = rss_conf->rss_hf;
845 if (rss_conf->rss_key) {
846 u32 key[10], mod_key[10];
849 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
851 for (i = 9, j = 0; i >= 0; i--, j++)
852 mod_key[j] = cpu_to_be32(key[i]);
854 t4_write_rss_key(adapter, mod_key, -1);
860 /* Get RSS hash configuration
862 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
863 struct rte_eth_rss_conf *rss_conf)
865 struct port_info *pi = dev->data->dev_private;
866 struct adapter *adapter = pi->adapter;
871 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
877 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
878 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
879 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
880 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
883 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
884 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
886 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
887 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
888 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
889 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
892 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
893 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
895 rss_conf->rss_hf = rss_hf;
897 if (rss_conf->rss_key) {
898 u32 key[10], mod_key[10];
901 t4_read_rss_key(adapter, key);
903 for (i = 9, j = 0; i >= 0; i--, j++)
904 mod_key[j] = be32_to_cpu(key[i]);
906 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
912 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
919 * eeprom_ptov - translate a physical EEPROM address to virtual
920 * @phys_addr: the physical EEPROM address
921 * @fn: the PCI function number
922 * @sz: size of function-specific area
924 * Translate a physical EEPROM address to virtual. The first 1K is
925 * accessed through virtual addresses starting at 31K, the rest is
926 * accessed through virtual addresses starting at 0.
928 * The mapping is as follows:
929 * [0..1K) -> [31K..32K)
930 * [1K..1K+A) -> [31K-A..31K)
931 * [1K+A..ES) -> [0..ES-A-1K)
933 * where A = @fn * @sz, and ES = EEPROM size.
935 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
938 if (phys_addr < 1024)
939 return phys_addr + (31 << 10);
940 if (phys_addr < 1024 + fn)
941 return fn + phys_addr - 1024;
942 if (phys_addr < EEPROMSIZE)
943 return phys_addr - 1024 - fn;
944 if (phys_addr < EEPROMVSIZE)
945 return phys_addr - 1024;
949 /* The next two routines implement eeprom read/write from physical addresses.
951 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
953 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
956 vaddr = t4_seeprom_read(adap, vaddr, v);
957 return vaddr < 0 ? vaddr : 0;
960 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
962 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
965 vaddr = t4_seeprom_write(adap, vaddr, v);
966 return vaddr < 0 ? vaddr : 0;
969 #define EEPROM_MAGIC 0x38E2F10C
971 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
972 struct rte_dev_eeprom_info *e)
974 struct port_info *pi = dev->data->dev_private;
975 struct adapter *adapter = pi->adapter;
977 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
982 e->magic = EEPROM_MAGIC;
983 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
984 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
987 rte_memcpy(e->data, buf + e->offset, e->length);
992 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
993 struct rte_dev_eeprom_info *eeprom)
995 struct port_info *pi = dev->data->dev_private;
996 struct adapter *adapter = pi->adapter;
999 u32 aligned_offset, aligned_len, *p;
1001 if (eeprom->magic != EEPROM_MAGIC)
1004 aligned_offset = eeprom->offset & ~3;
1005 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1007 if (adapter->pf > 0) {
1008 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1010 if (aligned_offset < start ||
1011 aligned_offset + aligned_len > start + EEPROMPFSIZE)
1015 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1016 /* RMW possibly needed for first or last words.
1018 buf = rte_zmalloc(NULL, aligned_len, 0);
1021 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1022 if (!err && aligned_len > 4)
1023 err = eeprom_rd_phys(adapter,
1024 aligned_offset + aligned_len - 4,
1025 (u32 *)&buf[aligned_len - 4]);
1028 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1034 err = t4_seeprom_wp(adapter, false);
1038 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1039 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1040 aligned_offset += 4;
1044 err = t4_seeprom_wp(adapter, true);
1046 if (buf != eeprom->data)
1051 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1053 struct port_info *pi = eth_dev->data->dev_private;
1054 struct adapter *adapter = pi->adapter;
1056 return t4_get_regs_len(adapter) / sizeof(uint32_t);
1059 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1060 struct rte_dev_reg_info *regs)
1062 struct port_info *pi = eth_dev->data->dev_private;
1063 struct adapter *adapter = pi->adapter;
1065 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1066 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1069 if (regs->data == NULL) {
1070 regs->length = cxgbe_get_regs_len(eth_dev);
1071 regs->width = sizeof(uint32_t);
1076 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1081 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1083 struct port_info *pi = dev->data->dev_private;
1086 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1088 dev_err(adapter, "failed to set mac addr; err = %d\n",
1092 pi->xact_addr_filt = ret;
1096 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1097 .dev_start = cxgbe_dev_start,
1098 .dev_stop = cxgbe_dev_stop,
1099 .dev_close = cxgbe_dev_close,
1100 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1101 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1102 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1103 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1104 .dev_configure = cxgbe_dev_configure,
1105 .dev_infos_get = cxgbe_dev_info_get,
1106 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1107 .link_update = cxgbe_dev_link_update,
1108 .dev_set_link_up = cxgbe_dev_set_link_up,
1109 .dev_set_link_down = cxgbe_dev_set_link_down,
1110 .mtu_set = cxgbe_dev_mtu_set,
1111 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1112 .tx_queue_start = cxgbe_dev_tx_queue_start,
1113 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1114 .tx_queue_release = cxgbe_dev_tx_queue_release,
1115 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1116 .rx_queue_start = cxgbe_dev_rx_queue_start,
1117 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1118 .rx_queue_release = cxgbe_dev_rx_queue_release,
1119 .filter_ctrl = cxgbe_dev_filter_ctrl,
1120 .stats_get = cxgbe_dev_stats_get,
1121 .stats_reset = cxgbe_dev_stats_reset,
1122 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1123 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1124 .get_eeprom_length = cxgbe_get_eeprom_length,
1125 .get_eeprom = cxgbe_get_eeprom,
1126 .set_eeprom = cxgbe_set_eeprom,
1127 .get_reg = cxgbe_get_regs,
1128 .rss_hash_update = cxgbe_dev_rss_hash_update,
1129 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1130 .mac_addr_set = cxgbe_mac_addr_set,
1135 * It returns 0 on success.
1137 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1139 struct rte_pci_device *pci_dev;
1140 struct port_info *pi = eth_dev->data->dev_private;
1141 struct adapter *adapter = NULL;
1142 char name[RTE_ETH_NAME_MAX_LEN];
1147 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1148 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1149 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1150 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1152 /* for secondary processes, we attach to ethdevs allocated by primary
1153 * and do minimal initialization.
1155 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1158 for (i = 1; i < MAX_NPORTS; i++) {
1159 struct rte_eth_dev *rest_eth_dev;
1160 char namei[RTE_ETH_NAME_MAX_LEN];
1162 snprintf(namei, sizeof(namei), "%s_%d",
1163 pci_dev->device.name, i);
1164 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1166 rest_eth_dev->device = &pci_dev->device;
1167 rest_eth_dev->dev_ops =
1169 rest_eth_dev->rx_pkt_burst =
1170 eth_dev->rx_pkt_burst;
1171 rest_eth_dev->tx_pkt_burst =
1172 eth_dev->tx_pkt_burst;
1173 rte_eth_dev_probing_finish(rest_eth_dev);
1179 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1180 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1184 adapter->use_unpacked_mode = 1;
1185 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1186 if (!adapter->regs) {
1187 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1189 goto out_free_adapter;
1191 adapter->pdev = pci_dev;
1192 adapter->eth_dev = eth_dev;
1193 pi->adapter = adapter;
1195 cxgbe_process_devargs(adapter);
1197 err = cxgbe_probe(adapter);
1199 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1201 goto out_free_adapter;
1211 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1213 struct port_info *pi = eth_dev->data->dev_private;
1214 struct adapter *adap = pi->adapter;
1216 /* Free up other ports and all resources */
1221 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1222 struct rte_pci_device *pci_dev)
1224 return rte_eth_dev_pci_generic_probe(pci_dev,
1225 sizeof(struct port_info), eth_cxgbe_dev_init);
1228 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1230 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1233 static struct rte_pci_driver rte_cxgbe_pmd = {
1234 .id_table = cxgb4_pci_tbl,
1235 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1236 .probe = eth_cxgbe_pci_probe,
1237 .remove = eth_cxgbe_pci_remove,
1240 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1241 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1242 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1243 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1244 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "
1245 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> ");
1247 RTE_INIT(cxgbe_init_log)
1249 cxgbe_logtype = rte_log_register("pmd.net.cxgbe");
1250 if (cxgbe_logtype >= 0)
1251 rte_log_set_level(cxgbe_logtype, RTE_LOG_NOTICE);
1252 cxgbe_mbox_logtype = rte_log_register("pmd.net.cxgbe.mbox");
1253 if (cxgbe_mbox_logtype >= 0)
1254 rte_log_set_level(cxgbe_mbox_logtype, RTE_LOG_NOTICE);