1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
39 #include "cxgbe_flow.h"
42 * Macros needed to support the PCI Device ID Table ...
44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
45 static const struct rte_pci_id cxgb4_pci_tbl[] = {
46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
48 #define PCI_VENDOR_ID_CHELSIO 0x1425
50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
58 *... and the PCI ID Table itself ...
60 #include "t4_pci_id_tbl.h"
62 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
63 DEV_TX_OFFLOAD_IPV4_CKSUM |\
64 DEV_TX_OFFLOAD_UDP_CKSUM |\
65 DEV_TX_OFFLOAD_TCP_CKSUM |\
66 DEV_TX_OFFLOAD_TCP_TSO)
68 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
69 DEV_RX_OFFLOAD_CRC_STRIP |\
70 DEV_RX_OFFLOAD_IPV4_CKSUM |\
71 DEV_RX_OFFLOAD_JUMBO_FRAME |\
72 DEV_RX_OFFLOAD_UDP_CKSUM |\
73 DEV_RX_OFFLOAD_TCP_CKSUM)
75 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
78 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
79 uint16_t pkts_sent, pkts_remain;
80 uint16_t total_sent = 0;
83 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
84 __func__, txq, tx_pkts, nb_pkts);
86 t4_os_lock(&txq->txq_lock);
87 /* free up desc from already completed tx */
88 reclaim_completed_tx(&txq->q);
89 while (total_sent < nb_pkts) {
90 pkts_remain = nb_pkts - total_sent;
92 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
93 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
100 total_sent += pkts_sent;
101 /* reclaim as much as possible */
102 reclaim_completed_tx(&txq->q);
105 t4_os_unlock(&txq->txq_lock);
109 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
112 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
113 unsigned int work_done;
115 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
116 __func__, rxq->rspq.cntxt_id, nb_pkts);
118 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
119 dev_err(adapter, "error in cxgbe poll\n");
121 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
125 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
126 struct rte_eth_dev_info *device_info)
128 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
129 struct adapter *adapter = pi->adapter;
130 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
132 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
133 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
134 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
138 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
139 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
140 device_info->max_rx_queues = max_queues;
141 device_info->max_tx_queues = max_queues;
142 device_info->max_mac_addrs = 1;
143 /* XXX: For now we support one MAC/port */
144 device_info->max_vfs = adapter->params.arch.vfcount;
145 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
147 device_info->rx_queue_offload_capa = 0UL;
148 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
150 device_info->tx_queue_offload_capa = 0UL;
151 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
153 device_info->reta_size = pi->rss_size;
154 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
155 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
157 device_info->rx_desc_lim = cxgbe_desc_lim;
158 device_info->tx_desc_lim = cxgbe_desc_lim;
159 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
162 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
164 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
165 struct adapter *adapter = pi->adapter;
167 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
168 1, -1, 1, -1, false);
171 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
173 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
174 struct adapter *adapter = pi->adapter;
176 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
177 0, -1, 1, -1, false);
180 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
182 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
183 struct adapter *adapter = pi->adapter;
185 /* TODO: address filters ?? */
187 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
188 -1, 1, 1, -1, false);
191 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
193 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
194 struct adapter *adapter = pi->adapter;
196 /* TODO: address filters ?? */
198 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
199 -1, 0, 1, -1, false);
202 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
203 int wait_to_complete)
205 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
206 struct adapter *adapter = pi->adapter;
207 struct sge *s = &adapter->sge;
208 struct rte_eth_link new_link = { 0 };
209 unsigned int i, work_done, budget = 32;
210 u8 old_link = pi->link_cfg.link_ok;
212 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
213 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
215 /* Exit if link status changed or always forced up */
216 if (pi->link_cfg.link_ok != old_link || force_linkup(adapter))
219 if (!wait_to_complete)
222 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
225 new_link.link_status = force_linkup(adapter) ?
226 ETH_LINK_UP : pi->link_cfg.link_ok;
227 new_link.link_autoneg = pi->link_cfg.autoneg;
228 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
229 new_link.link_speed = pi->link_cfg.speed;
231 return rte_eth_linkstatus_set(eth_dev, &new_link);
235 * Set device link up.
237 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
239 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
240 struct adapter *adapter = pi->adapter;
241 unsigned int work_done, budget = 32;
242 struct sge *s = &adapter->sge;
245 /* Flush all link events */
246 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
248 /* If link already up, nothing to do */
249 if (pi->link_cfg.link_ok)
252 ret = cxgbe_set_link_status(pi, true);
256 cxgbe_dev_link_update(dev, 1);
261 * Set device link down.
263 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
265 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
266 struct adapter *adapter = pi->adapter;
267 unsigned int work_done, budget = 32;
268 struct sge *s = &adapter->sge;
271 /* Flush all link events */
272 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
274 /* If link already down, nothing to do */
275 if (!pi->link_cfg.link_ok)
278 ret = cxgbe_set_link_status(pi, false);
282 cxgbe_dev_link_update(dev, 0);
286 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
288 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
289 struct adapter *adapter = pi->adapter;
290 struct rte_eth_dev_info dev_info;
292 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
294 cxgbe_dev_info_get(eth_dev, &dev_info);
296 /* Must accommodate at least ETHER_MIN_MTU */
297 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
300 /* set to jumbo mode if needed */
301 if (new_mtu > ETHER_MAX_LEN)
302 eth_dev->data->dev_conf.rxmode.offloads |=
303 DEV_RX_OFFLOAD_JUMBO_FRAME;
305 eth_dev->data->dev_conf.rxmode.offloads &=
306 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
308 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
311 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
319 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
321 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
322 struct adapter *adapter = pi->adapter;
326 if (!(adapter->flags & FULL_INIT_DONE))
332 * We clear queues only if both tx and rx path of the port
335 t4_sge_eth_clear_queues(pi);
339 * It returns 0 on success.
341 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
343 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
344 struct adapter *adapter = pi->adapter;
350 * If we don't have a connection to the firmware there's nothing we
353 if (!(adapter->flags & FW_OK)) {
358 if (!(adapter->flags & FULL_INIT_DONE)) {
359 err = cxgbe_up(adapter);
364 cxgbe_enable_rx_queues(pi);
370 for (i = 0; i < pi->n_tx_qsets; i++) {
371 err = cxgbe_dev_tx_queue_start(eth_dev, i);
376 for (i = 0; i < pi->n_rx_qsets; i++) {
377 err = cxgbe_dev_rx_queue_start(eth_dev, i);
382 err = link_start(pi);
391 * Stop device: disable rx and tx functions to allow for reconfiguring.
393 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
395 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
396 struct adapter *adapter = pi->adapter;
400 if (!(adapter->flags & FULL_INIT_DONE))
406 * We clear queues only if both tx and rx path of the port
409 t4_sge_eth_clear_queues(pi);
412 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
414 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
415 struct adapter *adapter = pi->adapter;
416 uint64_t configured_offloads;
420 configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
422 /* KEEP_CRC offload flag is not supported by PMD
423 * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
425 if (rte_eth_dev_must_keep_crc(configured_offloads)) {
426 dev_info(adapter, "can't disable hw crc strip\n");
427 eth_dev->data->dev_conf.rxmode.offloads |=
428 DEV_RX_OFFLOAD_CRC_STRIP;
431 if (!(adapter->flags & FW_QUEUE_BOUND)) {
432 err = setup_sge_fwevtq(adapter);
435 adapter->flags |= FW_QUEUE_BOUND;
436 if (is_pf4(adapter)) {
437 err = setup_sge_ctrl_txq(adapter);
443 err = cfg_queue_count(eth_dev);
450 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
453 struct sge_eth_txq *txq = (struct sge_eth_txq *)
454 (eth_dev->data->tx_queues[tx_queue_id]);
456 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
458 ret = t4_sge_eth_txq_start(txq);
460 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
465 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
468 struct sge_eth_txq *txq = (struct sge_eth_txq *)
469 (eth_dev->data->tx_queues[tx_queue_id]);
471 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
473 ret = t4_sge_eth_txq_stop(txq);
475 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
480 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
481 uint16_t queue_idx, uint16_t nb_desc,
482 unsigned int socket_id,
483 const struct rte_eth_txconf *tx_conf __rte_unused)
485 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
486 struct adapter *adapter = pi->adapter;
487 struct sge *s = &adapter->sge;
488 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
490 unsigned int temp_nb_desc;
492 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
493 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
494 socket_id, pi->first_qset);
496 /* Free up the existing queue */
497 if (eth_dev->data->tx_queues[queue_idx]) {
498 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
499 eth_dev->data->tx_queues[queue_idx] = NULL;
502 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
506 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
508 temp_nb_desc = nb_desc;
509 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
510 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
511 __func__, CXGBE_MIN_RING_DESC_SIZE,
512 CXGBE_DEFAULT_TX_DESC_SIZE);
513 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
514 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
515 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
516 __func__, CXGBE_MIN_RING_DESC_SIZE,
517 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
521 txq->q.size = temp_nb_desc;
523 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
524 s->fw_evtq.cntxt_id, socket_id);
526 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
527 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
531 void cxgbe_dev_tx_queue_release(void *q)
533 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
536 struct port_info *pi = (struct port_info *)
537 (txq->eth_dev->data->dev_private);
538 struct adapter *adap = pi->adapter;
540 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
541 __func__, pi->port_id, txq->q.cntxt_id);
543 t4_sge_eth_txq_release(adap, txq);
547 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
550 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
551 struct adapter *adap = pi->adapter;
554 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
555 __func__, pi->port_id, rx_queue_id);
557 q = eth_dev->data->rx_queues[rx_queue_id];
559 ret = t4_sge_eth_rxq_start(adap, q);
561 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
566 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
569 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
570 struct adapter *adap = pi->adapter;
573 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
574 __func__, pi->port_id, rx_queue_id);
576 q = eth_dev->data->rx_queues[rx_queue_id];
577 ret = t4_sge_eth_rxq_stop(adap, q);
579 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
584 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
585 uint16_t queue_idx, uint16_t nb_desc,
586 unsigned int socket_id,
587 const struct rte_eth_rxconf *rx_conf __rte_unused,
588 struct rte_mempool *mp)
590 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
591 struct adapter *adapter = pi->adapter;
592 struct sge *s = &adapter->sge;
593 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
596 unsigned int temp_nb_desc;
597 struct rte_eth_dev_info dev_info;
598 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
600 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
601 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
604 cxgbe_dev_info_get(eth_dev, &dev_info);
606 /* Must accommodate at least ETHER_MIN_MTU */
607 if ((pkt_len < dev_info.min_rx_bufsize) ||
608 (pkt_len > dev_info.max_rx_pktlen)) {
609 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
610 __func__, dev_info.min_rx_bufsize,
611 dev_info.max_rx_pktlen);
615 /* Free up the existing queue */
616 if (eth_dev->data->rx_queues[queue_idx]) {
617 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
618 eth_dev->data->rx_queues[queue_idx] = NULL;
621 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
625 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
627 temp_nb_desc = nb_desc;
628 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
629 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
630 __func__, CXGBE_MIN_RING_DESC_SIZE,
631 CXGBE_DEFAULT_RX_DESC_SIZE);
632 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
633 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
634 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
635 __func__, CXGBE_MIN_RING_DESC_SIZE,
636 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
640 rxq->rspq.size = temp_nb_desc;
641 if ((&rxq->fl) != NULL)
642 rxq->fl.size = temp_nb_desc;
644 /* Set to jumbo mode if necessary */
645 if (pkt_len > ETHER_MAX_LEN)
646 eth_dev->data->dev_conf.rxmode.offloads |=
647 DEV_RX_OFFLOAD_JUMBO_FRAME;
649 eth_dev->data->dev_conf.rxmode.offloads &=
650 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
652 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
653 &rxq->fl, t4_ethrx_handler,
655 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
656 queue_idx, socket_id);
658 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
659 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
664 void cxgbe_dev_rx_queue_release(void *q)
666 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
667 struct sge_rspq *rq = &rxq->rspq;
670 struct port_info *pi = (struct port_info *)
671 (rq->eth_dev->data->dev_private);
672 struct adapter *adap = pi->adapter;
674 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
675 __func__, pi->port_id, rxq->rspq.cntxt_id);
677 t4_sge_eth_rxq_release(adap, rxq);
682 * Get port statistics.
684 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
685 struct rte_eth_stats *eth_stats)
687 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
688 struct adapter *adapter = pi->adapter;
689 struct sge *s = &adapter->sge;
690 struct port_stats ps;
693 cxgbe_stats_get(pi, &ps);
696 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
697 ps.rx_ovflow2 + ps.rx_ovflow3 +
698 ps.rx_trunc0 + ps.rx_trunc1 +
699 ps.rx_trunc2 + ps.rx_trunc3;
700 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
701 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
705 eth_stats->opackets = ps.tx_frames;
706 eth_stats->obytes = ps.tx_octets;
707 eth_stats->oerrors = ps.tx_error_frames;
709 for (i = 0; i < pi->n_rx_qsets; i++) {
710 struct sge_eth_rxq *rxq =
711 &s->ethrxq[pi->first_qset + i];
713 eth_stats->q_ipackets[i] = rxq->stats.pkts;
714 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
715 eth_stats->ipackets += eth_stats->q_ipackets[i];
716 eth_stats->ibytes += eth_stats->q_ibytes[i];
719 for (i = 0; i < pi->n_tx_qsets; i++) {
720 struct sge_eth_txq *txq =
721 &s->ethtxq[pi->first_qset + i];
723 eth_stats->q_opackets[i] = txq->stats.pkts;
724 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
725 eth_stats->q_errors[i] = txq->stats.mapping_err;
731 * Reset port statistics.
733 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
735 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
736 struct adapter *adapter = pi->adapter;
737 struct sge *s = &adapter->sge;
740 cxgbe_stats_reset(pi);
741 for (i = 0; i < pi->n_rx_qsets; i++) {
742 struct sge_eth_rxq *rxq =
743 &s->ethrxq[pi->first_qset + i];
746 rxq->stats.rx_bytes = 0;
748 for (i = 0; i < pi->n_tx_qsets; i++) {
749 struct sge_eth_txq *txq =
750 &s->ethtxq[pi->first_qset + i];
753 txq->stats.tx_bytes = 0;
754 txq->stats.mapping_err = 0;
758 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
759 struct rte_eth_fc_conf *fc_conf)
761 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
762 struct link_config *lc = &pi->link_cfg;
763 int rx_pause, tx_pause;
765 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
766 rx_pause = lc->fc & PAUSE_RX;
767 tx_pause = lc->fc & PAUSE_TX;
769 if (rx_pause && tx_pause)
770 fc_conf->mode = RTE_FC_FULL;
772 fc_conf->mode = RTE_FC_RX_PAUSE;
774 fc_conf->mode = RTE_FC_TX_PAUSE;
776 fc_conf->mode = RTE_FC_NONE;
780 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
781 struct rte_eth_fc_conf *fc_conf)
783 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
784 struct adapter *adapter = pi->adapter;
785 struct link_config *lc = &pi->link_cfg;
787 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
788 if (fc_conf->autoneg)
789 lc->requested_fc |= PAUSE_AUTONEG;
791 lc->requested_fc &= ~PAUSE_AUTONEG;
794 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
795 (fc_conf->mode & RTE_FC_RX_PAUSE))
796 lc->requested_fc |= PAUSE_RX;
798 lc->requested_fc &= ~PAUSE_RX;
800 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
801 (fc_conf->mode & RTE_FC_TX_PAUSE))
802 lc->requested_fc |= PAUSE_TX;
804 lc->requested_fc &= ~PAUSE_TX;
806 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
811 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
813 static const uint32_t ptypes[] = {
819 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
824 /* Update RSS hash configuration
826 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
827 struct rte_eth_rss_conf *rss_conf)
829 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
830 struct adapter *adapter = pi->adapter;
833 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
837 pi->rss_hf = rss_conf->rss_hf;
839 if (rss_conf->rss_key) {
840 u32 key[10], mod_key[10];
843 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
845 for (i = 9, j = 0; i >= 0; i--, j++)
846 mod_key[j] = cpu_to_be32(key[i]);
848 t4_write_rss_key(adapter, mod_key, -1);
854 /* Get RSS hash configuration
856 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
857 struct rte_eth_rss_conf *rss_conf)
859 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
860 struct adapter *adapter = pi->adapter;
865 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
871 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
872 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
873 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
874 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
877 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
878 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
880 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
881 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
882 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
883 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
886 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
887 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
889 rss_conf->rss_hf = rss_hf;
891 if (rss_conf->rss_key) {
892 u32 key[10], mod_key[10];
895 t4_read_rss_key(adapter, key);
897 for (i = 9, j = 0; i >= 0; i--, j++)
898 mod_key[j] = be32_to_cpu(key[i]);
900 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
906 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
913 * eeprom_ptov - translate a physical EEPROM address to virtual
914 * @phys_addr: the physical EEPROM address
915 * @fn: the PCI function number
916 * @sz: size of function-specific area
918 * Translate a physical EEPROM address to virtual. The first 1K is
919 * accessed through virtual addresses starting at 31K, the rest is
920 * accessed through virtual addresses starting at 0.
922 * The mapping is as follows:
923 * [0..1K) -> [31K..32K)
924 * [1K..1K+A) -> [31K-A..31K)
925 * [1K+A..ES) -> [0..ES-A-1K)
927 * where A = @fn * @sz, and ES = EEPROM size.
929 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
932 if (phys_addr < 1024)
933 return phys_addr + (31 << 10);
934 if (phys_addr < 1024 + fn)
935 return fn + phys_addr - 1024;
936 if (phys_addr < EEPROMSIZE)
937 return phys_addr - 1024 - fn;
938 if (phys_addr < EEPROMVSIZE)
939 return phys_addr - 1024;
943 /* The next two routines implement eeprom read/write from physical addresses.
945 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
947 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
950 vaddr = t4_seeprom_read(adap, vaddr, v);
951 return vaddr < 0 ? vaddr : 0;
954 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
956 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
959 vaddr = t4_seeprom_write(adap, vaddr, v);
960 return vaddr < 0 ? vaddr : 0;
963 #define EEPROM_MAGIC 0x38E2F10C
965 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
966 struct rte_dev_eeprom_info *e)
968 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
969 struct adapter *adapter = pi->adapter;
971 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
976 e->magic = EEPROM_MAGIC;
977 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
978 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
981 rte_memcpy(e->data, buf + e->offset, e->length);
986 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
987 struct rte_dev_eeprom_info *eeprom)
989 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
990 struct adapter *adapter = pi->adapter;
993 u32 aligned_offset, aligned_len, *p;
995 if (eeprom->magic != EEPROM_MAGIC)
998 aligned_offset = eeprom->offset & ~3;
999 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1001 if (adapter->pf > 0) {
1002 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1004 if (aligned_offset < start ||
1005 aligned_offset + aligned_len > start + EEPROMPFSIZE)
1009 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1010 /* RMW possibly needed for first or last words.
1012 buf = rte_zmalloc(NULL, aligned_len, 0);
1015 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1016 if (!err && aligned_len > 4)
1017 err = eeprom_rd_phys(adapter,
1018 aligned_offset + aligned_len - 4,
1019 (u32 *)&buf[aligned_len - 4]);
1022 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1028 err = t4_seeprom_wp(adapter, false);
1032 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1033 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1034 aligned_offset += 4;
1038 err = t4_seeprom_wp(adapter, true);
1040 if (buf != eeprom->data)
1045 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1047 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1048 struct adapter *adapter = pi->adapter;
1050 return t4_get_regs_len(adapter) / sizeof(uint32_t);
1053 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1054 struct rte_dev_reg_info *regs)
1056 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1057 struct adapter *adapter = pi->adapter;
1059 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1060 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1063 if (regs->data == NULL) {
1064 regs->length = cxgbe_get_regs_len(eth_dev);
1065 regs->width = sizeof(uint32_t);
1070 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1075 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1077 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1078 struct adapter *adapter = pi->adapter;
1081 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1082 pi->xact_addr_filt, (u8 *)addr, true, true);
1084 dev_err(adapter, "failed to set mac addr; err = %d\n",
1088 pi->xact_addr_filt = ret;
1092 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1093 .dev_start = cxgbe_dev_start,
1094 .dev_stop = cxgbe_dev_stop,
1095 .dev_close = cxgbe_dev_close,
1096 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1097 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1098 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1099 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1100 .dev_configure = cxgbe_dev_configure,
1101 .dev_infos_get = cxgbe_dev_info_get,
1102 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1103 .link_update = cxgbe_dev_link_update,
1104 .dev_set_link_up = cxgbe_dev_set_link_up,
1105 .dev_set_link_down = cxgbe_dev_set_link_down,
1106 .mtu_set = cxgbe_dev_mtu_set,
1107 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1108 .tx_queue_start = cxgbe_dev_tx_queue_start,
1109 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1110 .tx_queue_release = cxgbe_dev_tx_queue_release,
1111 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1112 .rx_queue_start = cxgbe_dev_rx_queue_start,
1113 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1114 .rx_queue_release = cxgbe_dev_rx_queue_release,
1115 .filter_ctrl = cxgbe_dev_filter_ctrl,
1116 .stats_get = cxgbe_dev_stats_get,
1117 .stats_reset = cxgbe_dev_stats_reset,
1118 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1119 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1120 .get_eeprom_length = cxgbe_get_eeprom_length,
1121 .get_eeprom = cxgbe_get_eeprom,
1122 .set_eeprom = cxgbe_set_eeprom,
1123 .get_reg = cxgbe_get_regs,
1124 .rss_hash_update = cxgbe_dev_rss_hash_update,
1125 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1126 .mac_addr_set = cxgbe_mac_addr_set,
1131 * It returns 0 on success.
1133 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1135 struct rte_pci_device *pci_dev;
1136 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1137 struct adapter *adapter = NULL;
1138 char name[RTE_ETH_NAME_MAX_LEN];
1143 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1144 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1145 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1146 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1148 /* for secondary processes, we attach to ethdevs allocated by primary
1149 * and do minimal initialization.
1151 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154 for (i = 1; i < MAX_NPORTS; i++) {
1155 struct rte_eth_dev *rest_eth_dev;
1156 char namei[RTE_ETH_NAME_MAX_LEN];
1158 snprintf(namei, sizeof(namei), "%s_%d",
1159 pci_dev->device.name, i);
1160 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1162 rest_eth_dev->device = &pci_dev->device;
1163 rest_eth_dev->dev_ops =
1165 rest_eth_dev->rx_pkt_burst =
1166 eth_dev->rx_pkt_burst;
1167 rest_eth_dev->tx_pkt_burst =
1168 eth_dev->tx_pkt_burst;
1169 rte_eth_dev_probing_finish(rest_eth_dev);
1175 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1176 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1180 adapter->use_unpacked_mode = 1;
1181 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1182 if (!adapter->regs) {
1183 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1185 goto out_free_adapter;
1187 adapter->pdev = pci_dev;
1188 adapter->eth_dev = eth_dev;
1189 pi->adapter = adapter;
1191 err = cxgbe_probe(adapter);
1193 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1195 goto out_free_adapter;
1205 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1207 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1208 struct adapter *adap = pi->adapter;
1210 /* Free up other ports and all resources */
1215 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1216 struct rte_pci_device *pci_dev)
1218 return rte_eth_dev_pci_generic_probe(pci_dev,
1219 sizeof(struct port_info), eth_cxgbe_dev_init);
1222 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1224 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1227 static struct rte_pci_driver rte_cxgbe_pmd = {
1228 .id_table = cxgb4_pci_tbl,
1229 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1230 .probe = eth_cxgbe_pci_probe,
1231 .remove = eth_cxgbe_pci_remove,
1234 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1235 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1236 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1237 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1238 CXGBE_DEVARG_KEEP_OVLAN "=<0|1> "
1239 CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> ");