1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
41 * Macros needed to support the PCI Device ID Table ...
43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
44 static const struct rte_pci_id cxgb4_pci_tbl[] = {
45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
47 #define PCI_VENDOR_ID_CHELSIO 0x1425
49 #define CH_PCI_ID_TABLE_ENTRY(devid) \
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
57 *... and the PCI ID Table itself ...
59 #include "t4_pci_id_tbl.h"
61 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
62 DEV_TX_OFFLOAD_IPV4_CKSUM |\
63 DEV_TX_OFFLOAD_UDP_CKSUM |\
64 DEV_TX_OFFLOAD_TCP_CKSUM |\
65 DEV_TX_OFFLOAD_TCP_TSO)
67 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
68 DEV_RX_OFFLOAD_CRC_STRIP |\
69 DEV_RX_OFFLOAD_IPV4_CKSUM |\
70 DEV_RX_OFFLOAD_JUMBO_FRAME |\
71 DEV_RX_OFFLOAD_UDP_CKSUM |\
72 DEV_RX_OFFLOAD_TCP_CKSUM)
74 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
77 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
78 uint16_t pkts_sent, pkts_remain;
79 uint16_t total_sent = 0;
82 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
83 __func__, txq, tx_pkts, nb_pkts);
85 t4_os_lock(&txq->txq_lock);
86 /* free up desc from already completed tx */
87 reclaim_completed_tx(&txq->q);
88 while (total_sent < nb_pkts) {
89 pkts_remain = nb_pkts - total_sent;
91 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
92 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
99 total_sent += pkts_sent;
100 /* reclaim as much as possible */
101 reclaim_completed_tx(&txq->q);
104 t4_os_unlock(&txq->txq_lock);
108 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
111 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
112 unsigned int work_done;
114 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
115 __func__, rxq->rspq.cntxt_id, nb_pkts);
117 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
118 dev_err(adapter, "error in cxgbe poll\n");
120 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
124 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
125 struct rte_eth_dev_info *device_info)
127 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
128 struct adapter *adapter = pi->adapter;
129 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
131 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
132 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
133 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
137 device_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
139 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
140 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
141 device_info->max_rx_queues = max_queues;
142 device_info->max_tx_queues = max_queues;
143 device_info->max_mac_addrs = 1;
144 /* XXX: For now we support one MAC/port */
145 device_info->max_vfs = adapter->params.arch.vfcount;
146 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
148 device_info->rx_queue_offload_capa = 0UL;
149 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
151 device_info->tx_queue_offload_capa = 0UL;
152 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
154 device_info->reta_size = pi->rss_size;
155 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
156 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
158 device_info->rx_desc_lim = cxgbe_desc_lim;
159 device_info->tx_desc_lim = cxgbe_desc_lim;
160 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
163 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
165 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
166 struct adapter *adapter = pi->adapter;
168 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
169 1, -1, 1, -1, false);
172 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
174 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
175 struct adapter *adapter = pi->adapter;
177 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
178 0, -1, 1, -1, false);
181 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
183 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
184 struct adapter *adapter = pi->adapter;
186 /* TODO: address filters ?? */
188 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
189 -1, 1, 1, -1, false);
192 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
194 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
195 struct adapter *adapter = pi->adapter;
197 /* TODO: address filters ?? */
199 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
200 -1, 0, 1, -1, false);
203 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
204 __rte_unused int wait_to_complete)
206 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
207 struct adapter *adapter = pi->adapter;
208 struct sge *s = &adapter->sge;
209 struct rte_eth_link *old_link = ð_dev->data->dev_link;
210 unsigned int work_done, budget = 4;
212 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
213 if (old_link->link_status == pi->link_cfg.link_ok)
214 return -1; /* link not changed */
216 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
217 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
218 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
220 /* link has changed */
224 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
226 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
227 struct adapter *adapter = pi->adapter;
228 struct rte_eth_dev_info dev_info;
230 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
232 cxgbe_dev_info_get(eth_dev, &dev_info);
234 /* Must accommodate at least ETHER_MIN_MTU */
235 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
238 /* set to jumbo mode if needed */
239 if (new_mtu > ETHER_MAX_LEN)
240 eth_dev->data->dev_conf.rxmode.offloads |=
241 DEV_RX_OFFLOAD_JUMBO_FRAME;
243 eth_dev->data->dev_conf.rxmode.offloads &=
244 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
246 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
249 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
257 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
259 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
260 struct adapter *adapter = pi->adapter;
265 if (!(adapter->flags & FULL_INIT_DONE))
271 * We clear queues only if both tx and rx path of the port
274 t4_sge_eth_clear_queues(pi);
276 /* See if all ports are down */
277 for_each_port(adapter, i) {
278 pi = adap2pinfo(adapter, i);
280 * Skip first port of the adapter since it will be closed
285 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
288 /* If rest of the ports are stopped, then free up resources */
289 if (dev_down == (adapter->params.nports - 1))
290 cxgbe_close(adapter);
294 * It returns 0 on success.
296 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
298 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
299 struct adapter *adapter = pi->adapter;
305 * If we don't have a connection to the firmware there's nothing we
308 if (!(adapter->flags & FW_OK)) {
313 if (!(adapter->flags & FULL_INIT_DONE)) {
314 err = cxgbe_up(adapter);
319 cxgbe_enable_rx_queues(pi);
325 for (i = 0; i < pi->n_tx_qsets; i++) {
326 err = cxgbe_dev_tx_queue_start(eth_dev, i);
331 for (i = 0; i < pi->n_rx_qsets; i++) {
332 err = cxgbe_dev_rx_queue_start(eth_dev, i);
337 err = link_start(pi);
346 * Stop device: disable rx and tx functions to allow for reconfiguring.
348 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
350 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
351 struct adapter *adapter = pi->adapter;
355 if (!(adapter->flags & FULL_INIT_DONE))
361 * We clear queues only if both tx and rx path of the port
364 t4_sge_eth_clear_queues(pi);
367 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
369 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
370 struct adapter *adapter = pi->adapter;
371 uint64_t unsupported_offloads, configured_offloads;
375 configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
376 if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
377 dev_info(adapter, "can't disable hw crc strip\n");
378 configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
381 unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS;
382 if (unsupported_offloads) {
383 dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. "
384 "Supported:0x%" PRIx64 "\n",
385 unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS);
389 configured_offloads = eth_dev->data->dev_conf.txmode.offloads;
390 unsupported_offloads = configured_offloads & ~CXGBE_TX_OFFLOADS;
391 if (unsupported_offloads) {
392 dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. "
393 "Supported:0x%" PRIx64 "\n",
394 unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS);
398 if (!(adapter->flags & FW_QUEUE_BOUND)) {
399 err = setup_sge_fwevtq(adapter);
402 adapter->flags |= FW_QUEUE_BOUND;
405 err = cfg_queue_count(eth_dev);
412 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
415 struct sge_eth_txq *txq = (struct sge_eth_txq *)
416 (eth_dev->data->tx_queues[tx_queue_id]);
418 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
420 ret = t4_sge_eth_txq_start(txq);
422 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
427 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
430 struct sge_eth_txq *txq = (struct sge_eth_txq *)
431 (eth_dev->data->tx_queues[tx_queue_id]);
433 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
435 ret = t4_sge_eth_txq_stop(txq);
437 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
442 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
443 uint16_t queue_idx, uint16_t nb_desc,
444 unsigned int socket_id,
445 const struct rte_eth_txconf *tx_conf)
447 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
448 struct adapter *adapter = pi->adapter;
449 struct sge *s = &adapter->sge;
450 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
452 unsigned int temp_nb_desc;
453 uint64_t unsupported_offloads;
455 unsupported_offloads = tx_conf->offloads & ~CXGBE_TX_OFFLOADS;
456 if (unsupported_offloads) {
457 dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. "
458 "Supported:0x%" PRIx64 "\n",
459 unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS);
463 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
464 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
465 socket_id, pi->first_qset);
467 /* Free up the existing queue */
468 if (eth_dev->data->tx_queues[queue_idx]) {
469 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
470 eth_dev->data->tx_queues[queue_idx] = NULL;
473 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
477 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
479 temp_nb_desc = nb_desc;
480 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
481 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
482 __func__, CXGBE_MIN_RING_DESC_SIZE,
483 CXGBE_DEFAULT_TX_DESC_SIZE);
484 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
485 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
486 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
487 __func__, CXGBE_MIN_RING_DESC_SIZE,
488 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
492 txq->q.size = temp_nb_desc;
494 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
495 s->fw_evtq.cntxt_id, socket_id);
497 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
498 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
502 void cxgbe_dev_tx_queue_release(void *q)
504 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
507 struct port_info *pi = (struct port_info *)
508 (txq->eth_dev->data->dev_private);
509 struct adapter *adap = pi->adapter;
511 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
512 __func__, pi->port_id, txq->q.cntxt_id);
514 t4_sge_eth_txq_release(adap, txq);
518 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
521 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
522 struct adapter *adap = pi->adapter;
525 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
526 __func__, pi->port_id, rx_queue_id);
528 q = eth_dev->data->rx_queues[rx_queue_id];
530 ret = t4_sge_eth_rxq_start(adap, q);
532 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
537 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
540 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
541 struct adapter *adap = pi->adapter;
544 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
545 __func__, pi->port_id, rx_queue_id);
547 q = eth_dev->data->rx_queues[rx_queue_id];
548 ret = t4_sge_eth_rxq_stop(adap, q);
550 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
555 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
556 uint16_t queue_idx, uint16_t nb_desc,
557 unsigned int socket_id,
558 const struct rte_eth_rxconf *rx_conf,
559 struct rte_mempool *mp)
561 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
562 struct adapter *adapter = pi->adapter;
563 struct sge *s = &adapter->sge;
564 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
567 unsigned int temp_nb_desc;
568 struct rte_eth_dev_info dev_info;
569 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
570 uint64_t unsupported_offloads, configured_offloads;
572 configured_offloads = rx_conf->offloads;
573 if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
574 dev_info(adapter, "can't disable hw crc strip\n");
575 configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
578 unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS;
579 if (unsupported_offloads) {
580 dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. "
581 "Supported:0x%" PRIx64 "\n",
582 unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS);
586 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
587 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
590 cxgbe_dev_info_get(eth_dev, &dev_info);
592 /* Must accommodate at least ETHER_MIN_MTU */
593 if ((pkt_len < dev_info.min_rx_bufsize) ||
594 (pkt_len > dev_info.max_rx_pktlen)) {
595 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
596 __func__, dev_info.min_rx_bufsize,
597 dev_info.max_rx_pktlen);
601 /* Free up the existing queue */
602 if (eth_dev->data->rx_queues[queue_idx]) {
603 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
604 eth_dev->data->rx_queues[queue_idx] = NULL;
607 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
611 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
613 temp_nb_desc = nb_desc;
614 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
615 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
616 __func__, CXGBE_MIN_RING_DESC_SIZE,
617 CXGBE_DEFAULT_RX_DESC_SIZE);
618 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
619 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
620 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
621 __func__, CXGBE_MIN_RING_DESC_SIZE,
622 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
626 rxq->rspq.size = temp_nb_desc;
627 if ((&rxq->fl) != NULL)
628 rxq->fl.size = temp_nb_desc;
630 /* Set to jumbo mode if necessary */
631 if (pkt_len > ETHER_MAX_LEN)
632 eth_dev->data->dev_conf.rxmode.offloads |=
633 DEV_RX_OFFLOAD_JUMBO_FRAME;
635 eth_dev->data->dev_conf.rxmode.offloads &=
636 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
638 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
639 &rxq->fl, t4_ethrx_handler,
641 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
642 queue_idx, socket_id);
644 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
645 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
650 void cxgbe_dev_rx_queue_release(void *q)
652 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
653 struct sge_rspq *rq = &rxq->rspq;
656 struct port_info *pi = (struct port_info *)
657 (rq->eth_dev->data->dev_private);
658 struct adapter *adap = pi->adapter;
660 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
661 __func__, pi->port_id, rxq->rspq.cntxt_id);
663 t4_sge_eth_rxq_release(adap, rxq);
668 * Get port statistics.
670 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
671 struct rte_eth_stats *eth_stats)
673 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
674 struct adapter *adapter = pi->adapter;
675 struct sge *s = &adapter->sge;
676 struct port_stats ps;
679 cxgbe_stats_get(pi, &ps);
682 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
683 ps.rx_ovflow2 + ps.rx_ovflow3 +
684 ps.rx_trunc0 + ps.rx_trunc1 +
685 ps.rx_trunc2 + ps.rx_trunc3;
686 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
687 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
691 eth_stats->opackets = ps.tx_frames;
692 eth_stats->obytes = ps.tx_octets;
693 eth_stats->oerrors = ps.tx_error_frames;
695 for (i = 0; i < pi->n_rx_qsets; i++) {
696 struct sge_eth_rxq *rxq =
697 &s->ethrxq[pi->first_qset + i];
699 eth_stats->q_ipackets[i] = rxq->stats.pkts;
700 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
701 eth_stats->ipackets += eth_stats->q_ipackets[i];
702 eth_stats->ibytes += eth_stats->q_ibytes[i];
705 for (i = 0; i < pi->n_tx_qsets; i++) {
706 struct sge_eth_txq *txq =
707 &s->ethtxq[pi->first_qset + i];
709 eth_stats->q_opackets[i] = txq->stats.pkts;
710 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
711 eth_stats->q_errors[i] = txq->stats.mapping_err;
717 * Reset port statistics.
719 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
721 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
722 struct adapter *adapter = pi->adapter;
723 struct sge *s = &adapter->sge;
726 cxgbe_stats_reset(pi);
727 for (i = 0; i < pi->n_rx_qsets; i++) {
728 struct sge_eth_rxq *rxq =
729 &s->ethrxq[pi->first_qset + i];
732 rxq->stats.rx_bytes = 0;
734 for (i = 0; i < pi->n_tx_qsets; i++) {
735 struct sge_eth_txq *txq =
736 &s->ethtxq[pi->first_qset + i];
739 txq->stats.tx_bytes = 0;
740 txq->stats.mapping_err = 0;
744 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
745 struct rte_eth_fc_conf *fc_conf)
747 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
748 struct link_config *lc = &pi->link_cfg;
749 int rx_pause, tx_pause;
751 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
752 rx_pause = lc->fc & PAUSE_RX;
753 tx_pause = lc->fc & PAUSE_TX;
755 if (rx_pause && tx_pause)
756 fc_conf->mode = RTE_FC_FULL;
758 fc_conf->mode = RTE_FC_RX_PAUSE;
760 fc_conf->mode = RTE_FC_TX_PAUSE;
762 fc_conf->mode = RTE_FC_NONE;
766 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
767 struct rte_eth_fc_conf *fc_conf)
769 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
770 struct adapter *adapter = pi->adapter;
771 struct link_config *lc = &pi->link_cfg;
773 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
774 if (fc_conf->autoneg)
775 lc->requested_fc |= PAUSE_AUTONEG;
777 lc->requested_fc &= ~PAUSE_AUTONEG;
780 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
781 (fc_conf->mode & RTE_FC_RX_PAUSE))
782 lc->requested_fc |= PAUSE_RX;
784 lc->requested_fc &= ~PAUSE_RX;
786 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
787 (fc_conf->mode & RTE_FC_TX_PAUSE))
788 lc->requested_fc |= PAUSE_TX;
790 lc->requested_fc &= ~PAUSE_TX;
792 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
797 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
799 static const uint32_t ptypes[] = {
805 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
810 /* Update RSS hash configuration
812 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
813 struct rte_eth_rss_conf *rss_conf)
815 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
816 struct adapter *adapter = pi->adapter;
819 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
823 pi->rss_hf = rss_conf->rss_hf;
825 if (rss_conf->rss_key) {
826 u32 key[10], mod_key[10];
829 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
831 for (i = 9, j = 0; i >= 0; i--, j++)
832 mod_key[j] = cpu_to_be32(key[i]);
834 t4_write_rss_key(adapter, mod_key, -1);
840 /* Get RSS hash configuration
842 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
843 struct rte_eth_rss_conf *rss_conf)
845 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
846 struct adapter *adapter = pi->adapter;
851 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
857 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
858 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
859 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
860 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
863 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
864 rss_hf |= ETH_RSS_IPV6;
866 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
867 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
868 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
869 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
872 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
873 rss_hf |= ETH_RSS_IPV4;
875 rss_conf->rss_hf = rss_hf;
877 if (rss_conf->rss_key) {
878 u32 key[10], mod_key[10];
881 t4_read_rss_key(adapter, key);
883 for (i = 9, j = 0; i >= 0; i--, j++)
884 mod_key[j] = be32_to_cpu(key[i]);
886 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
892 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
899 * eeprom_ptov - translate a physical EEPROM address to virtual
900 * @phys_addr: the physical EEPROM address
901 * @fn: the PCI function number
902 * @sz: size of function-specific area
904 * Translate a physical EEPROM address to virtual. The first 1K is
905 * accessed through virtual addresses starting at 31K, the rest is
906 * accessed through virtual addresses starting at 0.
908 * The mapping is as follows:
909 * [0..1K) -> [31K..32K)
910 * [1K..1K+A) -> [31K-A..31K)
911 * [1K+A..ES) -> [0..ES-A-1K)
913 * where A = @fn * @sz, and ES = EEPROM size.
915 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
918 if (phys_addr < 1024)
919 return phys_addr + (31 << 10);
920 if (phys_addr < 1024 + fn)
921 return fn + phys_addr - 1024;
922 if (phys_addr < EEPROMSIZE)
923 return phys_addr - 1024 - fn;
924 if (phys_addr < EEPROMVSIZE)
925 return phys_addr - 1024;
929 /* The next two routines implement eeprom read/write from physical addresses.
931 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
933 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
936 vaddr = t4_seeprom_read(adap, vaddr, v);
937 return vaddr < 0 ? vaddr : 0;
940 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
942 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
945 vaddr = t4_seeprom_write(adap, vaddr, v);
946 return vaddr < 0 ? vaddr : 0;
949 #define EEPROM_MAGIC 0x38E2F10C
951 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
952 struct rte_dev_eeprom_info *e)
954 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
955 struct adapter *adapter = pi->adapter;
957 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
962 e->magic = EEPROM_MAGIC;
963 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
964 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
967 rte_memcpy(e->data, buf + e->offset, e->length);
972 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
973 struct rte_dev_eeprom_info *eeprom)
975 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
976 struct adapter *adapter = pi->adapter;
979 u32 aligned_offset, aligned_len, *p;
981 if (eeprom->magic != EEPROM_MAGIC)
984 aligned_offset = eeprom->offset & ~3;
985 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
987 if (adapter->pf > 0) {
988 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
990 if (aligned_offset < start ||
991 aligned_offset + aligned_len > start + EEPROMPFSIZE)
995 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
996 /* RMW possibly needed for first or last words.
998 buf = rte_zmalloc(NULL, aligned_len, 0);
1001 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1002 if (!err && aligned_len > 4)
1003 err = eeprom_rd_phys(adapter,
1004 aligned_offset + aligned_len - 4,
1005 (u32 *)&buf[aligned_len - 4]);
1008 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1014 err = t4_seeprom_wp(adapter, false);
1018 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1019 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1020 aligned_offset += 4;
1024 err = t4_seeprom_wp(adapter, true);
1026 if (buf != eeprom->data)
1031 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1033 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1034 struct adapter *adapter = pi->adapter;
1036 return t4_get_regs_len(adapter) / sizeof(uint32_t);
1039 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1040 struct rte_dev_reg_info *regs)
1042 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1043 struct adapter *adapter = pi->adapter;
1045 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1046 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1049 if (regs->data == NULL) {
1050 regs->length = cxgbe_get_regs_len(eth_dev);
1051 regs->width = sizeof(uint32_t);
1056 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1061 void cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1063 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1064 struct adapter *adapter = pi->adapter;
1067 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1068 pi->xact_addr_filt, (u8 *)addr, true, true);
1070 dev_err(adapter, "failed to set mac addr; err = %d\n",
1074 pi->xact_addr_filt = ret;
1077 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1078 .dev_start = cxgbe_dev_start,
1079 .dev_stop = cxgbe_dev_stop,
1080 .dev_close = cxgbe_dev_close,
1081 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1082 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1083 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1084 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1085 .dev_configure = cxgbe_dev_configure,
1086 .dev_infos_get = cxgbe_dev_info_get,
1087 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1088 .link_update = cxgbe_dev_link_update,
1089 .mtu_set = cxgbe_dev_mtu_set,
1090 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1091 .tx_queue_start = cxgbe_dev_tx_queue_start,
1092 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1093 .tx_queue_release = cxgbe_dev_tx_queue_release,
1094 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1095 .rx_queue_start = cxgbe_dev_rx_queue_start,
1096 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1097 .rx_queue_release = cxgbe_dev_rx_queue_release,
1098 .stats_get = cxgbe_dev_stats_get,
1099 .stats_reset = cxgbe_dev_stats_reset,
1100 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1101 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1102 .get_eeprom_length = cxgbe_get_eeprom_length,
1103 .get_eeprom = cxgbe_get_eeprom,
1104 .set_eeprom = cxgbe_set_eeprom,
1105 .get_reg = cxgbe_get_regs,
1106 .rss_hash_update = cxgbe_dev_rss_hash_update,
1107 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1108 .mac_addr_set = cxgbe_mac_addr_set,
1113 * It returns 0 on success.
1115 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1117 struct rte_pci_device *pci_dev;
1118 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1119 struct adapter *adapter = NULL;
1120 char name[RTE_ETH_NAME_MAX_LEN];
1125 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1126 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1127 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1128 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1130 /* for secondary processes, we attach to ethdevs allocated by primary
1131 * and do minimal initialization.
1133 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1136 for (i = 1; i < MAX_NPORTS; i++) {
1137 struct rte_eth_dev *rest_eth_dev;
1138 char namei[RTE_ETH_NAME_MAX_LEN];
1140 snprintf(namei, sizeof(namei), "%s_%d",
1141 pci_dev->device.name, i);
1142 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1144 rest_eth_dev->device = &pci_dev->device;
1145 rest_eth_dev->dev_ops =
1147 rest_eth_dev->rx_pkt_burst =
1148 eth_dev->rx_pkt_burst;
1149 rest_eth_dev->tx_pkt_burst =
1150 eth_dev->tx_pkt_burst;
1156 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1157 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1161 adapter->use_unpacked_mode = 1;
1162 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1163 if (!adapter->regs) {
1164 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1166 goto out_free_adapter;
1168 adapter->pdev = pci_dev;
1169 adapter->eth_dev = eth_dev;
1170 pi->adapter = adapter;
1172 err = cxgbe_probe(adapter);
1174 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1176 goto out_free_adapter;
1186 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1187 struct rte_pci_device *pci_dev)
1189 return rte_eth_dev_pci_generic_probe(pci_dev,
1190 sizeof(struct port_info), eth_cxgbe_dev_init);
1193 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1195 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1198 static struct rte_pci_driver rte_cxgbe_pmd = {
1199 .id_table = cxgb4_pci_tbl,
1200 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1201 .probe = eth_cxgbe_pci_probe,
1202 .remove = eth_cxgbe_pci_remove,
1205 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1206 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1207 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");