1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
39 #include "cxgbe_flow.h"
42 * Macros needed to support the PCI Device ID Table ...
44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
45 static const struct rte_pci_id cxgb4_pci_tbl[] = {
46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
48 #define PCI_VENDOR_ID_CHELSIO 0x1425
50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
58 *... and the PCI ID Table itself ...
60 #include "base/t4_pci_id_tbl.h"
62 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
65 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
66 uint16_t pkts_sent, pkts_remain;
67 uint16_t total_sent = 0;
71 t4_os_lock(&txq->txq_lock);
72 /* free up desc from already completed tx */
73 reclaim_completed_tx(&txq->q);
74 if (unlikely(!nb_pkts))
77 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
78 while (total_sent < nb_pkts) {
79 pkts_remain = nb_pkts - total_sent;
81 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
82 idx = total_sent + pkts_sent;
83 if ((idx + 1) < nb_pkts)
84 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
86 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
92 total_sent += pkts_sent;
93 /* reclaim as much as possible */
94 reclaim_completed_tx(&txq->q);
98 t4_os_unlock(&txq->txq_lock);
102 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
105 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
106 unsigned int work_done;
108 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
109 dev_err(adapter, "error in cxgbe poll\n");
114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
115 struct rte_eth_dev_info *device_info)
117 struct port_info *pi = eth_dev->data->dev_private;
118 struct adapter *adapter = pi->adapter;
120 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
121 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
122 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
126 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
127 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
128 device_info->max_rx_queues = adapter->sge.max_ethqsets;
129 device_info->max_tx_queues = adapter->sge.max_ethqsets;
130 device_info->max_mac_addrs = 1;
131 /* XXX: For now we support one MAC/port */
132 device_info->max_vfs = adapter->params.arch.vfcount;
133 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
135 device_info->rx_queue_offload_capa = 0UL;
136 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
138 device_info->tx_queue_offload_capa = 0UL;
139 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
141 device_info->reta_size = pi->rss_size;
142 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
143 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
145 device_info->rx_desc_lim = cxgbe_desc_lim;
146 device_info->tx_desc_lim = cxgbe_desc_lim;
147 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
152 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
154 struct port_info *pi = eth_dev->data->dev_private;
155 struct adapter *adapter = pi->adapter;
157 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
158 1, -1, 1, -1, false);
161 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
163 struct port_info *pi = eth_dev->data->dev_private;
164 struct adapter *adapter = pi->adapter;
166 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
167 0, -1, 1, -1, false);
170 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
172 struct port_info *pi = eth_dev->data->dev_private;
173 struct adapter *adapter = pi->adapter;
175 /* TODO: address filters ?? */
177 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
178 -1, 1, 1, -1, false);
181 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
183 struct port_info *pi = eth_dev->data->dev_private;
184 struct adapter *adapter = pi->adapter;
186 /* TODO: address filters ?? */
188 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
189 -1, 0, 1, -1, false);
192 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
193 int wait_to_complete)
195 struct port_info *pi = eth_dev->data->dev_private;
196 struct adapter *adapter = pi->adapter;
197 struct sge *s = &adapter->sge;
198 struct rte_eth_link new_link = { 0 };
199 unsigned int i, work_done, budget = 32;
200 u8 old_link = pi->link_cfg.link_ok;
202 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
203 if (!s->fw_evtq.desc)
206 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
208 /* Exit if link status changed or always forced up */
209 if (pi->link_cfg.link_ok != old_link ||
210 cxgbe_force_linkup(adapter))
213 if (!wait_to_complete)
216 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
219 new_link.link_status = cxgbe_force_linkup(adapter) ?
220 ETH_LINK_UP : pi->link_cfg.link_ok;
221 new_link.link_autoneg = pi->link_cfg.autoneg;
222 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
223 new_link.link_speed = pi->link_cfg.speed;
225 return rte_eth_linkstatus_set(eth_dev, &new_link);
229 * Set device link up.
231 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
233 struct port_info *pi = dev->data->dev_private;
234 struct adapter *adapter = pi->adapter;
235 unsigned int work_done, budget = 32;
236 struct sge *s = &adapter->sge;
239 if (!s->fw_evtq.desc)
242 /* Flush all link events */
243 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
245 /* If link already up, nothing to do */
246 if (pi->link_cfg.link_ok)
249 ret = cxgbe_set_link_status(pi, true);
253 cxgbe_dev_link_update(dev, 1);
258 * Set device link down.
260 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
262 struct port_info *pi = dev->data->dev_private;
263 struct adapter *adapter = pi->adapter;
264 unsigned int work_done, budget = 32;
265 struct sge *s = &adapter->sge;
268 if (!s->fw_evtq.desc)
271 /* Flush all link events */
272 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
274 /* If link already down, nothing to do */
275 if (!pi->link_cfg.link_ok)
278 ret = cxgbe_set_link_status(pi, false);
282 cxgbe_dev_link_update(dev, 0);
286 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
288 struct port_info *pi = eth_dev->data->dev_private;
289 struct adapter *adapter = pi->adapter;
290 struct rte_eth_dev_info dev_info;
292 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
294 err = cxgbe_dev_info_get(eth_dev, &dev_info);
298 /* Must accommodate at least RTE_ETHER_MIN_MTU */
299 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen)
302 /* set to jumbo mode if needed */
303 if (new_mtu > RTE_ETHER_MAX_LEN)
304 eth_dev->data->dev_conf.rxmode.offloads |=
305 DEV_RX_OFFLOAD_JUMBO_FRAME;
307 eth_dev->data->dev_conf.rxmode.offloads &=
308 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
310 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
313 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
321 int cxgbe_dev_close(struct rte_eth_dev *eth_dev)
323 struct port_info *temp_pi, *pi = eth_dev->data->dev_private;
324 struct adapter *adapter = pi->adapter;
329 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
332 if (!(adapter->flags & FULL_INIT_DONE))
339 t4_sge_eth_release_queues(pi);
340 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid);
343 /* Free up the adapter-wide resources only after all the ports
344 * under this PF have been closed.
346 for_each_port(adapter, i) {
347 temp_pi = adap2pinfo(adapter, i);
352 cxgbe_close(adapter);
359 * It returns 0 on success.
361 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
363 struct port_info *pi = eth_dev->data->dev_private;
364 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode;
365 struct adapter *adapter = pi->adapter;
371 * If we don't have a connection to the firmware there's nothing we
374 if (!(adapter->flags & FW_OK)) {
379 if (!(adapter->flags & FULL_INIT_DONE)) {
380 err = cxgbe_up(adapter);
385 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
386 eth_dev->data->scattered_rx = 1;
388 eth_dev->data->scattered_rx = 0;
390 cxgbe_enable_rx_queues(pi);
392 err = cxgbe_setup_rss(pi);
396 for (i = 0; i < pi->n_tx_qsets; i++) {
397 err = cxgbe_dev_tx_queue_start(eth_dev, i);
402 for (i = 0; i < pi->n_rx_qsets; i++) {
403 err = cxgbe_dev_rx_queue_start(eth_dev, i);
408 err = cxgbe_link_start(pi);
417 * Stop device: disable rx and tx functions to allow for reconfiguring.
419 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
421 struct port_info *pi = eth_dev->data->dev_private;
422 struct adapter *adapter = pi->adapter;
426 if (!(adapter->flags & FULL_INIT_DONE))
432 * We clear queues only if both tx and rx path of the port
435 t4_sge_eth_clear_queues(pi);
436 eth_dev->data->scattered_rx = 0;
441 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
443 struct port_info *pi = eth_dev->data->dev_private;
444 struct adapter *adapter = pi->adapter;
449 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
450 eth_dev->data->dev_conf.rxmode.offloads |=
451 DEV_RX_OFFLOAD_RSS_HASH;
453 if (!(adapter->flags & FW_QUEUE_BOUND)) {
454 err = cxgbe_setup_sge_fwevtq(adapter);
457 adapter->flags |= FW_QUEUE_BOUND;
458 if (is_pf4(adapter)) {
459 err = cxgbe_setup_sge_ctrl_txq(adapter);
465 err = cxgbe_cfg_queue_count(eth_dev);
472 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
475 struct sge_eth_txq *txq = (struct sge_eth_txq *)
476 (eth_dev->data->tx_queues[tx_queue_id]);
478 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
480 ret = t4_sge_eth_txq_start(txq);
482 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
487 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
490 struct sge_eth_txq *txq = (struct sge_eth_txq *)
491 (eth_dev->data->tx_queues[tx_queue_id]);
493 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
495 ret = t4_sge_eth_txq_stop(txq);
497 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
502 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
503 uint16_t queue_idx, uint16_t nb_desc,
504 unsigned int socket_id,
505 const struct rte_eth_txconf *tx_conf __rte_unused)
507 struct port_info *pi = eth_dev->data->dev_private;
508 struct adapter *adapter = pi->adapter;
509 struct sge *s = &adapter->sge;
510 unsigned int temp_nb_desc;
511 struct sge_eth_txq *txq;
514 txq = &s->ethtxq[pi->first_txqset + queue_idx];
515 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
516 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
517 socket_id, pi->first_txqset);
519 /* Free up the existing queue */
520 if (eth_dev->data->tx_queues[queue_idx]) {
521 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
522 eth_dev->data->tx_queues[queue_idx] = NULL;
525 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
529 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
531 temp_nb_desc = nb_desc;
532 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
533 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
534 __func__, CXGBE_MIN_RING_DESC_SIZE,
535 CXGBE_DEFAULT_TX_DESC_SIZE);
536 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
537 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
538 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
539 __func__, CXGBE_MIN_RING_DESC_SIZE,
540 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
544 txq->q.size = temp_nb_desc;
546 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
547 s->fw_evtq.cntxt_id, socket_id);
549 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
550 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
554 void cxgbe_dev_tx_queue_release(void *q)
556 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
559 struct port_info *pi = (struct port_info *)
560 (txq->eth_dev->data->dev_private);
561 struct adapter *adap = pi->adapter;
563 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
564 __func__, pi->port_id, txq->q.cntxt_id);
566 t4_sge_eth_txq_release(adap, txq);
570 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
572 struct port_info *pi = eth_dev->data->dev_private;
573 struct adapter *adap = pi->adapter;
574 struct sge_eth_rxq *rxq;
577 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
578 __func__, pi->port_id, rx_queue_id);
580 rxq = eth_dev->data->rx_queues[rx_queue_id];
581 ret = t4_sge_eth_rxq_start(adap, rxq);
583 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
588 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
590 struct port_info *pi = eth_dev->data->dev_private;
591 struct adapter *adap = pi->adapter;
592 struct sge_eth_rxq *rxq;
595 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
596 __func__, pi->port_id, rx_queue_id);
598 rxq = eth_dev->data->rx_queues[rx_queue_id];
599 ret = t4_sge_eth_rxq_stop(adap, rxq);
601 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
606 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
607 uint16_t queue_idx, uint16_t nb_desc,
608 unsigned int socket_id,
609 const struct rte_eth_rxconf *rx_conf __rte_unused,
610 struct rte_mempool *mp)
612 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
613 struct port_info *pi = eth_dev->data->dev_private;
614 struct adapter *adapter = pi->adapter;
615 struct rte_eth_dev_info dev_info;
616 struct sge *s = &adapter->sge;
617 unsigned int temp_nb_desc;
618 int err = 0, msi_idx = 0;
619 struct sge_eth_rxq *rxq;
621 rxq = &s->ethrxq[pi->first_rxqset + queue_idx];
622 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
623 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
626 err = cxgbe_dev_info_get(eth_dev, &dev_info);
628 dev_err(adap, "%s: error during getting ethernet device info",
633 /* Must accommodate at least RTE_ETHER_MIN_MTU */
634 if ((pkt_len < dev_info.min_rx_bufsize) ||
635 (pkt_len > dev_info.max_rx_pktlen)) {
636 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
637 __func__, dev_info.min_rx_bufsize,
638 dev_info.max_rx_pktlen);
642 /* Free up the existing queue */
643 if (eth_dev->data->rx_queues[queue_idx]) {
644 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
645 eth_dev->data->rx_queues[queue_idx] = NULL;
648 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
652 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
654 temp_nb_desc = nb_desc;
655 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
656 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
657 __func__, CXGBE_MIN_RING_DESC_SIZE,
658 CXGBE_DEFAULT_RX_DESC_SIZE);
659 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
660 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
661 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
662 __func__, CXGBE_MIN_RING_DESC_SIZE,
663 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
667 rxq->rspq.size = temp_nb_desc;
668 if ((&rxq->fl) != NULL)
669 rxq->fl.size = temp_nb_desc;
671 /* Set to jumbo mode if necessary */
672 if (pkt_len > RTE_ETHER_MAX_LEN)
673 eth_dev->data->dev_conf.rxmode.offloads |=
674 DEV_RX_OFFLOAD_JUMBO_FRAME;
676 eth_dev->data->dev_conf.rxmode.offloads &=
677 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
679 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
682 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
683 queue_idx, socket_id);
685 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
686 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
691 void cxgbe_dev_rx_queue_release(void *q)
693 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
696 struct port_info *pi = (struct port_info *)
697 (rxq->rspq.eth_dev->data->dev_private);
698 struct adapter *adap = pi->adapter;
700 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
701 __func__, pi->port_id, rxq->rspq.cntxt_id);
703 t4_sge_eth_rxq_release(adap, rxq);
708 * Get port statistics.
710 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
711 struct rte_eth_stats *eth_stats)
713 struct port_info *pi = eth_dev->data->dev_private;
714 struct adapter *adapter = pi->adapter;
715 struct sge *s = &adapter->sge;
716 struct port_stats ps;
719 cxgbe_stats_get(pi, &ps);
722 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
723 ps.rx_ovflow2 + ps.rx_ovflow3 +
724 ps.rx_trunc0 + ps.rx_trunc1 +
725 ps.rx_trunc2 + ps.rx_trunc3;
726 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
727 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
731 eth_stats->opackets = ps.tx_frames;
732 eth_stats->obytes = ps.tx_octets;
733 eth_stats->oerrors = ps.tx_error_frames;
735 for (i = 0; i < pi->n_rx_qsets; i++) {
736 struct sge_eth_rxq *rxq =
737 &s->ethrxq[pi->first_rxqset + i];
739 eth_stats->q_ipackets[i] = rxq->stats.pkts;
740 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
741 eth_stats->ipackets += eth_stats->q_ipackets[i];
742 eth_stats->ibytes += eth_stats->q_ibytes[i];
745 for (i = 0; i < pi->n_tx_qsets; i++) {
746 struct sge_eth_txq *txq =
747 &s->ethtxq[pi->first_txqset + i];
749 eth_stats->q_opackets[i] = txq->stats.pkts;
750 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
756 * Reset port statistics.
758 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
760 struct port_info *pi = eth_dev->data->dev_private;
761 struct adapter *adapter = pi->adapter;
762 struct sge *s = &adapter->sge;
765 cxgbe_stats_reset(pi);
766 for (i = 0; i < pi->n_rx_qsets; i++) {
767 struct sge_eth_rxq *rxq =
768 &s->ethrxq[pi->first_rxqset + i];
771 rxq->stats.rx_bytes = 0;
773 for (i = 0; i < pi->n_tx_qsets; i++) {
774 struct sge_eth_txq *txq =
775 &s->ethtxq[pi->first_txqset + i];
778 txq->stats.tx_bytes = 0;
779 txq->stats.mapping_err = 0;
785 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
786 struct rte_eth_fc_conf *fc_conf)
788 struct port_info *pi = eth_dev->data->dev_private;
789 struct link_config *lc = &pi->link_cfg;
790 int rx_pause, tx_pause;
792 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
793 rx_pause = lc->fc & PAUSE_RX;
794 tx_pause = lc->fc & PAUSE_TX;
796 if (rx_pause && tx_pause)
797 fc_conf->mode = RTE_FC_FULL;
799 fc_conf->mode = RTE_FC_RX_PAUSE;
801 fc_conf->mode = RTE_FC_TX_PAUSE;
803 fc_conf->mode = RTE_FC_NONE;
807 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
808 struct rte_eth_fc_conf *fc_conf)
810 struct port_info *pi = eth_dev->data->dev_private;
811 struct adapter *adapter = pi->adapter;
812 struct link_config *lc = &pi->link_cfg;
814 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
815 if (fc_conf->autoneg)
816 lc->requested_fc |= PAUSE_AUTONEG;
818 lc->requested_fc &= ~PAUSE_AUTONEG;
821 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
822 (fc_conf->mode & RTE_FC_RX_PAUSE))
823 lc->requested_fc |= PAUSE_RX;
825 lc->requested_fc &= ~PAUSE_RX;
827 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
828 (fc_conf->mode & RTE_FC_TX_PAUSE))
829 lc->requested_fc |= PAUSE_TX;
831 lc->requested_fc &= ~PAUSE_TX;
833 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
838 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
840 static const uint32_t ptypes[] = {
846 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
851 /* Update RSS hash configuration
853 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
854 struct rte_eth_rss_conf *rss_conf)
856 struct port_info *pi = dev->data->dev_private;
857 struct adapter *adapter = pi->adapter;
860 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
864 pi->rss_hf = rss_conf->rss_hf;
866 if (rss_conf->rss_key) {
867 u32 key[10], mod_key[10];
870 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
872 for (i = 9, j = 0; i >= 0; i--, j++)
873 mod_key[j] = cpu_to_be32(key[i]);
875 t4_write_rss_key(adapter, mod_key, -1);
881 /* Get RSS hash configuration
883 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
884 struct rte_eth_rss_conf *rss_conf)
886 struct port_info *pi = dev->data->dev_private;
887 struct adapter *adapter = pi->adapter;
892 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
898 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
899 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
900 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
901 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
904 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
905 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
907 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
908 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
909 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
910 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
913 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
914 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
916 rss_conf->rss_hf = rss_hf;
918 if (rss_conf->rss_key) {
919 u32 key[10], mod_key[10];
922 t4_read_rss_key(adapter, key);
924 for (i = 9, j = 0; i >= 0; i--, j++)
925 mod_key[j] = be32_to_cpu(key[i]);
927 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
933 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
934 struct rte_eth_rss_reta_entry64 *reta_conf,
937 struct port_info *pi = dev->data->dev_private;
938 struct adapter *adapter = pi->adapter;
939 u16 i, idx, shift, *rss;
942 if (!(adapter->flags & FULL_INIT_DONE))
945 if (!reta_size || reta_size > pi->rss_size)
948 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0);
952 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16));
953 for (i = 0; i < reta_size; i++) {
954 idx = i / RTE_RETA_GROUP_SIZE;
955 shift = i % RTE_RETA_GROUP_SIZE;
956 if (!(reta_conf[idx].mask & (1ULL << shift)))
959 rss[i] = reta_conf[idx].reta[shift];
962 ret = cxgbe_write_rss(pi, rss);
964 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16));
970 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
971 struct rte_eth_rss_reta_entry64 *reta_conf,
974 struct port_info *pi = dev->data->dev_private;
975 struct adapter *adapter = pi->adapter;
978 if (!(adapter->flags & FULL_INIT_DONE))
981 if (!reta_size || reta_size > pi->rss_size)
984 for (i = 0; i < reta_size; i++) {
985 idx = i / RTE_RETA_GROUP_SIZE;
986 shift = i % RTE_RETA_GROUP_SIZE;
987 if (!(reta_conf[idx].mask & (1ULL << shift)))
990 reta_conf[idx].reta[shift] = pi->rss[i];
996 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
1003 * eeprom_ptov - translate a physical EEPROM address to virtual
1004 * @phys_addr: the physical EEPROM address
1005 * @fn: the PCI function number
1006 * @sz: size of function-specific area
1008 * Translate a physical EEPROM address to virtual. The first 1K is
1009 * accessed through virtual addresses starting at 31K, the rest is
1010 * accessed through virtual addresses starting at 0.
1012 * The mapping is as follows:
1013 * [0..1K) -> [31K..32K)
1014 * [1K..1K+A) -> [31K-A..31K)
1015 * [1K+A..ES) -> [0..ES-A-1K)
1017 * where A = @fn * @sz, and ES = EEPROM size.
1019 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
1022 if (phys_addr < 1024)
1023 return phys_addr + (31 << 10);
1024 if (phys_addr < 1024 + fn)
1025 return fn + phys_addr - 1024;
1026 if (phys_addr < EEPROMSIZE)
1027 return phys_addr - 1024 - fn;
1028 if (phys_addr < EEPROMVSIZE)
1029 return phys_addr - 1024;
1033 /* The next two routines implement eeprom read/write from physical addresses.
1035 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
1037 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1040 vaddr = t4_seeprom_read(adap, vaddr, v);
1041 return vaddr < 0 ? vaddr : 0;
1044 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
1046 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1049 vaddr = t4_seeprom_write(adap, vaddr, v);
1050 return vaddr < 0 ? vaddr : 0;
1053 #define EEPROM_MAGIC 0x38E2F10C
1055 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
1056 struct rte_dev_eeprom_info *e)
1058 struct port_info *pi = dev->data->dev_private;
1059 struct adapter *adapter = pi->adapter;
1061 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
1066 e->magic = EEPROM_MAGIC;
1067 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
1068 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1071 rte_memcpy(e->data, buf + e->offset, e->length);
1076 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
1077 struct rte_dev_eeprom_info *eeprom)
1079 struct port_info *pi = dev->data->dev_private;
1080 struct adapter *adapter = pi->adapter;
1083 u32 aligned_offset, aligned_len, *p;
1085 if (eeprom->magic != EEPROM_MAGIC)
1088 aligned_offset = eeprom->offset & ~3;
1089 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1091 if (adapter->pf > 0) {
1092 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1094 if (aligned_offset < start ||
1095 aligned_offset + aligned_len > start + EEPROMPFSIZE)
1099 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1100 /* RMW possibly needed for first or last words.
1102 buf = rte_zmalloc(NULL, aligned_len, 0);
1105 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1106 if (!err && aligned_len > 4)
1107 err = eeprom_rd_phys(adapter,
1108 aligned_offset + aligned_len - 4,
1109 (u32 *)&buf[aligned_len - 4]);
1112 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1118 err = t4_seeprom_wp(adapter, false);
1122 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1123 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1124 aligned_offset += 4;
1128 err = t4_seeprom_wp(adapter, true);
1130 if (buf != eeprom->data)
1135 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1137 struct port_info *pi = eth_dev->data->dev_private;
1138 struct adapter *adapter = pi->adapter;
1140 return t4_get_regs_len(adapter) / sizeof(uint32_t);
1143 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1144 struct rte_dev_reg_info *regs)
1146 struct port_info *pi = eth_dev->data->dev_private;
1147 struct adapter *adapter = pi->adapter;
1149 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1150 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1153 if (regs->data == NULL) {
1154 regs->length = cxgbe_get_regs_len(eth_dev);
1155 regs->width = sizeof(uint32_t);
1160 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1165 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1167 struct port_info *pi = dev->data->dev_private;
1170 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1172 dev_err(adapter, "failed to set mac addr; err = %d\n",
1176 pi->xact_addr_filt = ret;
1180 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1181 .dev_start = cxgbe_dev_start,
1182 .dev_stop = cxgbe_dev_stop,
1183 .dev_close = cxgbe_dev_close,
1184 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1185 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1186 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1187 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1188 .dev_configure = cxgbe_dev_configure,
1189 .dev_infos_get = cxgbe_dev_info_get,
1190 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1191 .link_update = cxgbe_dev_link_update,
1192 .dev_set_link_up = cxgbe_dev_set_link_up,
1193 .dev_set_link_down = cxgbe_dev_set_link_down,
1194 .mtu_set = cxgbe_dev_mtu_set,
1195 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1196 .tx_queue_start = cxgbe_dev_tx_queue_start,
1197 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1198 .tx_queue_release = cxgbe_dev_tx_queue_release,
1199 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1200 .rx_queue_start = cxgbe_dev_rx_queue_start,
1201 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1202 .rx_queue_release = cxgbe_dev_rx_queue_release,
1203 .filter_ctrl = cxgbe_dev_filter_ctrl,
1204 .stats_get = cxgbe_dev_stats_get,
1205 .stats_reset = cxgbe_dev_stats_reset,
1206 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1207 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1208 .get_eeprom_length = cxgbe_get_eeprom_length,
1209 .get_eeprom = cxgbe_get_eeprom,
1210 .set_eeprom = cxgbe_set_eeprom,
1211 .get_reg = cxgbe_get_regs,
1212 .rss_hash_update = cxgbe_dev_rss_hash_update,
1213 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1214 .mac_addr_set = cxgbe_mac_addr_set,
1215 .reta_update = cxgbe_dev_rss_reta_update,
1216 .reta_query = cxgbe_dev_rss_reta_query,
1221 * It returns 0 on success.
1223 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1225 struct rte_pci_device *pci_dev;
1226 struct port_info *pi = eth_dev->data->dev_private;
1227 struct adapter *adapter = NULL;
1228 char name[RTE_ETH_NAME_MAX_LEN];
1233 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1234 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1235 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1236 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1238 /* for secondary processes, we attach to ethdevs allocated by primary
1239 * and do minimal initialization.
1241 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1244 for (i = 1; i < MAX_NPORTS; i++) {
1245 struct rte_eth_dev *rest_eth_dev;
1246 char namei[RTE_ETH_NAME_MAX_LEN];
1248 snprintf(namei, sizeof(namei), "%s_%d",
1249 pci_dev->device.name, i);
1250 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1252 rest_eth_dev->device = &pci_dev->device;
1253 rest_eth_dev->dev_ops =
1255 rest_eth_dev->rx_pkt_burst =
1256 eth_dev->rx_pkt_burst;
1257 rest_eth_dev->tx_pkt_burst =
1258 eth_dev->tx_pkt_burst;
1259 rte_eth_dev_probing_finish(rest_eth_dev);
1265 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1267 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1268 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1272 adapter->use_unpacked_mode = 1;
1273 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1274 if (!adapter->regs) {
1275 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1277 goto out_free_adapter;
1279 adapter->pdev = pci_dev;
1280 adapter->eth_dev = eth_dev;
1281 pi->adapter = adapter;
1283 cxgbe_process_devargs(adapter);
1285 err = cxgbe_probe(adapter);
1287 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1289 goto out_free_adapter;
1299 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1301 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1305 /* Free up other ports and all resources */
1306 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
1307 err |= rte_eth_dev_close(port_id);
1309 return err == 0 ? 0 : -EIO;
1312 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1313 struct rte_pci_device *pci_dev)
1315 return rte_eth_dev_pci_generic_probe(pci_dev,
1316 sizeof(struct port_info), eth_cxgbe_dev_init);
1319 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1321 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1324 static struct rte_pci_driver rte_cxgbe_pmd = {
1325 .id_table = cxgb4_pci_tbl,
1326 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1327 .probe = eth_cxgbe_pci_probe,
1328 .remove = eth_cxgbe_pci_remove,
1331 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1332 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1333 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1334 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1335 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "
1336 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> "
1337 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> "
1338 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> ");
1339 RTE_LOG_REGISTER(cxgbe_logtype, pmd.net.cxgbe, NOTICE);
1340 RTE_LOG_REGISTER(cxgbe_mbox_logtype, pmd.net.cxgbe.mbox, NOTICE);