1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <ethdev_driver.h>
32 #include <ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
39 #include "cxgbe_flow.h"
42 * Macros needed to support the PCI Device ID Table ...
44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
45 static const struct rte_pci_id cxgb4_pci_tbl[] = {
46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
48 #define PCI_VENDOR_ID_CHELSIO 0x1425
50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
58 *... and the PCI ID Table itself ...
60 #include "base/t4_pci_id_tbl.h"
62 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
65 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
66 uint16_t pkts_sent, pkts_remain;
67 uint16_t total_sent = 0;
71 t4_os_lock(&txq->txq_lock);
72 /* free up desc from already completed tx */
73 reclaim_completed_tx(&txq->q);
74 if (unlikely(!nb_pkts))
77 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
78 while (total_sent < nb_pkts) {
79 pkts_remain = nb_pkts - total_sent;
81 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
82 idx = total_sent + pkts_sent;
83 if ((idx + 1) < nb_pkts)
84 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
86 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
92 total_sent += pkts_sent;
93 /* reclaim as much as possible */
94 reclaim_completed_tx(&txq->q);
98 t4_os_unlock(&txq->txq_lock);
102 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
105 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
106 unsigned int work_done;
108 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
109 dev_err(adapter, "error in cxgbe poll\n");
114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
115 struct rte_eth_dev_info *device_info)
117 struct port_info *pi = eth_dev->data->dev_private;
118 struct adapter *adapter = pi->adapter;
120 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
121 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
122 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
126 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
127 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
128 device_info->max_rx_queues = adapter->sge.max_ethqsets;
129 device_info->max_tx_queues = adapter->sge.max_ethqsets;
130 device_info->max_mac_addrs = 1;
131 /* XXX: For now we support one MAC/port */
132 device_info->max_vfs = adapter->params.arch.vfcount;
133 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
135 device_info->rx_queue_offload_capa = 0UL;
136 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
138 device_info->tx_queue_offload_capa = 0UL;
139 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
141 device_info->reta_size = pi->rss_size;
142 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
143 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
145 device_info->rx_desc_lim = cxgbe_desc_lim;
146 device_info->tx_desc_lim = cxgbe_desc_lim;
147 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
152 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
154 struct port_info *pi = eth_dev->data->dev_private;
155 struct adapter *adapter = pi->adapter;
157 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
158 1, -1, 1, -1, false);
161 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
163 struct port_info *pi = eth_dev->data->dev_private;
164 struct adapter *adapter = pi->adapter;
166 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
167 0, -1, 1, -1, false);
170 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
172 struct port_info *pi = eth_dev->data->dev_private;
173 struct adapter *adapter = pi->adapter;
175 /* TODO: address filters ?? */
177 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
178 -1, 1, 1, -1, false);
181 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
183 struct port_info *pi = eth_dev->data->dev_private;
184 struct adapter *adapter = pi->adapter;
186 /* TODO: address filters ?? */
188 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
189 -1, 0, 1, -1, false);
192 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
193 int wait_to_complete)
195 struct port_info *pi = eth_dev->data->dev_private;
196 unsigned int i, work_done, budget = 32;
197 struct link_config *lc = &pi->link_cfg;
198 struct adapter *adapter = pi->adapter;
199 struct rte_eth_link new_link = { 0 };
200 u8 old_link = pi->link_cfg.link_ok;
201 struct sge *s = &adapter->sge;
203 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
204 if (!s->fw_evtq.desc)
207 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
209 /* Exit if link status changed or always forced up */
210 if (pi->link_cfg.link_ok != old_link ||
211 cxgbe_force_linkup(adapter))
214 if (!wait_to_complete)
217 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
220 new_link.link_status = cxgbe_force_linkup(adapter) ?
221 ETH_LINK_UP : pi->link_cfg.link_ok;
222 new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0;
223 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
224 new_link.link_speed = t4_fwcap_to_speed(lc->link_caps);
226 return rte_eth_linkstatus_set(eth_dev, &new_link);
230 * Set device link up.
232 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
234 struct port_info *pi = dev->data->dev_private;
235 struct adapter *adapter = pi->adapter;
236 unsigned int work_done, budget = 32;
237 struct sge *s = &adapter->sge;
240 if (!s->fw_evtq.desc)
243 /* Flush all link events */
244 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
246 /* If link already up, nothing to do */
247 if (pi->link_cfg.link_ok)
250 ret = cxgbe_set_link_status(pi, true);
254 cxgbe_dev_link_update(dev, 1);
259 * Set device link down.
261 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
263 struct port_info *pi = dev->data->dev_private;
264 struct adapter *adapter = pi->adapter;
265 unsigned int work_done, budget = 32;
266 struct sge *s = &adapter->sge;
269 if (!s->fw_evtq.desc)
272 /* Flush all link events */
273 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
275 /* If link already down, nothing to do */
276 if (!pi->link_cfg.link_ok)
279 ret = cxgbe_set_link_status(pi, false);
283 cxgbe_dev_link_update(dev, 0);
287 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
289 struct port_info *pi = eth_dev->data->dev_private;
290 struct adapter *adapter = pi->adapter;
291 struct rte_eth_dev_info dev_info;
293 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
295 err = cxgbe_dev_info_get(eth_dev, &dev_info);
299 /* Must accommodate at least RTE_ETHER_MIN_MTU */
300 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen)
303 /* set to jumbo mode if needed */
304 if (new_mtu > CXGBE_ETH_MAX_LEN)
305 eth_dev->data->dev_conf.rxmode.offloads |=
306 DEV_RX_OFFLOAD_JUMBO_FRAME;
308 eth_dev->data->dev_conf.rxmode.offloads &=
309 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
311 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
314 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
322 int cxgbe_dev_close(struct rte_eth_dev *eth_dev)
324 struct port_info *temp_pi, *pi = eth_dev->data->dev_private;
325 struct adapter *adapter = pi->adapter;
330 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
333 if (!(adapter->flags & FULL_INIT_DONE))
340 t4_sge_eth_release_queues(pi);
341 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid);
344 /* Free up the adapter-wide resources only after all the ports
345 * under this PF have been closed.
347 for_each_port(adapter, i) {
348 temp_pi = adap2pinfo(adapter, i);
353 cxgbe_close(adapter);
360 * It returns 0 on success.
362 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
364 struct port_info *pi = eth_dev->data->dev_private;
365 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode;
366 struct adapter *adapter = pi->adapter;
372 * If we don't have a connection to the firmware there's nothing we
375 if (!(adapter->flags & FW_OK)) {
380 if (!(adapter->flags & FULL_INIT_DONE)) {
381 err = cxgbe_up(adapter);
386 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
387 eth_dev->data->scattered_rx = 1;
389 eth_dev->data->scattered_rx = 0;
391 cxgbe_enable_rx_queues(pi);
393 err = cxgbe_setup_rss(pi);
397 for (i = 0; i < pi->n_tx_qsets; i++) {
398 err = cxgbe_dev_tx_queue_start(eth_dev, i);
403 for (i = 0; i < pi->n_rx_qsets; i++) {
404 err = cxgbe_dev_rx_queue_start(eth_dev, i);
409 err = cxgbe_link_start(pi);
418 * Stop device: disable rx and tx functions to allow for reconfiguring.
420 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
422 struct port_info *pi = eth_dev->data->dev_private;
423 struct adapter *adapter = pi->adapter;
427 if (!(adapter->flags & FULL_INIT_DONE))
433 * We clear queues only if both tx and rx path of the port
436 t4_sge_eth_clear_queues(pi);
437 eth_dev->data->scattered_rx = 0;
442 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
444 struct port_info *pi = eth_dev->data->dev_private;
445 struct adapter *adapter = pi->adapter;
450 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
451 eth_dev->data->dev_conf.rxmode.offloads |=
452 DEV_RX_OFFLOAD_RSS_HASH;
454 if (!(adapter->flags & FW_QUEUE_BOUND)) {
455 err = cxgbe_setup_sge_fwevtq(adapter);
458 adapter->flags |= FW_QUEUE_BOUND;
459 if (is_pf4(adapter)) {
460 err = cxgbe_setup_sge_ctrl_txq(adapter);
466 err = cxgbe_cfg_queue_count(eth_dev);
473 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
476 struct sge_eth_txq *txq = (struct sge_eth_txq *)
477 (eth_dev->data->tx_queues[tx_queue_id]);
479 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
481 ret = t4_sge_eth_txq_start(txq);
483 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
488 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
491 struct sge_eth_txq *txq = (struct sge_eth_txq *)
492 (eth_dev->data->tx_queues[tx_queue_id]);
494 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
496 ret = t4_sge_eth_txq_stop(txq);
498 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
503 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
504 uint16_t queue_idx, uint16_t nb_desc,
505 unsigned int socket_id,
506 const struct rte_eth_txconf *tx_conf __rte_unused)
508 struct port_info *pi = eth_dev->data->dev_private;
509 struct adapter *adapter = pi->adapter;
510 struct sge *s = &adapter->sge;
511 unsigned int temp_nb_desc;
512 struct sge_eth_txq *txq;
515 txq = &s->ethtxq[pi->first_txqset + queue_idx];
516 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
517 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
518 socket_id, pi->first_txqset);
520 /* Free up the existing queue */
521 if (eth_dev->data->tx_queues[queue_idx]) {
522 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
523 eth_dev->data->tx_queues[queue_idx] = NULL;
526 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
530 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
532 temp_nb_desc = nb_desc;
533 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
534 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
535 __func__, CXGBE_MIN_RING_DESC_SIZE,
536 CXGBE_DEFAULT_TX_DESC_SIZE);
537 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
538 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
539 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
540 __func__, CXGBE_MIN_RING_DESC_SIZE,
541 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
545 txq->q.size = temp_nb_desc;
547 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
548 s->fw_evtq.cntxt_id, socket_id);
550 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
551 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
555 void cxgbe_dev_tx_queue_release(void *q)
557 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
560 struct port_info *pi = (struct port_info *)
561 (txq->eth_dev->data->dev_private);
562 struct adapter *adap = pi->adapter;
564 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
565 __func__, pi->port_id, txq->q.cntxt_id);
567 t4_sge_eth_txq_release(adap, txq);
571 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
573 struct port_info *pi = eth_dev->data->dev_private;
574 struct adapter *adap = pi->adapter;
575 struct sge_eth_rxq *rxq;
578 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
579 __func__, pi->port_id, rx_queue_id);
581 rxq = eth_dev->data->rx_queues[rx_queue_id];
582 ret = t4_sge_eth_rxq_start(adap, rxq);
584 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
589 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
591 struct port_info *pi = eth_dev->data->dev_private;
592 struct adapter *adap = pi->adapter;
593 struct sge_eth_rxq *rxq;
596 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
597 __func__, pi->port_id, rx_queue_id);
599 rxq = eth_dev->data->rx_queues[rx_queue_id];
600 ret = t4_sge_eth_rxq_stop(adap, rxq);
602 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
607 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
608 uint16_t queue_idx, uint16_t nb_desc,
609 unsigned int socket_id,
610 const struct rte_eth_rxconf *rx_conf __rte_unused,
611 struct rte_mempool *mp)
613 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
614 struct port_info *pi = eth_dev->data->dev_private;
615 struct adapter *adapter = pi->adapter;
616 struct rte_eth_dev_info dev_info;
617 struct sge *s = &adapter->sge;
618 unsigned int temp_nb_desc;
619 int err = 0, msi_idx = 0;
620 struct sge_eth_rxq *rxq;
622 rxq = &s->ethrxq[pi->first_rxqset + queue_idx];
623 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
624 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
627 err = cxgbe_dev_info_get(eth_dev, &dev_info);
629 dev_err(adap, "%s: error during getting ethernet device info",
634 /* Must accommodate at least RTE_ETHER_MIN_MTU */
635 if ((pkt_len < dev_info.min_rx_bufsize) ||
636 (pkt_len > dev_info.max_rx_pktlen)) {
637 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
638 __func__, dev_info.min_rx_bufsize,
639 dev_info.max_rx_pktlen);
643 /* Free up the existing queue */
644 if (eth_dev->data->rx_queues[queue_idx]) {
645 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
646 eth_dev->data->rx_queues[queue_idx] = NULL;
649 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
653 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
655 temp_nb_desc = nb_desc;
656 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
657 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
658 __func__, CXGBE_MIN_RING_DESC_SIZE,
659 CXGBE_DEFAULT_RX_DESC_SIZE);
660 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
661 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
662 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
663 __func__, CXGBE_MIN_RING_DESC_SIZE,
664 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
668 rxq->rspq.size = temp_nb_desc;
669 if ((&rxq->fl) != NULL)
670 rxq->fl.size = temp_nb_desc;
672 /* Set to jumbo mode if necessary */
673 if (pkt_len > CXGBE_ETH_MAX_LEN)
674 eth_dev->data->dev_conf.rxmode.offloads |=
675 DEV_RX_OFFLOAD_JUMBO_FRAME;
677 eth_dev->data->dev_conf.rxmode.offloads &=
678 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
680 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
683 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
684 queue_idx, socket_id);
686 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
687 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
692 void cxgbe_dev_rx_queue_release(void *q)
694 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
697 struct port_info *pi = (struct port_info *)
698 (rxq->rspq.eth_dev->data->dev_private);
699 struct adapter *adap = pi->adapter;
701 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
702 __func__, pi->port_id, rxq->rspq.cntxt_id);
704 t4_sge_eth_rxq_release(adap, rxq);
709 * Get port statistics.
711 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
712 struct rte_eth_stats *eth_stats)
714 struct port_info *pi = eth_dev->data->dev_private;
715 struct adapter *adapter = pi->adapter;
716 struct sge *s = &adapter->sge;
717 struct port_stats ps;
720 cxgbe_stats_get(pi, &ps);
723 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
724 ps.rx_ovflow2 + ps.rx_ovflow3 +
725 ps.rx_trunc0 + ps.rx_trunc1 +
726 ps.rx_trunc2 + ps.rx_trunc3;
727 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
728 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
732 eth_stats->opackets = ps.tx_frames;
733 eth_stats->obytes = ps.tx_octets;
734 eth_stats->oerrors = ps.tx_error_frames;
736 for (i = 0; i < pi->n_rx_qsets; i++) {
737 struct sge_eth_rxq *rxq =
738 &s->ethrxq[pi->first_rxqset + i];
740 eth_stats->q_ipackets[i] = rxq->stats.pkts;
741 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
742 eth_stats->ipackets += eth_stats->q_ipackets[i];
743 eth_stats->ibytes += eth_stats->q_ibytes[i];
746 for (i = 0; i < pi->n_tx_qsets; i++) {
747 struct sge_eth_txq *txq =
748 &s->ethtxq[pi->first_txqset + i];
750 eth_stats->q_opackets[i] = txq->stats.pkts;
751 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
757 * Reset port statistics.
759 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
761 struct port_info *pi = eth_dev->data->dev_private;
762 struct adapter *adapter = pi->adapter;
763 struct sge *s = &adapter->sge;
766 cxgbe_stats_reset(pi);
767 for (i = 0; i < pi->n_rx_qsets; i++) {
768 struct sge_eth_rxq *rxq =
769 &s->ethrxq[pi->first_rxqset + i];
772 rxq->stats.rx_bytes = 0;
774 for (i = 0; i < pi->n_tx_qsets; i++) {
775 struct sge_eth_txq *txq =
776 &s->ethtxq[pi->first_txqset + i];
779 txq->stats.tx_bytes = 0;
780 txq->stats.mapping_err = 0;
786 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
787 struct rte_eth_fc_conf *fc_conf)
789 struct port_info *pi = eth_dev->data->dev_private;
790 struct link_config *lc = &pi->link_cfg;
791 u8 rx_pause = 0, tx_pause = 0;
792 u32 caps = lc->link_caps;
794 if (caps & FW_PORT_CAP32_ANEG)
795 fc_conf->autoneg = 1;
797 if (caps & FW_PORT_CAP32_FC_TX)
800 if (caps & FW_PORT_CAP32_FC_RX)
803 if (rx_pause && tx_pause)
804 fc_conf->mode = RTE_FC_FULL;
806 fc_conf->mode = RTE_FC_RX_PAUSE;
808 fc_conf->mode = RTE_FC_TX_PAUSE;
810 fc_conf->mode = RTE_FC_NONE;
814 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
815 struct rte_eth_fc_conf *fc_conf)
817 struct port_info *pi = eth_dev->data->dev_private;
818 struct link_config *lc = &pi->link_cfg;
819 u32 new_caps = lc->admin_caps;
820 u8 tx_pause = 0, rx_pause = 0;
823 if (fc_conf->mode == RTE_FC_FULL) {
826 } else if (fc_conf->mode == RTE_FC_TX_PAUSE) {
828 } else if (fc_conf->mode == RTE_FC_RX_PAUSE) {
832 ret = t4_set_link_pause(pi, fc_conf->autoneg, tx_pause,
833 rx_pause, &new_caps);
837 if (!fc_conf->autoneg) {
838 if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)
839 new_caps |= FW_PORT_CAP32_FORCE_PAUSE;
841 new_caps &= ~FW_PORT_CAP32_FORCE_PAUSE;
844 if (new_caps != lc->admin_caps) {
845 ret = t4_link_l1cfg(pi, new_caps);
847 lc->admin_caps = new_caps;
854 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
856 static const uint32_t ptypes[] = {
862 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
867 /* Update RSS hash configuration
869 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
870 struct rte_eth_rss_conf *rss_conf)
872 struct port_info *pi = dev->data->dev_private;
873 struct adapter *adapter = pi->adapter;
876 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
880 pi->rss_hf = rss_conf->rss_hf;
882 if (rss_conf->rss_key) {
883 u32 key[10], mod_key[10];
886 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
888 for (i = 9, j = 0; i >= 0; i--, j++)
889 mod_key[j] = cpu_to_be32(key[i]);
891 t4_write_rss_key(adapter, mod_key, -1);
897 /* Get RSS hash configuration
899 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
900 struct rte_eth_rss_conf *rss_conf)
902 struct port_info *pi = dev->data->dev_private;
903 struct adapter *adapter = pi->adapter;
908 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
914 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
915 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
916 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
917 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
920 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
921 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
923 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
924 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
925 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
926 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
929 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
930 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
932 rss_conf->rss_hf = rss_hf;
934 if (rss_conf->rss_key) {
935 u32 key[10], mod_key[10];
938 t4_read_rss_key(adapter, key);
940 for (i = 9, j = 0; i >= 0; i--, j++)
941 mod_key[j] = be32_to_cpu(key[i]);
943 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
949 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
950 struct rte_eth_rss_reta_entry64 *reta_conf,
953 struct port_info *pi = dev->data->dev_private;
954 struct adapter *adapter = pi->adapter;
955 u16 i, idx, shift, *rss;
958 if (!(adapter->flags & FULL_INIT_DONE))
961 if (!reta_size || reta_size > pi->rss_size)
964 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0);
968 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16));
969 for (i = 0; i < reta_size; i++) {
970 idx = i / RTE_RETA_GROUP_SIZE;
971 shift = i % RTE_RETA_GROUP_SIZE;
972 if (!(reta_conf[idx].mask & (1ULL << shift)))
975 rss[i] = reta_conf[idx].reta[shift];
978 ret = cxgbe_write_rss(pi, rss);
980 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16));
986 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
987 struct rte_eth_rss_reta_entry64 *reta_conf,
990 struct port_info *pi = dev->data->dev_private;
991 struct adapter *adapter = pi->adapter;
994 if (!(adapter->flags & FULL_INIT_DONE))
997 if (!reta_size || reta_size > pi->rss_size)
1000 for (i = 0; i < reta_size; i++) {
1001 idx = i / RTE_RETA_GROUP_SIZE;
1002 shift = i % RTE_RETA_GROUP_SIZE;
1003 if (!(reta_conf[idx].mask & (1ULL << shift)))
1006 reta_conf[idx].reta[shift] = pi->rss[i];
1012 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
1019 * eeprom_ptov - translate a physical EEPROM address to virtual
1020 * @phys_addr: the physical EEPROM address
1021 * @fn: the PCI function number
1022 * @sz: size of function-specific area
1024 * Translate a physical EEPROM address to virtual. The first 1K is
1025 * accessed through virtual addresses starting at 31K, the rest is
1026 * accessed through virtual addresses starting at 0.
1028 * The mapping is as follows:
1029 * [0..1K) -> [31K..32K)
1030 * [1K..1K+A) -> [31K-A..31K)
1031 * [1K+A..ES) -> [0..ES-A-1K)
1033 * where A = @fn * @sz, and ES = EEPROM size.
1035 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
1038 if (phys_addr < 1024)
1039 return phys_addr + (31 << 10);
1040 if (phys_addr < 1024 + fn)
1041 return fn + phys_addr - 1024;
1042 if (phys_addr < EEPROMSIZE)
1043 return phys_addr - 1024 - fn;
1044 if (phys_addr < EEPROMVSIZE)
1045 return phys_addr - 1024;
1049 /* The next two routines implement eeprom read/write from physical addresses.
1051 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
1053 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1056 vaddr = t4_seeprom_read(adap, vaddr, v);
1057 return vaddr < 0 ? vaddr : 0;
1060 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
1062 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1065 vaddr = t4_seeprom_write(adap, vaddr, v);
1066 return vaddr < 0 ? vaddr : 0;
1069 #define EEPROM_MAGIC 0x38E2F10C
1071 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
1072 struct rte_dev_eeprom_info *e)
1074 struct port_info *pi = dev->data->dev_private;
1075 struct adapter *adapter = pi->adapter;
1077 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
1082 e->magic = EEPROM_MAGIC;
1083 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
1084 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1087 rte_memcpy(e->data, buf + e->offset, e->length);
1092 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
1093 struct rte_dev_eeprom_info *eeprom)
1095 struct port_info *pi = dev->data->dev_private;
1096 struct adapter *adapter = pi->adapter;
1099 u32 aligned_offset, aligned_len, *p;
1101 if (eeprom->magic != EEPROM_MAGIC)
1104 aligned_offset = eeprom->offset & ~3;
1105 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1107 if (adapter->pf > 0) {
1108 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1110 if (aligned_offset < start ||
1111 aligned_offset + aligned_len > start + EEPROMPFSIZE)
1115 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1116 /* RMW possibly needed for first or last words.
1118 buf = rte_zmalloc(NULL, aligned_len, 0);
1121 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1122 if (!err && aligned_len > 4)
1123 err = eeprom_rd_phys(adapter,
1124 aligned_offset + aligned_len - 4,
1125 (u32 *)&buf[aligned_len - 4]);
1128 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1134 err = t4_seeprom_wp(adapter, false);
1138 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1139 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1140 aligned_offset += 4;
1144 err = t4_seeprom_wp(adapter, true);
1146 if (buf != eeprom->data)
1151 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1153 struct port_info *pi = eth_dev->data->dev_private;
1154 struct adapter *adapter = pi->adapter;
1156 return t4_get_regs_len(adapter) / sizeof(uint32_t);
1159 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1160 struct rte_dev_reg_info *regs)
1162 struct port_info *pi = eth_dev->data->dev_private;
1163 struct adapter *adapter = pi->adapter;
1165 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1166 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1169 if (regs->data == NULL) {
1170 regs->length = cxgbe_get_regs_len(eth_dev);
1171 regs->width = sizeof(uint32_t);
1176 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1181 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1183 struct port_info *pi = dev->data->dev_private;
1186 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1188 dev_err(adapter, "failed to set mac addr; err = %d\n",
1192 pi->xact_addr_filt = ret;
1196 static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc,
1197 struct rte_eth_fec_capa *capa_arr)
1201 if (lc->pcaps & FW_PORT_CAP32_SPEED_100G) {
1203 capa_arr[num].speed = ETH_SPEED_NUM_100G;
1204 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1205 RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1210 if (lc->pcaps & FW_PORT_CAP32_SPEED_50G) {
1212 capa_arr[num].speed = ETH_SPEED_NUM_50G;
1213 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1214 RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
1219 if (lc->pcaps & FW_PORT_CAP32_SPEED_25G) {
1221 capa_arr[num].speed = ETH_SPEED_NUM_25G;
1222 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1223 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
1224 RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1232 static int cxgbe_fec_get_capability(struct rte_eth_dev *dev,
1233 struct rte_eth_fec_capa *speed_fec_capa,
1236 struct port_info *pi = dev->data->dev_private;
1237 struct link_config *lc = &pi->link_cfg;
1240 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1243 num_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL);
1244 if (!speed_fec_capa || num < num_entries)
1247 return cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa);
1250 static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
1252 struct port_info *pi = dev->data->dev_private;
1253 struct link_config *lc = &pi->link_cfg;
1254 u32 fec_caps = 0, caps = lc->link_caps;
1256 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1259 if (caps & FW_PORT_CAP32_FEC_RS)
1260 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1261 else if (caps & FW_PORT_CAP32_FEC_BASER_RS)
1262 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
1264 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
1266 *fec_capa = fec_caps;
1270 static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa)
1272 struct port_info *pi = dev->data->dev_private;
1273 u8 fec_rs = 0, fec_baser = 0, fec_none = 0;
1274 struct link_config *lc = &pi->link_cfg;
1275 u32 new_caps = lc->admin_caps;
1278 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1284 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO))
1287 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC))
1290 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER))
1293 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS))
1297 ret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps);
1301 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
1302 new_caps |= FW_PORT_CAP32_FORCE_FEC;
1304 new_caps &= ~FW_PORT_CAP32_FORCE_FEC;
1306 if (new_caps != lc->admin_caps) {
1307 ret = t4_link_l1cfg(pi, new_caps);
1309 lc->admin_caps = new_caps;
1315 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1316 .dev_start = cxgbe_dev_start,
1317 .dev_stop = cxgbe_dev_stop,
1318 .dev_close = cxgbe_dev_close,
1319 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1320 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1321 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1322 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1323 .dev_configure = cxgbe_dev_configure,
1324 .dev_infos_get = cxgbe_dev_info_get,
1325 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1326 .link_update = cxgbe_dev_link_update,
1327 .dev_set_link_up = cxgbe_dev_set_link_up,
1328 .dev_set_link_down = cxgbe_dev_set_link_down,
1329 .mtu_set = cxgbe_dev_mtu_set,
1330 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1331 .tx_queue_start = cxgbe_dev_tx_queue_start,
1332 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1333 .tx_queue_release = cxgbe_dev_tx_queue_release,
1334 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1335 .rx_queue_start = cxgbe_dev_rx_queue_start,
1336 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1337 .rx_queue_release = cxgbe_dev_rx_queue_release,
1338 .filter_ctrl = cxgbe_dev_filter_ctrl,
1339 .stats_get = cxgbe_dev_stats_get,
1340 .stats_reset = cxgbe_dev_stats_reset,
1341 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1342 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1343 .get_eeprom_length = cxgbe_get_eeprom_length,
1344 .get_eeprom = cxgbe_get_eeprom,
1345 .set_eeprom = cxgbe_set_eeprom,
1346 .get_reg = cxgbe_get_regs,
1347 .rss_hash_update = cxgbe_dev_rss_hash_update,
1348 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1349 .mac_addr_set = cxgbe_mac_addr_set,
1350 .reta_update = cxgbe_dev_rss_reta_update,
1351 .reta_query = cxgbe_dev_rss_reta_query,
1352 .fec_get_capability = cxgbe_fec_get_capability,
1353 .fec_get = cxgbe_fec_get,
1354 .fec_set = cxgbe_fec_set,
1359 * It returns 0 on success.
1361 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1363 struct rte_pci_device *pci_dev;
1364 struct port_info *pi = eth_dev->data->dev_private;
1365 struct adapter *adapter = NULL;
1366 char name[RTE_ETH_NAME_MAX_LEN];
1371 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1372 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1373 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1374 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1376 /* for secondary processes, we attach to ethdevs allocated by primary
1377 * and do minimal initialization.
1379 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1382 for (i = 1; i < MAX_NPORTS; i++) {
1383 struct rte_eth_dev *rest_eth_dev;
1384 char namei[RTE_ETH_NAME_MAX_LEN];
1386 snprintf(namei, sizeof(namei), "%s_%d",
1387 pci_dev->device.name, i);
1388 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1390 rest_eth_dev->device = &pci_dev->device;
1391 rest_eth_dev->dev_ops =
1393 rest_eth_dev->rx_pkt_burst =
1394 eth_dev->rx_pkt_burst;
1395 rest_eth_dev->tx_pkt_burst =
1396 eth_dev->tx_pkt_burst;
1397 rte_eth_dev_probing_finish(rest_eth_dev);
1403 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1405 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1406 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1410 adapter->use_unpacked_mode = 1;
1411 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1412 if (!adapter->regs) {
1413 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1415 goto out_free_adapter;
1417 adapter->pdev = pci_dev;
1418 adapter->eth_dev = eth_dev;
1419 pi->adapter = adapter;
1421 cxgbe_process_devargs(adapter);
1423 err = cxgbe_probe(adapter);
1425 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1427 goto out_free_adapter;
1437 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1439 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1443 /* Free up other ports and all resources */
1444 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
1445 err |= rte_eth_dev_close(port_id);
1447 return err == 0 ? 0 : -EIO;
1450 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1451 struct rte_pci_device *pci_dev)
1453 return rte_eth_dev_pci_generic_probe(pci_dev,
1454 sizeof(struct port_info), eth_cxgbe_dev_init);
1457 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1459 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1462 static struct rte_pci_driver rte_cxgbe_pmd = {
1463 .id_table = cxgb4_pci_tbl,
1464 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1465 .probe = eth_cxgbe_pci_probe,
1466 .remove = eth_cxgbe_pci_remove,
1469 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1470 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1471 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1472 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1473 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "
1474 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> "
1475 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> "
1476 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> ");
1477 RTE_LOG_REGISTER(cxgbe_logtype, pmd.net.cxgbe, NOTICE);
1478 RTE_LOG_REGISTER(cxgbe_mbox_logtype, pmd.net.cxgbe.mbox, NOTICE);