1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_tailq.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <ethdev_driver.h>
31 #include <ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
37 #include "cxgbe_pfvf.h"
38 #include "cxgbe_flow.h"
41 * Macros needed to support the PCI Device ID Table ...
43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
44 static const struct rte_pci_id cxgb4_pci_tbl[] = {
45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
47 #define PCI_VENDOR_ID_CHELSIO 0x1425
49 #define CH_PCI_ID_TABLE_ENTRY(devid) \
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
57 *... and the PCI ID Table itself ...
59 #include "base/t4_pci_id_tbl.h"
61 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
64 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
65 uint16_t pkts_sent, pkts_remain;
66 uint16_t total_sent = 0;
70 t4_os_lock(&txq->txq_lock);
71 /* free up desc from already completed tx */
72 reclaim_completed_tx(&txq->q);
73 if (unlikely(!nb_pkts))
76 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
77 while (total_sent < nb_pkts) {
78 pkts_remain = nb_pkts - total_sent;
80 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
81 idx = total_sent + pkts_sent;
82 if ((idx + 1) < nb_pkts)
83 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
85 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
91 total_sent += pkts_sent;
92 /* reclaim as much as possible */
93 reclaim_completed_tx(&txq->q);
97 t4_os_unlock(&txq->txq_lock);
101 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
104 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
105 unsigned int work_done;
107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
108 dev_err(adapter, "error in cxgbe poll\n");
113 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
114 struct rte_eth_dev_info *device_info)
116 struct port_info *pi = eth_dev->data->dev_private;
117 struct adapter *adapter = pi->adapter;
119 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
120 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
121 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
125 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
126 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
127 device_info->max_rx_queues = adapter->sge.max_ethqsets;
128 device_info->max_tx_queues = adapter->sge.max_ethqsets;
129 device_info->max_mac_addrs = 1;
130 /* XXX: For now we support one MAC/port */
131 device_info->max_vfs = adapter->params.arch.vfcount;
132 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
134 device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
136 device_info->rx_queue_offload_capa = 0UL;
137 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
139 device_info->tx_queue_offload_capa = 0UL;
140 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
142 device_info->reta_size = pi->rss_size;
143 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
144 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
146 device_info->rx_desc_lim = cxgbe_desc_lim;
147 device_info->tx_desc_lim = cxgbe_desc_lim;
148 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
153 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
155 struct port_info *pi = eth_dev->data->dev_private;
156 struct adapter *adapter = pi->adapter;
159 if (adapter->params.rawf_size != 0) {
160 ret = cxgbe_mpstcam_rawf_enable(pi);
165 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
166 1, -1, 1, -1, false);
169 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
171 struct port_info *pi = eth_dev->data->dev_private;
172 struct adapter *adapter = pi->adapter;
175 if (adapter->params.rawf_size != 0) {
176 ret = cxgbe_mpstcam_rawf_disable(pi);
181 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
182 0, -1, 1, -1, false);
185 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
187 struct port_info *pi = eth_dev->data->dev_private;
188 struct adapter *adapter = pi->adapter;
190 /* TODO: address filters ?? */
192 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
193 -1, 1, 1, -1, false);
196 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
198 struct port_info *pi = eth_dev->data->dev_private;
199 struct adapter *adapter = pi->adapter;
201 /* TODO: address filters ?? */
203 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
204 -1, 0, 1, -1, false);
207 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
208 int wait_to_complete)
210 struct port_info *pi = eth_dev->data->dev_private;
211 unsigned int i, work_done, budget = 32;
212 struct link_config *lc = &pi->link_cfg;
213 struct adapter *adapter = pi->adapter;
214 struct rte_eth_link new_link = { 0 };
215 u8 old_link = pi->link_cfg.link_ok;
216 struct sge *s = &adapter->sge;
218 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
219 if (!s->fw_evtq.desc)
222 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
224 /* Exit if link status changed or always forced up */
225 if (pi->link_cfg.link_ok != old_link ||
226 cxgbe_force_linkup(adapter))
229 if (!wait_to_complete)
232 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
235 new_link.link_status = cxgbe_force_linkup(adapter) ?
236 RTE_ETH_LINK_UP : pi->link_cfg.link_ok;
237 new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0;
238 new_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
239 new_link.link_speed = t4_fwcap_to_speed(lc->link_caps);
241 return rte_eth_linkstatus_set(eth_dev, &new_link);
245 * Set device link up.
247 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
249 struct port_info *pi = dev->data->dev_private;
250 struct adapter *adapter = pi->adapter;
251 unsigned int work_done, budget = 32;
252 struct sge *s = &adapter->sge;
255 if (!s->fw_evtq.desc)
258 /* Flush all link events */
259 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
261 /* If link already up, nothing to do */
262 if (pi->link_cfg.link_ok)
265 ret = cxgbe_set_link_status(pi, true);
269 cxgbe_dev_link_update(dev, 1);
274 * Set device link down.
276 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
278 struct port_info *pi = dev->data->dev_private;
279 struct adapter *adapter = pi->adapter;
280 unsigned int work_done, budget = 32;
281 struct sge *s = &adapter->sge;
284 if (!s->fw_evtq.desc)
287 /* Flush all link events */
288 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
290 /* If link already down, nothing to do */
291 if (!pi->link_cfg.link_ok)
294 ret = cxgbe_set_link_status(pi, false);
298 cxgbe_dev_link_update(dev, 0);
302 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
304 struct port_info *pi = eth_dev->data->dev_private;
305 struct adapter *adapter = pi->adapter;
306 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
308 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
315 int cxgbe_dev_close(struct rte_eth_dev *eth_dev)
317 struct port_info *temp_pi, *pi = eth_dev->data->dev_private;
318 struct adapter *adapter = pi->adapter;
323 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
326 if (!(adapter->flags & FULL_INIT_DONE))
333 t4_sge_eth_release_queues(pi);
334 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid);
337 /* Free up the adapter-wide resources only after all the ports
338 * under this PF have been closed.
340 for_each_port(adapter, i) {
341 temp_pi = adap2pinfo(adapter, i);
346 cxgbe_close(adapter);
353 * It returns 0 on success.
355 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
357 struct port_info *pi = eth_dev->data->dev_private;
358 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode;
359 struct adapter *adapter = pi->adapter;
365 * If we don't have a connection to the firmware there's nothing we
368 if (!(adapter->flags & FW_OK)) {
373 if (!(adapter->flags & FULL_INIT_DONE)) {
374 err = cxgbe_up(adapter);
379 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
380 eth_dev->data->scattered_rx = 1;
382 eth_dev->data->scattered_rx = 0;
384 cxgbe_enable_rx_queues(pi);
386 err = cxgbe_setup_rss(pi);
390 for (i = 0; i < pi->n_tx_qsets; i++) {
391 err = cxgbe_dev_tx_queue_start(eth_dev, i);
396 for (i = 0; i < pi->n_rx_qsets; i++) {
397 err = cxgbe_dev_rx_queue_start(eth_dev, i);
402 err = cxgbe_link_start(pi);
411 * Stop device: disable rx and tx functions to allow for reconfiguring.
413 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
415 struct port_info *pi = eth_dev->data->dev_private;
416 struct adapter *adapter = pi->adapter;
420 if (!(adapter->flags & FULL_INIT_DONE))
426 * We clear queues only if both tx and rx path of the port
429 t4_sge_eth_clear_queues(pi);
430 eth_dev->data->scattered_rx = 0;
435 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
437 struct port_info *pi = eth_dev->data->dev_private;
438 struct adapter *adapter = pi->adapter;
443 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
444 eth_dev->data->dev_conf.rxmode.offloads |=
445 RTE_ETH_RX_OFFLOAD_RSS_HASH;
447 if (!(adapter->flags & FW_QUEUE_BOUND)) {
448 err = cxgbe_setup_sge_fwevtq(adapter);
451 adapter->flags |= FW_QUEUE_BOUND;
452 if (is_pf4(adapter)) {
453 err = cxgbe_setup_sge_ctrl_txq(adapter);
459 err = cxgbe_cfg_queue_count(eth_dev);
466 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
469 struct sge_eth_txq *txq = (struct sge_eth_txq *)
470 (eth_dev->data->tx_queues[tx_queue_id]);
472 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
474 ret = t4_sge_eth_txq_start(txq);
476 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
481 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
484 struct sge_eth_txq *txq = (struct sge_eth_txq *)
485 (eth_dev->data->tx_queues[tx_queue_id]);
487 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
489 ret = t4_sge_eth_txq_stop(txq);
491 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
496 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
497 uint16_t queue_idx, uint16_t nb_desc,
498 unsigned int socket_id,
499 const struct rte_eth_txconf *tx_conf __rte_unused)
501 struct port_info *pi = eth_dev->data->dev_private;
502 struct adapter *adapter = pi->adapter;
503 struct sge *s = &adapter->sge;
504 unsigned int temp_nb_desc;
505 struct sge_eth_txq *txq;
508 txq = &s->ethtxq[pi->first_txqset + queue_idx];
509 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
510 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
511 socket_id, pi->first_txqset);
513 /* Free up the existing queue */
514 if (eth_dev->data->tx_queues[queue_idx]) {
515 cxgbe_dev_tx_queue_release(eth_dev, queue_idx);
516 eth_dev->data->tx_queues[queue_idx] = NULL;
519 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
523 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
525 temp_nb_desc = nb_desc;
526 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
527 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
528 __func__, CXGBE_MIN_RING_DESC_SIZE,
529 CXGBE_DEFAULT_TX_DESC_SIZE);
530 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
531 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
532 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
533 __func__, CXGBE_MIN_RING_DESC_SIZE,
534 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
538 txq->q.size = temp_nb_desc;
540 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
541 s->fw_evtq.cntxt_id, socket_id);
543 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
544 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
548 void cxgbe_dev_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
550 struct sge_eth_txq *txq = eth_dev->data->tx_queues[qid];
553 struct port_info *pi = (struct port_info *)
554 (txq->eth_dev->data->dev_private);
555 struct adapter *adap = pi->adapter;
557 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
558 __func__, pi->port_id, txq->q.cntxt_id);
560 t4_sge_eth_txq_release(adap, txq);
564 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
566 struct port_info *pi = eth_dev->data->dev_private;
567 struct adapter *adap = pi->adapter;
568 struct sge_eth_rxq *rxq;
571 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
572 __func__, pi->port_id, rx_queue_id);
574 rxq = eth_dev->data->rx_queues[rx_queue_id];
575 ret = t4_sge_eth_rxq_start(adap, rxq);
577 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
582 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
584 struct port_info *pi = eth_dev->data->dev_private;
585 struct adapter *adap = pi->adapter;
586 struct sge_eth_rxq *rxq;
589 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
590 __func__, pi->port_id, rx_queue_id);
592 rxq = eth_dev->data->rx_queues[rx_queue_id];
593 ret = t4_sge_eth_rxq_stop(adap, rxq);
595 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
600 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
601 uint16_t queue_idx, uint16_t nb_desc,
602 unsigned int socket_id,
603 const struct rte_eth_rxconf *rx_conf __rte_unused,
604 struct rte_mempool *mp)
606 unsigned int pkt_len = eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
608 struct port_info *pi = eth_dev->data->dev_private;
609 struct adapter *adapter = pi->adapter;
610 struct rte_eth_dev_info dev_info;
611 struct sge *s = &adapter->sge;
612 unsigned int temp_nb_desc;
613 int err = 0, msi_idx = 0;
614 struct sge_eth_rxq *rxq;
616 rxq = &s->ethrxq[pi->first_rxqset + queue_idx];
617 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
618 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
621 err = cxgbe_dev_info_get(eth_dev, &dev_info);
623 dev_err(adap, "%s: error during getting ethernet device info",
628 /* Must accommodate at least RTE_ETHER_MIN_MTU */
629 if ((pkt_len < dev_info.min_rx_bufsize) ||
630 (pkt_len > dev_info.max_rx_pktlen)) {
631 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
632 __func__, dev_info.min_rx_bufsize,
633 dev_info.max_rx_pktlen);
637 /* Free up the existing queue */
638 if (eth_dev->data->rx_queues[queue_idx]) {
639 cxgbe_dev_rx_queue_release(eth_dev, queue_idx);
640 eth_dev->data->rx_queues[queue_idx] = NULL;
643 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
647 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
649 temp_nb_desc = nb_desc;
650 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
651 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
652 __func__, CXGBE_MIN_RING_DESC_SIZE,
653 CXGBE_DEFAULT_RX_DESC_SIZE);
654 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
655 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
656 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
657 __func__, CXGBE_MIN_RING_DESC_SIZE,
658 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
662 rxq->rspq.size = temp_nb_desc;
663 rxq->fl.size = temp_nb_desc;
665 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
668 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
669 queue_idx, socket_id);
671 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
672 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
677 void cxgbe_dev_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
679 struct sge_eth_rxq *rxq = eth_dev->data->rx_queues[qid];
682 struct port_info *pi = (struct port_info *)
683 (rxq->rspq.eth_dev->data->dev_private);
684 struct adapter *adap = pi->adapter;
686 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
687 __func__, pi->port_id, rxq->rspq.cntxt_id);
689 t4_sge_eth_rxq_release(adap, rxq);
694 * Get port statistics.
696 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
697 struct rte_eth_stats *eth_stats)
699 struct port_info *pi = eth_dev->data->dev_private;
700 struct adapter *adapter = pi->adapter;
701 struct sge *s = &adapter->sge;
702 struct port_stats ps;
705 cxgbe_stats_get(pi, &ps);
708 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
709 ps.rx_ovflow2 + ps.rx_ovflow3 +
710 ps.rx_trunc0 + ps.rx_trunc1 +
711 ps.rx_trunc2 + ps.rx_trunc3;
712 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
713 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
717 eth_stats->opackets = ps.tx_frames;
718 eth_stats->obytes = ps.tx_octets;
719 eth_stats->oerrors = ps.tx_error_frames;
721 for (i = 0; i < pi->n_rx_qsets; i++) {
722 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i];
724 eth_stats->ipackets += rxq->stats.pkts;
725 eth_stats->ibytes += rxq->stats.rx_bytes;
732 * Reset port statistics.
734 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
736 struct port_info *pi = eth_dev->data->dev_private;
737 struct adapter *adapter = pi->adapter;
738 struct sge *s = &adapter->sge;
741 cxgbe_stats_reset(pi);
742 for (i = 0; i < pi->n_rx_qsets; i++) {
743 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i];
745 memset(&rxq->stats, 0, sizeof(rxq->stats));
747 for (i = 0; i < pi->n_tx_qsets; i++) {
748 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + i];
750 memset(&txq->stats, 0, sizeof(txq->stats));
756 /* Store extended statistics names and its offset in stats structure */
757 struct cxgbe_dev_xstats_name_off {
758 char name[RTE_ETH_XSTATS_NAME_SIZE];
762 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_rxq_stats_strings[] = {
763 {"packets", offsetof(struct sge_eth_rx_stats, pkts)},
764 {"bytes", offsetof(struct sge_eth_rx_stats, rx_bytes)},
765 {"checksum_offloads", offsetof(struct sge_eth_rx_stats, rx_cso)},
766 {"vlan_extractions", offsetof(struct sge_eth_rx_stats, vlan_ex)},
767 {"dropped_packets", offsetof(struct sge_eth_rx_stats, rx_drops)},
770 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_txq_stats_strings[] = {
771 {"packets", offsetof(struct sge_eth_tx_stats, pkts)},
772 {"bytes", offsetof(struct sge_eth_tx_stats, tx_bytes)},
773 {"tso_requests", offsetof(struct sge_eth_tx_stats, tso)},
774 {"checksum_offloads", offsetof(struct sge_eth_tx_stats, tx_cso)},
775 {"vlan_insertions", offsetof(struct sge_eth_tx_stats, vlan_ins)},
776 {"packet_mapping_errors",
777 offsetof(struct sge_eth_tx_stats, mapping_err)},
778 {"coalesced_wrs", offsetof(struct sge_eth_tx_stats, coal_wr)},
779 {"coalesced_packets", offsetof(struct sge_eth_tx_stats, coal_pkts)},
782 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_port_stats_strings[] = {
783 {"tx_bytes", offsetof(struct port_stats, tx_octets)},
784 {"tx_packets", offsetof(struct port_stats, tx_frames)},
785 {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)},
786 {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)},
787 {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)},
788 {"tx_error_packets", offsetof(struct port_stats, tx_error_frames)},
789 {"tx_size_64_packets", offsetof(struct port_stats, tx_frames_64)},
790 {"tx_size_65_to_127_packets",
791 offsetof(struct port_stats, tx_frames_65_127)},
792 {"tx_size_128_to_255_packets",
793 offsetof(struct port_stats, tx_frames_128_255)},
794 {"tx_size_256_to_511_packets",
795 offsetof(struct port_stats, tx_frames_256_511)},
796 {"tx_size_512_to_1023_packets",
797 offsetof(struct port_stats, tx_frames_512_1023)},
798 {"tx_size_1024_to_1518_packets",
799 offsetof(struct port_stats, tx_frames_1024_1518)},
800 {"tx_size_1519_to_max_packets",
801 offsetof(struct port_stats, tx_frames_1519_max)},
802 {"tx_drop_packets", offsetof(struct port_stats, tx_drop)},
803 {"tx_pause_frames", offsetof(struct port_stats, tx_pause)},
804 {"tx_ppp_pri0_packets", offsetof(struct port_stats, tx_ppp0)},
805 {"tx_ppp_pri1_packets", offsetof(struct port_stats, tx_ppp1)},
806 {"tx_ppp_pri2_packets", offsetof(struct port_stats, tx_ppp2)},
807 {"tx_ppp_pri3_packets", offsetof(struct port_stats, tx_ppp3)},
808 {"tx_ppp_pri4_packets", offsetof(struct port_stats, tx_ppp4)},
809 {"tx_ppp_pri5_packets", offsetof(struct port_stats, tx_ppp5)},
810 {"tx_ppp_pri6_packets", offsetof(struct port_stats, tx_ppp6)},
811 {"tx_ppp_pri7_packets", offsetof(struct port_stats, tx_ppp7)},
812 {"rx_bytes", offsetof(struct port_stats, rx_octets)},
813 {"rx_packets", offsetof(struct port_stats, rx_frames)},
814 {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)},
815 {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)},
816 {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)},
817 {"rx_too_long_packets", offsetof(struct port_stats, rx_too_long)},
818 {"rx_jabber_packets", offsetof(struct port_stats, rx_jabber)},
819 {"rx_fcs_error_packets", offsetof(struct port_stats, rx_fcs_err)},
820 {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)},
821 {"rx_symbol_error_packets",
822 offsetof(struct port_stats, rx_symbol_err)},
823 {"rx_short_packets", offsetof(struct port_stats, rx_runt)},
824 {"rx_size_64_packets", offsetof(struct port_stats, rx_frames_64)},
825 {"rx_size_65_to_127_packets",
826 offsetof(struct port_stats, rx_frames_65_127)},
827 {"rx_size_128_to_255_packets",
828 offsetof(struct port_stats, rx_frames_128_255)},
829 {"rx_size_256_to_511_packets",
830 offsetof(struct port_stats, rx_frames_256_511)},
831 {"rx_size_512_to_1023_packets",
832 offsetof(struct port_stats, rx_frames_512_1023)},
833 {"rx_size_1024_to_1518_packets",
834 offsetof(struct port_stats, rx_frames_1024_1518)},
835 {"rx_size_1519_to_max_packets",
836 offsetof(struct port_stats, rx_frames_1519_max)},
837 {"rx_pause_packets", offsetof(struct port_stats, rx_pause)},
838 {"rx_ppp_pri0_packets", offsetof(struct port_stats, rx_ppp0)},
839 {"rx_ppp_pri1_packets", offsetof(struct port_stats, rx_ppp1)},
840 {"rx_ppp_pri2_packets", offsetof(struct port_stats, rx_ppp2)},
841 {"rx_ppp_pri3_packets", offsetof(struct port_stats, rx_ppp3)},
842 {"rx_ppp_pri4_packets", offsetof(struct port_stats, rx_ppp4)},
843 {"rx_ppp_pri5_packets", offsetof(struct port_stats, rx_ppp5)},
844 {"rx_ppp_pri6_packets", offsetof(struct port_stats, rx_ppp6)},
845 {"rx_ppp_pri7_packets", offsetof(struct port_stats, rx_ppp7)},
846 {"rx_bg0_dropped_packets", offsetof(struct port_stats, rx_ovflow0)},
847 {"rx_bg1_dropped_packets", offsetof(struct port_stats, rx_ovflow1)},
848 {"rx_bg2_dropped_packets", offsetof(struct port_stats, rx_ovflow2)},
849 {"rx_bg3_dropped_packets", offsetof(struct port_stats, rx_ovflow3)},
850 {"rx_bg0_truncated_packets", offsetof(struct port_stats, rx_trunc0)},
851 {"rx_bg1_truncated_packets", offsetof(struct port_stats, rx_trunc1)},
852 {"rx_bg2_truncated_packets", offsetof(struct port_stats, rx_trunc2)},
853 {"rx_bg3_truncated_packets", offsetof(struct port_stats, rx_trunc3)},
856 static const struct cxgbe_dev_xstats_name_off
857 cxgbevf_dev_port_stats_strings[] = {
858 {"tx_bytes", offsetof(struct port_stats, tx_octets)},
859 {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)},
860 {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)},
861 {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)},
862 {"tx_drop_packets", offsetof(struct port_stats, tx_drop)},
863 {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)},
864 {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)},
865 {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)},
866 {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)},
869 #define CXGBE_NB_RXQ_STATS RTE_DIM(cxgbe_dev_rxq_stats_strings)
870 #define CXGBE_NB_TXQ_STATS RTE_DIM(cxgbe_dev_txq_stats_strings)
871 #define CXGBE_NB_PORT_STATS RTE_DIM(cxgbe_dev_port_stats_strings)
872 #define CXGBEVF_NB_PORT_STATS RTE_DIM(cxgbevf_dev_port_stats_strings)
874 static u16 cxgbe_dev_xstats_count(struct port_info *pi)
878 count = (pi->n_tx_qsets * CXGBE_NB_TXQ_STATS) +
879 (pi->n_rx_qsets * CXGBE_NB_RXQ_STATS);
881 if (is_pf4(pi->adapter) != 0)
882 count += CXGBE_NB_PORT_STATS;
884 count += CXGBEVF_NB_PORT_STATS;
889 static int cxgbe_dev_xstats(struct rte_eth_dev *dev,
890 struct rte_eth_xstat_name *xstats_names,
891 struct rte_eth_xstat *xstats, unsigned int size)
893 const struct cxgbe_dev_xstats_name_off *xstats_str;
894 struct port_info *pi = dev->data->dev_private;
895 struct adapter *adap = pi->adapter;
896 struct sge *s = &adap->sge;
897 u16 count, i, qid, nstats;
898 struct port_stats ps;
901 count = cxgbe_dev_xstats_count(pi);
905 if (is_pf4(adap) != 0) {
906 /* port stats for PF*/
907 cxgbe_stats_get(pi, &ps);
908 xstats_str = cxgbe_dev_port_stats_strings;
909 nstats = CXGBE_NB_PORT_STATS;
911 /* port stats for VF*/
912 cxgbevf_stats_get(pi, &ps);
913 xstats_str = cxgbevf_dev_port_stats_strings;
914 nstats = CXGBEVF_NB_PORT_STATS;
918 for (i = 0; i < nstats; i++, count++) {
919 if (xstats_names != NULL)
920 snprintf(xstats_names[count].name,
921 sizeof(xstats_names[count].name),
922 "%s", xstats_str[i].name);
923 if (xstats != NULL) {
924 stats_ptr = RTE_PTR_ADD(&ps,
925 xstats_str[i].offset);
926 xstats[count].value = *stats_ptr;
927 xstats[count].id = count;
932 xstats_str = cxgbe_dev_txq_stats_strings;
933 for (qid = 0; qid < pi->n_tx_qsets; qid++) {
934 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + qid];
936 for (i = 0; i < CXGBE_NB_TXQ_STATS; i++, count++) {
937 if (xstats_names != NULL)
938 snprintf(xstats_names[count].name,
939 sizeof(xstats_names[count].name),
941 qid, xstats_str[i].name);
942 if (xstats != NULL) {
943 stats_ptr = RTE_PTR_ADD(&txq->stats,
944 xstats_str[i].offset);
945 xstats[count].value = *stats_ptr;
946 xstats[count].id = count;
952 xstats_str = cxgbe_dev_rxq_stats_strings;
953 for (qid = 0; qid < pi->n_rx_qsets; qid++) {
954 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + qid];
956 for (i = 0; i < CXGBE_NB_RXQ_STATS; i++, count++) {
957 if (xstats_names != NULL)
958 snprintf(xstats_names[count].name,
959 sizeof(xstats_names[count].name),
961 qid, xstats_str[i].name);
962 if (xstats != NULL) {
963 stats_ptr = RTE_PTR_ADD(&rxq->stats,
964 xstats_str[i].offset);
965 xstats[count].value = *stats_ptr;
966 xstats[count].id = count;
974 /* Get port extended statistics by ID. */
975 int cxgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev,
976 const uint64_t *ids, uint64_t *values,
979 struct port_info *pi = dev->data->dev_private;
980 struct rte_eth_xstat *xstats_copy;
984 count = cxgbe_dev_xstats_count(pi);
985 if (ids == NULL || values == NULL)
988 xstats_copy = rte_calloc(NULL, count, sizeof(*xstats_copy), 0);
989 if (xstats_copy == NULL)
992 cxgbe_dev_xstats(dev, NULL, xstats_copy, count);
994 for (i = 0; i < n; i++) {
995 if (ids[i] >= count) {
999 values[i] = xstats_copy[ids[i]].value;
1005 rte_free(xstats_copy);
1009 /* Get names of port extended statistics by ID. */
1010 int cxgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
1011 const uint64_t *ids,
1012 struct rte_eth_xstat_name *xnames,
1015 struct port_info *pi = dev->data->dev_private;
1016 struct rte_eth_xstat_name *xnames_copy;
1020 count = cxgbe_dev_xstats_count(pi);
1021 if (ids == NULL || xnames == NULL)
1024 xnames_copy = rte_calloc(NULL, count, sizeof(*xnames_copy), 0);
1025 if (xnames_copy == NULL)
1028 cxgbe_dev_xstats(dev, xnames_copy, NULL, count);
1030 for (i = 0; i < n; i++) {
1031 if (ids[i] >= count) {
1035 rte_strlcpy(xnames[i].name, xnames_copy[ids[i]].name,
1036 sizeof(xnames[i].name));
1042 rte_free(xnames_copy);
1046 /* Get port extended statistics. */
1047 int cxgbe_dev_xstats_get(struct rte_eth_dev *dev,
1048 struct rte_eth_xstat *xstats, unsigned int n)
1050 return cxgbe_dev_xstats(dev, NULL, xstats, n);
1053 /* Get names of port extended statistics. */
1054 int cxgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
1055 struct rte_eth_xstat_name *xstats_names,
1058 return cxgbe_dev_xstats(dev, xstats_names, NULL, n);
1061 /* Reset port extended statistics. */
1062 static int cxgbe_dev_xstats_reset(struct rte_eth_dev *dev)
1064 return cxgbe_dev_stats_reset(dev);
1067 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1068 struct rte_eth_fc_conf *fc_conf)
1070 struct port_info *pi = eth_dev->data->dev_private;
1071 struct link_config *lc = &pi->link_cfg;
1072 u8 rx_pause = 0, tx_pause = 0;
1073 u32 caps = lc->link_caps;
1075 if (caps & FW_PORT_CAP32_ANEG)
1076 fc_conf->autoneg = 1;
1078 if (caps & FW_PORT_CAP32_FC_TX)
1081 if (caps & FW_PORT_CAP32_FC_RX)
1084 if (rx_pause && tx_pause)
1085 fc_conf->mode = RTE_ETH_FC_FULL;
1087 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
1089 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
1091 fc_conf->mode = RTE_ETH_FC_NONE;
1095 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1096 struct rte_eth_fc_conf *fc_conf)
1098 struct port_info *pi = eth_dev->data->dev_private;
1099 struct link_config *lc = &pi->link_cfg;
1100 u32 new_caps = lc->admin_caps;
1101 u8 tx_pause = 0, rx_pause = 0;
1104 if (fc_conf->mode == RTE_ETH_FC_FULL) {
1107 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE) {
1109 } else if (fc_conf->mode == RTE_ETH_FC_RX_PAUSE) {
1113 ret = t4_set_link_pause(pi, fc_conf->autoneg, tx_pause,
1114 rx_pause, &new_caps);
1118 if (!fc_conf->autoneg) {
1119 if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)
1120 new_caps |= FW_PORT_CAP32_FORCE_PAUSE;
1122 new_caps &= ~FW_PORT_CAP32_FORCE_PAUSE;
1125 if (new_caps != lc->admin_caps) {
1126 ret = t4_link_l1cfg(pi, new_caps);
1128 lc->admin_caps = new_caps;
1135 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1137 static const uint32_t ptypes[] = {
1143 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
1148 /* Update RSS hash configuration
1150 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
1151 struct rte_eth_rss_conf *rss_conf)
1153 struct port_info *pi = dev->data->dev_private;
1154 struct adapter *adapter = pi->adapter;
1157 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
1161 pi->rss_hf = rss_conf->rss_hf;
1163 if (rss_conf->rss_key) {
1164 u32 key[10], mod_key[10];
1167 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
1169 for (i = 9, j = 0; i >= 0; i--, j++)
1170 mod_key[j] = cpu_to_be32(key[i]);
1172 t4_write_rss_key(adapter, mod_key, -1);
1178 /* Get RSS hash configuration
1180 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1181 struct rte_eth_rss_conf *rss_conf)
1183 struct port_info *pi = dev->data->dev_private;
1184 struct adapter *adapter = pi->adapter;
1189 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
1195 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
1196 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
1197 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
1198 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
1201 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1202 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
1204 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
1205 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP;
1206 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
1207 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP;
1210 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1211 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
1213 rss_conf->rss_hf = rss_hf;
1215 if (rss_conf->rss_key) {
1216 u32 key[10], mod_key[10];
1219 t4_read_rss_key(adapter, key);
1221 for (i = 9, j = 0; i >= 0; i--, j++)
1222 mod_key[j] = be32_to_cpu(key[i]);
1224 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
1230 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
1231 struct rte_eth_rss_reta_entry64 *reta_conf,
1234 struct port_info *pi = dev->data->dev_private;
1235 struct adapter *adapter = pi->adapter;
1236 u16 i, idx, shift, *rss;
1239 if (!(adapter->flags & FULL_INIT_DONE))
1242 if (!reta_size || reta_size > pi->rss_size)
1245 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0);
1249 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16));
1250 for (i = 0; i < reta_size; i++) {
1251 idx = i / RTE_ETH_RETA_GROUP_SIZE;
1252 shift = i % RTE_ETH_RETA_GROUP_SIZE;
1253 if (!(reta_conf[idx].mask & (1ULL << shift)))
1256 rss[i] = reta_conf[idx].reta[shift];
1259 ret = cxgbe_write_rss(pi, rss);
1261 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16));
1267 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
1268 struct rte_eth_rss_reta_entry64 *reta_conf,
1271 struct port_info *pi = dev->data->dev_private;
1272 struct adapter *adapter = pi->adapter;
1275 if (!(adapter->flags & FULL_INIT_DONE))
1278 if (!reta_size || reta_size > pi->rss_size)
1281 for (i = 0; i < reta_size; i++) {
1282 idx = i / RTE_ETH_RETA_GROUP_SIZE;
1283 shift = i % RTE_ETH_RETA_GROUP_SIZE;
1284 if (!(reta_conf[idx].mask & (1ULL << shift)))
1287 reta_conf[idx].reta[shift] = pi->rss[i];
1293 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
1300 * eeprom_ptov - translate a physical EEPROM address to virtual
1301 * @phys_addr: the physical EEPROM address
1302 * @fn: the PCI function number
1303 * @sz: size of function-specific area
1305 * Translate a physical EEPROM address to virtual. The first 1K is
1306 * accessed through virtual addresses starting at 31K, the rest is
1307 * accessed through virtual addresses starting at 0.
1309 * The mapping is as follows:
1310 * [0..1K) -> [31K..32K)
1311 * [1K..1K+A) -> [31K-A..31K)
1312 * [1K+A..ES) -> [0..ES-A-1K)
1314 * where A = @fn * @sz, and ES = EEPROM size.
1316 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
1319 if (phys_addr < 1024)
1320 return phys_addr + (31 << 10);
1321 if (phys_addr < 1024 + fn)
1322 return fn + phys_addr - 1024;
1323 if (phys_addr < EEPROMSIZE)
1324 return phys_addr - 1024 - fn;
1325 if (phys_addr < EEPROMVSIZE)
1326 return phys_addr - 1024;
1330 /* The next two routines implement eeprom read/write from physical addresses.
1332 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
1334 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1337 vaddr = t4_seeprom_read(adap, vaddr, v);
1338 return vaddr < 0 ? vaddr : 0;
1341 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
1343 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1346 vaddr = t4_seeprom_write(adap, vaddr, v);
1347 return vaddr < 0 ? vaddr : 0;
1350 #define EEPROM_MAGIC 0x38E2F10C
1352 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
1353 struct rte_dev_eeprom_info *e)
1355 struct port_info *pi = dev->data->dev_private;
1356 struct adapter *adapter = pi->adapter;
1358 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
1363 e->magic = EEPROM_MAGIC;
1364 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
1365 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1368 rte_memcpy(e->data, buf + e->offset, e->length);
1373 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
1374 struct rte_dev_eeprom_info *eeprom)
1376 struct port_info *pi = dev->data->dev_private;
1377 struct adapter *adapter = pi->adapter;
1380 u32 aligned_offset, aligned_len, *p;
1382 if (eeprom->magic != EEPROM_MAGIC)
1385 aligned_offset = eeprom->offset & ~3;
1386 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1388 if (adapter->pf > 0) {
1389 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1391 if (aligned_offset < start ||
1392 aligned_offset + aligned_len > start + EEPROMPFSIZE)
1396 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1397 /* RMW possibly needed for first or last words.
1399 buf = rte_zmalloc(NULL, aligned_len, 0);
1402 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1403 if (!err && aligned_len > 4)
1404 err = eeprom_rd_phys(adapter,
1405 aligned_offset + aligned_len - 4,
1406 (u32 *)&buf[aligned_len - 4]);
1409 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1415 err = t4_seeprom_wp(adapter, false);
1419 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1420 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1421 aligned_offset += 4;
1425 err = t4_seeprom_wp(adapter, true);
1427 if (buf != eeprom->data)
1432 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1434 struct port_info *pi = eth_dev->data->dev_private;
1435 struct adapter *adapter = pi->adapter;
1437 return t4_get_regs_len(adapter) / sizeof(uint32_t);
1440 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1441 struct rte_dev_reg_info *regs)
1443 struct port_info *pi = eth_dev->data->dev_private;
1444 struct adapter *adapter = pi->adapter;
1446 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1447 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1450 if (regs->data == NULL) {
1451 regs->length = cxgbe_get_regs_len(eth_dev);
1452 regs->width = sizeof(uint32_t);
1457 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1462 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1464 struct port_info *pi = dev->data->dev_private;
1467 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1469 dev_err(adapter, "failed to set mac addr; err = %d\n",
1473 pi->xact_addr_filt = ret;
1477 static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc,
1478 struct rte_eth_fec_capa *capa_arr)
1482 if (lc->pcaps & FW_PORT_CAP32_SPEED_100G) {
1484 capa_arr[num].speed = RTE_ETH_SPEED_NUM_100G;
1485 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1486 RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1491 if (lc->pcaps & FW_PORT_CAP32_SPEED_50G) {
1493 capa_arr[num].speed = RTE_ETH_SPEED_NUM_50G;
1494 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1495 RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
1500 if (lc->pcaps & FW_PORT_CAP32_SPEED_25G) {
1502 capa_arr[num].speed = RTE_ETH_SPEED_NUM_25G;
1503 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
1504 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
1505 RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1513 static int cxgbe_fec_get_capability(struct rte_eth_dev *dev,
1514 struct rte_eth_fec_capa *speed_fec_capa,
1517 struct port_info *pi = dev->data->dev_private;
1518 struct link_config *lc = &pi->link_cfg;
1521 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1524 num_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL);
1525 if (!speed_fec_capa || num < num_entries)
1528 return cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa);
1531 static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
1533 struct port_info *pi = dev->data->dev_private;
1534 struct link_config *lc = &pi->link_cfg;
1535 u32 fec_caps = 0, caps = lc->link_caps;
1537 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1540 if (caps & FW_PORT_CAP32_FEC_RS)
1541 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
1542 else if (caps & FW_PORT_CAP32_FEC_BASER_RS)
1543 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
1545 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
1547 *fec_capa = fec_caps;
1551 static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa)
1553 struct port_info *pi = dev->data->dev_private;
1554 u8 fec_rs = 0, fec_baser = 0, fec_none = 0;
1555 struct link_config *lc = &pi->link_cfg;
1556 u32 new_caps = lc->admin_caps;
1559 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))
1565 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO))
1568 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC))
1571 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER))
1574 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS))
1578 ret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps);
1582 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
1583 new_caps |= FW_PORT_CAP32_FORCE_FEC;
1585 new_caps &= ~FW_PORT_CAP32_FORCE_FEC;
1587 if (new_caps != lc->admin_caps) {
1588 ret = t4_link_l1cfg(pi, new_caps);
1590 lc->admin_caps = new_caps;
1596 int cxgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
1599 struct port_info *pi = dev->data->dev_private;
1600 struct adapter *adapter = pi->adapter;
1603 if (adapter->params.fw_vers == 0)
1606 ret = snprintf(fw_version, fw_size, "%u.%u.%u.%u",
1607 G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
1608 G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
1609 G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
1610 G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
1615 if (fw_size < (size_t)ret)
1621 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1622 .dev_start = cxgbe_dev_start,
1623 .dev_stop = cxgbe_dev_stop,
1624 .dev_close = cxgbe_dev_close,
1625 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1626 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1627 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1628 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1629 .dev_configure = cxgbe_dev_configure,
1630 .dev_infos_get = cxgbe_dev_info_get,
1631 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1632 .link_update = cxgbe_dev_link_update,
1633 .dev_set_link_up = cxgbe_dev_set_link_up,
1634 .dev_set_link_down = cxgbe_dev_set_link_down,
1635 .mtu_set = cxgbe_dev_mtu_set,
1636 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1637 .tx_queue_start = cxgbe_dev_tx_queue_start,
1638 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1639 .tx_queue_release = cxgbe_dev_tx_queue_release,
1640 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1641 .rx_queue_start = cxgbe_dev_rx_queue_start,
1642 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1643 .rx_queue_release = cxgbe_dev_rx_queue_release,
1644 .flow_ops_get = cxgbe_dev_flow_ops_get,
1645 .stats_get = cxgbe_dev_stats_get,
1646 .stats_reset = cxgbe_dev_stats_reset,
1647 .xstats_get = cxgbe_dev_xstats_get,
1648 .xstats_get_by_id = cxgbe_dev_xstats_get_by_id,
1649 .xstats_get_names = cxgbe_dev_xstats_get_names,
1650 .xstats_get_names_by_id = cxgbe_dev_xstats_get_names_by_id,
1651 .xstats_reset = cxgbe_dev_xstats_reset,
1652 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1653 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1654 .get_eeprom_length = cxgbe_get_eeprom_length,
1655 .get_eeprom = cxgbe_get_eeprom,
1656 .set_eeprom = cxgbe_set_eeprom,
1657 .get_reg = cxgbe_get_regs,
1658 .rss_hash_update = cxgbe_dev_rss_hash_update,
1659 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1660 .mac_addr_set = cxgbe_mac_addr_set,
1661 .reta_update = cxgbe_dev_rss_reta_update,
1662 .reta_query = cxgbe_dev_rss_reta_query,
1663 .fec_get_capability = cxgbe_fec_get_capability,
1664 .fec_get = cxgbe_fec_get,
1665 .fec_set = cxgbe_fec_set,
1666 .fw_version_get = cxgbe_fw_version_get,
1671 * It returns 0 on success.
1673 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1675 struct rte_pci_device *pci_dev;
1676 struct port_info *pi = eth_dev->data->dev_private;
1677 struct adapter *adapter = NULL;
1678 char name[RTE_ETH_NAME_MAX_LEN];
1683 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1684 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1685 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1686 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1688 /* for secondary processes, we attach to ethdevs allocated by primary
1689 * and do minimal initialization.
1691 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1694 for (i = 1; i < MAX_NPORTS; i++) {
1695 struct rte_eth_dev *rest_eth_dev;
1696 char namei[RTE_ETH_NAME_MAX_LEN];
1698 snprintf(namei, sizeof(namei), "%s_%d",
1699 pci_dev->device.name, i);
1700 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1702 rest_eth_dev->device = &pci_dev->device;
1703 rest_eth_dev->dev_ops =
1705 rest_eth_dev->rx_pkt_burst =
1706 eth_dev->rx_pkt_burst;
1707 rest_eth_dev->tx_pkt_burst =
1708 eth_dev->tx_pkt_burst;
1709 rte_eth_dev_probing_finish(rest_eth_dev);
1715 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1716 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1720 adapter->use_unpacked_mode = 1;
1721 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1722 if (!adapter->regs) {
1723 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1725 goto out_free_adapter;
1727 adapter->pdev = pci_dev;
1728 adapter->eth_dev = eth_dev;
1729 pi->adapter = adapter;
1731 cxgbe_process_devargs(adapter);
1733 err = cxgbe_probe(adapter);
1735 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1737 goto out_free_adapter;
1747 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1749 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1753 /* Free up other ports and all resources */
1754 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
1755 err |= rte_eth_dev_close(port_id);
1757 return err == 0 ? 0 : -EIO;
1760 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1761 struct rte_pci_device *pci_dev)
1763 return rte_eth_dev_pci_generic_probe(pci_dev,
1764 sizeof(struct port_info), eth_cxgbe_dev_init);
1767 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1769 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1772 static struct rte_pci_driver rte_cxgbe_pmd = {
1773 .id_table = cxgb4_pci_tbl,
1774 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1775 .probe = eth_cxgbe_pci_probe,
1776 .remove = eth_cxgbe_pci_remove,
1779 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1780 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1781 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1782 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1783 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "
1784 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> "
1785 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> "
1786 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> ");
1787 RTE_LOG_REGISTER_DEFAULT(cxgbe_logtype, NOTICE);
1788 RTE_LOG_REGISTER_SUFFIX(cxgbe_mbox_logtype, mbox, NOTICE);