1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
39 #include "cxgbe_flow.h"
42 * Macros needed to support the PCI Device ID Table ...
44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
45 static const struct rte_pci_id cxgb4_pci_tbl[] = {
46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
48 #define PCI_VENDOR_ID_CHELSIO 0x1425
50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
58 *... and the PCI ID Table itself ...
60 #include "t4_pci_id_tbl.h"
62 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
63 DEV_TX_OFFLOAD_IPV4_CKSUM |\
64 DEV_TX_OFFLOAD_UDP_CKSUM |\
65 DEV_TX_OFFLOAD_TCP_CKSUM |\
66 DEV_TX_OFFLOAD_TCP_TSO)
68 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
69 DEV_RX_OFFLOAD_CRC_STRIP |\
70 DEV_RX_OFFLOAD_IPV4_CKSUM |\
71 DEV_RX_OFFLOAD_JUMBO_FRAME |\
72 DEV_RX_OFFLOAD_UDP_CKSUM |\
73 DEV_RX_OFFLOAD_TCP_CKSUM)
75 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
78 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
79 uint16_t pkts_sent, pkts_remain;
80 uint16_t total_sent = 0;
83 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
84 __func__, txq, tx_pkts, nb_pkts);
86 t4_os_lock(&txq->txq_lock);
87 /* free up desc from already completed tx */
88 reclaim_completed_tx(&txq->q);
89 while (total_sent < nb_pkts) {
90 pkts_remain = nb_pkts - total_sent;
92 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
93 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
100 total_sent += pkts_sent;
101 /* reclaim as much as possible */
102 reclaim_completed_tx(&txq->q);
105 t4_os_unlock(&txq->txq_lock);
109 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
112 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
113 unsigned int work_done;
115 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
116 __func__, rxq->rspq.cntxt_id, nb_pkts);
118 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
119 dev_err(adapter, "error in cxgbe poll\n");
121 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
125 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
126 struct rte_eth_dev_info *device_info)
128 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
129 struct adapter *adapter = pi->adapter;
130 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
132 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
133 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
134 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
138 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
139 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
140 device_info->max_rx_queues = max_queues;
141 device_info->max_tx_queues = max_queues;
142 device_info->max_mac_addrs = 1;
143 /* XXX: For now we support one MAC/port */
144 device_info->max_vfs = adapter->params.arch.vfcount;
145 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
147 device_info->rx_queue_offload_capa = 0UL;
148 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
150 device_info->tx_queue_offload_capa = 0UL;
151 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
153 device_info->reta_size = pi->rss_size;
154 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
155 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
157 device_info->rx_desc_lim = cxgbe_desc_lim;
158 device_info->tx_desc_lim = cxgbe_desc_lim;
159 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
162 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
164 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
165 struct adapter *adapter = pi->adapter;
167 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
168 1, -1, 1, -1, false);
171 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
173 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
174 struct adapter *adapter = pi->adapter;
176 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
177 0, -1, 1, -1, false);
180 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
182 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
183 struct adapter *adapter = pi->adapter;
185 /* TODO: address filters ?? */
187 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
188 -1, 1, 1, -1, false);
191 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
193 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
194 struct adapter *adapter = pi->adapter;
196 /* TODO: address filters ?? */
198 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
199 -1, 0, 1, -1, false);
202 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
203 int wait_to_complete)
205 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
206 struct adapter *adapter = pi->adapter;
207 struct sge *s = &adapter->sge;
208 struct rte_eth_link new_link = { 0 };
209 unsigned int i, work_done, budget = 32;
210 u8 old_link = pi->link_cfg.link_ok;
212 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
213 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
215 /* Exit if link status changed or always forced up */
216 if (pi->link_cfg.link_ok != old_link || force_linkup(adapter))
219 if (!wait_to_complete)
222 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
225 new_link.link_status = force_linkup(adapter) ?
226 ETH_LINK_UP : pi->link_cfg.link_ok;
227 new_link.link_autoneg = pi->link_cfg.autoneg;
228 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
229 new_link.link_speed = pi->link_cfg.speed;
231 return rte_eth_linkstatus_set(eth_dev, &new_link);
235 * Set device link up.
237 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
239 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
240 struct adapter *adapter = pi->adapter;
241 unsigned int work_done, budget = 32;
242 struct sge *s = &adapter->sge;
245 /* Flush all link events */
246 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
248 /* If link already up, nothing to do */
249 if (pi->link_cfg.link_ok)
252 ret = cxgbe_set_link_status(pi, true);
256 cxgbe_dev_link_update(dev, 1);
261 * Set device link down.
263 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
265 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
266 struct adapter *adapter = pi->adapter;
267 unsigned int work_done, budget = 32;
268 struct sge *s = &adapter->sge;
271 /* Flush all link events */
272 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
274 /* If link already down, nothing to do */
275 if (!pi->link_cfg.link_ok)
278 ret = cxgbe_set_link_status(pi, false);
282 cxgbe_dev_link_update(dev, 0);
286 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
288 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
289 struct adapter *adapter = pi->adapter;
290 struct rte_eth_dev_info dev_info;
292 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
294 cxgbe_dev_info_get(eth_dev, &dev_info);
296 /* Must accommodate at least ETHER_MIN_MTU */
297 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
300 /* set to jumbo mode if needed */
301 if (new_mtu > ETHER_MAX_LEN)
302 eth_dev->data->dev_conf.rxmode.offloads |=
303 DEV_RX_OFFLOAD_JUMBO_FRAME;
305 eth_dev->data->dev_conf.rxmode.offloads &=
306 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
308 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
311 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
319 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
321 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
322 struct adapter *adapter = pi->adapter;
326 if (!(adapter->flags & FULL_INIT_DONE))
332 * We clear queues only if both tx and rx path of the port
335 t4_sge_eth_clear_queues(pi);
339 * It returns 0 on success.
341 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
343 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
344 struct adapter *adapter = pi->adapter;
350 * If we don't have a connection to the firmware there's nothing we
353 if (!(adapter->flags & FW_OK)) {
358 if (!(adapter->flags & FULL_INIT_DONE)) {
359 err = cxgbe_up(adapter);
364 cxgbe_enable_rx_queues(pi);
370 for (i = 0; i < pi->n_tx_qsets; i++) {
371 err = cxgbe_dev_tx_queue_start(eth_dev, i);
376 for (i = 0; i < pi->n_rx_qsets; i++) {
377 err = cxgbe_dev_rx_queue_start(eth_dev, i);
382 err = link_start(pi);
391 * Stop device: disable rx and tx functions to allow for reconfiguring.
393 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
395 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
396 struct adapter *adapter = pi->adapter;
400 if (!(adapter->flags & FULL_INIT_DONE))
406 * We clear queues only if both tx and rx path of the port
409 t4_sge_eth_clear_queues(pi);
412 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
414 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
415 struct adapter *adapter = pi->adapter;
416 uint64_t configured_offloads;
420 configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
422 /* KEEP_CRC offload flag is not supported by PMD
423 * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
425 if (rte_eth_dev_must_keep_crc(configured_offloads)) {
426 dev_info(adapter, "can't disable hw crc strip\n");
427 eth_dev->data->dev_conf.rxmode.offloads |=
428 DEV_RX_OFFLOAD_CRC_STRIP;
431 if (!(adapter->flags & FW_QUEUE_BOUND)) {
432 err = setup_sge_fwevtq(adapter);
435 adapter->flags |= FW_QUEUE_BOUND;
436 err = setup_sge_ctrl_txq(adapter);
441 err = cfg_queue_count(eth_dev);
448 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
451 struct sge_eth_txq *txq = (struct sge_eth_txq *)
452 (eth_dev->data->tx_queues[tx_queue_id]);
454 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
456 ret = t4_sge_eth_txq_start(txq);
458 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
463 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
466 struct sge_eth_txq *txq = (struct sge_eth_txq *)
467 (eth_dev->data->tx_queues[tx_queue_id]);
469 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
471 ret = t4_sge_eth_txq_stop(txq);
473 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
478 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
479 uint16_t queue_idx, uint16_t nb_desc,
480 unsigned int socket_id,
481 const struct rte_eth_txconf *tx_conf __rte_unused)
483 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
484 struct adapter *adapter = pi->adapter;
485 struct sge *s = &adapter->sge;
486 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
488 unsigned int temp_nb_desc;
490 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
491 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
492 socket_id, pi->first_qset);
494 /* Free up the existing queue */
495 if (eth_dev->data->tx_queues[queue_idx]) {
496 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
497 eth_dev->data->tx_queues[queue_idx] = NULL;
500 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
504 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
506 temp_nb_desc = nb_desc;
507 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
508 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
509 __func__, CXGBE_MIN_RING_DESC_SIZE,
510 CXGBE_DEFAULT_TX_DESC_SIZE);
511 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
512 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
513 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
514 __func__, CXGBE_MIN_RING_DESC_SIZE,
515 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
519 txq->q.size = temp_nb_desc;
521 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
522 s->fw_evtq.cntxt_id, socket_id);
524 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
525 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
529 void cxgbe_dev_tx_queue_release(void *q)
531 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
534 struct port_info *pi = (struct port_info *)
535 (txq->eth_dev->data->dev_private);
536 struct adapter *adap = pi->adapter;
538 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
539 __func__, pi->port_id, txq->q.cntxt_id);
541 t4_sge_eth_txq_release(adap, txq);
545 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
548 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
549 struct adapter *adap = pi->adapter;
552 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
553 __func__, pi->port_id, rx_queue_id);
555 q = eth_dev->data->rx_queues[rx_queue_id];
557 ret = t4_sge_eth_rxq_start(adap, q);
559 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
564 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
567 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
568 struct adapter *adap = pi->adapter;
571 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
572 __func__, pi->port_id, rx_queue_id);
574 q = eth_dev->data->rx_queues[rx_queue_id];
575 ret = t4_sge_eth_rxq_stop(adap, q);
577 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
582 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
583 uint16_t queue_idx, uint16_t nb_desc,
584 unsigned int socket_id,
585 const struct rte_eth_rxconf *rx_conf __rte_unused,
586 struct rte_mempool *mp)
588 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
589 struct adapter *adapter = pi->adapter;
590 struct sge *s = &adapter->sge;
591 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
594 unsigned int temp_nb_desc;
595 struct rte_eth_dev_info dev_info;
596 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
598 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
599 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
602 cxgbe_dev_info_get(eth_dev, &dev_info);
604 /* Must accommodate at least ETHER_MIN_MTU */
605 if ((pkt_len < dev_info.min_rx_bufsize) ||
606 (pkt_len > dev_info.max_rx_pktlen)) {
607 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
608 __func__, dev_info.min_rx_bufsize,
609 dev_info.max_rx_pktlen);
613 /* Free up the existing queue */
614 if (eth_dev->data->rx_queues[queue_idx]) {
615 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
616 eth_dev->data->rx_queues[queue_idx] = NULL;
619 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
623 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
625 temp_nb_desc = nb_desc;
626 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
627 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
628 __func__, CXGBE_MIN_RING_DESC_SIZE,
629 CXGBE_DEFAULT_RX_DESC_SIZE);
630 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
631 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
632 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
633 __func__, CXGBE_MIN_RING_DESC_SIZE,
634 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
638 rxq->rspq.size = temp_nb_desc;
639 if ((&rxq->fl) != NULL)
640 rxq->fl.size = temp_nb_desc;
642 /* Set to jumbo mode if necessary */
643 if (pkt_len > ETHER_MAX_LEN)
644 eth_dev->data->dev_conf.rxmode.offloads |=
645 DEV_RX_OFFLOAD_JUMBO_FRAME;
647 eth_dev->data->dev_conf.rxmode.offloads &=
648 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
650 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
651 &rxq->fl, t4_ethrx_handler,
653 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
654 queue_idx, socket_id);
656 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
657 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
662 void cxgbe_dev_rx_queue_release(void *q)
664 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
665 struct sge_rspq *rq = &rxq->rspq;
668 struct port_info *pi = (struct port_info *)
669 (rq->eth_dev->data->dev_private);
670 struct adapter *adap = pi->adapter;
672 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
673 __func__, pi->port_id, rxq->rspq.cntxt_id);
675 t4_sge_eth_rxq_release(adap, rxq);
680 * Get port statistics.
682 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
683 struct rte_eth_stats *eth_stats)
685 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
686 struct adapter *adapter = pi->adapter;
687 struct sge *s = &adapter->sge;
688 struct port_stats ps;
691 cxgbe_stats_get(pi, &ps);
694 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
695 ps.rx_ovflow2 + ps.rx_ovflow3 +
696 ps.rx_trunc0 + ps.rx_trunc1 +
697 ps.rx_trunc2 + ps.rx_trunc3;
698 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
699 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
703 eth_stats->opackets = ps.tx_frames;
704 eth_stats->obytes = ps.tx_octets;
705 eth_stats->oerrors = ps.tx_error_frames;
707 for (i = 0; i < pi->n_rx_qsets; i++) {
708 struct sge_eth_rxq *rxq =
709 &s->ethrxq[pi->first_qset + i];
711 eth_stats->q_ipackets[i] = rxq->stats.pkts;
712 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
713 eth_stats->ipackets += eth_stats->q_ipackets[i];
714 eth_stats->ibytes += eth_stats->q_ibytes[i];
717 for (i = 0; i < pi->n_tx_qsets; i++) {
718 struct sge_eth_txq *txq =
719 &s->ethtxq[pi->first_qset + i];
721 eth_stats->q_opackets[i] = txq->stats.pkts;
722 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
723 eth_stats->q_errors[i] = txq->stats.mapping_err;
729 * Reset port statistics.
731 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
733 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
734 struct adapter *adapter = pi->adapter;
735 struct sge *s = &adapter->sge;
738 cxgbe_stats_reset(pi);
739 for (i = 0; i < pi->n_rx_qsets; i++) {
740 struct sge_eth_rxq *rxq =
741 &s->ethrxq[pi->first_qset + i];
744 rxq->stats.rx_bytes = 0;
746 for (i = 0; i < pi->n_tx_qsets; i++) {
747 struct sge_eth_txq *txq =
748 &s->ethtxq[pi->first_qset + i];
751 txq->stats.tx_bytes = 0;
752 txq->stats.mapping_err = 0;
756 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
757 struct rte_eth_fc_conf *fc_conf)
759 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
760 struct link_config *lc = &pi->link_cfg;
761 int rx_pause, tx_pause;
763 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
764 rx_pause = lc->fc & PAUSE_RX;
765 tx_pause = lc->fc & PAUSE_TX;
767 if (rx_pause && tx_pause)
768 fc_conf->mode = RTE_FC_FULL;
770 fc_conf->mode = RTE_FC_RX_PAUSE;
772 fc_conf->mode = RTE_FC_TX_PAUSE;
774 fc_conf->mode = RTE_FC_NONE;
778 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
779 struct rte_eth_fc_conf *fc_conf)
781 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
782 struct adapter *adapter = pi->adapter;
783 struct link_config *lc = &pi->link_cfg;
785 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
786 if (fc_conf->autoneg)
787 lc->requested_fc |= PAUSE_AUTONEG;
789 lc->requested_fc &= ~PAUSE_AUTONEG;
792 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
793 (fc_conf->mode & RTE_FC_RX_PAUSE))
794 lc->requested_fc |= PAUSE_RX;
796 lc->requested_fc &= ~PAUSE_RX;
798 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
799 (fc_conf->mode & RTE_FC_TX_PAUSE))
800 lc->requested_fc |= PAUSE_TX;
802 lc->requested_fc &= ~PAUSE_TX;
804 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
809 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
811 static const uint32_t ptypes[] = {
817 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
822 /* Update RSS hash configuration
824 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
825 struct rte_eth_rss_conf *rss_conf)
827 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
828 struct adapter *adapter = pi->adapter;
831 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
835 pi->rss_hf = rss_conf->rss_hf;
837 if (rss_conf->rss_key) {
838 u32 key[10], mod_key[10];
841 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
843 for (i = 9, j = 0; i >= 0; i--, j++)
844 mod_key[j] = cpu_to_be32(key[i]);
846 t4_write_rss_key(adapter, mod_key, -1);
852 /* Get RSS hash configuration
854 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
855 struct rte_eth_rss_conf *rss_conf)
857 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
858 struct adapter *adapter = pi->adapter;
863 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
869 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
870 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
871 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
872 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
875 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
876 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
878 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
879 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
880 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
881 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
884 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
885 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
887 rss_conf->rss_hf = rss_hf;
889 if (rss_conf->rss_key) {
890 u32 key[10], mod_key[10];
893 t4_read_rss_key(adapter, key);
895 for (i = 9, j = 0; i >= 0; i--, j++)
896 mod_key[j] = be32_to_cpu(key[i]);
898 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
904 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
911 * eeprom_ptov - translate a physical EEPROM address to virtual
912 * @phys_addr: the physical EEPROM address
913 * @fn: the PCI function number
914 * @sz: size of function-specific area
916 * Translate a physical EEPROM address to virtual. The first 1K is
917 * accessed through virtual addresses starting at 31K, the rest is
918 * accessed through virtual addresses starting at 0.
920 * The mapping is as follows:
921 * [0..1K) -> [31K..32K)
922 * [1K..1K+A) -> [31K-A..31K)
923 * [1K+A..ES) -> [0..ES-A-1K)
925 * where A = @fn * @sz, and ES = EEPROM size.
927 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
930 if (phys_addr < 1024)
931 return phys_addr + (31 << 10);
932 if (phys_addr < 1024 + fn)
933 return fn + phys_addr - 1024;
934 if (phys_addr < EEPROMSIZE)
935 return phys_addr - 1024 - fn;
936 if (phys_addr < EEPROMVSIZE)
937 return phys_addr - 1024;
941 /* The next two routines implement eeprom read/write from physical addresses.
943 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
945 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
948 vaddr = t4_seeprom_read(adap, vaddr, v);
949 return vaddr < 0 ? vaddr : 0;
952 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
954 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
957 vaddr = t4_seeprom_write(adap, vaddr, v);
958 return vaddr < 0 ? vaddr : 0;
961 #define EEPROM_MAGIC 0x38E2F10C
963 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
964 struct rte_dev_eeprom_info *e)
966 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
967 struct adapter *adapter = pi->adapter;
969 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
974 e->magic = EEPROM_MAGIC;
975 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
976 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
979 rte_memcpy(e->data, buf + e->offset, e->length);
984 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
985 struct rte_dev_eeprom_info *eeprom)
987 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
988 struct adapter *adapter = pi->adapter;
991 u32 aligned_offset, aligned_len, *p;
993 if (eeprom->magic != EEPROM_MAGIC)
996 aligned_offset = eeprom->offset & ~3;
997 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
999 if (adapter->pf > 0) {
1000 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1002 if (aligned_offset < start ||
1003 aligned_offset + aligned_len > start + EEPROMPFSIZE)
1007 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1008 /* RMW possibly needed for first or last words.
1010 buf = rte_zmalloc(NULL, aligned_len, 0);
1013 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1014 if (!err && aligned_len > 4)
1015 err = eeprom_rd_phys(adapter,
1016 aligned_offset + aligned_len - 4,
1017 (u32 *)&buf[aligned_len - 4]);
1020 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1026 err = t4_seeprom_wp(adapter, false);
1030 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1031 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1032 aligned_offset += 4;
1036 err = t4_seeprom_wp(adapter, true);
1038 if (buf != eeprom->data)
1043 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1045 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1046 struct adapter *adapter = pi->adapter;
1048 return t4_get_regs_len(adapter) / sizeof(uint32_t);
1051 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1052 struct rte_dev_reg_info *regs)
1054 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1055 struct adapter *adapter = pi->adapter;
1057 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1058 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1061 if (regs->data == NULL) {
1062 regs->length = cxgbe_get_regs_len(eth_dev);
1063 regs->width = sizeof(uint32_t);
1068 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1073 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1075 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1076 struct adapter *adapter = pi->adapter;
1079 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1080 pi->xact_addr_filt, (u8 *)addr, true, true);
1082 dev_err(adapter, "failed to set mac addr; err = %d\n",
1086 pi->xact_addr_filt = ret;
1090 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1091 .dev_start = cxgbe_dev_start,
1092 .dev_stop = cxgbe_dev_stop,
1093 .dev_close = cxgbe_dev_close,
1094 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1095 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1096 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1097 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1098 .dev_configure = cxgbe_dev_configure,
1099 .dev_infos_get = cxgbe_dev_info_get,
1100 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1101 .link_update = cxgbe_dev_link_update,
1102 .dev_set_link_up = cxgbe_dev_set_link_up,
1103 .dev_set_link_down = cxgbe_dev_set_link_down,
1104 .mtu_set = cxgbe_dev_mtu_set,
1105 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1106 .tx_queue_start = cxgbe_dev_tx_queue_start,
1107 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1108 .tx_queue_release = cxgbe_dev_tx_queue_release,
1109 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1110 .rx_queue_start = cxgbe_dev_rx_queue_start,
1111 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1112 .rx_queue_release = cxgbe_dev_rx_queue_release,
1113 .filter_ctrl = cxgbe_dev_filter_ctrl,
1114 .stats_get = cxgbe_dev_stats_get,
1115 .stats_reset = cxgbe_dev_stats_reset,
1116 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1117 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1118 .get_eeprom_length = cxgbe_get_eeprom_length,
1119 .get_eeprom = cxgbe_get_eeprom,
1120 .set_eeprom = cxgbe_set_eeprom,
1121 .get_reg = cxgbe_get_regs,
1122 .rss_hash_update = cxgbe_dev_rss_hash_update,
1123 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1124 .mac_addr_set = cxgbe_mac_addr_set,
1129 * It returns 0 on success.
1131 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1133 struct rte_pci_device *pci_dev;
1134 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1135 struct adapter *adapter = NULL;
1136 char name[RTE_ETH_NAME_MAX_LEN];
1141 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1142 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1143 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1144 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1146 /* for secondary processes, we attach to ethdevs allocated by primary
1147 * and do minimal initialization.
1149 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1152 for (i = 1; i < MAX_NPORTS; i++) {
1153 struct rte_eth_dev *rest_eth_dev;
1154 char namei[RTE_ETH_NAME_MAX_LEN];
1156 snprintf(namei, sizeof(namei), "%s_%d",
1157 pci_dev->device.name, i);
1158 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1160 rest_eth_dev->device = &pci_dev->device;
1161 rest_eth_dev->dev_ops =
1163 rest_eth_dev->rx_pkt_burst =
1164 eth_dev->rx_pkt_burst;
1165 rest_eth_dev->tx_pkt_burst =
1166 eth_dev->tx_pkt_burst;
1167 rte_eth_dev_probing_finish(rest_eth_dev);
1173 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1174 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1178 adapter->use_unpacked_mode = 1;
1179 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1180 if (!adapter->regs) {
1181 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1183 goto out_free_adapter;
1185 adapter->pdev = pci_dev;
1186 adapter->eth_dev = eth_dev;
1187 pi->adapter = adapter;
1189 err = cxgbe_probe(adapter);
1191 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1193 goto out_free_adapter;
1203 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1205 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1206 struct adapter *adap = pi->adapter;
1208 /* Free up other ports and all resources */
1213 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1214 struct rte_pci_device *pci_dev)
1216 return rte_eth_dev_pci_generic_probe(pci_dev,
1217 sizeof(struct port_info), eth_cxgbe_dev_init);
1220 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1222 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1225 static struct rte_pci_driver rte_cxgbe_pmd = {
1226 .id_table = cxgb4_pci_tbl,
1227 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1228 .probe = eth_cxgbe_pci_probe,
1229 .remove = eth_cxgbe_pci_remove,
1232 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1233 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1234 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1235 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1236 CXGBE_DEVARG_KEEP_OVLAN "=<0|1> "
1237 CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> ");